1 /* 2 * rt5514.c -- RT5514 ALSA SoC audio codec driver 3 * 4 * Copyright 2015 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/acpi.h> 13 #include <linux/fs.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/regmap.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/firmware.h> 23 #include <linux/gpio.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 32 #include "rl6231.h" 33 #include "rt5514.h" 34 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 35 #include "rt5514-spi.h" 36 #endif 37 38 static const struct reg_sequence rt5514_i2c_patch[] = { 39 {0x1800101c, 0x00000000}, 40 {0x18001100, 0x0000031f}, 41 {0x18001104, 0x00000007}, 42 {0x18001108, 0x00000000}, 43 {0x1800110c, 0x00000000}, 44 {0x18001110, 0x00000000}, 45 {0x18001114, 0x00000001}, 46 {0x18001118, 0x00000000}, 47 {0x18002f08, 0x00000006}, 48 {0x18002f00, 0x00055149}, 49 {0x18002f00, 0x0005514b}, 50 {0x18002f00, 0x00055149}, 51 {0xfafafafa, 0x00000001}, 52 {0x18002f10, 0x00000001}, 53 {0x18002f10, 0x00000000}, 54 {0x18002f10, 0x00000001}, 55 {0xfafafafa, 0x00000001}, 56 {0x18002000, 0x000010ec}, 57 {0xfafafafa, 0x00000000}, 58 }; 59 60 static const struct reg_sequence rt5514_patch[] = { 61 {RT5514_DIG_IO_CTRL, 0x00000040}, 62 {RT5514_CLK_CTRL1, 0x38020041}, 63 {RT5514_SRC_CTRL, 0x44000eee}, 64 {RT5514_ANA_CTRL_LDO10, 0x00028604}, 65 {RT5514_ANA_CTRL_ADCFED, 0x00000800}, 66 {RT5514_ASRC_IN_CTRL1, 0x00000003}, 67 {RT5514_DOWNFILTER0_CTRL3, 0x10000362}, 68 {RT5514_DOWNFILTER1_CTRL3, 0x10000362}, 69 }; 70 71 static const struct reg_default rt5514_reg[] = { 72 {RT5514_RESET, 0x00000000}, 73 {RT5514_PWR_ANA1, 0x00808880}, 74 {RT5514_PWR_ANA2, 0x00220000}, 75 {RT5514_I2S_CTRL1, 0x00000330}, 76 {RT5514_I2S_CTRL2, 0x20000000}, 77 {RT5514_VAD_CTRL6, 0xc00007d2}, 78 {RT5514_EXT_VAD_CTRL, 0x80000080}, 79 {RT5514_DIG_IO_CTRL, 0x00000040}, 80 {RT5514_PAD_CTRL1, 0x00804000}, 81 {RT5514_DMIC_DATA_CTRL, 0x00000005}, 82 {RT5514_DIG_SOURCE_CTRL, 0x00000002}, 83 {RT5514_SRC_CTRL, 0x44000eee}, 84 {RT5514_DOWNFILTER2_CTRL1, 0x0000882f}, 85 {RT5514_PLL_SOURCE_CTRL, 0x00000004}, 86 {RT5514_CLK_CTRL1, 0x38020041}, 87 {RT5514_CLK_CTRL2, 0x00000000}, 88 {RT5514_PLL3_CALIB_CTRL1, 0x00400200}, 89 {RT5514_PLL3_CALIB_CTRL5, 0x40220012}, 90 {RT5514_DELAY_BUF_CTRL1, 0x7fff006a}, 91 {RT5514_DELAY_BUF_CTRL3, 0x00000000}, 92 {RT5514_DOWNFILTER0_CTRL1, 0x00020c2f}, 93 {RT5514_DOWNFILTER0_CTRL2, 0x00020c2f}, 94 {RT5514_DOWNFILTER0_CTRL3, 0x10000362}, 95 {RT5514_DOWNFILTER1_CTRL1, 0x00020c2f}, 96 {RT5514_DOWNFILTER1_CTRL2, 0x00020c2f}, 97 {RT5514_DOWNFILTER1_CTRL3, 0x10000362}, 98 {RT5514_ANA_CTRL_LDO10, 0x00028604}, 99 {RT5514_ANA_CTRL_LDO18_16, 0x02000345}, 100 {RT5514_ANA_CTRL_ADC12, 0x0000a2a8}, 101 {RT5514_ANA_CTRL_ADC21, 0x00001180}, 102 {RT5514_ANA_CTRL_ADC22, 0x0000aaa8}, 103 {RT5514_ANA_CTRL_ADC23, 0x00151427}, 104 {RT5514_ANA_CTRL_MICBST, 0x00002000}, 105 {RT5514_ANA_CTRL_ADCFED, 0x00000800}, 106 {RT5514_ANA_CTRL_INBUF, 0x00000143}, 107 {RT5514_ANA_CTRL_VREF, 0x00008d50}, 108 {RT5514_ANA_CTRL_PLL3, 0x0000000e}, 109 {RT5514_ANA_CTRL_PLL1_1, 0x00000000}, 110 {RT5514_ANA_CTRL_PLL1_2, 0x00030220}, 111 {RT5514_DMIC_LP_CTRL, 0x00000000}, 112 {RT5514_MISC_CTRL_DSP, 0x00000000}, 113 {RT5514_DSP_CTRL1, 0x00055149}, 114 {RT5514_DSP_CTRL3, 0x00000006}, 115 {RT5514_DSP_CTRL4, 0x00000001}, 116 {RT5514_VENDOR_ID1, 0x00000001}, 117 {RT5514_VENDOR_ID2, 0x10ec5514}, 118 }; 119 120 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514) 121 { 122 /* Reset */ 123 regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec); 124 /* LDO_I_limit */ 125 regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604); 126 /* I2C bypass enable */ 127 regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001); 128 /* mini-core reset */ 129 regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b); 130 regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149); 131 /* I2C bypass disable */ 132 regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000); 133 /* PIN config */ 134 regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040); 135 /* PLL3(QN)=RCOSC*(10+2) */ 136 regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a); 137 /* PLL3 source=RCOSC, fsi=rt_clk */ 138 regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b); 139 /* Power on RCOSC, pll3 */ 140 regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81); 141 /* DSP clk source = pll3, ENABLE DSP clk */ 142 regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005); 143 /* Enable DSP clk auto switch */ 144 regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001); 145 /* Reduce DSP power */ 146 regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001); 147 } 148 149 static bool rt5514_volatile_register(struct device *dev, unsigned int reg) 150 { 151 switch (reg) { 152 case RT5514_VENDOR_ID1: 153 case RT5514_VENDOR_ID2: 154 return true; 155 156 default: 157 return false; 158 } 159 } 160 161 static bool rt5514_readable_register(struct device *dev, unsigned int reg) 162 { 163 switch (reg) { 164 case RT5514_RESET: 165 case RT5514_PWR_ANA1: 166 case RT5514_PWR_ANA2: 167 case RT5514_I2S_CTRL1: 168 case RT5514_I2S_CTRL2: 169 case RT5514_VAD_CTRL6: 170 case RT5514_EXT_VAD_CTRL: 171 case RT5514_DIG_IO_CTRL: 172 case RT5514_PAD_CTRL1: 173 case RT5514_DMIC_DATA_CTRL: 174 case RT5514_DIG_SOURCE_CTRL: 175 case RT5514_SRC_CTRL: 176 case RT5514_DOWNFILTER2_CTRL1: 177 case RT5514_PLL_SOURCE_CTRL: 178 case RT5514_CLK_CTRL1: 179 case RT5514_CLK_CTRL2: 180 case RT5514_PLL3_CALIB_CTRL1: 181 case RT5514_PLL3_CALIB_CTRL5: 182 case RT5514_DELAY_BUF_CTRL1: 183 case RT5514_DELAY_BUF_CTRL3: 184 case RT5514_DOWNFILTER0_CTRL1: 185 case RT5514_DOWNFILTER0_CTRL2: 186 case RT5514_DOWNFILTER0_CTRL3: 187 case RT5514_DOWNFILTER1_CTRL1: 188 case RT5514_DOWNFILTER1_CTRL2: 189 case RT5514_DOWNFILTER1_CTRL3: 190 case RT5514_ANA_CTRL_LDO10: 191 case RT5514_ANA_CTRL_LDO18_16: 192 case RT5514_ANA_CTRL_ADC12: 193 case RT5514_ANA_CTRL_ADC21: 194 case RT5514_ANA_CTRL_ADC22: 195 case RT5514_ANA_CTRL_ADC23: 196 case RT5514_ANA_CTRL_MICBST: 197 case RT5514_ANA_CTRL_ADCFED: 198 case RT5514_ANA_CTRL_INBUF: 199 case RT5514_ANA_CTRL_VREF: 200 case RT5514_ANA_CTRL_PLL3: 201 case RT5514_ANA_CTRL_PLL1_1: 202 case RT5514_ANA_CTRL_PLL1_2: 203 case RT5514_DMIC_LP_CTRL: 204 case RT5514_MISC_CTRL_DSP: 205 case RT5514_DSP_CTRL1: 206 case RT5514_DSP_CTRL3: 207 case RT5514_DSP_CTRL4: 208 case RT5514_VENDOR_ID1: 209 case RT5514_VENDOR_ID2: 210 return true; 211 212 default: 213 return false; 214 } 215 } 216 217 static bool rt5514_i2c_readable_register(struct device *dev, 218 unsigned int reg) 219 { 220 switch (reg) { 221 case RT5514_DSP_MAPPING | RT5514_RESET: 222 case RT5514_DSP_MAPPING | RT5514_PWR_ANA1: 223 case RT5514_DSP_MAPPING | RT5514_PWR_ANA2: 224 case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1: 225 case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2: 226 case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6: 227 case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL: 228 case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL: 229 case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1: 230 case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL: 231 case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL: 232 case RT5514_DSP_MAPPING | RT5514_SRC_CTRL: 233 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1: 234 case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL: 235 case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1: 236 case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2: 237 case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1: 238 case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5: 239 case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1: 240 case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3: 241 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1: 242 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2: 243 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3: 244 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1: 245 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2: 246 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3: 247 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10: 248 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16: 249 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12: 250 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21: 251 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22: 252 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23: 253 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST: 254 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED: 255 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF: 256 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF: 257 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3: 258 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1: 259 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2: 260 case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL: 261 case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP: 262 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1: 263 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3: 264 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4: 265 case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1: 266 case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2: 267 return true; 268 269 default: 270 return false; 271 } 272 } 273 274 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */ 275 static const DECLARE_TLV_DB_RANGE(bst_tlv, 276 0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0), 277 3, 3, TLV_DB_SCALE_ITEM(450, 0, 0), 278 4, 4, TLV_DB_SCALE_ITEM(750, 0, 0), 279 5, 5, TLV_DB_SCALE_ITEM(950, 0, 0), 280 6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0), 281 7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0), 282 8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0) 283 ); 284 285 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 286 287 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol, 288 struct snd_ctl_elem_value *ucontrol) 289 { 290 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 291 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 292 293 ucontrol->value.integer.value[0] = rt5514->dsp_enabled; 294 295 return 0; 296 } 297 298 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol, 299 struct snd_ctl_elem_value *ucontrol) 300 { 301 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 302 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 303 struct snd_soc_codec *codec = rt5514->codec; 304 const struct firmware *fw = NULL; 305 306 if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled) 307 return 0; 308 309 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 310 rt5514->dsp_enabled = ucontrol->value.integer.value[0]; 311 312 if (rt5514->dsp_enabled) { 313 rt5514_enable_dsp_prepare(rt5514); 314 315 request_firmware(&fw, RT5514_FIRMWARE1, codec->dev); 316 if (fw) { 317 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 318 rt5514_spi_burst_write(0x4ff60000, fw->data, 319 ((fw->size/8)+1)*8); 320 #else 321 dev_err(codec->dev, "There is no SPI driver for" 322 " loading the firmware\n"); 323 #endif 324 release_firmware(fw); 325 fw = NULL; 326 } 327 328 request_firmware(&fw, RT5514_FIRMWARE2, codec->dev); 329 if (fw) { 330 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 331 rt5514_spi_burst_write(0x4ffc0000, fw->data, 332 ((fw->size/8)+1)*8); 333 #else 334 dev_err(codec->dev, "There is no SPI driver for" 335 " loading the firmware\n"); 336 #endif 337 release_firmware(fw); 338 fw = NULL; 339 } 340 341 if (rt5514->model_buf && rt5514->model_len) { 342 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 343 int ret; 344 345 ret = rt5514_spi_burst_write(0x4ff80000, 346 rt5514->model_buf, 347 ((rt5514->model_len / 8) + 1) * 8); 348 if (ret) { 349 dev_err(codec->dev, 350 "Model load failed %d\n", ret); 351 return ret; 352 } 353 #else 354 dev_err(codec->dev, 355 "No SPI driver for loading firmware\n"); 356 #endif 357 } else { 358 request_firmware(&fw, RT5514_FIRMWARE3, 359 codec->dev); 360 if (fw) { 361 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 362 rt5514_spi_burst_write(0x4ff80000, 363 fw->data, 364 ((fw->size/8)+1)*8); 365 #else 366 dev_err(codec->dev, 367 "No SPI driver to load fw\n"); 368 #endif 369 release_firmware(fw); 370 fw = NULL; 371 } 372 } 373 374 /* DSP run */ 375 regmap_write(rt5514->i2c_regmap, 0x18002f00, 376 0x00055148); 377 } else { 378 regmap_multi_reg_write(rt5514->i2c_regmap, 379 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch)); 380 regcache_mark_dirty(rt5514->regmap); 381 regcache_sync(rt5514->regmap); 382 } 383 } 384 385 return 0; 386 } 387 388 static int rt5514_hotword_model_put(struct snd_kcontrol *kcontrol, 389 const unsigned int __user *bytes, unsigned int size) 390 { 391 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 392 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 393 struct snd_soc_codec *codec = rt5514->codec; 394 int ret = 0; 395 396 if (rt5514->model_buf || rt5514->model_len < size) { 397 if (rt5514->model_buf) 398 devm_kfree(codec->dev, rt5514->model_buf); 399 rt5514->model_buf = devm_kmalloc(codec->dev, size, GFP_KERNEL); 400 if (!rt5514->model_buf) { 401 ret = -ENOMEM; 402 goto done; 403 } 404 } 405 406 /* Skips the TLV header. */ 407 bytes += 2; 408 409 if (copy_from_user(rt5514->model_buf, bytes, size)) 410 ret = -EFAULT; 411 done: 412 rt5514->model_len = (ret ? 0 : size); 413 return ret; 414 } 415 416 static const struct snd_kcontrol_new rt5514_snd_controls[] = { 417 SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST, 418 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv), 419 SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1, 420 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0, 421 adc_vol_tlv), 422 SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1, 423 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0, 424 adc_vol_tlv), 425 SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0, 426 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put), 427 SND_SOC_BYTES_TLV("Hotword Model", 0x8504, 428 NULL, rt5514_hotword_model_put), 429 }; 430 431 /* ADC Mixer*/ 432 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = { 433 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1, 434 RT5514_AD_DMIC_MIX_BIT, 1, 1), 435 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1, 436 RT5514_AD_AD_MIX_BIT, 1, 1), 437 }; 438 439 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = { 440 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2, 441 RT5514_AD_DMIC_MIX_BIT, 1, 1), 442 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2, 443 RT5514_AD_AD_MIX_BIT, 1, 1), 444 }; 445 446 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = { 447 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1, 448 RT5514_AD_DMIC_MIX_BIT, 1, 1), 449 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1, 450 RT5514_AD_AD_MIX_BIT, 1, 1), 451 }; 452 453 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = { 454 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2, 455 RT5514_AD_DMIC_MIX_BIT, 1, 1), 456 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2, 457 RT5514_AD_AD_MIX_BIT, 1, 1), 458 }; 459 460 /* DMIC Source */ 461 static const char * const rt5514_dmic_src[] = { 462 "DMIC1", "DMIC2" 463 }; 464 465 static SOC_ENUM_SINGLE_DECL( 466 rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL, 467 RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src); 468 469 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux = 470 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum); 471 472 static SOC_ENUM_SINGLE_DECL( 473 rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL, 474 RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src); 475 476 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux = 477 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum); 478 479 /** 480 * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic. 481 * 482 * @rate: base clock rate. 483 * 484 * Choose divider parameter that gives the highest possible DMIC frequency in 485 * 1MHz - 3MHz range. 486 */ 487 static int rt5514_calc_dmic_clk(struct snd_soc_codec *codec, int rate) 488 { 489 int div[] = {2, 3, 4, 8, 12, 16, 24, 32}; 490 int i; 491 492 if (rate < 1000000 * div[0]) { 493 pr_warn("Base clock rate %d is too low\n", rate); 494 return -EINVAL; 495 } 496 497 for (i = 0; i < ARRAY_SIZE(div); i++) { 498 /* find divider that gives DMIC frequency below 3.072MHz */ 499 if (3072000 * div[i] >= rate) 500 return i; 501 } 502 503 dev_warn(codec->dev, "Base clock rate %d is too high\n", rate); 504 return -EINVAL; 505 } 506 507 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w, 508 struct snd_kcontrol *kcontrol, int event) 509 { 510 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 511 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 512 int idx; 513 514 idx = rt5514_calc_dmic_clk(codec, rt5514->sysclk); 515 if (idx < 0) 516 dev_err(codec->dev, "Failed to set DMIC clock\n"); 517 else 518 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1, 519 RT5514_CLK_DMIC_OUT_SEL_MASK, 520 idx << RT5514_CLK_DMIC_OUT_SEL_SFT); 521 522 if (rt5514->pdata.dmic_init_delay) 523 msleep(rt5514->pdata.dmic_init_delay); 524 525 return idx; 526 } 527 528 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 529 struct snd_soc_dapm_widget *sink) 530 { 531 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 532 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 533 534 if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1) 535 return 1; 536 else 537 return 0; 538 } 539 540 static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source, 541 struct snd_soc_dapm_widget *sink) 542 { 543 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 544 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 545 546 return (rt5514->sysclk > rt5514->lrck * 384); 547 } 548 549 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = { 550 /* Input Lines */ 551 SND_SOC_DAPM_INPUT("DMIC1L"), 552 SND_SOC_DAPM_INPUT("DMIC1R"), 553 SND_SOC_DAPM_INPUT("DMIC2L"), 554 SND_SOC_DAPM_INPUT("DMIC2R"), 555 556 SND_SOC_DAPM_INPUT("AMICL"), 557 SND_SOC_DAPM_INPUT("AMICR"), 558 559 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 560 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 561 562 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 563 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 564 565 SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1, 566 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0), 567 568 SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1, 569 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0), 570 SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1, 571 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0), 572 SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0, 573 NULL, 0), 574 SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1, 575 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0), 576 SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1, 577 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0), 578 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2, 579 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0), 580 SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0, 581 NULL, 0), 582 SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0, 583 NULL, 0), 584 SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0, 585 NULL, 0), 586 SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0), 587 588 589 SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0, 590 NULL, 0), 591 SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0, 592 NULL, 0), 593 SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0, 594 NULL, 0), 595 SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0, 596 NULL, 0), 597 SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT, 598 0, NULL, 0), 599 SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0), 600 601 SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0, 602 NULL, 0), 603 SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0, 604 NULL, 0), 605 SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0, 606 NULL, 0), 607 SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0, 608 NULL, 0), 609 SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT, 610 0, NULL, 0), 611 SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0), 612 613 SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2, 614 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0), 615 SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2, 616 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0), 617 SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0, 618 NULL, 0), 619 SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2, 620 RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0), 621 SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2, 622 RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0), 623 624 /* ADC Mux */ 625 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 626 &rt5514_sto1_dmic_mux), 627 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 628 &rt5514_sto2_dmic_mux), 629 630 /* ADC Mixer */ 631 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1, 632 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0), 633 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1, 634 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0), 635 636 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 637 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)), 638 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 639 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)), 640 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 641 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)), 642 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 643 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)), 644 645 SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1, 646 RT5514_AD_AD_MUTE_BIT, 1), 647 SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2, 648 RT5514_AD_AD_MUTE_BIT, 1), 649 SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1, 650 RT5514_AD_AD_MUTE_BIT, 1), 651 SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2, 652 RT5514_AD_AD_MUTE_BIT, 1), 653 654 /* ADC PGA */ 655 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 656 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 657 658 /* Audio Interface */ 659 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 660 }; 661 662 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = { 663 { "DMIC1", NULL, "DMIC1L" }, 664 { "DMIC1", NULL, "DMIC1R" }, 665 { "DMIC2", NULL, "DMIC2L" }, 666 { "DMIC2", NULL, "DMIC2R" }, 667 668 { "DMIC1L", NULL, "DMIC CLK" }, 669 { "DMIC1R", NULL, "DMIC CLK" }, 670 { "DMIC2L", NULL, "DMIC CLK" }, 671 { "DMIC2R", NULL, "DMIC CLK" }, 672 673 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 674 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 675 676 { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" }, 677 { "Sto1 ADC MIXL", "ADC Switch", "AMICL" }, 678 { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" }, 679 { "Sto1 ADC MIXR", "ADC Switch", "AMICR" }, 680 681 { "ADC Power", NULL, "LDO18 IN" }, 682 { "ADC Power", NULL, "LDO18 ADC" }, 683 { "ADC Power", NULL, "LDO21" }, 684 { "ADC Power", NULL, "BG LDO18 IN" }, 685 { "ADC Power", NULL, "BG LDO21" }, 686 { "ADC Power", NULL, "BG MBIAS" }, 687 { "ADC Power", NULL, "MBIAS" }, 688 { "ADC Power", NULL, "VREF2" }, 689 { "ADC Power", NULL, "VREF1" }, 690 691 { "ADCL Power", NULL, "LDO16L" }, 692 { "ADCL Power", NULL, "ADC1L" }, 693 { "ADCL Power", NULL, "BSTL2" }, 694 { "ADCL Power", NULL, "BSTL" }, 695 { "ADCL Power", NULL, "ADCFEDL" }, 696 697 { "ADCR Power", NULL, "LDO16R" }, 698 { "ADCR Power", NULL, "ADC1R" }, 699 { "ADCR Power", NULL, "BSTR2" }, 700 { "ADCR Power", NULL, "BSTR" }, 701 { "ADCR Power", NULL, "ADCFEDR" }, 702 703 { "AMICL", NULL, "ADC CLK" }, 704 { "AMICL", NULL, "ADC Power" }, 705 { "AMICL", NULL, "ADCL Power" }, 706 { "AMICR", NULL, "ADC CLK" }, 707 { "AMICR", NULL, "ADC Power" }, 708 { "AMICR", NULL, "ADCR Power" }, 709 710 { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" }, 711 { "PLL1", NULL, "PLL1 LDO" }, 712 713 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 714 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 715 716 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 717 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 718 { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" }, 719 { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll }, 720 { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc }, 721 722 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 723 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 724 725 { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" }, 726 { "Sto2 ADC MIXL", "ADC Switch", "AMICL" }, 727 { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" }, 728 { "Sto2 ADC MIXR", "ADC Switch", "AMICR" }, 729 730 { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" }, 731 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 732 733 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 734 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 735 { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" }, 736 { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll }, 737 { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc }, 738 739 { "AIF1TX", NULL, "Stereo1 ADC MIX"}, 740 { "AIF1TX", NULL, "Stereo2 ADC MIX"}, 741 }; 742 743 static int rt5514_hw_params(struct snd_pcm_substream *substream, 744 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 745 { 746 struct snd_soc_codec *codec = dai->codec; 747 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 748 int pre_div, bclk_ms, frame_size; 749 unsigned int val_len = 0; 750 751 rt5514->lrck = params_rate(params); 752 pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck); 753 if (pre_div < 0) { 754 dev_err(codec->dev, "Unsupported clock setting\n"); 755 return -EINVAL; 756 } 757 758 frame_size = snd_soc_params_to_frame_size(params); 759 if (frame_size < 0) { 760 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 761 return -EINVAL; 762 } 763 764 bclk_ms = frame_size > 32; 765 rt5514->bclk = rt5514->lrck * (32 << bclk_ms); 766 767 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 768 rt5514->bclk, rt5514->lrck); 769 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 770 bclk_ms, pre_div, dai->id); 771 772 switch (params_format(params)) { 773 case SNDRV_PCM_FORMAT_S16_LE: 774 break; 775 case SNDRV_PCM_FORMAT_S20_3LE: 776 val_len = RT5514_I2S_DL_20; 777 break; 778 case SNDRV_PCM_FORMAT_S24_LE: 779 val_len = RT5514_I2S_DL_24; 780 break; 781 case SNDRV_PCM_FORMAT_S8: 782 val_len = RT5514_I2S_DL_8; 783 break; 784 default: 785 return -EINVAL; 786 } 787 788 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK, 789 val_len); 790 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1, 791 RT5514_CLK_AD_ANA1_SEL_MASK, 792 (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT); 793 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 794 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK, 795 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT | 796 pre_div << RT5514_SEL_ADC_OSR_SFT); 797 798 return 0; 799 } 800 801 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 802 { 803 struct snd_soc_codec *codec = dai->codec; 804 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 805 unsigned int reg_val = 0; 806 807 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 808 case SND_SOC_DAIFMT_NB_NF: 809 break; 810 811 case SND_SOC_DAIFMT_NB_IF: 812 reg_val |= RT5514_I2S_LR_INV; 813 break; 814 815 case SND_SOC_DAIFMT_IB_NF: 816 reg_val |= RT5514_I2S_BP_INV; 817 break; 818 819 case SND_SOC_DAIFMT_IB_IF: 820 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV; 821 break; 822 823 default: 824 return -EINVAL; 825 } 826 827 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 828 case SND_SOC_DAIFMT_I2S: 829 break; 830 831 case SND_SOC_DAIFMT_LEFT_J: 832 reg_val |= RT5514_I2S_DF_LEFT; 833 break; 834 835 case SND_SOC_DAIFMT_DSP_A: 836 reg_val |= RT5514_I2S_DF_PCM_A; 837 break; 838 839 case SND_SOC_DAIFMT_DSP_B: 840 reg_val |= RT5514_I2S_DF_PCM_B; 841 break; 842 843 default: 844 return -EINVAL; 845 } 846 847 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, 848 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK, 849 reg_val); 850 851 return 0; 852 } 853 854 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai, 855 int clk_id, unsigned int freq, int dir) 856 { 857 struct snd_soc_codec *codec = dai->codec; 858 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 859 unsigned int reg_val = 0; 860 861 if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src) 862 return 0; 863 864 switch (clk_id) { 865 case RT5514_SCLK_S_MCLK: 866 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK; 867 break; 868 869 case RT5514_SCLK_S_PLL1: 870 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL; 871 break; 872 873 default: 874 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 875 return -EINVAL; 876 } 877 878 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 879 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val); 880 881 rt5514->sysclk = freq; 882 rt5514->sysclk_src = clk_id; 883 884 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 885 886 return 0; 887 } 888 889 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 890 unsigned int freq_in, unsigned int freq_out) 891 { 892 struct snd_soc_codec *codec = dai->codec; 893 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 894 struct rl6231_pll_code pll_code; 895 int ret; 896 897 if (!freq_in || !freq_out) { 898 dev_dbg(codec->dev, "PLL disabled\n"); 899 900 rt5514->pll_in = 0; 901 rt5514->pll_out = 0; 902 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 903 RT5514_CLK_SYS_PRE_SEL_MASK, 904 RT5514_CLK_SYS_PRE_SEL_MCLK); 905 906 return 0; 907 } 908 909 if (source == rt5514->pll_src && freq_in == rt5514->pll_in && 910 freq_out == rt5514->pll_out) 911 return 0; 912 913 switch (source) { 914 case RT5514_PLL1_S_MCLK: 915 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 916 RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK); 917 break; 918 919 case RT5514_PLL1_S_BCLK: 920 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 921 RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK); 922 break; 923 924 default: 925 dev_err(codec->dev, "Unknown PLL source %d\n", source); 926 return -EINVAL; 927 } 928 929 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 930 if (ret < 0) { 931 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 932 return ret; 933 } 934 935 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 936 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 937 pll_code.n_code, pll_code.k_code); 938 939 regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1, 940 pll_code.k_code << RT5514_PLL_K_SFT | 941 pll_code.n_code << RT5514_PLL_N_SFT | 942 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT); 943 regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2, 944 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT); 945 946 rt5514->pll_in = freq_in; 947 rt5514->pll_out = freq_out; 948 rt5514->pll_src = source; 949 950 return 0; 951 } 952 953 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 954 unsigned int rx_mask, int slots, int slot_width) 955 { 956 struct snd_soc_codec *codec = dai->codec; 957 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 958 unsigned int val = 0, val2 = 0; 959 960 if (rx_mask || tx_mask) 961 val |= RT5514_TDM_MODE; 962 963 switch (tx_mask) { 964 case 0x3: 965 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 | 966 RT5514_TDM_DOCKING_START_SLOT0; 967 break; 968 969 case 0x30: 970 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 | 971 RT5514_TDM_DOCKING_START_SLOT4; 972 break; 973 974 case 0xf: 975 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 | 976 RT5514_TDM_DOCKING_START_SLOT0; 977 break; 978 979 case 0xf0: 980 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 | 981 RT5514_TDM_DOCKING_START_SLOT4; 982 break; 983 984 default: 985 break; 986 } 987 988 989 990 switch (slots) { 991 case 4: 992 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH; 993 break; 994 995 case 6: 996 val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH; 997 break; 998 999 case 8: 1000 val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH; 1001 break; 1002 1003 case 2: 1004 default: 1005 break; 1006 } 1007 1008 switch (slot_width) { 1009 case 20: 1010 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20; 1011 break; 1012 1013 case 24: 1014 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24; 1015 break; 1016 1017 case 25: 1018 val |= RT5514_TDM_MODE2; 1019 break; 1020 1021 case 32: 1022 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32; 1023 break; 1024 1025 case 16: 1026 default: 1027 break; 1028 } 1029 1030 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE | 1031 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK | 1032 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK | 1033 RT5514_TDM_MODE2, val); 1034 1035 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2, 1036 RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK | 1037 RT5514_TDM_DOCKING_START_MASK, val2); 1038 1039 return 0; 1040 } 1041 1042 static int rt5514_set_bias_level(struct snd_soc_codec *codec, 1043 enum snd_soc_bias_level level) 1044 { 1045 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 1046 int ret; 1047 1048 switch (level) { 1049 case SND_SOC_BIAS_PREPARE: 1050 if (IS_ERR(rt5514->mclk)) 1051 break; 1052 1053 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) { 1054 clk_disable_unprepare(rt5514->mclk); 1055 } else { 1056 ret = clk_prepare_enable(rt5514->mclk); 1057 if (ret) 1058 return ret; 1059 } 1060 break; 1061 1062 case SND_SOC_BIAS_STANDBY: 1063 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 1064 /* 1065 * If the DSP is enabled in start of recording, the DSP 1066 * should be disabled, and sync back to normal recording 1067 * settings to make sure recording properly. 1068 */ 1069 if (rt5514->dsp_enabled) { 1070 rt5514->dsp_enabled = 0; 1071 regmap_multi_reg_write(rt5514->i2c_regmap, 1072 rt5514_i2c_patch, 1073 ARRAY_SIZE(rt5514_i2c_patch)); 1074 regcache_mark_dirty(rt5514->regmap); 1075 regcache_sync(rt5514->regmap); 1076 } 1077 } 1078 break; 1079 1080 default: 1081 break; 1082 } 1083 1084 return 0; 1085 } 1086 1087 static int rt5514_probe(struct snd_soc_codec *codec) 1088 { 1089 struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec); 1090 1091 rt5514->mclk = devm_clk_get(codec->dev, "mclk"); 1092 if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER) 1093 return -EPROBE_DEFER; 1094 1095 rt5514->codec = codec; 1096 1097 return 0; 1098 } 1099 1100 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val) 1101 { 1102 struct i2c_client *client = context; 1103 struct rt5514_priv *rt5514 = i2c_get_clientdata(client); 1104 1105 regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); 1106 1107 return 0; 1108 } 1109 1110 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val) 1111 { 1112 struct i2c_client *client = context; 1113 struct rt5514_priv *rt5514 = i2c_get_clientdata(client); 1114 1115 regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); 1116 1117 return 0; 1118 } 1119 1120 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1121 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1122 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1123 1124 static const struct snd_soc_dai_ops rt5514_aif_dai_ops = { 1125 .hw_params = rt5514_hw_params, 1126 .set_fmt = rt5514_set_dai_fmt, 1127 .set_sysclk = rt5514_set_dai_sysclk, 1128 .set_pll = rt5514_set_dai_pll, 1129 .set_tdm_slot = rt5514_set_tdm_slot, 1130 }; 1131 1132 static struct snd_soc_dai_driver rt5514_dai[] = { 1133 { 1134 .name = "rt5514-aif1", 1135 .id = 0, 1136 .capture = { 1137 .stream_name = "AIF1 Capture", 1138 .channels_min = 1, 1139 .channels_max = 4, 1140 .rates = RT5514_STEREO_RATES, 1141 .formats = RT5514_FORMATS, 1142 }, 1143 .ops = &rt5514_aif_dai_ops, 1144 } 1145 }; 1146 1147 static const struct snd_soc_codec_driver soc_codec_dev_rt5514 = { 1148 .probe = rt5514_probe, 1149 .idle_bias_off = true, 1150 .set_bias_level = rt5514_set_bias_level, 1151 .component_driver = { 1152 .controls = rt5514_snd_controls, 1153 .num_controls = ARRAY_SIZE(rt5514_snd_controls), 1154 .dapm_widgets = rt5514_dapm_widgets, 1155 .num_dapm_widgets = ARRAY_SIZE(rt5514_dapm_widgets), 1156 .dapm_routes = rt5514_dapm_routes, 1157 .num_dapm_routes = ARRAY_SIZE(rt5514_dapm_routes), 1158 }, 1159 }; 1160 1161 static const struct regmap_config rt5514_i2c_regmap = { 1162 .name = "i2c", 1163 .reg_bits = 32, 1164 .val_bits = 32, 1165 1166 .readable_reg = rt5514_i2c_readable_register, 1167 1168 .cache_type = REGCACHE_NONE, 1169 }; 1170 1171 static const struct regmap_config rt5514_regmap = { 1172 .reg_bits = 16, 1173 .val_bits = 32, 1174 1175 .max_register = RT5514_VENDOR_ID2, 1176 .volatile_reg = rt5514_volatile_register, 1177 .readable_reg = rt5514_readable_register, 1178 .reg_read = rt5514_i2c_read, 1179 .reg_write = rt5514_i2c_write, 1180 1181 .cache_type = REGCACHE_RBTREE, 1182 .reg_defaults = rt5514_reg, 1183 .num_reg_defaults = ARRAY_SIZE(rt5514_reg), 1184 .use_single_rw = true, 1185 }; 1186 1187 static const struct i2c_device_id rt5514_i2c_id[] = { 1188 { "rt5514", 0 }, 1189 { } 1190 }; 1191 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id); 1192 1193 #if defined(CONFIG_OF) 1194 static const struct of_device_id rt5514_of_match[] = { 1195 { .compatible = "realtek,rt5514", }, 1196 {}, 1197 }; 1198 MODULE_DEVICE_TABLE(of, rt5514_of_match); 1199 #endif 1200 1201 #ifdef CONFIG_ACPI 1202 static const struct acpi_device_id rt5514_acpi_match[] = { 1203 { "10EC5514", 0}, 1204 {}, 1205 }; 1206 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match); 1207 #endif 1208 1209 static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev) 1210 { 1211 device_property_read_u32(dev, "realtek,dmic-init-delay-ms", 1212 &rt5514->pdata.dmic_init_delay); 1213 1214 return 0; 1215 } 1216 1217 static __maybe_unused int rt5514_i2c_resume(struct device *dev) 1218 { 1219 struct rt5514_priv *rt5514 = dev_get_drvdata(dev); 1220 unsigned int val; 1221 1222 /* 1223 * Add a bogus read to avoid rt5514's confusion after s2r in case it 1224 * saw glitches on the i2c lines and thought the other side sent a 1225 * start bit. 1226 */ 1227 regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1228 1229 return 0; 1230 } 1231 1232 static int rt5514_i2c_probe(struct i2c_client *i2c, 1233 const struct i2c_device_id *id) 1234 { 1235 struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev); 1236 struct rt5514_priv *rt5514; 1237 int ret; 1238 unsigned int val = ~0; 1239 1240 rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv), 1241 GFP_KERNEL); 1242 if (rt5514 == NULL) 1243 return -ENOMEM; 1244 1245 i2c_set_clientdata(i2c, rt5514); 1246 1247 if (pdata) 1248 rt5514->pdata = *pdata; 1249 else if (i2c->dev.of_node) 1250 rt5514_parse_dt(rt5514, &i2c->dev); 1251 1252 rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap); 1253 if (IS_ERR(rt5514->i2c_regmap)) { 1254 ret = PTR_ERR(rt5514->i2c_regmap); 1255 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1256 ret); 1257 return ret; 1258 } 1259 1260 rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap); 1261 if (IS_ERR(rt5514->regmap)) { 1262 ret = PTR_ERR(rt5514->regmap); 1263 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1264 ret); 1265 return ret; 1266 } 1267 1268 /* 1269 * The rt5514 can get confused if the i2c lines glitch together, as 1270 * can happen at bootup as regulators are turned off and on. If it's 1271 * in this glitched state the first i2c read will fail, so we'll give 1272 * it one change to retry. 1273 */ 1274 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1275 if (ret || val != RT5514_DEVICE_ID) 1276 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1277 if (ret || val != RT5514_DEVICE_ID) { 1278 dev_err(&i2c->dev, 1279 "Device with ID register %x is not rt5514\n", val); 1280 return -ENODEV; 1281 } 1282 1283 ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch, 1284 ARRAY_SIZE(rt5514_i2c_patch)); 1285 if (ret != 0) 1286 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n", 1287 ret); 1288 1289 ret = regmap_register_patch(rt5514->regmap, rt5514_patch, 1290 ARRAY_SIZE(rt5514_patch)); 1291 if (ret != 0) 1292 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 1293 1294 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5514, 1295 rt5514_dai, ARRAY_SIZE(rt5514_dai)); 1296 } 1297 1298 static int rt5514_i2c_remove(struct i2c_client *i2c) 1299 { 1300 snd_soc_unregister_codec(&i2c->dev); 1301 1302 return 0; 1303 } 1304 1305 static const struct dev_pm_ops rt5514_i2_pm_ops = { 1306 SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume) 1307 }; 1308 1309 static struct i2c_driver rt5514_i2c_driver = { 1310 .driver = { 1311 .name = "rt5514", 1312 .acpi_match_table = ACPI_PTR(rt5514_acpi_match), 1313 .of_match_table = of_match_ptr(rt5514_of_match), 1314 .pm = &rt5514_i2_pm_ops, 1315 }, 1316 .probe = rt5514_i2c_probe, 1317 .remove = rt5514_i2c_remove, 1318 .id_table = rt5514_i2c_id, 1319 }; 1320 module_i2c_driver(rt5514_i2c_driver); 1321 1322 MODULE_DESCRIPTION("ASoC RT5514 driver"); 1323 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 1324 MODULE_LICENSE("GPL v2"); 1325