1 /* 2 * rt5514.c -- RT5514 ALSA SoC audio codec driver 3 * 4 * Copyright 2015 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/acpi.h> 13 #include <linux/fs.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/regmap.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/firmware.h> 23 #include <linux/gpio.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 32 #include "rl6231.h" 33 #include "rt5514.h" 34 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 35 #include "rt5514-spi.h" 36 #endif 37 38 static const struct reg_sequence rt5514_i2c_patch[] = { 39 {0x1800101c, 0x00000000}, 40 {0x18001100, 0x0000031f}, 41 {0x18001104, 0x00000007}, 42 {0x18001108, 0x00000000}, 43 {0x1800110c, 0x00000000}, 44 {0x18001110, 0x00000000}, 45 {0x18001114, 0x00000001}, 46 {0x18001118, 0x00000000}, 47 {0x18002f08, 0x00000006}, 48 {0x18002f00, 0x00055149}, 49 {0x18002f00, 0x0005514b}, 50 {0x18002f00, 0x00055149}, 51 {0xfafafafa, 0x00000001}, 52 {0x18002f10, 0x00000001}, 53 {0x18002f10, 0x00000000}, 54 {0x18002f10, 0x00000001}, 55 {0xfafafafa, 0x00000001}, 56 {0x18002000, 0x000010ec}, 57 {0xfafafafa, 0x00000000}, 58 }; 59 60 static const struct reg_sequence rt5514_patch[] = { 61 {RT5514_DIG_IO_CTRL, 0x00000040}, 62 {RT5514_CLK_CTRL1, 0x38020041}, 63 {RT5514_SRC_CTRL, 0x44000eee}, 64 {RT5514_ANA_CTRL_LDO10, 0x00028604}, 65 {RT5514_ANA_CTRL_ADCFED, 0x00000800}, 66 {RT5514_ASRC_IN_CTRL1, 0x00000003}, 67 {RT5514_DOWNFILTER0_CTRL3, 0x10000342}, 68 {RT5514_DOWNFILTER1_CTRL3, 0x10000342}, 69 }; 70 71 static const struct reg_default rt5514_reg[] = { 72 {RT5514_RESET, 0x00000000}, 73 {RT5514_PWR_ANA1, 0x00808880}, 74 {RT5514_PWR_ANA2, 0x00220000}, 75 {RT5514_I2S_CTRL1, 0x00000330}, 76 {RT5514_I2S_CTRL2, 0x20000000}, 77 {RT5514_VAD_CTRL6, 0xc00007d2}, 78 {RT5514_EXT_VAD_CTRL, 0x80000080}, 79 {RT5514_DIG_IO_CTRL, 0x00000040}, 80 {RT5514_PAD_CTRL1, 0x00804000}, 81 {RT5514_DMIC_DATA_CTRL, 0x00000005}, 82 {RT5514_DIG_SOURCE_CTRL, 0x00000002}, 83 {RT5514_SRC_CTRL, 0x44000eee}, 84 {RT5514_DOWNFILTER2_CTRL1, 0x0000882f}, 85 {RT5514_PLL_SOURCE_CTRL, 0x00000004}, 86 {RT5514_CLK_CTRL1, 0x38020041}, 87 {RT5514_CLK_CTRL2, 0x00000000}, 88 {RT5514_PLL3_CALIB_CTRL1, 0x00400200}, 89 {RT5514_PLL3_CALIB_CTRL5, 0x40220012}, 90 {RT5514_DELAY_BUF_CTRL1, 0x7fff006a}, 91 {RT5514_DELAY_BUF_CTRL3, 0x00000000}, 92 {RT5514_ASRC_IN_CTRL1, 0x00000003}, 93 {RT5514_DOWNFILTER0_CTRL1, 0x00020c2f}, 94 {RT5514_DOWNFILTER0_CTRL2, 0x00020c2f}, 95 {RT5514_DOWNFILTER0_CTRL3, 0x10000342}, 96 {RT5514_DOWNFILTER1_CTRL1, 0x00020c2f}, 97 {RT5514_DOWNFILTER1_CTRL2, 0x00020c2f}, 98 {RT5514_DOWNFILTER1_CTRL3, 0x10000342}, 99 {RT5514_ANA_CTRL_LDO10, 0x00028604}, 100 {RT5514_ANA_CTRL_LDO18_16, 0x02000345}, 101 {RT5514_ANA_CTRL_ADC12, 0x0000a2a8}, 102 {RT5514_ANA_CTRL_ADC21, 0x00001180}, 103 {RT5514_ANA_CTRL_ADC22, 0x0000aaa8}, 104 {RT5514_ANA_CTRL_ADC23, 0x00151427}, 105 {RT5514_ANA_CTRL_MICBST, 0x00002000}, 106 {RT5514_ANA_CTRL_ADCFED, 0x00000800}, 107 {RT5514_ANA_CTRL_INBUF, 0x00000143}, 108 {RT5514_ANA_CTRL_VREF, 0x00008d50}, 109 {RT5514_ANA_CTRL_PLL3, 0x0000000e}, 110 {RT5514_ANA_CTRL_PLL1_1, 0x00000000}, 111 {RT5514_ANA_CTRL_PLL1_2, 0x00030220}, 112 {RT5514_DMIC_LP_CTRL, 0x00000000}, 113 {RT5514_MISC_CTRL_DSP, 0x00000000}, 114 {RT5514_DSP_CTRL1, 0x00055149}, 115 {RT5514_DSP_CTRL3, 0x00000006}, 116 {RT5514_DSP_CTRL4, 0x00000001}, 117 {RT5514_VENDOR_ID1, 0x00000001}, 118 {RT5514_VENDOR_ID2, 0x10ec5514}, 119 }; 120 121 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514) 122 { 123 /* Reset */ 124 regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec); 125 /* LDO_I_limit */ 126 regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604); 127 /* I2C bypass enable */ 128 regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001); 129 /* mini-core reset */ 130 regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b); 131 regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149); 132 /* I2C bypass disable */ 133 regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000); 134 /* PIN config */ 135 regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040); 136 /* PLL3(QN)=RCOSC*(10+2) */ 137 regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a); 138 /* PLL3 source=RCOSC, fsi=rt_clk */ 139 regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b); 140 /* Power on RCOSC, pll3 */ 141 regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81); 142 /* DSP clk source = pll3, ENABLE DSP clk */ 143 regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005); 144 /* Enable DSP clk auto switch */ 145 regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001); 146 /* Reduce DSP power */ 147 regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001); 148 } 149 150 static bool rt5514_volatile_register(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case RT5514_VENDOR_ID1: 154 case RT5514_VENDOR_ID2: 155 return true; 156 157 default: 158 return false; 159 } 160 } 161 162 static bool rt5514_readable_register(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case RT5514_RESET: 166 case RT5514_PWR_ANA1: 167 case RT5514_PWR_ANA2: 168 case RT5514_I2S_CTRL1: 169 case RT5514_I2S_CTRL2: 170 case RT5514_VAD_CTRL6: 171 case RT5514_EXT_VAD_CTRL: 172 case RT5514_DIG_IO_CTRL: 173 case RT5514_PAD_CTRL1: 174 case RT5514_DMIC_DATA_CTRL: 175 case RT5514_DIG_SOURCE_CTRL: 176 case RT5514_SRC_CTRL: 177 case RT5514_DOWNFILTER2_CTRL1: 178 case RT5514_PLL_SOURCE_CTRL: 179 case RT5514_CLK_CTRL1: 180 case RT5514_CLK_CTRL2: 181 case RT5514_PLL3_CALIB_CTRL1: 182 case RT5514_PLL3_CALIB_CTRL5: 183 case RT5514_DELAY_BUF_CTRL1: 184 case RT5514_DELAY_BUF_CTRL3: 185 case RT5514_ASRC_IN_CTRL1: 186 case RT5514_DOWNFILTER0_CTRL1: 187 case RT5514_DOWNFILTER0_CTRL2: 188 case RT5514_DOWNFILTER0_CTRL3: 189 case RT5514_DOWNFILTER1_CTRL1: 190 case RT5514_DOWNFILTER1_CTRL2: 191 case RT5514_DOWNFILTER1_CTRL3: 192 case RT5514_ANA_CTRL_LDO10: 193 case RT5514_ANA_CTRL_LDO18_16: 194 case RT5514_ANA_CTRL_ADC12: 195 case RT5514_ANA_CTRL_ADC21: 196 case RT5514_ANA_CTRL_ADC22: 197 case RT5514_ANA_CTRL_ADC23: 198 case RT5514_ANA_CTRL_MICBST: 199 case RT5514_ANA_CTRL_ADCFED: 200 case RT5514_ANA_CTRL_INBUF: 201 case RT5514_ANA_CTRL_VREF: 202 case RT5514_ANA_CTRL_PLL3: 203 case RT5514_ANA_CTRL_PLL1_1: 204 case RT5514_ANA_CTRL_PLL1_2: 205 case RT5514_DMIC_LP_CTRL: 206 case RT5514_MISC_CTRL_DSP: 207 case RT5514_DSP_CTRL1: 208 case RT5514_DSP_CTRL3: 209 case RT5514_DSP_CTRL4: 210 case RT5514_VENDOR_ID1: 211 case RT5514_VENDOR_ID2: 212 return true; 213 214 default: 215 return false; 216 } 217 } 218 219 static bool rt5514_i2c_readable_register(struct device *dev, 220 unsigned int reg) 221 { 222 switch (reg) { 223 case RT5514_DSP_MAPPING | RT5514_RESET: 224 case RT5514_DSP_MAPPING | RT5514_PWR_ANA1: 225 case RT5514_DSP_MAPPING | RT5514_PWR_ANA2: 226 case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1: 227 case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2: 228 case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6: 229 case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL: 230 case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL: 231 case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1: 232 case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL: 233 case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL: 234 case RT5514_DSP_MAPPING | RT5514_SRC_CTRL: 235 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1: 236 case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL: 237 case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1: 238 case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2: 239 case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1: 240 case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5: 241 case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1: 242 case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3: 243 case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1: 244 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1: 245 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2: 246 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3: 247 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1: 248 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2: 249 case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3: 250 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10: 251 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16: 252 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12: 253 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21: 254 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22: 255 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23: 256 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST: 257 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED: 258 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF: 259 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF: 260 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3: 261 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1: 262 case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2: 263 case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL: 264 case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP: 265 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1: 266 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3: 267 case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4: 268 case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1: 269 case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2: 270 return true; 271 272 default: 273 return false; 274 } 275 } 276 277 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */ 278 static const DECLARE_TLV_DB_RANGE(bst_tlv, 279 0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0), 280 3, 3, TLV_DB_SCALE_ITEM(450, 0, 0), 281 4, 4, TLV_DB_SCALE_ITEM(750, 0, 0), 282 5, 5, TLV_DB_SCALE_ITEM(950, 0, 0), 283 6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0), 284 7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0), 285 8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0) 286 ); 287 288 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 289 290 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol, 291 struct snd_ctl_elem_value *ucontrol) 292 { 293 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 294 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 295 296 ucontrol->value.integer.value[0] = rt5514->dsp_enabled; 297 298 return 0; 299 } 300 301 static int rt5514_calibration(struct rt5514_priv *rt5514, bool on) 302 { 303 if (on) { 304 regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a); 305 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf, 306 0xa); 307 regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 308 0x301); 309 regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4, 310 0x80000000 | rt5514->pll3_cal_value); 311 regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1, 312 0x8bb80800); 313 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5, 314 0xc0000000, 0x80000000); 315 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5, 316 0xc0000000, 0xc0000000); 317 } else { 318 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5, 319 0xc0000000, 0x40000000); 320 regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0); 321 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf, 322 0x4); 323 } 324 325 return 0; 326 } 327 328 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol, 329 struct snd_ctl_elem_value *ucontrol) 330 { 331 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 332 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 333 const struct firmware *fw = NULL; 334 u8 buf[8]; 335 336 if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled) 337 return 0; 338 339 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 340 rt5514->dsp_enabled = ucontrol->value.integer.value[0]; 341 342 if (rt5514->dsp_enabled) { 343 if (rt5514->pdata.dsp_calib_clk_name && 344 !IS_ERR(rt5514->dsp_calib_clk)) { 345 if (clk_set_rate(rt5514->dsp_calib_clk, 346 rt5514->pdata.dsp_calib_clk_rate)) 347 dev_err(component->dev, 348 "Can't set rate for mclk"); 349 350 if (clk_prepare_enable(rt5514->dsp_calib_clk)) 351 dev_err(component->dev, 352 "Can't enable dsp_calib_clk"); 353 354 rt5514_calibration(rt5514, true); 355 356 msleep(20); 357 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 358 rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 | 359 RT5514_DSP_MAPPING, buf, sizeof(buf)); 360 #else 361 dev_err(component->dev, "There is no SPI driver for" 362 " loading the firmware\n"); 363 memset(buf, 0, sizeof(buf)); 364 #endif 365 rt5514->pll3_cal_value = buf[0] | buf[1] << 8 | 366 buf[2] << 16 | buf[3] << 24; 367 368 rt5514_calibration(rt5514, false); 369 clk_disable_unprepare(rt5514->dsp_calib_clk); 370 } 371 372 rt5514_enable_dsp_prepare(rt5514); 373 374 request_firmware(&fw, RT5514_FIRMWARE1, component->dev); 375 if (fw) { 376 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 377 rt5514_spi_burst_write(0x4ff60000, fw->data, 378 ((fw->size/8)+1)*8); 379 #else 380 dev_err(component->dev, "There is no SPI driver for" 381 " loading the firmware\n"); 382 #endif 383 release_firmware(fw); 384 fw = NULL; 385 } 386 387 request_firmware(&fw, RT5514_FIRMWARE2, component->dev); 388 if (fw) { 389 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI) 390 rt5514_spi_burst_write(0x4ffc0000, fw->data, 391 ((fw->size/8)+1)*8); 392 #else 393 dev_err(component->dev, "There is no SPI driver for" 394 " loading the firmware\n"); 395 #endif 396 release_firmware(fw); 397 fw = NULL; 398 } 399 400 /* DSP run */ 401 regmap_write(rt5514->i2c_regmap, 0x18002f00, 402 0x00055148); 403 404 if (rt5514->pdata.dsp_calib_clk_name && 405 !IS_ERR(rt5514->dsp_calib_clk)) { 406 msleep(20); 407 408 regmap_write(rt5514->i2c_regmap, 0x1800211c, 409 rt5514->pll3_cal_value); 410 regmap_write(rt5514->i2c_regmap, 0x18002124, 411 0x00220012); 412 regmap_write(rt5514->i2c_regmap, 0x18002124, 413 0x80220042); 414 regmap_write(rt5514->i2c_regmap, 0x18002124, 415 0xe0220042); 416 } 417 } else { 418 regmap_multi_reg_write(rt5514->i2c_regmap, 419 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch)); 420 regcache_mark_dirty(rt5514->regmap); 421 regcache_sync(rt5514->regmap); 422 } 423 } 424 425 return 0; 426 } 427 428 static const struct snd_kcontrol_new rt5514_snd_controls[] = { 429 SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST, 430 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv), 431 SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1, 432 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0, 433 adc_vol_tlv), 434 SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1, 435 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0, 436 adc_vol_tlv), 437 SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0, 438 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put), 439 }; 440 441 /* ADC Mixer*/ 442 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = { 443 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1, 444 RT5514_AD_DMIC_MIX_BIT, 1, 1), 445 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1, 446 RT5514_AD_AD_MIX_BIT, 1, 1), 447 }; 448 449 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = { 450 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2, 451 RT5514_AD_DMIC_MIX_BIT, 1, 1), 452 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2, 453 RT5514_AD_AD_MIX_BIT, 1, 1), 454 }; 455 456 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = { 457 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1, 458 RT5514_AD_DMIC_MIX_BIT, 1, 1), 459 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1, 460 RT5514_AD_AD_MIX_BIT, 1, 1), 461 }; 462 463 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = { 464 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2, 465 RT5514_AD_DMIC_MIX_BIT, 1, 1), 466 SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2, 467 RT5514_AD_AD_MIX_BIT, 1, 1), 468 }; 469 470 /* DMIC Source */ 471 static const char * const rt5514_dmic_src[] = { 472 "DMIC1", "DMIC2" 473 }; 474 475 static SOC_ENUM_SINGLE_DECL( 476 rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL, 477 RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src); 478 479 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux = 480 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum); 481 482 static SOC_ENUM_SINGLE_DECL( 483 rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL, 484 RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src); 485 486 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux = 487 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum); 488 489 /** 490 * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic. 491 * 492 * @component: only used for dev_warn 493 * @rate: base clock rate. 494 * 495 * Choose divider parameter that gives the highest possible DMIC frequency in 496 * 1MHz - 3MHz range. 497 */ 498 static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate) 499 { 500 int div[] = {2, 3, 4, 8, 12, 16, 24, 32}; 501 int i; 502 503 if (rate < 1000000 * div[0]) { 504 pr_warn("Base clock rate %d is too low\n", rate); 505 return -EINVAL; 506 } 507 508 for (i = 0; i < ARRAY_SIZE(div); i++) { 509 /* find divider that gives DMIC frequency below 3.072MHz */ 510 if (3072000 * div[i] >= rate) 511 return i; 512 } 513 514 dev_warn(component->dev, "Base clock rate %d is too high\n", rate); 515 return -EINVAL; 516 } 517 518 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w, 519 struct snd_kcontrol *kcontrol, int event) 520 { 521 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 522 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 523 int idx; 524 525 idx = rt5514_calc_dmic_clk(component, rt5514->sysclk); 526 if (idx < 0) 527 dev_err(component->dev, "Failed to set DMIC clock\n"); 528 else 529 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1, 530 RT5514_CLK_DMIC_OUT_SEL_MASK, 531 idx << RT5514_CLK_DMIC_OUT_SEL_SFT); 532 533 if (rt5514->pdata.dmic_init_delay) 534 msleep(rt5514->pdata.dmic_init_delay); 535 536 return idx; 537 } 538 539 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 540 struct snd_soc_dapm_widget *sink) 541 { 542 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 543 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 544 545 if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1) 546 return 1; 547 else 548 return 0; 549 } 550 551 static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source, 552 struct snd_soc_dapm_widget *sink) 553 { 554 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 555 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 556 557 return (rt5514->sysclk > rt5514->lrck * 384); 558 } 559 560 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = { 561 /* Input Lines */ 562 SND_SOC_DAPM_INPUT("DMIC1L"), 563 SND_SOC_DAPM_INPUT("DMIC1R"), 564 SND_SOC_DAPM_INPUT("DMIC2L"), 565 SND_SOC_DAPM_INPUT("DMIC2R"), 566 567 SND_SOC_DAPM_INPUT("AMICL"), 568 SND_SOC_DAPM_INPUT("AMICR"), 569 570 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 571 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 572 573 SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0, 574 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 575 576 SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1, 577 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0), 578 579 SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1, 580 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0), 581 SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1, 582 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0), 583 SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0, 584 NULL, 0), 585 SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1, 586 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0), 587 SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1, 588 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0), 589 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2, 590 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0), 591 SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0, 592 NULL, 0), 593 SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0, 594 NULL, 0), 595 SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0, 596 NULL, 0), 597 SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0), 598 599 600 SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0, 601 NULL, 0), 602 SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0, 603 NULL, 0), 604 SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0, 605 NULL, 0), 606 SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0, 607 NULL, 0), 608 SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT, 609 0, NULL, 0), 610 SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0), 611 612 SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0, 613 NULL, 0), 614 SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0, 615 NULL, 0), 616 SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0, 617 NULL, 0), 618 SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0, 619 NULL, 0), 620 SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT, 621 0, NULL, 0), 622 SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0), 623 624 SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2, 625 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0), 626 SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2, 627 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0), 628 SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0, 629 NULL, 0), 630 SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2, 631 RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0), 632 SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2, 633 RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0), 634 635 /* ADC Mux */ 636 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 637 &rt5514_sto1_dmic_mux), 638 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 639 &rt5514_sto2_dmic_mux), 640 641 /* ADC Mixer */ 642 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1, 643 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0), 644 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1, 645 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0), 646 647 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 648 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)), 649 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 650 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)), 651 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 652 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)), 653 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 654 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)), 655 656 SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1, 657 RT5514_AD_AD_MUTE_BIT, 1), 658 SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2, 659 RT5514_AD_AD_MUTE_BIT, 1), 660 SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1, 661 RT5514_AD_AD_MUTE_BIT, 1), 662 SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2, 663 RT5514_AD_AD_MUTE_BIT, 1), 664 665 /* ADC PGA */ 666 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 667 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 668 669 /* Audio Interface */ 670 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 671 }; 672 673 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = { 674 { "DMIC1", NULL, "DMIC1L" }, 675 { "DMIC1", NULL, "DMIC1R" }, 676 { "DMIC2", NULL, "DMIC2L" }, 677 { "DMIC2", NULL, "DMIC2R" }, 678 679 { "DMIC1L", NULL, "DMIC CLK" }, 680 { "DMIC1R", NULL, "DMIC CLK" }, 681 { "DMIC2L", NULL, "DMIC CLK" }, 682 { "DMIC2R", NULL, "DMIC CLK" }, 683 684 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 685 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 686 687 { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" }, 688 { "Sto1 ADC MIXL", "ADC Switch", "AMICL" }, 689 { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" }, 690 { "Sto1 ADC MIXR", "ADC Switch", "AMICR" }, 691 692 { "ADC Power", NULL, "LDO18 IN" }, 693 { "ADC Power", NULL, "LDO18 ADC" }, 694 { "ADC Power", NULL, "LDO21" }, 695 { "ADC Power", NULL, "BG LDO18 IN" }, 696 { "ADC Power", NULL, "BG LDO21" }, 697 { "ADC Power", NULL, "BG MBIAS" }, 698 { "ADC Power", NULL, "MBIAS" }, 699 { "ADC Power", NULL, "VREF2" }, 700 { "ADC Power", NULL, "VREF1" }, 701 702 { "ADCL Power", NULL, "LDO16L" }, 703 { "ADCL Power", NULL, "ADC1L" }, 704 { "ADCL Power", NULL, "BSTL2" }, 705 { "ADCL Power", NULL, "BSTL" }, 706 { "ADCL Power", NULL, "ADCFEDL" }, 707 708 { "ADCR Power", NULL, "LDO16R" }, 709 { "ADCR Power", NULL, "ADC1R" }, 710 { "ADCR Power", NULL, "BSTR2" }, 711 { "ADCR Power", NULL, "BSTR" }, 712 { "ADCR Power", NULL, "ADCFEDR" }, 713 714 { "AMICL", NULL, "ADC CLK" }, 715 { "AMICL", NULL, "ADC Power" }, 716 { "AMICL", NULL, "ADCL Power" }, 717 { "AMICR", NULL, "ADC CLK" }, 718 { "AMICR", NULL, "ADC Power" }, 719 { "AMICR", NULL, "ADCR Power" }, 720 721 { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" }, 722 { "PLL1", NULL, "PLL1 LDO" }, 723 724 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 725 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 726 727 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 728 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 729 { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" }, 730 { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll }, 731 { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc }, 732 733 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 734 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 735 736 { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" }, 737 { "Sto2 ADC MIXL", "ADC Switch", "AMICL" }, 738 { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" }, 739 { "Sto2 ADC MIXR", "ADC Switch", "AMICR" }, 740 741 { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" }, 742 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 743 744 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 745 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 746 { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" }, 747 { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll }, 748 { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc }, 749 750 { "AIF1TX", NULL, "Stereo1 ADC MIX"}, 751 { "AIF1TX", NULL, "Stereo2 ADC MIX"}, 752 }; 753 754 static int rt5514_hw_params(struct snd_pcm_substream *substream, 755 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 756 { 757 struct snd_soc_component *component = dai->component; 758 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 759 int pre_div, bclk_ms, frame_size; 760 unsigned int val_len = 0; 761 762 rt5514->lrck = params_rate(params); 763 pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck); 764 if (pre_div < 0) { 765 dev_err(component->dev, "Unsupported clock setting\n"); 766 return -EINVAL; 767 } 768 769 frame_size = snd_soc_params_to_frame_size(params); 770 if (frame_size < 0) { 771 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 772 return -EINVAL; 773 } 774 775 bclk_ms = frame_size > 32; 776 rt5514->bclk = rt5514->lrck * (32 << bclk_ms); 777 778 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 779 rt5514->bclk, rt5514->lrck); 780 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 781 bclk_ms, pre_div, dai->id); 782 783 switch (params_format(params)) { 784 case SNDRV_PCM_FORMAT_S16_LE: 785 break; 786 case SNDRV_PCM_FORMAT_S20_3LE: 787 val_len = RT5514_I2S_DL_20; 788 break; 789 case SNDRV_PCM_FORMAT_S24_LE: 790 val_len = RT5514_I2S_DL_24; 791 break; 792 case SNDRV_PCM_FORMAT_S8: 793 val_len = RT5514_I2S_DL_8; 794 break; 795 default: 796 return -EINVAL; 797 } 798 799 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK, 800 val_len); 801 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1, 802 RT5514_CLK_AD_ANA1_SEL_MASK, 803 (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT); 804 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 805 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK, 806 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT | 807 pre_div << RT5514_SEL_ADC_OSR_SFT); 808 809 return 0; 810 } 811 812 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 813 { 814 struct snd_soc_component *component = dai->component; 815 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 816 unsigned int reg_val = 0; 817 818 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 819 case SND_SOC_DAIFMT_NB_NF: 820 break; 821 822 case SND_SOC_DAIFMT_NB_IF: 823 reg_val |= RT5514_I2S_LR_INV; 824 break; 825 826 case SND_SOC_DAIFMT_IB_NF: 827 reg_val |= RT5514_I2S_BP_INV; 828 break; 829 830 case SND_SOC_DAIFMT_IB_IF: 831 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV; 832 break; 833 834 default: 835 return -EINVAL; 836 } 837 838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 839 case SND_SOC_DAIFMT_I2S: 840 break; 841 842 case SND_SOC_DAIFMT_LEFT_J: 843 reg_val |= RT5514_I2S_DF_LEFT; 844 break; 845 846 case SND_SOC_DAIFMT_DSP_A: 847 reg_val |= RT5514_I2S_DF_PCM_A; 848 break; 849 850 case SND_SOC_DAIFMT_DSP_B: 851 reg_val |= RT5514_I2S_DF_PCM_B; 852 break; 853 854 default: 855 return -EINVAL; 856 } 857 858 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, 859 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK, 860 reg_val); 861 862 return 0; 863 } 864 865 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai, 866 int clk_id, unsigned int freq, int dir) 867 { 868 struct snd_soc_component *component = dai->component; 869 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 870 unsigned int reg_val = 0; 871 872 if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src) 873 return 0; 874 875 switch (clk_id) { 876 case RT5514_SCLK_S_MCLK: 877 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK; 878 break; 879 880 case RT5514_SCLK_S_PLL1: 881 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL; 882 break; 883 884 default: 885 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 886 return -EINVAL; 887 } 888 889 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 890 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val); 891 892 rt5514->sysclk = freq; 893 rt5514->sysclk_src = clk_id; 894 895 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 896 897 return 0; 898 } 899 900 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 901 unsigned int freq_in, unsigned int freq_out) 902 { 903 struct snd_soc_component *component = dai->component; 904 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 905 struct rl6231_pll_code pll_code; 906 int ret; 907 908 if (!freq_in || !freq_out) { 909 dev_dbg(component->dev, "PLL disabled\n"); 910 911 rt5514->pll_in = 0; 912 rt5514->pll_out = 0; 913 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2, 914 RT5514_CLK_SYS_PRE_SEL_MASK, 915 RT5514_CLK_SYS_PRE_SEL_MCLK); 916 917 return 0; 918 } 919 920 if (source == rt5514->pll_src && freq_in == rt5514->pll_in && 921 freq_out == rt5514->pll_out) 922 return 0; 923 924 switch (source) { 925 case RT5514_PLL1_S_MCLK: 926 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 927 RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK); 928 break; 929 930 case RT5514_PLL1_S_BCLK: 931 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 932 RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK); 933 break; 934 935 default: 936 dev_err(component->dev, "Unknown PLL source %d\n", source); 937 return -EINVAL; 938 } 939 940 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 941 if (ret < 0) { 942 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 943 return ret; 944 } 945 946 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 947 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 948 pll_code.n_code, pll_code.k_code); 949 950 regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1, 951 pll_code.k_code << RT5514_PLL_K_SFT | 952 pll_code.n_code << RT5514_PLL_N_SFT | 953 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT); 954 regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2, 955 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT); 956 957 rt5514->pll_in = freq_in; 958 rt5514->pll_out = freq_out; 959 rt5514->pll_src = source; 960 961 return 0; 962 } 963 964 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 965 unsigned int rx_mask, int slots, int slot_width) 966 { 967 struct snd_soc_component *component = dai->component; 968 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 969 unsigned int val = 0, val2 = 0; 970 971 if (rx_mask || tx_mask) 972 val |= RT5514_TDM_MODE; 973 974 switch (tx_mask) { 975 case 0x3: 976 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 | 977 RT5514_TDM_DOCKING_START_SLOT0; 978 break; 979 980 case 0x30: 981 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 | 982 RT5514_TDM_DOCKING_START_SLOT4; 983 break; 984 985 case 0xf: 986 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 | 987 RT5514_TDM_DOCKING_START_SLOT0; 988 break; 989 990 case 0xf0: 991 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 | 992 RT5514_TDM_DOCKING_START_SLOT4; 993 break; 994 995 default: 996 break; 997 } 998 999 1000 1001 switch (slots) { 1002 case 4: 1003 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH; 1004 break; 1005 1006 case 6: 1007 val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH; 1008 break; 1009 1010 case 8: 1011 val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH; 1012 break; 1013 1014 case 2: 1015 default: 1016 break; 1017 } 1018 1019 switch (slot_width) { 1020 case 20: 1021 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20; 1022 break; 1023 1024 case 24: 1025 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24; 1026 break; 1027 1028 case 25: 1029 val |= RT5514_TDM_MODE2; 1030 break; 1031 1032 case 32: 1033 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32; 1034 break; 1035 1036 case 16: 1037 default: 1038 break; 1039 } 1040 1041 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE | 1042 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK | 1043 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK | 1044 RT5514_TDM_MODE2, val); 1045 1046 regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2, 1047 RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK | 1048 RT5514_TDM_DOCKING_START_MASK, val2); 1049 1050 return 0; 1051 } 1052 1053 static int rt5514_set_bias_level(struct snd_soc_component *component, 1054 enum snd_soc_bias_level level) 1055 { 1056 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 1057 int ret; 1058 1059 switch (level) { 1060 case SND_SOC_BIAS_PREPARE: 1061 if (IS_ERR(rt5514->mclk)) 1062 break; 1063 1064 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { 1065 clk_disable_unprepare(rt5514->mclk); 1066 } else { 1067 ret = clk_prepare_enable(rt5514->mclk); 1068 if (ret) 1069 return ret; 1070 } 1071 break; 1072 1073 case SND_SOC_BIAS_STANDBY: 1074 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1075 /* 1076 * If the DSP is enabled in start of recording, the DSP 1077 * should be disabled, and sync back to normal recording 1078 * settings to make sure recording properly. 1079 */ 1080 if (rt5514->dsp_enabled) { 1081 rt5514->dsp_enabled = 0; 1082 regmap_multi_reg_write(rt5514->i2c_regmap, 1083 rt5514_i2c_patch, 1084 ARRAY_SIZE(rt5514_i2c_patch)); 1085 regcache_mark_dirty(rt5514->regmap); 1086 regcache_sync(rt5514->regmap); 1087 } 1088 } 1089 break; 1090 1091 default: 1092 break; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int rt5514_probe(struct snd_soc_component *component) 1099 { 1100 struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component); 1101 struct platform_device *pdev = container_of(component->dev, 1102 struct platform_device, dev); 1103 1104 rt5514->mclk = devm_clk_get(component->dev, "mclk"); 1105 if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER) 1106 return -EPROBE_DEFER; 1107 1108 if (rt5514->pdata.dsp_calib_clk_name) { 1109 rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev, 1110 rt5514->pdata.dsp_calib_clk_name); 1111 if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER) 1112 return -EPROBE_DEFER; 1113 } 1114 1115 rt5514->component = component; 1116 rt5514->pll3_cal_value = 0x0078b000; 1117 1118 return 0; 1119 } 1120 1121 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val) 1122 { 1123 struct i2c_client *client = context; 1124 struct rt5514_priv *rt5514 = i2c_get_clientdata(client); 1125 1126 regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); 1127 1128 return 0; 1129 } 1130 1131 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val) 1132 { 1133 struct i2c_client *client = context; 1134 struct rt5514_priv *rt5514 = i2c_get_clientdata(client); 1135 1136 regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); 1137 1138 return 0; 1139 } 1140 1141 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1142 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1143 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1144 1145 static const struct snd_soc_dai_ops rt5514_aif_dai_ops = { 1146 .hw_params = rt5514_hw_params, 1147 .set_fmt = rt5514_set_dai_fmt, 1148 .set_sysclk = rt5514_set_dai_sysclk, 1149 .set_pll = rt5514_set_dai_pll, 1150 .set_tdm_slot = rt5514_set_tdm_slot, 1151 }; 1152 1153 static struct snd_soc_dai_driver rt5514_dai[] = { 1154 { 1155 .name = "rt5514-aif1", 1156 .id = 0, 1157 .capture = { 1158 .stream_name = "AIF1 Capture", 1159 .channels_min = 1, 1160 .channels_max = 4, 1161 .rates = RT5514_STEREO_RATES, 1162 .formats = RT5514_FORMATS, 1163 }, 1164 .ops = &rt5514_aif_dai_ops, 1165 } 1166 }; 1167 1168 static const struct snd_soc_component_driver soc_component_dev_rt5514 = { 1169 .probe = rt5514_probe, 1170 .set_bias_level = rt5514_set_bias_level, 1171 .controls = rt5514_snd_controls, 1172 .num_controls = ARRAY_SIZE(rt5514_snd_controls), 1173 .dapm_widgets = rt5514_dapm_widgets, 1174 .num_dapm_widgets = ARRAY_SIZE(rt5514_dapm_widgets), 1175 .dapm_routes = rt5514_dapm_routes, 1176 .num_dapm_routes = ARRAY_SIZE(rt5514_dapm_routes), 1177 .use_pmdown_time = 1, 1178 .endianness = 1, 1179 .non_legacy_dai_naming = 1, 1180 }; 1181 1182 static const struct regmap_config rt5514_i2c_regmap = { 1183 .name = "i2c", 1184 .reg_bits = 32, 1185 .val_bits = 32, 1186 1187 .readable_reg = rt5514_i2c_readable_register, 1188 1189 .cache_type = REGCACHE_NONE, 1190 }; 1191 1192 static const struct regmap_config rt5514_regmap = { 1193 .reg_bits = 16, 1194 .val_bits = 32, 1195 1196 .max_register = RT5514_VENDOR_ID2, 1197 .volatile_reg = rt5514_volatile_register, 1198 .readable_reg = rt5514_readable_register, 1199 .reg_read = rt5514_i2c_read, 1200 .reg_write = rt5514_i2c_write, 1201 1202 .cache_type = REGCACHE_RBTREE, 1203 .reg_defaults = rt5514_reg, 1204 .num_reg_defaults = ARRAY_SIZE(rt5514_reg), 1205 .use_single_read = true, 1206 .use_single_write = true, 1207 }; 1208 1209 static const struct i2c_device_id rt5514_i2c_id[] = { 1210 { "rt5514", 0 }, 1211 { } 1212 }; 1213 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id); 1214 1215 #if defined(CONFIG_OF) 1216 static const struct of_device_id rt5514_of_match[] = { 1217 { .compatible = "realtek,rt5514", }, 1218 {}, 1219 }; 1220 MODULE_DEVICE_TABLE(of, rt5514_of_match); 1221 #endif 1222 1223 #ifdef CONFIG_ACPI 1224 static const struct acpi_device_id rt5514_acpi_match[] = { 1225 { "10EC5514", 0}, 1226 {}, 1227 }; 1228 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match); 1229 #endif 1230 1231 static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev) 1232 { 1233 device_property_read_u32(dev, "realtek,dmic-init-delay-ms", 1234 &rt5514->pdata.dmic_init_delay); 1235 device_property_read_string(dev, "realtek,dsp-calib-clk-name", 1236 &rt5514->pdata.dsp_calib_clk_name); 1237 device_property_read_u32(dev, "realtek,dsp-calib-clk-rate", 1238 &rt5514->pdata.dsp_calib_clk_rate); 1239 1240 return 0; 1241 } 1242 1243 static __maybe_unused int rt5514_i2c_resume(struct device *dev) 1244 { 1245 struct rt5514_priv *rt5514 = dev_get_drvdata(dev); 1246 unsigned int val; 1247 1248 /* 1249 * Add a bogus read to avoid rt5514's confusion after s2r in case it 1250 * saw glitches on the i2c lines and thought the other side sent a 1251 * start bit. 1252 */ 1253 regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1254 1255 return 0; 1256 } 1257 1258 static int rt5514_i2c_probe(struct i2c_client *i2c, 1259 const struct i2c_device_id *id) 1260 { 1261 struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev); 1262 struct rt5514_priv *rt5514; 1263 int ret; 1264 unsigned int val = ~0; 1265 1266 rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv), 1267 GFP_KERNEL); 1268 if (rt5514 == NULL) 1269 return -ENOMEM; 1270 1271 i2c_set_clientdata(i2c, rt5514); 1272 1273 if (pdata) 1274 rt5514->pdata = *pdata; 1275 else 1276 rt5514_parse_dp(rt5514, &i2c->dev); 1277 1278 rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap); 1279 if (IS_ERR(rt5514->i2c_regmap)) { 1280 ret = PTR_ERR(rt5514->i2c_regmap); 1281 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1282 ret); 1283 return ret; 1284 } 1285 1286 rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap); 1287 if (IS_ERR(rt5514->regmap)) { 1288 ret = PTR_ERR(rt5514->regmap); 1289 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1290 ret); 1291 return ret; 1292 } 1293 1294 /* 1295 * The rt5514 can get confused if the i2c lines glitch together, as 1296 * can happen at bootup as regulators are turned off and on. If it's 1297 * in this glitched state the first i2c read will fail, so we'll give 1298 * it one change to retry. 1299 */ 1300 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1301 if (ret || val != RT5514_DEVICE_ID) 1302 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); 1303 if (ret || val != RT5514_DEVICE_ID) { 1304 dev_err(&i2c->dev, 1305 "Device with ID register %x is not rt5514\n", val); 1306 return -ENODEV; 1307 } 1308 1309 ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch, 1310 ARRAY_SIZE(rt5514_i2c_patch)); 1311 if (ret != 0) 1312 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n", 1313 ret); 1314 1315 ret = regmap_register_patch(rt5514->regmap, rt5514_patch, 1316 ARRAY_SIZE(rt5514_patch)); 1317 if (ret != 0) 1318 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 1319 1320 return devm_snd_soc_register_component(&i2c->dev, 1321 &soc_component_dev_rt5514, 1322 rt5514_dai, ARRAY_SIZE(rt5514_dai)); 1323 } 1324 1325 static const struct dev_pm_ops rt5514_i2_pm_ops = { 1326 SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume) 1327 }; 1328 1329 static struct i2c_driver rt5514_i2c_driver = { 1330 .driver = { 1331 .name = "rt5514", 1332 .acpi_match_table = ACPI_PTR(rt5514_acpi_match), 1333 .of_match_table = of_match_ptr(rt5514_of_match), 1334 .pm = &rt5514_i2_pm_ops, 1335 }, 1336 .probe = rt5514_i2c_probe, 1337 .id_table = rt5514_i2c_id, 1338 }; 1339 module_i2c_driver(rt5514_i2c_driver); 1340 1341 MODULE_DESCRIPTION("ASoC RT5514 driver"); 1342 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 1343 MODULE_LICENSE("GPL v2"); 1344