1 /* 2 * rt298.c -- RT298 ALSA SoC audio codec driver 3 * 4 * Copyright 2015 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dmi.h> 21 #include <linux/acpi.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/jack.h> 30 #include <linux/workqueue.h> 31 #include <sound/rt298.h> 32 33 #include "rl6347a.h" 34 #include "rt298.h" 35 36 #define RT298_VENDOR_ID 0x10ec0298 37 38 struct rt298_priv { 39 struct reg_default *index_cache; 40 int index_cache_size; 41 struct regmap *regmap; 42 struct snd_soc_component *component; 43 struct rt298_platform_data pdata; 44 struct i2c_client *i2c; 45 struct snd_soc_jack *jack; 46 struct delayed_work jack_detect_work; 47 int sys_clk; 48 int clk_id; 49 int is_hp_in; 50 }; 51 52 static const struct reg_default rt298_index_def[] = { 53 { 0x01, 0xa5a8 }, 54 { 0x02, 0x8e95 }, 55 { 0x03, 0x0002 }, 56 { 0x04, 0xaf67 }, 57 { 0x08, 0x200f }, 58 { 0x09, 0xd010 }, 59 { 0x0a, 0x0100 }, 60 { 0x0b, 0x0000 }, 61 { 0x0d, 0x2800 }, 62 { 0x0f, 0x0022 }, 63 { 0x19, 0x0217 }, 64 { 0x20, 0x0020 }, 65 { 0x33, 0x0208 }, 66 { 0x46, 0x0300 }, 67 { 0x49, 0x4004 }, 68 { 0x4f, 0x50c9 }, 69 { 0x50, 0x3000 }, 70 { 0x63, 0x1b02 }, 71 { 0x67, 0x1111 }, 72 { 0x68, 0x1016 }, 73 { 0x69, 0x273f }, 74 }; 75 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def) 76 77 static const struct reg_default rt298_reg[] = { 78 { 0x00170500, 0x00000400 }, 79 { 0x00220000, 0x00000031 }, 80 { 0x00239000, 0x0000007f }, 81 { 0x0023a000, 0x0000007f }, 82 { 0x00270500, 0x00000400 }, 83 { 0x00370500, 0x00000400 }, 84 { 0x00870500, 0x00000400 }, 85 { 0x00920000, 0x00000031 }, 86 { 0x00935000, 0x000000c3 }, 87 { 0x00936000, 0x000000c3 }, 88 { 0x00970500, 0x00000400 }, 89 { 0x00b37000, 0x00000097 }, 90 { 0x00b37200, 0x00000097 }, 91 { 0x00b37300, 0x00000097 }, 92 { 0x00c37000, 0x00000000 }, 93 { 0x00c37100, 0x00000080 }, 94 { 0x01270500, 0x00000400 }, 95 { 0x01370500, 0x00000400 }, 96 { 0x01371f00, 0x411111f0 }, 97 { 0x01439000, 0x00000080 }, 98 { 0x0143a000, 0x00000080 }, 99 { 0x01470700, 0x00000000 }, 100 { 0x01470500, 0x00000400 }, 101 { 0x01470c00, 0x00000000 }, 102 { 0x01470100, 0x00000000 }, 103 { 0x01837000, 0x00000000 }, 104 { 0x01870500, 0x00000400 }, 105 { 0x02050000, 0x00000000 }, 106 { 0x02139000, 0x00000080 }, 107 { 0x0213a000, 0x00000080 }, 108 { 0x02170100, 0x00000000 }, 109 { 0x02170500, 0x00000400 }, 110 { 0x02170700, 0x00000000 }, 111 { 0x02270100, 0x00000000 }, 112 { 0x02370100, 0x00000000 }, 113 { 0x01870700, 0x00000020 }, 114 { 0x00830000, 0x000000c3 }, 115 { 0x00930000, 0x000000c3 }, 116 { 0x01270700, 0x00000000 }, 117 }; 118 119 static bool rt298_volatile_register(struct device *dev, unsigned int reg) 120 { 121 switch (reg) { 122 case 0 ... 0xff: 123 case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 124 case RT298_GET_HP_SENSE: 125 case RT298_GET_MIC1_SENSE: 126 case RT298_PROC_COEF: 127 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): 128 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): 129 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): 130 return true; 131 default: 132 return false; 133 } 134 135 136 } 137 138 static bool rt298_readable_register(struct device *dev, unsigned int reg) 139 { 140 switch (reg) { 141 case 0 ... 0xff: 142 case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 143 case RT298_GET_HP_SENSE: 144 case RT298_GET_MIC1_SENSE: 145 case RT298_SET_AUDIO_POWER: 146 case RT298_SET_HPO_POWER: 147 case RT298_SET_SPK_POWER: 148 case RT298_SET_DMIC1_POWER: 149 case RT298_SPK_MUX: 150 case RT298_HPO_MUX: 151 case RT298_ADC0_MUX: 152 case RT298_ADC1_MUX: 153 case RT298_SET_MIC1: 154 case RT298_SET_PIN_HPO: 155 case RT298_SET_PIN_SPK: 156 case RT298_SET_PIN_DMIC1: 157 case RT298_SPK_EAPD: 158 case RT298_SET_AMP_GAIN_HPO: 159 case RT298_SET_DMIC2_DEFAULT: 160 case RT298_DACL_GAIN: 161 case RT298_DACR_GAIN: 162 case RT298_ADCL_GAIN: 163 case RT298_ADCR_GAIN: 164 case RT298_MIC_GAIN: 165 case RT298_SPOL_GAIN: 166 case RT298_SPOR_GAIN: 167 case RT298_HPOL_GAIN: 168 case RT298_HPOR_GAIN: 169 case RT298_F_DAC_SWITCH: 170 case RT298_F_RECMIX_SWITCH: 171 case RT298_REC_MIC_SWITCH: 172 case RT298_REC_I2S_SWITCH: 173 case RT298_REC_LINE_SWITCH: 174 case RT298_REC_BEEP_SWITCH: 175 case RT298_DAC_FORMAT: 176 case RT298_ADC_FORMAT: 177 case RT298_COEF_INDEX: 178 case RT298_PROC_COEF: 179 case RT298_SET_AMP_GAIN_ADC_IN1: 180 case RT298_SET_AMP_GAIN_ADC_IN2: 181 case RT298_SET_POWER(RT298_DAC_OUT1): 182 case RT298_SET_POWER(RT298_DAC_OUT2): 183 case RT298_SET_POWER(RT298_ADC_IN1): 184 case RT298_SET_POWER(RT298_ADC_IN2): 185 case RT298_SET_POWER(RT298_DMIC2): 186 case RT298_SET_POWER(RT298_MIC1): 187 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): 188 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): 189 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): 190 return true; 191 default: 192 return false; 193 } 194 } 195 196 #ifdef CONFIG_PM 197 static void rt298_index_sync(struct snd_soc_component *component) 198 { 199 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 200 int i; 201 202 for (i = 0; i < INDEX_CACHE_SIZE; i++) { 203 snd_soc_component_write(component, rt298->index_cache[i].reg, 204 rt298->index_cache[i].def); 205 } 206 } 207 #endif 208 209 static int rt298_support_power_controls[] = { 210 RT298_DAC_OUT1, 211 RT298_DAC_OUT2, 212 RT298_ADC_IN1, 213 RT298_ADC_IN2, 214 RT298_MIC1, 215 RT298_DMIC1, 216 RT298_DMIC2, 217 RT298_SPK_OUT, 218 RT298_HP_OUT, 219 }; 220 #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls) 221 222 static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic) 223 { 224 struct snd_soc_dapm_context *dapm; 225 unsigned int val, buf; 226 227 *hp = false; 228 *mic = false; 229 230 if (!rt298->component) 231 return -EINVAL; 232 233 dapm = snd_soc_component_get_dapm(rt298->component); 234 235 if (rt298->pdata.cbj_en) { 236 regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); 237 *hp = buf & 0x80000000; 238 if (*hp == rt298->is_hp_in) 239 return -1; 240 rt298->is_hp_in = *hp; 241 if (*hp) { 242 /* power on HV,VERF */ 243 regmap_update_bits(rt298->regmap, 244 RT298_DC_GAIN, 0x200, 0x200); 245 246 snd_soc_dapm_force_enable_pin(dapm, "HV"); 247 snd_soc_dapm_force_enable_pin(dapm, "VREF"); 248 /* power LDO1 */ 249 snd_soc_dapm_force_enable_pin(dapm, "LDO1"); 250 snd_soc_dapm_sync(dapm); 251 252 regmap_update_bits(rt298->regmap, 253 RT298_POWER_CTRL1, 0x1001, 0); 254 regmap_update_bits(rt298->regmap, 255 RT298_POWER_CTRL2, 0x4, 0x4); 256 257 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24); 258 msleep(50); 259 260 regmap_update_bits(rt298->regmap, 261 RT298_CBJ_CTRL1, 0xfcc0, 0xd400); 262 msleep(300); 263 regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val); 264 265 if (0x0070 == (val & 0x0070)) { 266 *mic = true; 267 } else { 268 regmap_update_bits(rt298->regmap, 269 RT298_CBJ_CTRL1, 0xfcc0, 0xe400); 270 msleep(300); 271 regmap_read(rt298->regmap, 272 RT298_CBJ_CTRL2, &val); 273 if (0x0070 == (val & 0x0070)) 274 *mic = true; 275 else 276 *mic = false; 277 } 278 regmap_update_bits(rt298->regmap, 279 RT298_DC_GAIN, 0x200, 0x0); 280 281 } else { 282 *mic = false; 283 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20); 284 regmap_update_bits(rt298->regmap, 285 RT298_CBJ_CTRL1, 0x0400, 0x0000); 286 } 287 } else { 288 regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); 289 *hp = buf & 0x80000000; 290 regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf); 291 *mic = buf & 0x80000000; 292 } 293 if (!*mic) { 294 snd_soc_dapm_disable_pin(dapm, "HV"); 295 snd_soc_dapm_disable_pin(dapm, "VREF"); 296 } 297 if (!*hp) 298 snd_soc_dapm_disable_pin(dapm, "LDO1"); 299 snd_soc_dapm_sync(dapm); 300 301 pr_debug("*hp = %d *mic = %d\n", *hp, *mic); 302 303 return 0; 304 } 305 306 static void rt298_jack_detect_work(struct work_struct *work) 307 { 308 struct rt298_priv *rt298 = 309 container_of(work, struct rt298_priv, jack_detect_work.work); 310 int status = 0; 311 bool hp = false; 312 bool mic = false; 313 314 if (rt298_jack_detect(rt298, &hp, &mic) < 0) 315 return; 316 317 if (hp) 318 status |= SND_JACK_HEADPHONE; 319 320 if (mic) 321 status |= SND_JACK_MICROPHONE; 322 323 snd_soc_jack_report(rt298->jack, status, 324 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 325 } 326 327 int rt298_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack) 328 { 329 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 330 struct snd_soc_dapm_context *dapm; 331 bool hp = false; 332 bool mic = false; 333 int status = 0; 334 335 /* If jack in NULL, disable HS jack */ 336 if (!jack) { 337 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x0); 338 dapm = snd_soc_component_get_dapm(component); 339 snd_soc_dapm_disable_pin(dapm, "LDO1"); 340 snd_soc_dapm_sync(dapm); 341 return 0; 342 } 343 344 rt298->jack = jack; 345 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x2); 346 347 rt298_jack_detect(rt298, &hp, &mic); 348 if (hp) 349 status |= SND_JACK_HEADPHONE; 350 351 if (mic) 352 status |= SND_JACK_MICROPHONE; 353 354 snd_soc_jack_report(rt298->jack, status, 355 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 356 357 return 0; 358 } 359 EXPORT_SYMBOL_GPL(rt298_mic_detect); 360 361 static int is_mclk_mode(struct snd_soc_dapm_widget *source, 362 struct snd_soc_dapm_widget *sink) 363 { 364 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 365 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 366 367 if (rt298->clk_id == RT298_SCLK_S_MCLK) 368 return 1; 369 else 370 return 0; 371 } 372 373 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); 374 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 375 376 static const struct snd_kcontrol_new rt298_snd_controls[] = { 377 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN, 378 RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), 379 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN, 380 RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), 381 SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN, 382 0, 0x3, 0, mic_vol_tlv), 383 SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN, 384 RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1), 385 }; 386 387 /* Digital Mixer */ 388 static const struct snd_kcontrol_new rt298_front_mix[] = { 389 SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH, 390 RT298_MUTE_SFT, 1, 1), 391 SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH, 392 RT298_MUTE_SFT, 1, 1), 393 }; 394 395 /* Analog Input Mixer */ 396 static const struct snd_kcontrol_new rt298_rec_mix[] = { 397 SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH, 398 RT298_MUTE_SFT, 1, 1), 399 SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH, 400 RT298_MUTE_SFT, 1, 1), 401 SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH, 402 RT298_MUTE_SFT, 1, 1), 403 SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH, 404 RT298_MUTE_SFT, 1, 1), 405 }; 406 407 static const struct snd_kcontrol_new spo_enable_control = 408 SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK, 409 RT298_SET_PIN_SFT, 1, 0); 410 411 static const struct snd_kcontrol_new hpol_enable_control = 412 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN, 413 RT298_MUTE_SFT, 1, 1); 414 415 static const struct snd_kcontrol_new hpor_enable_control = 416 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN, 417 RT298_MUTE_SFT, 1, 1); 418 419 /* ADC0 source */ 420 static const char * const rt298_adc_src[] = { 421 "Mic", "RECMIX", "Dmic" 422 }; 423 424 static const int rt298_adc_values[] = { 425 0, 4, 5, 426 }; 427 428 static SOC_VALUE_ENUM_SINGLE_DECL( 429 rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT, 430 RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); 431 432 static const struct snd_kcontrol_new rt298_adc0_mux = 433 SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum); 434 435 static SOC_VALUE_ENUM_SINGLE_DECL( 436 rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT, 437 RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); 438 439 static const struct snd_kcontrol_new rt298_adc1_mux = 440 SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum); 441 442 static const char * const rt298_dac_src[] = { 443 "Front", "Surround" 444 }; 445 /* HP-OUT source */ 446 static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX, 447 0, rt298_dac_src); 448 449 static const struct snd_kcontrol_new rt298_hpo_mux = 450 SOC_DAPM_ENUM("HPO source", rt298_hpo_enum); 451 452 /* SPK-OUT source */ 453 static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX, 454 0, rt298_dac_src); 455 456 static const struct snd_kcontrol_new rt298_spo_mux = 457 SOC_DAPM_ENUM("SPO source", rt298_spo_enum); 458 459 static int rt298_spk_event(struct snd_soc_dapm_widget *w, 460 struct snd_kcontrol *kcontrol, int event) 461 { 462 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 463 464 switch (event) { 465 case SND_SOC_DAPM_POST_PMU: 466 snd_soc_component_write(component, 467 RT298_SPK_EAPD, RT298_SET_EAPD_HIGH); 468 break; 469 case SND_SOC_DAPM_PRE_PMD: 470 snd_soc_component_write(component, 471 RT298_SPK_EAPD, RT298_SET_EAPD_LOW); 472 break; 473 474 default: 475 return 0; 476 } 477 478 return 0; 479 } 480 481 static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w, 482 struct snd_kcontrol *kcontrol, int event) 483 { 484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 485 486 switch (event) { 487 case SND_SOC_DAPM_POST_PMU: 488 snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0x20); 489 break; 490 case SND_SOC_DAPM_PRE_PMD: 491 snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0); 492 break; 493 default: 494 return 0; 495 } 496 497 return 0; 498 } 499 500 static int rt298_adc_event(struct snd_soc_dapm_widget *w, 501 struct snd_kcontrol *kcontrol, int event) 502 { 503 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 504 unsigned int nid; 505 506 nid = (w->reg >> 20) & 0xff; 507 508 switch (event) { 509 case SND_SOC_DAPM_POST_PMU: 510 snd_soc_component_update_bits(component, 511 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), 512 0x7080, 0x7000); 513 /* If MCLK doesn't exist, reset AD filter */ 514 if (!(snd_soc_component_read32(component, RT298_VAD_CTRL) & 0x200)) { 515 pr_info("NO MCLK\n"); 516 switch (nid) { 517 case RT298_ADC_IN1: 518 snd_soc_component_update_bits(component, 519 RT298_D_FILTER_CTRL, 0x2, 0x2); 520 mdelay(10); 521 snd_soc_component_update_bits(component, 522 RT298_D_FILTER_CTRL, 0x2, 0x0); 523 break; 524 case RT298_ADC_IN2: 525 snd_soc_component_update_bits(component, 526 RT298_D_FILTER_CTRL, 0x4, 0x4); 527 mdelay(10); 528 snd_soc_component_update_bits(component, 529 RT298_D_FILTER_CTRL, 0x4, 0x0); 530 break; 531 } 532 } 533 break; 534 case SND_SOC_DAPM_PRE_PMD: 535 snd_soc_component_update_bits(component, 536 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), 537 0x7080, 0x7080); 538 break; 539 default: 540 return 0; 541 } 542 543 return 0; 544 } 545 546 static int rt298_mic1_event(struct snd_soc_dapm_widget *w, 547 struct snd_kcontrol *kcontrol, int event) 548 { 549 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 550 551 switch (event) { 552 case SND_SOC_DAPM_PRE_PMU: 553 snd_soc_component_update_bits(component, 554 RT298_A_BIAS_CTRL3, 0xc000, 0x8000); 555 snd_soc_component_update_bits(component, 556 RT298_A_BIAS_CTRL2, 0xc000, 0x8000); 557 break; 558 case SND_SOC_DAPM_POST_PMD: 559 snd_soc_component_update_bits(component, 560 RT298_A_BIAS_CTRL3, 0xc000, 0x0000); 561 snd_soc_component_update_bits(component, 562 RT298_A_BIAS_CTRL2, 0xc000, 0x0000); 563 break; 564 default: 565 return 0; 566 } 567 568 return 0; 569 } 570 571 static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = { 572 573 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1, 574 12, 1, NULL, 0), 575 SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1, 576 0, 1, NULL, 0), 577 SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2, 578 1, 0, NULL, 0), 579 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2, 580 2, 0, NULL, 0), 581 SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2, 582 3, 0, NULL, 0), 583 SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2, 584 4, 1, NULL, 0), 585 SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1, 586 13, 1, NULL, 0), 587 588 589 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1, 590 5, 0, NULL, 0), 591 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, 592 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU | 593 SND_SOC_DAPM_POST_PMD), 594 595 /* Input Lines */ 596 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 597 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 598 SND_SOC_DAPM_INPUT("MIC1"), 599 SND_SOC_DAPM_INPUT("LINE1"), 600 SND_SOC_DAPM_INPUT("Beep"), 601 602 /* DMIC */ 603 SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1, 604 NULL, 0, rt298_set_dmic1_event, 605 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 606 SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1, 607 NULL, 0), 608 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, 609 0, 0, NULL, 0), 610 611 /* REC Mixer */ 612 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, 613 rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)), 614 615 /* ADCs */ 616 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), 617 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), 618 619 /* ADC Mux */ 620 SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1, 621 &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | 622 SND_SOC_DAPM_POST_PMU), 623 SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1, 624 &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | 625 SND_SOC_DAPM_POST_PMU), 626 627 /* Audio Interface */ 628 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 629 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 630 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 631 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 632 633 /* Output Side */ 634 /* DACs */ 635 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), 636 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), 637 638 /* Output Mux */ 639 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux), 640 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux), 641 642 SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO, 643 RT298_SET_PIN_SFT, 0, NULL, 0), 644 645 /* Output Mixer */ 646 SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1, 647 rt298_front_mix, ARRAY_SIZE(rt298_front_mix)), 648 SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1, 649 NULL, 0), 650 651 /* Output Pga */ 652 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, 653 &spo_enable_control, rt298_spk_event, 654 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 655 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, 656 &hpol_enable_control), 657 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, 658 &hpor_enable_control), 659 660 /* Output Lines */ 661 SND_SOC_DAPM_OUTPUT("SPOL"), 662 SND_SOC_DAPM_OUTPUT("SPOR"), 663 SND_SOC_DAPM_OUTPUT("HPO Pin"), 664 SND_SOC_DAPM_OUTPUT("SPDIF"), 665 }; 666 667 static const struct snd_soc_dapm_route rt298_dapm_routes[] = { 668 669 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, 670 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, 671 {"Front", NULL, "MCLK MODE", is_mclk_mode}, 672 {"Surround", NULL, "MCLK MODE", is_mclk_mode}, 673 674 {"HP Power", NULL, "LDO1"}, 675 {"HP Power", NULL, "LDO2"}, 676 {"HP Power", NULL, "LV"}, 677 {"HP Power", NULL, "VREF1"}, 678 {"HP Power", NULL, "BG_MBIAS"}, 679 680 {"MIC1", NULL, "LDO1"}, 681 {"MIC1", NULL, "LDO2"}, 682 {"MIC1", NULL, "HV"}, 683 {"MIC1", NULL, "LV"}, 684 {"MIC1", NULL, "VREF"}, 685 {"MIC1", NULL, "VREF1"}, 686 {"MIC1", NULL, "BG_MBIAS"}, 687 {"MIC1", NULL, "MIC1 Input Buffer"}, 688 689 {"SPO", NULL, "LDO1"}, 690 {"SPO", NULL, "LDO2"}, 691 {"SPO", NULL, "HV"}, 692 {"SPO", NULL, "LV"}, 693 {"SPO", NULL, "VREF"}, 694 {"SPO", NULL, "VREF1"}, 695 {"SPO", NULL, "BG_MBIAS"}, 696 697 {"DMIC1", NULL, "DMIC1 Pin"}, 698 {"DMIC2", NULL, "DMIC2 Pin"}, 699 {"DMIC1", NULL, "DMIC Receiver"}, 700 {"DMIC2", NULL, "DMIC Receiver"}, 701 702 {"RECMIX", "Beep Switch", "Beep"}, 703 {"RECMIX", "Line1 Switch", "LINE1"}, 704 {"RECMIX", "Mic1 Switch", "MIC1"}, 705 706 {"ADC 0 Mux", "Dmic", "DMIC1"}, 707 {"ADC 0 Mux", "RECMIX", "RECMIX"}, 708 {"ADC 0 Mux", "Mic", "MIC1"}, 709 {"ADC 1 Mux", "Dmic", "DMIC2"}, 710 {"ADC 1 Mux", "RECMIX", "RECMIX"}, 711 {"ADC 1 Mux", "Mic", "MIC1"}, 712 713 {"ADC 0", NULL, "ADC 0 Mux"}, 714 {"ADC 1", NULL, "ADC 1 Mux"}, 715 716 {"AIF1TX", NULL, "ADC 0"}, 717 {"AIF2TX", NULL, "ADC 1"}, 718 719 {"DAC 0", NULL, "AIF1RX"}, 720 {"DAC 1", NULL, "AIF2RX"}, 721 722 {"Front", "DAC Switch", "DAC 0"}, 723 {"Front", "RECMIX Switch", "RECMIX"}, 724 725 {"Surround", NULL, "DAC 1"}, 726 727 {"SPK Mux", "Front", "Front"}, 728 {"SPK Mux", "Surround", "Surround"}, 729 730 {"HPO Mux", "Front", "Front"}, 731 {"HPO Mux", "Surround", "Surround"}, 732 733 {"SPO", "Switch", "SPK Mux"}, 734 {"HPO L", "Switch", "HPO Mux"}, 735 {"HPO R", "Switch", "HPO Mux"}, 736 {"HPO L", NULL, "HP Power"}, 737 {"HPO R", NULL, "HP Power"}, 738 739 {"SPOL", NULL, "SPO"}, 740 {"SPOR", NULL, "SPO"}, 741 {"HPO Pin", NULL, "HPO L"}, 742 {"HPO Pin", NULL, "HPO R"}, 743 }; 744 745 static int rt298_hw_params(struct snd_pcm_substream *substream, 746 struct snd_pcm_hw_params *params, 747 struct snd_soc_dai *dai) 748 { 749 struct snd_soc_component *component = dai->component; 750 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 751 unsigned int val = 0; 752 int d_len_code; 753 754 switch (params_rate(params)) { 755 /* bit 14 0:48K 1:44.1K */ 756 case 44100: 757 case 48000: 758 break; 759 default: 760 dev_err(component->dev, "Unsupported sample rate %d\n", 761 params_rate(params)); 762 return -EINVAL; 763 } 764 switch (rt298->sys_clk) { 765 case 12288000: 766 case 24576000: 767 if (params_rate(params) != 48000) { 768 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 769 params_rate(params), rt298->sys_clk); 770 return -EINVAL; 771 } 772 break; 773 case 11289600: 774 case 22579200: 775 if (params_rate(params) != 44100) { 776 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 777 params_rate(params), rt298->sys_clk); 778 return -EINVAL; 779 } 780 break; 781 } 782 783 if (params_channels(params) <= 16) { 784 /* bit 3:0 Number of Channel */ 785 val |= (params_channels(params) - 1); 786 } else { 787 dev_err(component->dev, "Unsupported channels %d\n", 788 params_channels(params)); 789 return -EINVAL; 790 } 791 792 d_len_code = 0; 793 switch (params_width(params)) { 794 /* bit 6:4 Bits per Sample */ 795 case 16: 796 d_len_code = 0; 797 val |= (0x1 << 4); 798 break; 799 case 32: 800 d_len_code = 2; 801 val |= (0x4 << 4); 802 break; 803 case 20: 804 d_len_code = 1; 805 val |= (0x2 << 4); 806 break; 807 case 24: 808 d_len_code = 2; 809 val |= (0x3 << 4); 810 break; 811 case 8: 812 d_len_code = 3; 813 break; 814 default: 815 return -EINVAL; 816 } 817 818 snd_soc_component_update_bits(component, 819 RT298_I2S_CTRL1, 0x0018, d_len_code << 3); 820 dev_dbg(component->dev, "format val = 0x%x\n", val); 821 822 snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val); 823 snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val); 824 825 return 0; 826 } 827 828 static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 829 { 830 struct snd_soc_component *component = dai->component; 831 832 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 833 case SND_SOC_DAIFMT_CBM_CFM: 834 snd_soc_component_update_bits(component, 835 RT298_I2S_CTRL1, 0x800, 0x800); 836 break; 837 case SND_SOC_DAIFMT_CBS_CFS: 838 snd_soc_component_update_bits(component, 839 RT298_I2S_CTRL1, 0x800, 0x0); 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 846 case SND_SOC_DAIFMT_I2S: 847 snd_soc_component_update_bits(component, 848 RT298_I2S_CTRL1, 0x300, 0x0); 849 break; 850 case SND_SOC_DAIFMT_LEFT_J: 851 snd_soc_component_update_bits(component, 852 RT298_I2S_CTRL1, 0x300, 0x1 << 8); 853 break; 854 case SND_SOC_DAIFMT_DSP_A: 855 snd_soc_component_update_bits(component, 856 RT298_I2S_CTRL1, 0x300, 0x2 << 8); 857 break; 858 case SND_SOC_DAIFMT_DSP_B: 859 snd_soc_component_update_bits(component, 860 RT298_I2S_CTRL1, 0x300, 0x3 << 8); 861 break; 862 default: 863 return -EINVAL; 864 } 865 /* bit 15 Stream Type 0:PCM 1:Non-PCM */ 866 snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x8000, 0); 867 snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x8000, 0); 868 869 return 0; 870 } 871 872 static int rt298_set_dai_sysclk(struct snd_soc_dai *dai, 873 int clk_id, unsigned int freq, int dir) 874 { 875 struct snd_soc_component *component = dai->component; 876 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 877 878 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq); 879 880 if (RT298_SCLK_S_MCLK == clk_id) { 881 snd_soc_component_update_bits(component, 882 RT298_I2S_CTRL2, 0x0100, 0x0); 883 snd_soc_component_update_bits(component, 884 RT298_PLL_CTRL1, 0x20, 0x20); 885 } else { 886 snd_soc_component_update_bits(component, 887 RT298_I2S_CTRL2, 0x0100, 0x0100); 888 snd_soc_component_update_bits(component, 889 RT298_PLL_CTRL1, 0x20, 0x0); 890 } 891 892 switch (freq) { 893 case 19200000: 894 if (RT298_SCLK_S_MCLK == clk_id) { 895 dev_err(component->dev, "Should not use MCLK\n"); 896 return -EINVAL; 897 } 898 snd_soc_component_update_bits(component, 899 RT298_I2S_CTRL2, 0x40, 0x40); 900 break; 901 case 24000000: 902 if (RT298_SCLK_S_MCLK == clk_id) { 903 dev_err(component->dev, "Should not use MCLK\n"); 904 return -EINVAL; 905 } 906 snd_soc_component_update_bits(component, 907 RT298_I2S_CTRL2, 0x40, 0x0); 908 break; 909 case 12288000: 910 case 11289600: 911 snd_soc_component_update_bits(component, 912 RT298_I2S_CTRL2, 0x8, 0x0); 913 snd_soc_component_update_bits(component, 914 RT298_CLK_DIV, 0xfc1e, 0x0004); 915 break; 916 case 24576000: 917 case 22579200: 918 snd_soc_component_update_bits(component, 919 RT298_I2S_CTRL2, 0x8, 0x8); 920 snd_soc_component_update_bits(component, 921 RT298_CLK_DIV, 0xfc1e, 0x5406); 922 break; 923 default: 924 dev_err(component->dev, "Unsupported system clock\n"); 925 return -EINVAL; 926 } 927 928 rt298->sys_clk = freq; 929 rt298->clk_id = clk_id; 930 931 return 0; 932 } 933 934 static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 935 { 936 struct snd_soc_component *component = dai->component; 937 938 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 939 if (50 == ratio) 940 snd_soc_component_update_bits(component, 941 RT298_I2S_CTRL1, 0x1000, 0x1000); 942 else 943 snd_soc_component_update_bits(component, 944 RT298_I2S_CTRL1, 0x1000, 0x0); 945 946 947 return 0; 948 } 949 950 static int rt298_set_bias_level(struct snd_soc_component *component, 951 enum snd_soc_bias_level level) 952 { 953 switch (level) { 954 case SND_SOC_BIAS_PREPARE: 955 if (SND_SOC_BIAS_STANDBY == 956 snd_soc_component_get_bias_level(component)) { 957 snd_soc_component_write(component, 958 RT298_SET_AUDIO_POWER, AC_PWRST_D0); 959 snd_soc_component_update_bits(component, 0x0d, 0x200, 0x200); 960 snd_soc_component_update_bits(component, 0x52, 0x80, 0x0); 961 mdelay(20); 962 snd_soc_component_update_bits(component, 0x0d, 0x200, 0x0); 963 snd_soc_component_update_bits(component, 0x52, 0x80, 0x80); 964 } 965 break; 966 967 case SND_SOC_BIAS_STANDBY: 968 snd_soc_component_write(component, 969 RT298_SET_AUDIO_POWER, AC_PWRST_D3); 970 break; 971 972 default: 973 break; 974 } 975 976 return 0; 977 } 978 979 static irqreturn_t rt298_irq(int irq, void *data) 980 { 981 struct rt298_priv *rt298 = data; 982 bool hp = false; 983 bool mic = false; 984 int ret, status = 0; 985 986 ret = rt298_jack_detect(rt298, &hp, &mic); 987 988 /* Clear IRQ */ 989 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1); 990 991 if (ret == 0) { 992 if (hp) 993 status |= SND_JACK_HEADPHONE; 994 995 if (mic) 996 status |= SND_JACK_MICROPHONE; 997 998 snd_soc_jack_report(rt298->jack, status, 999 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 1000 1001 pm_wakeup_event(&rt298->i2c->dev, 300); 1002 } 1003 1004 return IRQ_HANDLED; 1005 } 1006 1007 static int rt298_probe(struct snd_soc_component *component) 1008 { 1009 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 1010 1011 rt298->component = component; 1012 1013 if (rt298->i2c->irq) { 1014 regmap_update_bits(rt298->regmap, 1015 RT298_IRQ_CTRL, 0x2, 0x2); 1016 1017 INIT_DELAYED_WORK(&rt298->jack_detect_work, 1018 rt298_jack_detect_work); 1019 schedule_delayed_work(&rt298->jack_detect_work, 1020 msecs_to_jiffies(1250)); 1021 } 1022 1023 return 0; 1024 } 1025 1026 static void rt298_remove(struct snd_soc_component *component) 1027 { 1028 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 1029 1030 cancel_delayed_work_sync(&rt298->jack_detect_work); 1031 } 1032 1033 #ifdef CONFIG_PM 1034 static int rt298_suspend(struct snd_soc_component *component) 1035 { 1036 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 1037 1038 rt298->is_hp_in = -1; 1039 regcache_cache_only(rt298->regmap, true); 1040 regcache_mark_dirty(rt298->regmap); 1041 1042 return 0; 1043 } 1044 1045 static int rt298_resume(struct snd_soc_component *component) 1046 { 1047 struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component); 1048 1049 regcache_cache_only(rt298->regmap, false); 1050 rt298_index_sync(component); 1051 regcache_sync(rt298->regmap); 1052 1053 return 0; 1054 } 1055 #else 1056 #define rt298_suspend NULL 1057 #define rt298_resume NULL 1058 #endif 1059 1060 #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1061 #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1062 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1063 1064 static const struct snd_soc_dai_ops rt298_aif_dai_ops = { 1065 .hw_params = rt298_hw_params, 1066 .set_fmt = rt298_set_dai_fmt, 1067 .set_sysclk = rt298_set_dai_sysclk, 1068 .set_bclk_ratio = rt298_set_bclk_ratio, 1069 }; 1070 1071 static struct snd_soc_dai_driver rt298_dai[] = { 1072 { 1073 .name = "rt298-aif1", 1074 .id = RT298_AIF1, 1075 .playback = { 1076 .stream_name = "AIF1 Playback", 1077 .channels_min = 1, 1078 .channels_max = 2, 1079 .rates = RT298_STEREO_RATES, 1080 .formats = RT298_FORMATS, 1081 }, 1082 .capture = { 1083 .stream_name = "AIF1 Capture", 1084 .channels_min = 1, 1085 .channels_max = 2, 1086 .rates = RT298_STEREO_RATES, 1087 .formats = RT298_FORMATS, 1088 }, 1089 .ops = &rt298_aif_dai_ops, 1090 .symmetric_rates = 1, 1091 }, 1092 { 1093 .name = "rt298-aif2", 1094 .id = RT298_AIF2, 1095 .playback = { 1096 .stream_name = "AIF2 Playback", 1097 .channels_min = 1, 1098 .channels_max = 2, 1099 .rates = RT298_STEREO_RATES, 1100 .formats = RT298_FORMATS, 1101 }, 1102 .capture = { 1103 .stream_name = "AIF2 Capture", 1104 .channels_min = 1, 1105 .channels_max = 2, 1106 .rates = RT298_STEREO_RATES, 1107 .formats = RT298_FORMATS, 1108 }, 1109 .ops = &rt298_aif_dai_ops, 1110 .symmetric_rates = 1, 1111 }, 1112 1113 }; 1114 1115 static const struct snd_soc_component_driver soc_component_dev_rt298 = { 1116 .probe = rt298_probe, 1117 .remove = rt298_remove, 1118 .suspend = rt298_suspend, 1119 .resume = rt298_resume, 1120 .set_bias_level = rt298_set_bias_level, 1121 .controls = rt298_snd_controls, 1122 .num_controls = ARRAY_SIZE(rt298_snd_controls), 1123 .dapm_widgets = rt298_dapm_widgets, 1124 .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets), 1125 .dapm_routes = rt298_dapm_routes, 1126 .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes), 1127 .use_pmdown_time = 1, 1128 .endianness = 1, 1129 .non_legacy_dai_naming = 1, 1130 }; 1131 1132 static const struct regmap_config rt298_regmap = { 1133 .reg_bits = 32, 1134 .val_bits = 32, 1135 .max_register = 0x02370100, 1136 .volatile_reg = rt298_volatile_register, 1137 .readable_reg = rt298_readable_register, 1138 .reg_write = rl6347a_hw_write, 1139 .reg_read = rl6347a_hw_read, 1140 .cache_type = REGCACHE_RBTREE, 1141 .reg_defaults = rt298_reg, 1142 .num_reg_defaults = ARRAY_SIZE(rt298_reg), 1143 }; 1144 1145 static const struct i2c_device_id rt298_i2c_id[] = { 1146 {"rt298", 0}, 1147 {} 1148 }; 1149 MODULE_DEVICE_TABLE(i2c, rt298_i2c_id); 1150 1151 static const struct acpi_device_id rt298_acpi_match[] = { 1152 { "INT343A", 0 }, 1153 {}, 1154 }; 1155 MODULE_DEVICE_TABLE(acpi, rt298_acpi_match); 1156 1157 static const struct dmi_system_id force_combo_jack_table[] = { 1158 { 1159 .ident = "Intel Broxton P", 1160 .matches = { 1161 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"), 1162 DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P") 1163 } 1164 }, 1165 { 1166 .ident = "Intel Gemini Lake", 1167 .matches = { 1168 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"), 1169 DMI_MATCH(DMI_PRODUCT_NAME, "Geminilake") 1170 } 1171 }, 1172 { } 1173 }; 1174 1175 static int rt298_i2c_probe(struct i2c_client *i2c, 1176 const struct i2c_device_id *id) 1177 { 1178 struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev); 1179 struct rt298_priv *rt298; 1180 struct device *dev = &i2c->dev; 1181 const struct acpi_device_id *acpiid; 1182 int i, ret; 1183 1184 rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298), 1185 GFP_KERNEL); 1186 if (NULL == rt298) 1187 return -ENOMEM; 1188 1189 rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap); 1190 if (IS_ERR(rt298->regmap)) { 1191 ret = PTR_ERR(rt298->regmap); 1192 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1193 ret); 1194 return ret; 1195 } 1196 1197 regmap_read(rt298->regmap, 1198 RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); 1199 if (ret != RT298_VENDOR_ID) { 1200 dev_err(&i2c->dev, 1201 "Device with ID register %#x is not rt298\n", ret); 1202 return -ENODEV; 1203 } 1204 1205 rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def, 1206 sizeof(rt298_index_def), GFP_KERNEL); 1207 if (!rt298->index_cache) 1208 return -ENOMEM; 1209 1210 rt298->index_cache_size = INDEX_CACHE_SIZE; 1211 rt298->i2c = i2c; 1212 i2c_set_clientdata(i2c, rt298); 1213 1214 /* restore codec default */ 1215 for (i = 0; i < INDEX_CACHE_SIZE; i++) 1216 regmap_write(rt298->regmap, rt298->index_cache[i].reg, 1217 rt298->index_cache[i].def); 1218 for (i = 0; i < ARRAY_SIZE(rt298_reg); i++) 1219 regmap_write(rt298->regmap, rt298_reg[i].reg, 1220 rt298_reg[i].def); 1221 1222 if (pdata) 1223 rt298->pdata = *pdata; 1224 1225 /* enable jack combo mode on supported devices */ 1226 acpiid = acpi_match_device(dev->driver->acpi_match_table, dev); 1227 if (acpiid && acpiid->driver_data) { 1228 rt298->pdata = *(struct rt298_platform_data *) 1229 acpiid->driver_data; 1230 } 1231 1232 if (dmi_check_system(force_combo_jack_table)) { 1233 rt298->pdata.cbj_en = true; 1234 rt298->pdata.gpio2_en = false; 1235 } 1236 1237 /* VREF Charging */ 1238 regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80); 1239 regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860); 1240 /* Vref2 */ 1241 regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20); 1242 1243 regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3); 1244 1245 for (i = 0; i < RT298_POWER_REG_LEN; i++) 1246 regmap_write(rt298->regmap, 1247 RT298_SET_POWER(rt298_support_power_controls[i]), 1248 AC_PWRST_D1); 1249 1250 if (!rt298->pdata.cbj_en) { 1251 regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000); 1252 regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816); 1253 regmap_update_bits(rt298->regmap, 1254 RT298_CBJ_CTRL1, 0xf000, 0xb000); 1255 } else { 1256 regmap_update_bits(rt298->regmap, 1257 RT298_CBJ_CTRL1, 0xf000, 0x5000); 1258 } 1259 1260 mdelay(10); 1261 1262 if (!rt298->pdata.gpio2_en) 1263 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40); 1264 else 1265 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0); 1266 1267 mdelay(10); 1268 1269 regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000); 1270 regmap_update_bits(rt298->regmap, 1271 RT298_WIND_FILTER_CTRL, 0x0082, 0x0082); 1272 1273 regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81); 1274 regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82); 1275 regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84); 1276 regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2); 1277 1278 rt298->is_hp_in = -1; 1279 1280 if (rt298->i2c->irq) { 1281 ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq, 1282 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298); 1283 if (ret != 0) { 1284 dev_err(&i2c->dev, 1285 "Failed to reguest IRQ: %d\n", ret); 1286 return ret; 1287 } 1288 } 1289 1290 ret = devm_snd_soc_register_component(&i2c->dev, 1291 &soc_component_dev_rt298, 1292 rt298_dai, ARRAY_SIZE(rt298_dai)); 1293 1294 return ret; 1295 } 1296 1297 static int rt298_i2c_remove(struct i2c_client *i2c) 1298 { 1299 struct rt298_priv *rt298 = i2c_get_clientdata(i2c); 1300 1301 if (i2c->irq) 1302 free_irq(i2c->irq, rt298); 1303 1304 return 0; 1305 } 1306 1307 1308 static struct i2c_driver rt298_i2c_driver = { 1309 .driver = { 1310 .name = "rt298", 1311 .acpi_match_table = ACPI_PTR(rt298_acpi_match), 1312 }, 1313 .probe = rt298_i2c_probe, 1314 .remove = rt298_i2c_remove, 1315 .id_table = rt298_i2c_id, 1316 }; 1317 1318 module_i2c_driver(rt298_i2c_driver); 1319 1320 MODULE_DESCRIPTION("ASoC RT298 driver"); 1321 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 1322 MODULE_LICENSE("GPL"); 1323