1 /* 2 * rt298.c -- RT298 ALSA SoC audio codec driver 3 * 4 * Copyright 2015 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dmi.h> 21 #include <linux/acpi.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/jack.h> 30 #include <linux/workqueue.h> 31 #include <sound/rt298.h> 32 33 #include "rl6347a.h" 34 #include "rt298.h" 35 36 #define RT298_VENDOR_ID 0x10ec0298 37 38 struct rt298_priv { 39 struct reg_default *index_cache; 40 int index_cache_size; 41 struct regmap *regmap; 42 struct snd_soc_codec *codec; 43 struct rt298_platform_data pdata; 44 struct i2c_client *i2c; 45 struct snd_soc_jack *jack; 46 struct delayed_work jack_detect_work; 47 int sys_clk; 48 int clk_id; 49 int is_hp_in; 50 }; 51 52 static const struct reg_default rt298_index_def[] = { 53 { 0x01, 0xa5a8 }, 54 { 0x02, 0x8e95 }, 55 { 0x03, 0x0002 }, 56 { 0x04, 0xaf67 }, 57 { 0x08, 0x200f }, 58 { 0x09, 0xd010 }, 59 { 0x0a, 0x0100 }, 60 { 0x0b, 0x0000 }, 61 { 0x0d, 0x2800 }, 62 { 0x0f, 0x0022 }, 63 { 0x19, 0x0217 }, 64 { 0x20, 0x0020 }, 65 { 0x33, 0x0208 }, 66 { 0x46, 0x0300 }, 67 { 0x49, 0x4004 }, 68 { 0x4f, 0x50c9 }, 69 { 0x50, 0x3000 }, 70 { 0x63, 0x1b02 }, 71 { 0x67, 0x1111 }, 72 { 0x68, 0x1016 }, 73 { 0x69, 0x273f }, 74 }; 75 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def) 76 77 static const struct reg_default rt298_reg[] = { 78 { 0x00170500, 0x00000400 }, 79 { 0x00220000, 0x00000031 }, 80 { 0x00239000, 0x0000007f }, 81 { 0x0023a000, 0x0000007f }, 82 { 0x00270500, 0x00000400 }, 83 { 0x00370500, 0x00000400 }, 84 { 0x00870500, 0x00000400 }, 85 { 0x00920000, 0x00000031 }, 86 { 0x00935000, 0x000000c3 }, 87 { 0x00936000, 0x000000c3 }, 88 { 0x00970500, 0x00000400 }, 89 { 0x00b37000, 0x00000097 }, 90 { 0x00b37200, 0x00000097 }, 91 { 0x00b37300, 0x00000097 }, 92 { 0x00c37000, 0x00000000 }, 93 { 0x00c37100, 0x00000080 }, 94 { 0x01270500, 0x00000400 }, 95 { 0x01370500, 0x00000400 }, 96 { 0x01371f00, 0x411111f0 }, 97 { 0x01439000, 0x00000080 }, 98 { 0x0143a000, 0x00000080 }, 99 { 0x01470700, 0x00000000 }, 100 { 0x01470500, 0x00000400 }, 101 { 0x01470c00, 0x00000000 }, 102 { 0x01470100, 0x00000000 }, 103 { 0x01837000, 0x00000000 }, 104 { 0x01870500, 0x00000400 }, 105 { 0x02050000, 0x00000000 }, 106 { 0x02139000, 0x00000080 }, 107 { 0x0213a000, 0x00000080 }, 108 { 0x02170100, 0x00000000 }, 109 { 0x02170500, 0x00000400 }, 110 { 0x02170700, 0x00000000 }, 111 { 0x02270100, 0x00000000 }, 112 { 0x02370100, 0x00000000 }, 113 { 0x01870700, 0x00000020 }, 114 { 0x00830000, 0x000000c3 }, 115 { 0x00930000, 0x000000c3 }, 116 { 0x01270700, 0x00000000 }, 117 }; 118 119 static bool rt298_volatile_register(struct device *dev, unsigned int reg) 120 { 121 switch (reg) { 122 case 0 ... 0xff: 123 case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 124 case RT298_GET_HP_SENSE: 125 case RT298_GET_MIC1_SENSE: 126 case RT298_PROC_COEF: 127 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): 128 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): 129 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): 130 return true; 131 default: 132 return false; 133 } 134 135 136 } 137 138 static bool rt298_readable_register(struct device *dev, unsigned int reg) 139 { 140 switch (reg) { 141 case 0 ... 0xff: 142 case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 143 case RT298_GET_HP_SENSE: 144 case RT298_GET_MIC1_SENSE: 145 case RT298_SET_AUDIO_POWER: 146 case RT298_SET_HPO_POWER: 147 case RT298_SET_SPK_POWER: 148 case RT298_SET_DMIC1_POWER: 149 case RT298_SPK_MUX: 150 case RT298_HPO_MUX: 151 case RT298_ADC0_MUX: 152 case RT298_ADC1_MUX: 153 case RT298_SET_MIC1: 154 case RT298_SET_PIN_HPO: 155 case RT298_SET_PIN_SPK: 156 case RT298_SET_PIN_DMIC1: 157 case RT298_SPK_EAPD: 158 case RT298_SET_AMP_GAIN_HPO: 159 case RT298_SET_DMIC2_DEFAULT: 160 case RT298_DACL_GAIN: 161 case RT298_DACR_GAIN: 162 case RT298_ADCL_GAIN: 163 case RT298_ADCR_GAIN: 164 case RT298_MIC_GAIN: 165 case RT298_SPOL_GAIN: 166 case RT298_SPOR_GAIN: 167 case RT298_HPOL_GAIN: 168 case RT298_HPOR_GAIN: 169 case RT298_F_DAC_SWITCH: 170 case RT298_F_RECMIX_SWITCH: 171 case RT298_REC_MIC_SWITCH: 172 case RT298_REC_I2S_SWITCH: 173 case RT298_REC_LINE_SWITCH: 174 case RT298_REC_BEEP_SWITCH: 175 case RT298_DAC_FORMAT: 176 case RT298_ADC_FORMAT: 177 case RT298_COEF_INDEX: 178 case RT298_PROC_COEF: 179 case RT298_SET_AMP_GAIN_ADC_IN1: 180 case RT298_SET_AMP_GAIN_ADC_IN2: 181 case RT298_SET_POWER(RT298_DAC_OUT1): 182 case RT298_SET_POWER(RT298_DAC_OUT2): 183 case RT298_SET_POWER(RT298_ADC_IN1): 184 case RT298_SET_POWER(RT298_ADC_IN2): 185 case RT298_SET_POWER(RT298_DMIC2): 186 case RT298_SET_POWER(RT298_MIC1): 187 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): 188 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): 189 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): 190 return true; 191 default: 192 return false; 193 } 194 } 195 196 #ifdef CONFIG_PM 197 static void rt298_index_sync(struct snd_soc_codec *codec) 198 { 199 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 200 int i; 201 202 for (i = 0; i < INDEX_CACHE_SIZE; i++) { 203 snd_soc_write(codec, rt298->index_cache[i].reg, 204 rt298->index_cache[i].def); 205 } 206 } 207 #endif 208 209 static int rt298_support_power_controls[] = { 210 RT298_DAC_OUT1, 211 RT298_DAC_OUT2, 212 RT298_ADC_IN1, 213 RT298_ADC_IN2, 214 RT298_MIC1, 215 RT298_DMIC1, 216 RT298_DMIC2, 217 RT298_SPK_OUT, 218 RT298_HP_OUT, 219 }; 220 #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls) 221 222 static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic) 223 { 224 struct snd_soc_dapm_context *dapm; 225 unsigned int val, buf; 226 227 *hp = false; 228 *mic = false; 229 230 if (!rt298->codec) 231 return -EINVAL; 232 233 dapm = snd_soc_codec_get_dapm(rt298->codec); 234 235 if (rt298->pdata.cbj_en) { 236 regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); 237 *hp = buf & 0x80000000; 238 if (*hp == rt298->is_hp_in) 239 return -1; 240 rt298->is_hp_in = *hp; 241 if (*hp) { 242 /* power on HV,VERF */ 243 regmap_update_bits(rt298->regmap, 244 RT298_DC_GAIN, 0x200, 0x200); 245 246 snd_soc_dapm_force_enable_pin(dapm, "HV"); 247 snd_soc_dapm_force_enable_pin(dapm, "VREF"); 248 /* power LDO1 */ 249 snd_soc_dapm_force_enable_pin(dapm, "LDO1"); 250 snd_soc_dapm_sync(dapm); 251 252 regmap_update_bits(rt298->regmap, 253 RT298_POWER_CTRL1, 0x1001, 0); 254 regmap_update_bits(rt298->regmap, 255 RT298_POWER_CTRL2, 0x4, 0x4); 256 257 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24); 258 msleep(50); 259 260 regmap_update_bits(rt298->regmap, 261 RT298_CBJ_CTRL1, 0xfcc0, 0xd400); 262 msleep(300); 263 regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val); 264 265 if (0x0070 == (val & 0x0070)) { 266 *mic = true; 267 } else { 268 regmap_update_bits(rt298->regmap, 269 RT298_CBJ_CTRL1, 0xfcc0, 0xe400); 270 msleep(300); 271 regmap_read(rt298->regmap, 272 RT298_CBJ_CTRL2, &val); 273 if (0x0070 == (val & 0x0070)) 274 *mic = true; 275 else 276 *mic = false; 277 } 278 regmap_update_bits(rt298->regmap, 279 RT298_DC_GAIN, 0x200, 0x0); 280 281 } else { 282 *mic = false; 283 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20); 284 regmap_update_bits(rt298->regmap, 285 RT298_CBJ_CTRL1, 0x0400, 0x0000); 286 } 287 } else { 288 regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); 289 *hp = buf & 0x80000000; 290 regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf); 291 *mic = buf & 0x80000000; 292 } 293 294 snd_soc_dapm_disable_pin(dapm, "HV"); 295 snd_soc_dapm_disable_pin(dapm, "VREF"); 296 if (!*hp) 297 snd_soc_dapm_disable_pin(dapm, "LDO1"); 298 snd_soc_dapm_sync(dapm); 299 300 pr_debug("*hp = %d *mic = %d\n", *hp, *mic); 301 302 return 0; 303 } 304 305 static void rt298_jack_detect_work(struct work_struct *work) 306 { 307 struct rt298_priv *rt298 = 308 container_of(work, struct rt298_priv, jack_detect_work.work); 309 int status = 0; 310 bool hp = false; 311 bool mic = false; 312 313 if (rt298_jack_detect(rt298, &hp, &mic) < 0) 314 return; 315 316 if (hp == true) 317 status |= SND_JACK_HEADPHONE; 318 319 if (mic == true) 320 status |= SND_JACK_MICROPHONE; 321 322 snd_soc_jack_report(rt298->jack, status, 323 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 324 } 325 326 int rt298_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) 327 { 328 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 329 330 rt298->jack = jack; 331 332 /* Send an initial empty report */ 333 snd_soc_jack_report(rt298->jack, 0, 334 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 335 336 return 0; 337 } 338 EXPORT_SYMBOL_GPL(rt298_mic_detect); 339 340 static int is_mclk_mode(struct snd_soc_dapm_widget *source, 341 struct snd_soc_dapm_widget *sink) 342 { 343 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 344 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 345 346 if (rt298->clk_id == RT298_SCLK_S_MCLK) 347 return 1; 348 else 349 return 0; 350 } 351 352 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); 353 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 354 355 static const struct snd_kcontrol_new rt298_snd_controls[] = { 356 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN, 357 RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), 358 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN, 359 RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), 360 SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN, 361 0, 0x3, 0, mic_vol_tlv), 362 SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN, 363 RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1), 364 }; 365 366 /* Digital Mixer */ 367 static const struct snd_kcontrol_new rt298_front_mix[] = { 368 SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH, 369 RT298_MUTE_SFT, 1, 1), 370 SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH, 371 RT298_MUTE_SFT, 1, 1), 372 }; 373 374 /* Analog Input Mixer */ 375 static const struct snd_kcontrol_new rt298_rec_mix[] = { 376 SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH, 377 RT298_MUTE_SFT, 1, 1), 378 SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH, 379 RT298_MUTE_SFT, 1, 1), 380 SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH, 381 RT298_MUTE_SFT, 1, 1), 382 SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH, 383 RT298_MUTE_SFT, 1, 1), 384 }; 385 386 static const struct snd_kcontrol_new spo_enable_control = 387 SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK, 388 RT298_SET_PIN_SFT, 1, 0); 389 390 static const struct snd_kcontrol_new hpol_enable_control = 391 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN, 392 RT298_MUTE_SFT, 1, 1); 393 394 static const struct snd_kcontrol_new hpor_enable_control = 395 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN, 396 RT298_MUTE_SFT, 1, 1); 397 398 /* ADC0 source */ 399 static const char * const rt298_adc_src[] = { 400 "Mic", "RECMIX", "Dmic" 401 }; 402 403 static const int rt298_adc_values[] = { 404 0, 4, 5, 405 }; 406 407 static SOC_VALUE_ENUM_SINGLE_DECL( 408 rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT, 409 RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); 410 411 static const struct snd_kcontrol_new rt298_adc0_mux = 412 SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum); 413 414 static SOC_VALUE_ENUM_SINGLE_DECL( 415 rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT, 416 RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); 417 418 static const struct snd_kcontrol_new rt298_adc1_mux = 419 SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum); 420 421 static const char * const rt298_dac_src[] = { 422 "Front", "Surround" 423 }; 424 /* HP-OUT source */ 425 static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX, 426 0, rt298_dac_src); 427 428 static const struct snd_kcontrol_new rt298_hpo_mux = 429 SOC_DAPM_ENUM("HPO source", rt298_hpo_enum); 430 431 /* SPK-OUT source */ 432 static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX, 433 0, rt298_dac_src); 434 435 static const struct snd_kcontrol_new rt298_spo_mux = 436 SOC_DAPM_ENUM("SPO source", rt298_spo_enum); 437 438 static int rt298_spk_event(struct snd_soc_dapm_widget *w, 439 struct snd_kcontrol *kcontrol, int event) 440 { 441 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 442 443 switch (event) { 444 case SND_SOC_DAPM_POST_PMU: 445 snd_soc_write(codec, 446 RT298_SPK_EAPD, RT298_SET_EAPD_HIGH); 447 break; 448 case SND_SOC_DAPM_PRE_PMD: 449 snd_soc_write(codec, 450 RT298_SPK_EAPD, RT298_SET_EAPD_LOW); 451 break; 452 453 default: 454 return 0; 455 } 456 457 return 0; 458 } 459 460 static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w, 461 struct snd_kcontrol *kcontrol, int event) 462 { 463 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 464 465 switch (event) { 466 case SND_SOC_DAPM_POST_PMU: 467 snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0x20); 468 break; 469 case SND_SOC_DAPM_PRE_PMD: 470 snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0); 471 break; 472 default: 473 return 0; 474 } 475 476 return 0; 477 } 478 479 static int rt298_adc_event(struct snd_soc_dapm_widget *w, 480 struct snd_kcontrol *kcontrol, int event) 481 { 482 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 483 unsigned int nid; 484 485 nid = (w->reg >> 20) & 0xff; 486 487 switch (event) { 488 case SND_SOC_DAPM_POST_PMU: 489 snd_soc_update_bits(codec, 490 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), 491 0x7080, 0x7000); 492 /* If MCLK doesn't exist, reset AD filter */ 493 if (!(snd_soc_read(codec, RT298_VAD_CTRL) & 0x200)) { 494 pr_info("NO MCLK\n"); 495 switch (nid) { 496 case RT298_ADC_IN1: 497 snd_soc_update_bits(codec, 498 RT298_D_FILTER_CTRL, 0x2, 0x2); 499 mdelay(10); 500 snd_soc_update_bits(codec, 501 RT298_D_FILTER_CTRL, 0x2, 0x0); 502 break; 503 case RT298_ADC_IN2: 504 snd_soc_update_bits(codec, 505 RT298_D_FILTER_CTRL, 0x4, 0x4); 506 mdelay(10); 507 snd_soc_update_bits(codec, 508 RT298_D_FILTER_CTRL, 0x4, 0x0); 509 break; 510 } 511 } 512 break; 513 case SND_SOC_DAPM_PRE_PMD: 514 snd_soc_update_bits(codec, 515 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), 516 0x7080, 0x7080); 517 break; 518 default: 519 return 0; 520 } 521 522 return 0; 523 } 524 525 static int rt298_mic1_event(struct snd_soc_dapm_widget *w, 526 struct snd_kcontrol *kcontrol, int event) 527 { 528 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 529 530 switch (event) { 531 case SND_SOC_DAPM_PRE_PMU: 532 snd_soc_update_bits(codec, 533 RT298_A_BIAS_CTRL3, 0xc000, 0x8000); 534 snd_soc_update_bits(codec, 535 RT298_A_BIAS_CTRL2, 0xc000, 0x8000); 536 break; 537 case SND_SOC_DAPM_POST_PMD: 538 snd_soc_update_bits(codec, 539 RT298_A_BIAS_CTRL3, 0xc000, 0x0000); 540 snd_soc_update_bits(codec, 541 RT298_A_BIAS_CTRL2, 0xc000, 0x0000); 542 break; 543 default: 544 return 0; 545 } 546 547 return 0; 548 } 549 550 static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = { 551 552 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1, 553 12, 1, NULL, 0), 554 SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1, 555 0, 1, NULL, 0), 556 SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2, 557 1, 0, NULL, 0), 558 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2, 559 2, 0, NULL, 0), 560 SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2, 561 3, 0, NULL, 0), 562 SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2, 563 4, 1, NULL, 0), 564 SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1, 565 13, 1, NULL, 0), 566 567 568 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1, 569 5, 0, NULL, 0), 570 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, 571 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU | 572 SND_SOC_DAPM_POST_PMD), 573 574 /* Input Lines */ 575 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 576 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 577 SND_SOC_DAPM_INPUT("MIC1"), 578 SND_SOC_DAPM_INPUT("LINE1"), 579 SND_SOC_DAPM_INPUT("Beep"), 580 581 /* DMIC */ 582 SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1, 583 NULL, 0, rt298_set_dmic1_event, 584 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 585 SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1, 586 NULL, 0), 587 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, 588 0, 0, NULL, 0), 589 590 /* REC Mixer */ 591 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, 592 rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)), 593 594 /* ADCs */ 595 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), 596 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), 597 598 /* ADC Mux */ 599 SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1, 600 &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | 601 SND_SOC_DAPM_POST_PMU), 602 SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1, 603 &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | 604 SND_SOC_DAPM_POST_PMU), 605 606 /* Audio Interface */ 607 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 608 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 609 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 610 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 611 612 /* Output Side */ 613 /* DACs */ 614 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), 615 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), 616 617 /* Output Mux */ 618 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux), 619 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux), 620 621 SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO, 622 RT298_SET_PIN_SFT, 0, NULL, 0), 623 624 /* Output Mixer */ 625 SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1, 626 rt298_front_mix, ARRAY_SIZE(rt298_front_mix)), 627 SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1, 628 NULL, 0), 629 630 /* Output Pga */ 631 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, 632 &spo_enable_control, rt298_spk_event, 633 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 634 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, 635 &hpol_enable_control), 636 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, 637 &hpor_enable_control), 638 639 /* Output Lines */ 640 SND_SOC_DAPM_OUTPUT("SPOL"), 641 SND_SOC_DAPM_OUTPUT("SPOR"), 642 SND_SOC_DAPM_OUTPUT("HPO Pin"), 643 SND_SOC_DAPM_OUTPUT("SPDIF"), 644 }; 645 646 static const struct snd_soc_dapm_route rt298_dapm_routes[] = { 647 648 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, 649 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, 650 {"Front", NULL, "MCLK MODE", is_mclk_mode}, 651 {"Surround", NULL, "MCLK MODE", is_mclk_mode}, 652 653 {"HP Power", NULL, "LDO1"}, 654 {"HP Power", NULL, "LDO2"}, 655 {"HP Power", NULL, "LV"}, 656 {"HP Power", NULL, "VREF1"}, 657 {"HP Power", NULL, "BG_MBIAS"}, 658 659 {"MIC1", NULL, "LDO1"}, 660 {"MIC1", NULL, "LDO2"}, 661 {"MIC1", NULL, "HV"}, 662 {"MIC1", NULL, "LV"}, 663 {"MIC1", NULL, "VREF"}, 664 {"MIC1", NULL, "VREF1"}, 665 {"MIC1", NULL, "BG_MBIAS"}, 666 {"MIC1", NULL, "MIC1 Input Buffer"}, 667 668 {"SPO", NULL, "LDO1"}, 669 {"SPO", NULL, "LDO2"}, 670 {"SPO", NULL, "HV"}, 671 {"SPO", NULL, "LV"}, 672 {"SPO", NULL, "VREF"}, 673 {"SPO", NULL, "VREF1"}, 674 {"SPO", NULL, "BG_MBIAS"}, 675 676 {"DMIC1", NULL, "DMIC1 Pin"}, 677 {"DMIC2", NULL, "DMIC2 Pin"}, 678 {"DMIC1", NULL, "DMIC Receiver"}, 679 {"DMIC2", NULL, "DMIC Receiver"}, 680 681 {"RECMIX", "Beep Switch", "Beep"}, 682 {"RECMIX", "Line1 Switch", "LINE1"}, 683 {"RECMIX", "Mic1 Switch", "MIC1"}, 684 685 {"ADC 0 Mux", "Dmic", "DMIC1"}, 686 {"ADC 0 Mux", "RECMIX", "RECMIX"}, 687 {"ADC 0 Mux", "Mic", "MIC1"}, 688 {"ADC 1 Mux", "Dmic", "DMIC2"}, 689 {"ADC 1 Mux", "RECMIX", "RECMIX"}, 690 {"ADC 1 Mux", "Mic", "MIC1"}, 691 692 {"ADC 0", NULL, "ADC 0 Mux"}, 693 {"ADC 1", NULL, "ADC 1 Mux"}, 694 695 {"AIF1TX", NULL, "ADC 0"}, 696 {"AIF2TX", NULL, "ADC 1"}, 697 698 {"DAC 0", NULL, "AIF1RX"}, 699 {"DAC 1", NULL, "AIF2RX"}, 700 701 {"Front", "DAC Switch", "DAC 0"}, 702 {"Front", "RECMIX Switch", "RECMIX"}, 703 704 {"Surround", NULL, "DAC 1"}, 705 706 {"SPK Mux", "Front", "Front"}, 707 {"SPK Mux", "Surround", "Surround"}, 708 709 {"HPO Mux", "Front", "Front"}, 710 {"HPO Mux", "Surround", "Surround"}, 711 712 {"SPO", "Switch", "SPK Mux"}, 713 {"HPO L", "Switch", "HPO Mux"}, 714 {"HPO R", "Switch", "HPO Mux"}, 715 {"HPO L", NULL, "HP Power"}, 716 {"HPO R", NULL, "HP Power"}, 717 718 {"SPOL", NULL, "SPO"}, 719 {"SPOR", NULL, "SPO"}, 720 {"HPO Pin", NULL, "HPO L"}, 721 {"HPO Pin", NULL, "HPO R"}, 722 }; 723 724 static int rt298_hw_params(struct snd_pcm_substream *substream, 725 struct snd_pcm_hw_params *params, 726 struct snd_soc_dai *dai) 727 { 728 struct snd_soc_codec *codec = dai->codec; 729 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 730 unsigned int val = 0; 731 int d_len_code; 732 733 switch (params_rate(params)) { 734 /* bit 14 0:48K 1:44.1K */ 735 case 44100: 736 case 48000: 737 break; 738 default: 739 dev_err(codec->dev, "Unsupported sample rate %d\n", 740 params_rate(params)); 741 return -EINVAL; 742 } 743 switch (rt298->sys_clk) { 744 case 12288000: 745 case 24576000: 746 if (params_rate(params) != 48000) { 747 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", 748 params_rate(params), rt298->sys_clk); 749 return -EINVAL; 750 } 751 break; 752 case 11289600: 753 case 22579200: 754 if (params_rate(params) != 44100) { 755 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", 756 params_rate(params), rt298->sys_clk); 757 return -EINVAL; 758 } 759 break; 760 } 761 762 if (params_channels(params) <= 16) { 763 /* bit 3:0 Number of Channel */ 764 val |= (params_channels(params) - 1); 765 } else { 766 dev_err(codec->dev, "Unsupported channels %d\n", 767 params_channels(params)); 768 return -EINVAL; 769 } 770 771 d_len_code = 0; 772 switch (params_width(params)) { 773 /* bit 6:4 Bits per Sample */ 774 case 16: 775 d_len_code = 0; 776 val |= (0x1 << 4); 777 break; 778 case 32: 779 d_len_code = 2; 780 val |= (0x4 << 4); 781 break; 782 case 20: 783 d_len_code = 1; 784 val |= (0x2 << 4); 785 break; 786 case 24: 787 d_len_code = 2; 788 val |= (0x3 << 4); 789 break; 790 case 8: 791 d_len_code = 3; 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 snd_soc_update_bits(codec, 798 RT298_I2S_CTRL1, 0x0018, d_len_code << 3); 799 dev_dbg(codec->dev, "format val = 0x%x\n", val); 800 801 snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x407f, val); 802 snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x407f, val); 803 804 return 0; 805 } 806 807 static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 808 { 809 struct snd_soc_codec *codec = dai->codec; 810 811 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 812 case SND_SOC_DAIFMT_CBM_CFM: 813 snd_soc_update_bits(codec, 814 RT298_I2S_CTRL1, 0x800, 0x800); 815 break; 816 case SND_SOC_DAIFMT_CBS_CFS: 817 snd_soc_update_bits(codec, 818 RT298_I2S_CTRL1, 0x800, 0x0); 819 break; 820 default: 821 return -EINVAL; 822 } 823 824 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 825 case SND_SOC_DAIFMT_I2S: 826 snd_soc_update_bits(codec, 827 RT298_I2S_CTRL1, 0x300, 0x0); 828 break; 829 case SND_SOC_DAIFMT_LEFT_J: 830 snd_soc_update_bits(codec, 831 RT298_I2S_CTRL1, 0x300, 0x1 << 8); 832 break; 833 case SND_SOC_DAIFMT_DSP_A: 834 snd_soc_update_bits(codec, 835 RT298_I2S_CTRL1, 0x300, 0x2 << 8); 836 break; 837 case SND_SOC_DAIFMT_DSP_B: 838 snd_soc_update_bits(codec, 839 RT298_I2S_CTRL1, 0x300, 0x3 << 8); 840 break; 841 default: 842 return -EINVAL; 843 } 844 /* bit 15 Stream Type 0:PCM 1:Non-PCM */ 845 snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x8000, 0); 846 snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x8000, 0); 847 848 return 0; 849 } 850 851 static int rt298_set_dai_sysclk(struct snd_soc_dai *dai, 852 int clk_id, unsigned int freq, int dir) 853 { 854 struct snd_soc_codec *codec = dai->codec; 855 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 856 857 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); 858 859 if (RT298_SCLK_S_MCLK == clk_id) { 860 snd_soc_update_bits(codec, 861 RT298_I2S_CTRL2, 0x0100, 0x0); 862 snd_soc_update_bits(codec, 863 RT298_PLL_CTRL1, 0x20, 0x20); 864 } else { 865 snd_soc_update_bits(codec, 866 RT298_I2S_CTRL2, 0x0100, 0x0100); 867 snd_soc_update_bits(codec, 868 RT298_PLL_CTRL1, 0x20, 0x0); 869 } 870 871 switch (freq) { 872 case 19200000: 873 if (RT298_SCLK_S_MCLK == clk_id) { 874 dev_err(codec->dev, "Should not use MCLK\n"); 875 return -EINVAL; 876 } 877 snd_soc_update_bits(codec, 878 RT298_I2S_CTRL2, 0x40, 0x40); 879 break; 880 case 24000000: 881 if (RT298_SCLK_S_MCLK == clk_id) { 882 dev_err(codec->dev, "Should not use MCLK\n"); 883 return -EINVAL; 884 } 885 snd_soc_update_bits(codec, 886 RT298_I2S_CTRL2, 0x40, 0x0); 887 break; 888 case 12288000: 889 case 11289600: 890 snd_soc_update_bits(codec, 891 RT298_I2S_CTRL2, 0x8, 0x0); 892 snd_soc_update_bits(codec, 893 RT298_CLK_DIV, 0xfc1e, 0x0004); 894 break; 895 case 24576000: 896 case 22579200: 897 snd_soc_update_bits(codec, 898 RT298_I2S_CTRL2, 0x8, 0x8); 899 snd_soc_update_bits(codec, 900 RT298_CLK_DIV, 0xfc1e, 0x5406); 901 break; 902 default: 903 dev_err(codec->dev, "Unsupported system clock\n"); 904 return -EINVAL; 905 } 906 907 rt298->sys_clk = freq; 908 rt298->clk_id = clk_id; 909 910 return 0; 911 } 912 913 static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 914 { 915 struct snd_soc_codec *codec = dai->codec; 916 917 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); 918 if (50 == ratio) 919 snd_soc_update_bits(codec, 920 RT298_I2S_CTRL1, 0x1000, 0x1000); 921 else 922 snd_soc_update_bits(codec, 923 RT298_I2S_CTRL1, 0x1000, 0x0); 924 925 926 return 0; 927 } 928 929 static int rt298_set_bias_level(struct snd_soc_codec *codec, 930 enum snd_soc_bias_level level) 931 { 932 switch (level) { 933 case SND_SOC_BIAS_PREPARE: 934 if (SND_SOC_BIAS_STANDBY == 935 snd_soc_codec_get_bias_level(codec)) { 936 snd_soc_write(codec, 937 RT298_SET_AUDIO_POWER, AC_PWRST_D0); 938 snd_soc_update_bits(codec, 0x0d, 0x200, 0x200); 939 snd_soc_update_bits(codec, 0x52, 0x80, 0x0); 940 mdelay(20); 941 snd_soc_update_bits(codec, 0x0d, 0x200, 0x0); 942 snd_soc_update_bits(codec, 0x52, 0x80, 0x80); 943 } 944 break; 945 946 case SND_SOC_BIAS_STANDBY: 947 snd_soc_write(codec, 948 RT298_SET_AUDIO_POWER, AC_PWRST_D3); 949 break; 950 951 default: 952 break; 953 } 954 955 return 0; 956 } 957 958 static irqreturn_t rt298_irq(int irq, void *data) 959 { 960 struct rt298_priv *rt298 = data; 961 bool hp = false; 962 bool mic = false; 963 int ret, status = 0; 964 965 ret = rt298_jack_detect(rt298, &hp, &mic); 966 967 /* Clear IRQ */ 968 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1); 969 970 if (ret == 0) { 971 if (hp == true) 972 status |= SND_JACK_HEADPHONE; 973 974 if (mic == true) 975 status |= SND_JACK_MICROPHONE; 976 977 snd_soc_jack_report(rt298->jack, status, 978 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 979 980 pm_wakeup_event(&rt298->i2c->dev, 300); 981 } 982 983 return IRQ_HANDLED; 984 } 985 986 static int rt298_probe(struct snd_soc_codec *codec) 987 { 988 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 989 990 rt298->codec = codec; 991 992 if (rt298->i2c->irq) { 993 regmap_update_bits(rt298->regmap, 994 RT298_IRQ_CTRL, 0x2, 0x2); 995 996 INIT_DELAYED_WORK(&rt298->jack_detect_work, 997 rt298_jack_detect_work); 998 schedule_delayed_work(&rt298->jack_detect_work, 999 msecs_to_jiffies(1250)); 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int rt298_remove(struct snd_soc_codec *codec) 1006 { 1007 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 1008 1009 cancel_delayed_work_sync(&rt298->jack_detect_work); 1010 1011 return 0; 1012 } 1013 1014 #ifdef CONFIG_PM 1015 static int rt298_suspend(struct snd_soc_codec *codec) 1016 { 1017 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 1018 1019 rt298->is_hp_in = -1; 1020 regcache_cache_only(rt298->regmap, true); 1021 regcache_mark_dirty(rt298->regmap); 1022 1023 return 0; 1024 } 1025 1026 static int rt298_resume(struct snd_soc_codec *codec) 1027 { 1028 struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); 1029 1030 regcache_cache_only(rt298->regmap, false); 1031 rt298_index_sync(codec); 1032 regcache_sync(rt298->regmap); 1033 1034 return 0; 1035 } 1036 #else 1037 #define rt298_suspend NULL 1038 #define rt298_resume NULL 1039 #endif 1040 1041 #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1042 #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1043 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1044 1045 static const struct snd_soc_dai_ops rt298_aif_dai_ops = { 1046 .hw_params = rt298_hw_params, 1047 .set_fmt = rt298_set_dai_fmt, 1048 .set_sysclk = rt298_set_dai_sysclk, 1049 .set_bclk_ratio = rt298_set_bclk_ratio, 1050 }; 1051 1052 static struct snd_soc_dai_driver rt298_dai[] = { 1053 { 1054 .name = "rt298-aif1", 1055 .id = RT298_AIF1, 1056 .playback = { 1057 .stream_name = "AIF1 Playback", 1058 .channels_min = 1, 1059 .channels_max = 2, 1060 .rates = RT298_STEREO_RATES, 1061 .formats = RT298_FORMATS, 1062 }, 1063 .capture = { 1064 .stream_name = "AIF1 Capture", 1065 .channels_min = 1, 1066 .channels_max = 2, 1067 .rates = RT298_STEREO_RATES, 1068 .formats = RT298_FORMATS, 1069 }, 1070 .ops = &rt298_aif_dai_ops, 1071 .symmetric_rates = 1, 1072 }, 1073 { 1074 .name = "rt298-aif2", 1075 .id = RT298_AIF2, 1076 .playback = { 1077 .stream_name = "AIF2 Playback", 1078 .channels_min = 1, 1079 .channels_max = 2, 1080 .rates = RT298_STEREO_RATES, 1081 .formats = RT298_FORMATS, 1082 }, 1083 .capture = { 1084 .stream_name = "AIF2 Capture", 1085 .channels_min = 1, 1086 .channels_max = 2, 1087 .rates = RT298_STEREO_RATES, 1088 .formats = RT298_FORMATS, 1089 }, 1090 .ops = &rt298_aif_dai_ops, 1091 .symmetric_rates = 1, 1092 }, 1093 1094 }; 1095 1096 static struct snd_soc_codec_driver soc_codec_dev_rt298 = { 1097 .probe = rt298_probe, 1098 .remove = rt298_remove, 1099 .suspend = rt298_suspend, 1100 .resume = rt298_resume, 1101 .set_bias_level = rt298_set_bias_level, 1102 .idle_bias_off = true, 1103 .component_driver = { 1104 .controls = rt298_snd_controls, 1105 .num_controls = ARRAY_SIZE(rt298_snd_controls), 1106 .dapm_widgets = rt298_dapm_widgets, 1107 .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets), 1108 .dapm_routes = rt298_dapm_routes, 1109 .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes), 1110 }, 1111 }; 1112 1113 static const struct regmap_config rt298_regmap = { 1114 .reg_bits = 32, 1115 .val_bits = 32, 1116 .max_register = 0x02370100, 1117 .volatile_reg = rt298_volatile_register, 1118 .readable_reg = rt298_readable_register, 1119 .reg_write = rl6347a_hw_write, 1120 .reg_read = rl6347a_hw_read, 1121 .cache_type = REGCACHE_RBTREE, 1122 .reg_defaults = rt298_reg, 1123 .num_reg_defaults = ARRAY_SIZE(rt298_reg), 1124 }; 1125 1126 static const struct i2c_device_id rt298_i2c_id[] = { 1127 {"rt298", 0}, 1128 {} 1129 }; 1130 MODULE_DEVICE_TABLE(i2c, rt298_i2c_id); 1131 1132 static const struct acpi_device_id rt298_acpi_match[] = { 1133 { "INT343A", 0 }, 1134 {}, 1135 }; 1136 MODULE_DEVICE_TABLE(acpi, rt298_acpi_match); 1137 1138 static const struct dmi_system_id force_combo_jack_table[] = { 1139 { 1140 .ident = "Intel Broxton P", 1141 .matches = { 1142 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"), 1143 DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P") 1144 } 1145 }, 1146 { } 1147 }; 1148 1149 static int rt298_i2c_probe(struct i2c_client *i2c, 1150 const struct i2c_device_id *id) 1151 { 1152 struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev); 1153 struct rt298_priv *rt298; 1154 struct device *dev = &i2c->dev; 1155 const struct acpi_device_id *acpiid; 1156 int i, ret; 1157 1158 rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298), 1159 GFP_KERNEL); 1160 if (NULL == rt298) 1161 return -ENOMEM; 1162 1163 rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap); 1164 if (IS_ERR(rt298->regmap)) { 1165 ret = PTR_ERR(rt298->regmap); 1166 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1167 ret); 1168 return ret; 1169 } 1170 1171 regmap_read(rt298->regmap, 1172 RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); 1173 if (ret != RT298_VENDOR_ID) { 1174 dev_err(&i2c->dev, 1175 "Device with ID register %#x is not rt298\n", ret); 1176 return -ENODEV; 1177 } 1178 1179 rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def, 1180 sizeof(rt298_index_def), GFP_KERNEL); 1181 if (!rt298->index_cache) 1182 return -ENOMEM; 1183 1184 rt298->index_cache_size = INDEX_CACHE_SIZE; 1185 rt298->i2c = i2c; 1186 i2c_set_clientdata(i2c, rt298); 1187 1188 /* restore codec default */ 1189 for (i = 0; i < INDEX_CACHE_SIZE; i++) 1190 regmap_write(rt298->regmap, rt298->index_cache[i].reg, 1191 rt298->index_cache[i].def); 1192 for (i = 0; i < ARRAY_SIZE(rt298_reg); i++) 1193 regmap_write(rt298->regmap, rt298_reg[i].reg, 1194 rt298_reg[i].def); 1195 1196 if (pdata) 1197 rt298->pdata = *pdata; 1198 1199 /* enable jack combo mode on supported devices */ 1200 acpiid = acpi_match_device(dev->driver->acpi_match_table, dev); 1201 if (acpiid && acpiid->driver_data) { 1202 rt298->pdata = *(struct rt298_platform_data *) 1203 acpiid->driver_data; 1204 } 1205 1206 if (dmi_check_system(force_combo_jack_table)) { 1207 rt298->pdata.cbj_en = true; 1208 rt298->pdata.gpio2_en = false; 1209 } 1210 1211 /* VREF Charging */ 1212 regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80); 1213 regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860); 1214 /* Vref2 */ 1215 regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20); 1216 1217 regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3); 1218 1219 for (i = 0; i < RT298_POWER_REG_LEN; i++) 1220 regmap_write(rt298->regmap, 1221 RT298_SET_POWER(rt298_support_power_controls[i]), 1222 AC_PWRST_D1); 1223 1224 if (!rt298->pdata.cbj_en) { 1225 regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000); 1226 regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816); 1227 regmap_update_bits(rt298->regmap, 1228 RT298_CBJ_CTRL1, 0xf000, 0xb000); 1229 } else { 1230 regmap_update_bits(rt298->regmap, 1231 RT298_CBJ_CTRL1, 0xf000, 0x5000); 1232 } 1233 1234 mdelay(10); 1235 1236 if (!rt298->pdata.gpio2_en) 1237 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40); 1238 else 1239 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0); 1240 1241 mdelay(10); 1242 1243 regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000); 1244 regmap_update_bits(rt298->regmap, 1245 RT298_WIND_FILTER_CTRL, 0x0082, 0x0082); 1246 1247 regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81); 1248 regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82); 1249 regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84); 1250 regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2); 1251 1252 rt298->is_hp_in = -1; 1253 1254 if (rt298->i2c->irq) { 1255 ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq, 1256 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298); 1257 if (ret != 0) { 1258 dev_err(&i2c->dev, 1259 "Failed to reguest IRQ: %d\n", ret); 1260 return ret; 1261 } 1262 } 1263 1264 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt298, 1265 rt298_dai, ARRAY_SIZE(rt298_dai)); 1266 1267 return ret; 1268 } 1269 1270 static int rt298_i2c_remove(struct i2c_client *i2c) 1271 { 1272 struct rt298_priv *rt298 = i2c_get_clientdata(i2c); 1273 1274 if (i2c->irq) 1275 free_irq(i2c->irq, rt298); 1276 snd_soc_unregister_codec(&i2c->dev); 1277 1278 return 0; 1279 } 1280 1281 1282 static struct i2c_driver rt298_i2c_driver = { 1283 .driver = { 1284 .name = "rt298", 1285 .acpi_match_table = ACPI_PTR(rt298_acpi_match), 1286 }, 1287 .probe = rt298_i2c_probe, 1288 .remove = rt298_i2c_remove, 1289 .id_table = rt298_i2c_id, 1290 }; 1291 1292 module_i2c_driver(rt298_i2c_driver); 1293 1294 MODULE_DESCRIPTION("ASoC RT298 driver"); 1295 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 1296 MODULE_LICENSE("GPL"); 1297