1 /* 2 * rt274.c -- RT274 ALSA SoC audio codec driver 3 * 4 * Copyright 2017 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dmi.h> 21 #include <linux/acpi.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/jack.h> 30 #include <linux/workqueue.h> 31 32 #include "rl6347a.h" 33 #include "rt274.h" 34 35 #define RT274_VENDOR_ID 0x10ec0274 36 37 struct rt274_priv { 38 struct reg_default *index_cache; 39 int index_cache_size; 40 struct regmap *regmap; 41 struct snd_soc_component *component; 42 struct i2c_client *i2c; 43 struct snd_soc_jack *jack; 44 struct delayed_work jack_detect_work; 45 int sys_clk; 46 int clk_id; 47 int fs; 48 bool master; 49 }; 50 51 static const struct reg_default rt274_index_def[] = { 52 { 0x00, 0x1004 }, 53 { 0x01, 0xaaaa }, 54 { 0x02, 0x88aa }, 55 { 0x03, 0x0002 }, 56 { 0x04, 0xaa09 }, 57 { 0x05, 0x0700 }, 58 { 0x06, 0x6110 }, 59 { 0x07, 0x0200 }, 60 { 0x08, 0xa807 }, 61 { 0x09, 0x0021 }, 62 { 0x0a, 0x7770 }, 63 { 0x0b, 0x7770 }, 64 { 0x0c, 0x002b }, 65 { 0x0d, 0x2420 }, 66 { 0x0e, 0x65c0 }, 67 { 0x0f, 0x7770 }, 68 { 0x10, 0x0420 }, 69 { 0x11, 0x7418 }, 70 { 0x12, 0x6bd0 }, 71 { 0x13, 0x645f }, 72 { 0x14, 0x0400 }, 73 { 0x15, 0x8ccc }, 74 { 0x16, 0x4c50 }, 75 { 0x17, 0xff00 }, 76 { 0x18, 0x0003 }, 77 { 0x19, 0x2c11 }, 78 { 0x1a, 0x830b }, 79 { 0x1b, 0x4e4b }, 80 { 0x1c, 0x0000 }, 81 { 0x1d, 0x0000 }, 82 { 0x1e, 0x0000 }, 83 { 0x1f, 0x0000 }, 84 { 0x20, 0x51ff }, 85 { 0x21, 0x8000 }, 86 { 0x22, 0x8f00 }, 87 { 0x23, 0x88f4 }, 88 { 0x24, 0x0000 }, 89 { 0x25, 0x0000 }, 90 { 0x26, 0x0000 }, 91 { 0x27, 0x0000 }, 92 { 0x28, 0x0000 }, 93 { 0x29, 0x3000 }, 94 { 0x2a, 0x0000 }, 95 { 0x2b, 0x0000 }, 96 { 0x2c, 0x0f00 }, 97 { 0x2d, 0x100f }, 98 { 0x2e, 0x2902 }, 99 { 0x2f, 0xe280 }, 100 { 0x30, 0x1000 }, 101 { 0x31, 0x8400 }, 102 { 0x32, 0x5aaa }, 103 { 0x33, 0x8420 }, 104 { 0x34, 0xa20c }, 105 { 0x35, 0x096a }, 106 { 0x36, 0x5757 }, 107 { 0x37, 0xfe05 }, 108 { 0x38, 0x4901 }, 109 { 0x39, 0x110a }, 110 { 0x3a, 0x0010 }, 111 { 0x3b, 0x60d9 }, 112 { 0x3c, 0xf214 }, 113 { 0x3d, 0xc2ba }, 114 { 0x3e, 0xa928 }, 115 { 0x3f, 0x0000 }, 116 { 0x40, 0x9800 }, 117 { 0x41, 0x0000 }, 118 { 0x42, 0x2000 }, 119 { 0x43, 0x3d90 }, 120 { 0x44, 0x4900 }, 121 { 0x45, 0x5289 }, 122 { 0x46, 0x0004 }, 123 { 0x47, 0xa47a }, 124 { 0x48, 0xd049 }, 125 { 0x49, 0x0049 }, 126 { 0x4a, 0xa83b }, 127 { 0x4b, 0x0777 }, 128 { 0x4c, 0x065c }, 129 { 0x4d, 0x7fff }, 130 { 0x4e, 0x7fff }, 131 { 0x4f, 0x0000 }, 132 { 0x50, 0x0000 }, 133 { 0x51, 0x0000 }, 134 { 0x52, 0xbf5f }, 135 { 0x53, 0x3320 }, 136 { 0x54, 0xcc00 }, 137 { 0x55, 0x0000 }, 138 { 0x56, 0x3f00 }, 139 { 0x57, 0x0000 }, 140 { 0x58, 0x0000 }, 141 { 0x59, 0x0000 }, 142 { 0x5a, 0x1300 }, 143 { 0x5b, 0x005f }, 144 { 0x5c, 0x0000 }, 145 { 0x5d, 0x1001 }, 146 { 0x5e, 0x1000 }, 147 { 0x5f, 0x0000 }, 148 { 0x60, 0x5554 }, 149 { 0x61, 0xffc0 }, 150 { 0x62, 0xa000 }, 151 { 0x63, 0xd010 }, 152 { 0x64, 0x0000 }, 153 { 0x65, 0x3fb1 }, 154 { 0x66, 0x1881 }, 155 { 0x67, 0xc810 }, 156 { 0x68, 0x2000 }, 157 { 0x69, 0xfff0 }, 158 { 0x6a, 0x0300 }, 159 { 0x6b, 0x5060 }, 160 { 0x6c, 0x0000 }, 161 { 0x6d, 0x0000 }, 162 { 0x6e, 0x0c25 }, 163 { 0x6f, 0x0c0b }, 164 { 0x70, 0x8000 }, 165 { 0x71, 0x4008 }, 166 { 0x72, 0x0000 }, 167 { 0x73, 0x0800 }, 168 { 0x74, 0xa28f }, 169 { 0x75, 0xa050 }, 170 { 0x76, 0x7fe8 }, 171 { 0x77, 0xdb8c }, 172 { 0x78, 0x0000 }, 173 { 0x79, 0x0000 }, 174 { 0x7a, 0x2a96 }, 175 { 0x7b, 0x800f }, 176 { 0x7c, 0x0200 }, 177 { 0x7d, 0x1600 }, 178 { 0x7e, 0x0000 }, 179 { 0x7f, 0x0000 }, 180 }; 181 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def) 182 183 static const struct reg_default rt274_reg[] = { 184 { 0x00170500, 0x00000400 }, 185 { 0x00220000, 0x00000031 }, 186 { 0x00239000, 0x00000057 }, 187 { 0x0023a000, 0x00000057 }, 188 { 0x00270500, 0x00000400 }, 189 { 0x00370500, 0x00000400 }, 190 { 0x00870500, 0x00000400 }, 191 { 0x00920000, 0x00000031 }, 192 { 0x00935000, 0x00000097 }, 193 { 0x00936000, 0x00000097 }, 194 { 0x00970500, 0x00000400 }, 195 { 0x00b37000, 0x00000400 }, 196 { 0x00b37200, 0x00000400 }, 197 { 0x00b37300, 0x00000400 }, 198 { 0x00c37000, 0x00000400 }, 199 { 0x00c37100, 0x00000400 }, 200 { 0x01270500, 0x00000400 }, 201 { 0x01370500, 0x00000400 }, 202 { 0x01371f00, 0x411111f0 }, 203 { 0x01937000, 0x00000000 }, 204 { 0x01970500, 0x00000400 }, 205 { 0x02050000, 0x0000001b }, 206 { 0x02139000, 0x00000080 }, 207 { 0x0213a000, 0x00000080 }, 208 { 0x02170100, 0x00000001 }, 209 { 0x02170500, 0x00000400 }, 210 { 0x02170700, 0x00000000 }, 211 { 0x02270100, 0x00000000 }, 212 { 0x02370100, 0x00000000 }, 213 { 0x01970700, 0x00000020 }, 214 { 0x00830000, 0x00000097 }, 215 { 0x00930000, 0x00000097 }, 216 { 0x01270700, 0x00000000 }, 217 }; 218 219 static bool rt274_volatile_register(struct device *dev, unsigned int reg) 220 { 221 switch (reg) { 222 case 0 ... 0xff: 223 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 224 case RT274_GET_HP_SENSE: 225 case RT274_GET_MIC_SENSE: 226 case RT274_PROC_COEF: 227 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0): 228 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0): 229 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0): 230 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0): 231 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0): 232 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0): 233 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0): 234 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0): 235 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0): 236 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0): 237 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0): 238 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0): 239 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0): 240 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0): 241 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0): 242 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0): 243 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0): 244 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0): 245 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0): 246 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0): 247 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0): 248 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0): 249 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0): 250 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0): 251 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0): 252 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0): 253 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0): 254 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0): 255 return true; 256 default: 257 return false; 258 } 259 260 261 } 262 263 static bool rt274_readable_register(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case 0 ... 0xff: 267 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 268 case RT274_GET_HP_SENSE: 269 case RT274_GET_MIC_SENSE: 270 case RT274_SET_AUDIO_POWER: 271 case RT274_SET_HPO_POWER: 272 case RT274_SET_DMIC1_POWER: 273 case RT274_LOUT_MUX: 274 case RT274_HPO_MUX: 275 case RT274_ADC0_MUX: 276 case RT274_ADC1_MUX: 277 case RT274_SET_MIC: 278 case RT274_SET_PIN_HPO: 279 case RT274_SET_PIN_LOUT3: 280 case RT274_SET_PIN_DMIC1: 281 case RT274_SET_AMP_GAIN_HPO: 282 case RT274_SET_DMIC2_DEFAULT: 283 case RT274_DAC0L_GAIN: 284 case RT274_DAC0R_GAIN: 285 case RT274_DAC1L_GAIN: 286 case RT274_DAC1R_GAIN: 287 case RT274_ADCL_GAIN: 288 case RT274_ADCR_GAIN: 289 case RT274_MIC_GAIN: 290 case RT274_HPOL_GAIN: 291 case RT274_HPOR_GAIN: 292 case RT274_LOUTL_GAIN: 293 case RT274_LOUTR_GAIN: 294 case RT274_DAC_FORMAT: 295 case RT274_ADC_FORMAT: 296 case RT274_COEF_INDEX: 297 case RT274_PROC_COEF: 298 case RT274_SET_AMP_GAIN_ADC_IN1: 299 case RT274_SET_AMP_GAIN_ADC_IN2: 300 case RT274_SET_POWER(RT274_DAC_OUT0): 301 case RT274_SET_POWER(RT274_DAC_OUT1): 302 case RT274_SET_POWER(RT274_ADC_IN1): 303 case RT274_SET_POWER(RT274_ADC_IN2): 304 case RT274_SET_POWER(RT274_DMIC2): 305 case RT274_SET_POWER(RT274_MIC): 306 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0): 307 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0): 308 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0): 309 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0): 310 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0): 311 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0): 312 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0): 313 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0): 314 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0): 315 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0): 316 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0): 317 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0): 318 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0): 319 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0): 320 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0): 321 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0): 322 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0): 323 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0): 324 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0): 325 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0): 326 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0): 327 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0): 328 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0): 329 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0): 330 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0): 331 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0): 332 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0): 333 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0): 334 return true; 335 default: 336 return false; 337 } 338 } 339 340 #ifdef CONFIG_PM 341 static void rt274_index_sync(struct snd_soc_component *component) 342 { 343 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 344 int i; 345 346 for (i = 0; i < INDEX_CACHE_SIZE; i++) { 347 snd_soc_component_write(component, rt274->index_cache[i].reg, 348 rt274->index_cache[i].def); 349 } 350 } 351 #endif 352 353 static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic) 354 { 355 unsigned int buf; 356 int ret; 357 358 *hp = false; 359 *mic = false; 360 361 if (!rt274->component) 362 return -EINVAL; 363 364 ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf); 365 if (ret) 366 return ret; 367 368 *hp = buf & 0x80000000; 369 ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf); 370 if (ret) 371 return ret; 372 373 *mic = buf & 0x80000000; 374 375 pr_debug("*hp = %d *mic = %d\n", *hp, *mic); 376 377 return 0; 378 } 379 380 static void rt274_jack_detect_work(struct work_struct *work) 381 { 382 struct rt274_priv *rt274 = 383 container_of(work, struct rt274_priv, jack_detect_work.work); 384 int status = 0; 385 bool hp = false; 386 bool mic = false; 387 388 if (rt274_jack_detect(rt274, &hp, &mic) < 0) 389 return; 390 391 if (hp) 392 status |= SND_JACK_HEADPHONE; 393 394 if (mic) 395 status |= SND_JACK_MICROPHONE; 396 397 snd_soc_jack_report(rt274->jack, status, 398 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 399 } 400 401 static irqreturn_t rt274_irq(int irq, void *data); 402 403 static int rt274_mic_detect(struct snd_soc_component *component, 404 struct snd_soc_jack *jack, void *data) 405 { 406 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 407 408 if (jack == NULL) { 409 /* Disable jack detection */ 410 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 411 RT274_IRQ_EN, RT274_IRQ_DIS); 412 413 return 0; 414 } 415 rt274->jack = jack; 416 417 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 418 RT274_IRQ_EN, RT274_IRQ_EN); 419 420 /* Send an initial report */ 421 rt274_irq(0, rt274); 422 423 return 0; 424 } 425 426 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); 427 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 428 429 static const struct snd_kcontrol_new rt274_snd_controls[] = { 430 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN, 431 RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv), 432 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN, 433 RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv), 434 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN, 435 RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), 436 SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN, 437 RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1), 438 SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN, 439 0, 0x3, 0, mic_vol_tlv), 440 }; 441 442 static const struct snd_kcontrol_new hpol_enable_control = 443 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN, 444 RT274_MUTE_SFT, 1, 1); 445 446 static const struct snd_kcontrol_new hpor_enable_control = 447 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN, 448 RT274_MUTE_SFT, 1, 1); 449 450 static const struct snd_kcontrol_new loutl_enable_control = 451 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN, 452 RT274_MUTE_SFT, 1, 1); 453 454 static const struct snd_kcontrol_new loutr_enable_control = 455 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN, 456 RT274_MUTE_SFT, 1, 1); 457 458 /* ADC0 source */ 459 static const char * const rt274_adc_src[] = { 460 "Mic", "Line1", "Line2", "Dmic" 461 }; 462 463 static SOC_ENUM_SINGLE_DECL( 464 rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT, 465 rt274_adc_src); 466 467 static const struct snd_kcontrol_new rt274_adc0_mux = 468 SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum); 469 470 static SOC_ENUM_SINGLE_DECL( 471 rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT, 472 rt274_adc_src); 473 474 static const struct snd_kcontrol_new rt274_adc1_mux = 475 SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum); 476 477 static const char * const rt274_dac_src[] = { 478 "DAC OUT0", "DAC OUT1" 479 }; 480 /* HP-OUT source */ 481 static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX, 482 0, rt274_dac_src); 483 484 static const struct snd_kcontrol_new rt274_hpo_mux = 485 SOC_DAPM_ENUM("HPO source", rt274_hpo_enum); 486 487 /* Line out source */ 488 static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX, 489 0, rt274_dac_src); 490 491 static const struct snd_kcontrol_new rt274_lout_mux = 492 SOC_DAPM_ENUM("LOUT source", rt274_lout_enum); 493 494 static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = { 495 /* Input Lines */ 496 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 497 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 498 SND_SOC_DAPM_INPUT("MIC"), 499 SND_SOC_DAPM_INPUT("LINE1"), 500 SND_SOC_DAPM_INPUT("LINE2"), 501 502 /* DMIC */ 503 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 504 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 505 506 /* ADCs */ 507 SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0), 508 SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0), 509 510 /* ADC Mux */ 511 SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0, 512 &rt274_adc0_mux), 513 SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0, 514 &rt274_adc1_mux), 515 516 /* Audio Interface */ 517 SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 518 SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0), 519 SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 520 SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0), 521 SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0), 522 SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0), 523 SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0), 524 SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0), 525 526 /* Output Side */ 527 /* DACs */ 528 SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0), 529 SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0), 530 531 /* Output Mux */ 532 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux), 533 SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux), 534 535 SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO, 536 RT274_SET_PIN_SFT, 0, NULL, 0), 537 SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3, 538 RT274_SET_PIN_SFT, 0, NULL, 0), 539 540 /* Output Mixer */ 541 SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0, 542 NULL, 0), 543 SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0, 544 NULL, 0), 545 546 /* Output Pga */ 547 SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0, 548 &loutl_enable_control), 549 SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0, 550 &loutr_enable_control), 551 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, 552 &hpol_enable_control), 553 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, 554 &hpor_enable_control), 555 556 /* Output Lines */ 557 SND_SOC_DAPM_OUTPUT("HPO Pin"), 558 SND_SOC_DAPM_OUTPUT("SPDIF"), 559 SND_SOC_DAPM_OUTPUT("LINE3"), 560 }; 561 562 static const struct snd_soc_dapm_route rt274_dapm_routes[] = { 563 {"DMIC1", NULL, "DMIC1 Pin"}, 564 {"DMIC2", NULL, "DMIC2 Pin"}, 565 566 {"ADC 0 Mux", "Mic", "MIC"}, 567 {"ADC 0 Mux", "Dmic", "DMIC1"}, 568 {"ADC 0 Mux", "Line1", "LINE1"}, 569 {"ADC 0 Mux", "Line2", "LINE2"}, 570 {"ADC 1 Mux", "Mic", "MIC"}, 571 {"ADC 1 Mux", "Dmic", "DMIC2"}, 572 {"ADC 1 Mux", "Line1", "LINE1"}, 573 {"ADC 1 Mux", "Line2", "LINE2"}, 574 575 {"ADC 0", NULL, "ADC 0 Mux"}, 576 {"ADC 1", NULL, "ADC 1 Mux"}, 577 578 {"AIF1TXL", NULL, "ADC 0"}, 579 {"AIF1TXR", NULL, "ADC 0"}, 580 {"AIF2TXL", NULL, "ADC 1"}, 581 {"AIF2TXR", NULL, "ADC 1"}, 582 583 {"DAC 0", NULL, "AIF1RXL"}, 584 {"DAC 0", NULL, "AIF1RXR"}, 585 {"DAC 1", NULL, "AIF2RXL"}, 586 {"DAC 1", NULL, "AIF2RXR"}, 587 588 {"DAC OUT0", NULL, "DAC 0"}, 589 590 {"DAC OUT1", NULL, "DAC 1"}, 591 592 {"LOUT Mux", "DAC OUT0", "DAC OUT0"}, 593 {"LOUT Mux", "DAC OUT1", "DAC OUT1"}, 594 595 {"LOUT L", "Switch", "LOUT Mux"}, 596 {"LOUT R", "Switch", "LOUT Mux"}, 597 {"LOUT L", NULL, "LOUT Power"}, 598 {"LOUT R", NULL, "LOUT Power"}, 599 600 {"LINE3", NULL, "LOUT L"}, 601 {"LINE3", NULL, "LOUT R"}, 602 603 {"HPO Mux", "DAC OUT0", "DAC OUT0"}, 604 {"HPO Mux", "DAC OUT1", "DAC OUT1"}, 605 606 {"HPO L", "Switch", "HPO Mux"}, 607 {"HPO R", "Switch", "HPO Mux"}, 608 {"HPO L", NULL, "HP Power"}, 609 {"HPO R", NULL, "HP Power"}, 610 611 {"HPO Pin", NULL, "HPO L"}, 612 {"HPO Pin", NULL, "HPO R"}, 613 }; 614 615 static int rt274_hw_params(struct snd_pcm_substream *substream, 616 struct snd_pcm_hw_params *params, 617 struct snd_soc_dai *dai) 618 { 619 struct snd_soc_component *component = dai->component; 620 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 621 unsigned int val = 0; 622 int d_len_code = 0, c_len_code = 0; 623 624 switch (params_rate(params)) { 625 /* bit 14 0:48K 1:44.1K */ 626 case 44100: 627 case 48000: 628 break; 629 default: 630 dev_err(component->dev, "Unsupported sample rate %d\n", 631 params_rate(params)); 632 return -EINVAL; 633 } 634 switch (rt274->sys_clk) { 635 case 12288000: 636 case 24576000: 637 if (params_rate(params) != 48000) { 638 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 639 params_rate(params), rt274->sys_clk); 640 return -EINVAL; 641 } 642 break; 643 case 11289600: 644 case 22579200: 645 if (params_rate(params) != 44100) { 646 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 647 params_rate(params), rt274->sys_clk); 648 return -EINVAL; 649 } 650 break; 651 } 652 653 if (params_channels(params) <= 16) { 654 /* bit 3:0 Number of Channel */ 655 val |= (params_channels(params) - 1); 656 } else { 657 dev_err(component->dev, "Unsupported channels %d\n", 658 params_channels(params)); 659 return -EINVAL; 660 } 661 662 switch (params_width(params)) { 663 /* bit 6:4 Bits per Sample */ 664 case 16: 665 d_len_code = 0; 666 c_len_code = 0; 667 val |= (0x1 << 4); 668 break; 669 case 32: 670 d_len_code = 2; 671 c_len_code = 3; 672 val |= (0x4 << 4); 673 break; 674 case 20: 675 d_len_code = 1; 676 c_len_code = 1; 677 val |= (0x2 << 4); 678 break; 679 case 24: 680 d_len_code = 2; 681 c_len_code = 2; 682 val |= (0x3 << 4); 683 break; 684 case 8: 685 d_len_code = 3; 686 c_len_code = 0; 687 break; 688 default: 689 return -EINVAL; 690 } 691 692 if (rt274->master) 693 c_len_code = 0x3; 694 695 snd_soc_component_update_bits(component, 696 RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14); 697 dev_dbg(component->dev, "format val = 0x%x\n", val); 698 699 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val); 700 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val); 701 702 return 0; 703 } 704 705 static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 706 { 707 struct snd_soc_component *component = dai->component; 708 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 709 710 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 711 case SND_SOC_DAIFMT_CBM_CFM: 712 snd_soc_component_update_bits(component, 713 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M); 714 rt274->master = true; 715 break; 716 case SND_SOC_DAIFMT_CBS_CFS: 717 snd_soc_component_update_bits(component, 718 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S); 719 rt274->master = false; 720 break; 721 default: 722 return -EINVAL; 723 } 724 725 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 726 case SND_SOC_DAIFMT_I2S: 727 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 728 RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S); 729 break; 730 case SND_SOC_DAIFMT_LEFT_J: 731 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 732 RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ); 733 break; 734 case SND_SOC_DAIFMT_DSP_A: 735 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 736 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA); 737 break; 738 case SND_SOC_DAIFMT_DSP_B: 739 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 740 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB); 741 break; 742 default: 743 return -EINVAL; 744 } 745 /* bit 15 Stream Type 0:PCM 1:Non-PCM */ 746 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0); 747 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0); 748 749 return 0; 750 } 751 752 static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 753 unsigned int freq_in, unsigned int freq_out) 754 { 755 struct snd_soc_component *component = dai->component; 756 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 757 758 switch (source) { 759 case RT274_PLL2_S_MCLK: 760 snd_soc_component_update_bits(component, RT274_PLL2_CTRL, 761 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK); 762 break; 763 default: 764 dev_warn(component->dev, "invalid pll source, use BCLK\n"); 765 /* fall through */ 766 case RT274_PLL2_S_BCLK: 767 snd_soc_component_update_bits(component, RT274_PLL2_CTRL, 768 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK); 769 break; 770 } 771 772 if (source == RT274_PLL2_S_BCLK) { 773 snd_soc_component_update_bits(component, RT274_MCLK_CTRL, 774 (0x3 << 12), (0x3 << 12)); 775 switch (rt274->fs) { 776 case 50: 777 snd_soc_component_write(component, 0x7a, 0xaab6); 778 snd_soc_component_write(component, 0x7b, 0x0301); 779 snd_soc_component_write(component, 0x7c, 0x04fe); 780 break; 781 case 64: 782 snd_soc_component_write(component, 0x7a, 0xaa96); 783 snd_soc_component_write(component, 0x7b, 0x8003); 784 snd_soc_component_write(component, 0x7c, 0x081e); 785 break; 786 case 128: 787 snd_soc_component_write(component, 0x7a, 0xaa96); 788 snd_soc_component_write(component, 0x7b, 0x8003); 789 snd_soc_component_write(component, 0x7c, 0x080e); 790 break; 791 default: 792 dev_warn(component->dev, "invalid freq_in, assume 4.8M\n"); 793 /* fall through */ 794 case 100: 795 snd_soc_component_write(component, 0x7a, 0xaab6); 796 snd_soc_component_write(component, 0x7b, 0x0301); 797 snd_soc_component_write(component, 0x7c, 0x047e); 798 break; 799 } 800 } 801 802 return 0; 803 } 804 805 static int rt274_set_dai_sysclk(struct snd_soc_dai *dai, 806 int clk_id, unsigned int freq, int dir) 807 { 808 struct snd_soc_component *component = dai->component; 809 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 810 unsigned int clk_src, mclk_en; 811 812 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq); 813 814 switch (clk_id) { 815 case RT274_SCLK_S_MCLK: 816 mclk_en = RT274_MCLK_MODE_EN; 817 clk_src = RT274_CLK_SRC_MCLK; 818 break; 819 case RT274_SCLK_S_PLL1: 820 mclk_en = RT274_MCLK_MODE_DIS; 821 clk_src = RT274_CLK_SRC_MCLK; 822 break; 823 case RT274_SCLK_S_PLL2: 824 mclk_en = RT274_MCLK_MODE_EN; 825 clk_src = RT274_CLK_SRC_PLL2; 826 break; 827 default: 828 mclk_en = RT274_MCLK_MODE_DIS; 829 clk_src = RT274_CLK_SRC_MCLK; 830 dev_warn(component->dev, "invalid sysclk source, use PLL1\n"); 831 break; 832 } 833 snd_soc_component_update_bits(component, RT274_MCLK_CTRL, 834 RT274_MCLK_MODE_MASK, mclk_en); 835 snd_soc_component_update_bits(component, RT274_CLK_CTRL, 836 RT274_CLK_SRC_MASK, clk_src); 837 838 switch (freq) { 839 case 19200000: 840 if (clk_id == RT274_SCLK_S_MCLK) { 841 dev_err(component->dev, "Should not use MCLK\n"); 842 return -EINVAL; 843 } 844 snd_soc_component_update_bits(component, 845 RT274_I2S_CTRL2, 0x40, 0x40); 846 break; 847 case 24000000: 848 if (clk_id == RT274_SCLK_S_MCLK) { 849 dev_err(component->dev, "Should not use MCLK\n"); 850 return -EINVAL; 851 } 852 snd_soc_component_update_bits(component, 853 RT274_I2S_CTRL2, 0x40, 0x0); 854 break; 855 case 12288000: 856 case 11289600: 857 snd_soc_component_update_bits(component, 858 RT274_MCLK_CTRL, 0x1fcf, 0x0008); 859 break; 860 case 24576000: 861 case 22579200: 862 snd_soc_component_update_bits(component, 863 RT274_MCLK_CTRL, 0x1fcf, 0x1543); 864 break; 865 default: 866 dev_err(component->dev, "Unsupported system clock\n"); 867 return -EINVAL; 868 } 869 870 rt274->sys_clk = freq; 871 rt274->clk_id = clk_id; 872 873 return 0; 874 } 875 876 static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 877 { 878 struct snd_soc_component *component = dai->component; 879 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 880 881 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 882 rt274->fs = ratio; 883 if ((ratio / 50) == 0) 884 snd_soc_component_update_bits(component, 885 RT274_I2S_CTRL1, 0x1000, 0x1000); 886 else 887 snd_soc_component_update_bits(component, 888 RT274_I2S_CTRL1, 0x1000, 0x0); 889 890 891 return 0; 892 } 893 894 static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 895 unsigned int rx_mask, int slots, int slot_width) 896 897 { 898 struct snd_soc_component *component = dai->component; 899 900 if (rx_mask || tx_mask) { 901 snd_soc_component_update_bits(component, 902 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN); 903 } else { 904 snd_soc_component_update_bits(component, 905 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS); 906 return 0; 907 } 908 909 switch (slots) { 910 case 4: 911 snd_soc_component_update_bits(component, 912 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH); 913 break; 914 case 2: 915 snd_soc_component_update_bits(component, 916 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH); 917 break; 918 default: 919 dev_err(component->dev, 920 "Support 2 or 4 slots TDM only\n"); 921 return -EINVAL; 922 } 923 924 return 0; 925 } 926 927 static int rt274_set_bias_level(struct snd_soc_component *component, 928 enum snd_soc_bias_level level) 929 { 930 switch (level) { 931 case SND_SOC_BIAS_PREPARE: 932 if (SND_SOC_BIAS_STANDBY == 933 snd_soc_component_get_bias_level(component)) { 934 snd_soc_component_write(component, 935 RT274_SET_AUDIO_POWER, AC_PWRST_D0); 936 } 937 break; 938 939 case SND_SOC_BIAS_STANDBY: 940 snd_soc_component_write(component, 941 RT274_SET_AUDIO_POWER, AC_PWRST_D3); 942 break; 943 944 default: 945 break; 946 } 947 948 return 0; 949 } 950 951 static irqreturn_t rt274_irq(int irq, void *data) 952 { 953 struct rt274_priv *rt274 = data; 954 bool hp = false; 955 bool mic = false; 956 int ret, status = 0; 957 958 /* Clear IRQ */ 959 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 960 RT274_IRQ_CLR, RT274_IRQ_CLR); 961 962 ret = rt274_jack_detect(rt274, &hp, &mic); 963 964 if (ret == 0) { 965 if (hp) 966 status |= SND_JACK_HEADPHONE; 967 968 if (mic) 969 status |= SND_JACK_MICROPHONE; 970 971 snd_soc_jack_report(rt274->jack, status, 972 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 973 974 pm_wakeup_event(&rt274->i2c->dev, 300); 975 } 976 977 return IRQ_HANDLED; 978 } 979 980 static int rt274_probe(struct snd_soc_component *component) 981 { 982 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 983 984 rt274->component = component; 985 986 if (rt274->i2c->irq) { 987 INIT_DELAYED_WORK(&rt274->jack_detect_work, 988 rt274_jack_detect_work); 989 schedule_delayed_work(&rt274->jack_detect_work, 990 msecs_to_jiffies(1250)); 991 } 992 993 return 0; 994 } 995 996 static void rt274_remove(struct snd_soc_component *component) 997 { 998 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 999 1000 cancel_delayed_work_sync(&rt274->jack_detect_work); 1001 } 1002 1003 #ifdef CONFIG_PM 1004 static int rt274_suspend(struct snd_soc_component *component) 1005 { 1006 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 1007 1008 regcache_cache_only(rt274->regmap, true); 1009 regcache_mark_dirty(rt274->regmap); 1010 1011 return 0; 1012 } 1013 1014 static int rt274_resume(struct snd_soc_component *component) 1015 { 1016 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 1017 1018 regcache_cache_only(rt274->regmap, false); 1019 rt274_index_sync(component); 1020 regcache_sync(rt274->regmap); 1021 1022 return 0; 1023 } 1024 #else 1025 #define rt274_suspend NULL 1026 #define rt274_resume NULL 1027 #endif 1028 1029 #define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1030 #define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1031 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1032 1033 static const struct snd_soc_dai_ops rt274_aif_dai_ops = { 1034 .hw_params = rt274_hw_params, 1035 .set_fmt = rt274_set_dai_fmt, 1036 .set_sysclk = rt274_set_dai_sysclk, 1037 .set_pll = rt274_set_dai_pll, 1038 .set_bclk_ratio = rt274_set_bclk_ratio, 1039 .set_tdm_slot = rt274_set_tdm_slot, 1040 }; 1041 1042 static struct snd_soc_dai_driver rt274_dai[] = { 1043 { 1044 .name = "rt274-aif1", 1045 .id = RT274_AIF1, 1046 .playback = { 1047 .stream_name = "AIF1 Playback", 1048 .channels_min = 1, 1049 .channels_max = 2, 1050 .rates = RT274_STEREO_RATES, 1051 .formats = RT274_FORMATS, 1052 }, 1053 .capture = { 1054 .stream_name = "AIF1 Capture", 1055 .channels_min = 1, 1056 .channels_max = 2, 1057 .rates = RT274_STEREO_RATES, 1058 .formats = RT274_FORMATS, 1059 }, 1060 .ops = &rt274_aif_dai_ops, 1061 .symmetric_rates = 1, 1062 }, 1063 }; 1064 1065 static const struct snd_soc_component_driver soc_component_dev_rt274 = { 1066 .probe = rt274_probe, 1067 .remove = rt274_remove, 1068 .suspend = rt274_suspend, 1069 .resume = rt274_resume, 1070 .set_bias_level = rt274_set_bias_level, 1071 .set_jack = rt274_mic_detect, 1072 .controls = rt274_snd_controls, 1073 .num_controls = ARRAY_SIZE(rt274_snd_controls), 1074 .dapm_widgets = rt274_dapm_widgets, 1075 .num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets), 1076 .dapm_routes = rt274_dapm_routes, 1077 .num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes), 1078 .use_pmdown_time = 1, 1079 .endianness = 1, 1080 .non_legacy_dai_naming = 1, 1081 }; 1082 1083 static const struct regmap_config rt274_regmap = { 1084 .reg_bits = 32, 1085 .val_bits = 32, 1086 .max_register = 0x05bfffff, 1087 .volatile_reg = rt274_volatile_register, 1088 .readable_reg = rt274_readable_register, 1089 .reg_write = rl6347a_hw_write, 1090 .reg_read = rl6347a_hw_read, 1091 .cache_type = REGCACHE_RBTREE, 1092 .reg_defaults = rt274_reg, 1093 .num_reg_defaults = ARRAY_SIZE(rt274_reg), 1094 }; 1095 1096 #ifdef CONFIG_OF 1097 static const struct of_device_id rt274_of_match[] = { 1098 {.compatible = "realtek,rt274"}, 1099 {}, 1100 }; 1101 MODULE_DEVICE_TABLE(of, rt274_of_match); 1102 #endif 1103 1104 static const struct i2c_device_id rt274_i2c_id[] = { 1105 {"rt274", 0}, 1106 {} 1107 }; 1108 MODULE_DEVICE_TABLE(i2c, rt274_i2c_id); 1109 1110 static const struct acpi_device_id rt274_acpi_match[] = { 1111 { "10EC0274", 0 }, 1112 { "INT34C2", 0 }, 1113 {}, 1114 }; 1115 MODULE_DEVICE_TABLE(acpi, rt274_acpi_match); 1116 1117 static int rt274_i2c_probe(struct i2c_client *i2c, 1118 const struct i2c_device_id *id) 1119 { 1120 struct rt274_priv *rt274; 1121 1122 int ret; 1123 unsigned int val; 1124 1125 rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274), 1126 GFP_KERNEL); 1127 if (rt274 == NULL) 1128 return -ENOMEM; 1129 1130 rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap); 1131 if (IS_ERR(rt274->regmap)) { 1132 ret = PTR_ERR(rt274->regmap); 1133 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1134 ret); 1135 return ret; 1136 } 1137 1138 ret = regmap_read(rt274->regmap, 1139 RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val); 1140 if (ret) 1141 return ret; 1142 1143 if (val != RT274_VENDOR_ID) { 1144 dev_err(&i2c->dev, 1145 "Device with ID register %#x is not rt274\n", val); 1146 return -ENODEV; 1147 } 1148 1149 rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def, 1150 sizeof(rt274_index_def), GFP_KERNEL); 1151 if (!rt274->index_cache) 1152 return -ENOMEM; 1153 1154 rt274->index_cache_size = INDEX_CACHE_SIZE; 1155 rt274->i2c = i2c; 1156 i2c_set_clientdata(i2c, rt274); 1157 1158 /* reset codec */ 1159 regmap_write(rt274->regmap, RT274_RESET, 0); 1160 regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000); 1161 1162 /* Set Pad PDB is floating */ 1163 regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0); 1164 regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01); 1165 regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540); 1166 regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100); 1167 /* Combo jack auto detect */ 1168 regmap_write(rt274->regmap, 0x4a, 0x201b); 1169 /* Aux mode off */ 1170 regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000); 1171 /* HP DC Calibration */ 1172 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0); 1173 /* Set NID=58h.Index 00h [15]= 1b; */ 1174 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00); 1175 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888); 1176 msleep(500); 1177 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb); 1178 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00); 1179 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888); 1180 /* Set pin widget */ 1181 regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40); 1182 regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40); 1183 regmap_write(rt274->regmap, RT274_SET_MIC, 0x20); 1184 regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20); 1185 1186 regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004); 1187 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 1188 RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK); 1189 1190 /* jack detection */ 1191 regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81); 1192 regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82); 1193 1194 if (rt274->i2c->irq) { 1195 ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq, 1196 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274); 1197 if (ret != 0) { 1198 dev_err(&i2c->dev, 1199 "Failed to reguest IRQ: %d\n", ret); 1200 return ret; 1201 } 1202 } 1203 1204 ret = devm_snd_soc_register_component(&i2c->dev, 1205 &soc_component_dev_rt274, 1206 rt274_dai, ARRAY_SIZE(rt274_dai)); 1207 1208 return ret; 1209 } 1210 1211 static int rt274_i2c_remove(struct i2c_client *i2c) 1212 { 1213 struct rt274_priv *rt274 = i2c_get_clientdata(i2c); 1214 1215 if (i2c->irq) 1216 free_irq(i2c->irq, rt274); 1217 1218 return 0; 1219 } 1220 1221 1222 static struct i2c_driver rt274_i2c_driver = { 1223 .driver = { 1224 .name = "rt274", 1225 .acpi_match_table = ACPI_PTR(rt274_acpi_match), 1226 #ifdef CONFIG_OF 1227 .of_match_table = of_match_ptr(rt274_of_match), 1228 #endif 1229 }, 1230 .probe = rt274_i2c_probe, 1231 .remove = rt274_i2c_remove, 1232 .id_table = rt274_i2c_id, 1233 }; 1234 1235 module_i2c_driver(rt274_i2c_driver); 1236 1237 MODULE_DESCRIPTION("ASoC RT274 driver"); 1238 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 1239 MODULE_LICENSE("GPL v2"); 1240