1 /* 2 * rt274.c -- RT274 ALSA SoC audio codec driver 3 * 4 * Copyright 2017 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dmi.h> 21 #include <linux/acpi.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/jack.h> 30 #include <linux/workqueue.h> 31 32 #include "rl6347a.h" 33 #include "rt274.h" 34 35 #define RT274_VENDOR_ID 0x10ec0274 36 37 struct rt274_priv { 38 struct reg_default *index_cache; 39 int index_cache_size; 40 struct regmap *regmap; 41 struct snd_soc_component *component; 42 struct i2c_client *i2c; 43 struct snd_soc_jack *jack; 44 struct delayed_work jack_detect_work; 45 int sys_clk; 46 int clk_id; 47 int fs; 48 bool master; 49 }; 50 51 static const struct reg_default rt274_index_def[] = { 52 { 0x00, 0x1004 }, 53 { 0x01, 0xaaaa }, 54 { 0x02, 0x88aa }, 55 { 0x03, 0x0002 }, 56 { 0x04, 0xaa09 }, 57 { 0x05, 0x0700 }, 58 { 0x06, 0x6110 }, 59 { 0x07, 0x0200 }, 60 { 0x08, 0xa807 }, 61 { 0x09, 0x0021 }, 62 { 0x0a, 0x7770 }, 63 { 0x0b, 0x7770 }, 64 { 0x0c, 0x002b }, 65 { 0x0d, 0x2420 }, 66 { 0x0e, 0x65c0 }, 67 { 0x0f, 0x7770 }, 68 { 0x10, 0x0420 }, 69 { 0x11, 0x7418 }, 70 { 0x12, 0x6bd0 }, 71 { 0x13, 0x645f }, 72 { 0x14, 0x0400 }, 73 { 0x15, 0x8ccc }, 74 { 0x16, 0x4c50 }, 75 { 0x17, 0xff00 }, 76 { 0x18, 0x0003 }, 77 { 0x19, 0x2c11 }, 78 { 0x1a, 0x830b }, 79 { 0x1b, 0x4e4b }, 80 { 0x1c, 0x0000 }, 81 { 0x1d, 0x0000 }, 82 { 0x1e, 0x0000 }, 83 { 0x1f, 0x0000 }, 84 { 0x20, 0x51ff }, 85 { 0x21, 0x8000 }, 86 { 0x22, 0x8f00 }, 87 { 0x23, 0x88f4 }, 88 { 0x24, 0x0000 }, 89 { 0x25, 0x0000 }, 90 { 0x26, 0x0000 }, 91 { 0x27, 0x0000 }, 92 { 0x28, 0x0000 }, 93 { 0x29, 0x3000 }, 94 { 0x2a, 0x0000 }, 95 { 0x2b, 0x0000 }, 96 { 0x2c, 0x0f00 }, 97 { 0x2d, 0x100f }, 98 { 0x2e, 0x2902 }, 99 { 0x2f, 0xe280 }, 100 { 0x30, 0x1000 }, 101 { 0x31, 0x8400 }, 102 { 0x32, 0x5aaa }, 103 { 0x33, 0x8420 }, 104 { 0x34, 0xa20c }, 105 { 0x35, 0x096a }, 106 { 0x36, 0x5757 }, 107 { 0x37, 0xfe05 }, 108 { 0x38, 0x4901 }, 109 { 0x39, 0x110a }, 110 { 0x3a, 0x0010 }, 111 { 0x3b, 0x60d9 }, 112 { 0x3c, 0xf214 }, 113 { 0x3d, 0xc2ba }, 114 { 0x3e, 0xa928 }, 115 { 0x3f, 0x0000 }, 116 { 0x40, 0x9800 }, 117 { 0x41, 0x0000 }, 118 { 0x42, 0x2000 }, 119 { 0x43, 0x3d90 }, 120 { 0x44, 0x4900 }, 121 { 0x45, 0x5289 }, 122 { 0x46, 0x0004 }, 123 { 0x47, 0xa47a }, 124 { 0x48, 0xd049 }, 125 { 0x49, 0x0049 }, 126 { 0x4a, 0xa83b }, 127 { 0x4b, 0x0777 }, 128 { 0x4c, 0x065c }, 129 { 0x4d, 0x7fff }, 130 { 0x4e, 0x7fff }, 131 { 0x4f, 0x0000 }, 132 { 0x50, 0x0000 }, 133 { 0x51, 0x0000 }, 134 { 0x52, 0xbf5f }, 135 { 0x53, 0x3320 }, 136 { 0x54, 0xcc00 }, 137 { 0x55, 0x0000 }, 138 { 0x56, 0x3f00 }, 139 { 0x57, 0x0000 }, 140 { 0x58, 0x0000 }, 141 { 0x59, 0x0000 }, 142 { 0x5a, 0x1300 }, 143 { 0x5b, 0x005f }, 144 { 0x5c, 0x0000 }, 145 { 0x5d, 0x1001 }, 146 { 0x5e, 0x1000 }, 147 { 0x5f, 0x0000 }, 148 { 0x60, 0x5554 }, 149 { 0x61, 0xffc0 }, 150 { 0x62, 0xa000 }, 151 { 0x63, 0xd010 }, 152 { 0x64, 0x0000 }, 153 { 0x65, 0x3fb1 }, 154 { 0x66, 0x1881 }, 155 { 0x67, 0xc810 }, 156 { 0x68, 0x2000 }, 157 { 0x69, 0xfff0 }, 158 { 0x6a, 0x0300 }, 159 { 0x6b, 0x5060 }, 160 { 0x6c, 0x0000 }, 161 { 0x6d, 0x0000 }, 162 { 0x6e, 0x0c25 }, 163 { 0x6f, 0x0c0b }, 164 { 0x70, 0x8000 }, 165 { 0x71, 0x4008 }, 166 { 0x72, 0x0000 }, 167 { 0x73, 0x0800 }, 168 { 0x74, 0xa28f }, 169 { 0x75, 0xa050 }, 170 { 0x76, 0x7fe8 }, 171 { 0x77, 0xdb8c }, 172 { 0x78, 0x0000 }, 173 { 0x79, 0x0000 }, 174 { 0x7a, 0x2a96 }, 175 { 0x7b, 0x800f }, 176 { 0x7c, 0x0200 }, 177 { 0x7d, 0x1600 }, 178 { 0x7e, 0x0000 }, 179 { 0x7f, 0x0000 }, 180 }; 181 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def) 182 183 static const struct reg_default rt274_reg[] = { 184 { 0x00170500, 0x00000400 }, 185 { 0x00220000, 0x00000031 }, 186 { 0x00239000, 0x00000057 }, 187 { 0x0023a000, 0x00000057 }, 188 { 0x00270500, 0x00000400 }, 189 { 0x00370500, 0x00000400 }, 190 { 0x00870500, 0x00000400 }, 191 { 0x00920000, 0x00000031 }, 192 { 0x00935000, 0x00000097 }, 193 { 0x00936000, 0x00000097 }, 194 { 0x00970500, 0x00000400 }, 195 { 0x00b37000, 0x00000400 }, 196 { 0x00b37200, 0x00000400 }, 197 { 0x00b37300, 0x00000400 }, 198 { 0x00c37000, 0x00000400 }, 199 { 0x00c37100, 0x00000400 }, 200 { 0x01270500, 0x00000400 }, 201 { 0x01370500, 0x00000400 }, 202 { 0x01371f00, 0x411111f0 }, 203 { 0x01937000, 0x00000000 }, 204 { 0x01970500, 0x00000400 }, 205 { 0x02050000, 0x0000001b }, 206 { 0x02139000, 0x00000080 }, 207 { 0x0213a000, 0x00000080 }, 208 { 0x02170100, 0x00000001 }, 209 { 0x02170500, 0x00000400 }, 210 { 0x02170700, 0x00000000 }, 211 { 0x02270100, 0x00000000 }, 212 { 0x02370100, 0x00000000 }, 213 { 0x01970700, 0x00000020 }, 214 { 0x00830000, 0x00000097 }, 215 { 0x00930000, 0x00000097 }, 216 { 0x01270700, 0x00000000 }, 217 }; 218 219 static bool rt274_volatile_register(struct device *dev, unsigned int reg) 220 { 221 switch (reg) { 222 case 0 ... 0xff: 223 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 224 case RT274_GET_HP_SENSE: 225 case RT274_GET_MIC_SENSE: 226 case RT274_PROC_COEF: 227 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0): 228 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0): 229 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0): 230 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0): 231 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0): 232 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0): 233 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0): 234 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0): 235 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0): 236 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0): 237 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0): 238 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0): 239 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0): 240 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0): 241 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0): 242 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0): 243 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0): 244 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0): 245 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0): 246 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0): 247 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0): 248 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0): 249 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0): 250 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0): 251 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0): 252 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0): 253 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0): 254 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0): 255 return true; 256 default: 257 return false; 258 } 259 260 261 } 262 263 static bool rt274_readable_register(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case 0 ... 0xff: 267 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): 268 case RT274_GET_HP_SENSE: 269 case RT274_GET_MIC_SENSE: 270 case RT274_SET_AUDIO_POWER: 271 case RT274_SET_HPO_POWER: 272 case RT274_SET_DMIC1_POWER: 273 case RT274_LOUT_MUX: 274 case RT274_HPO_MUX: 275 case RT274_ADC0_MUX: 276 case RT274_ADC1_MUX: 277 case RT274_SET_MIC: 278 case RT274_SET_PIN_HPO: 279 case RT274_SET_PIN_LOUT3: 280 case RT274_SET_PIN_DMIC1: 281 case RT274_SET_AMP_GAIN_HPO: 282 case RT274_SET_DMIC2_DEFAULT: 283 case RT274_DAC0L_GAIN: 284 case RT274_DAC0R_GAIN: 285 case RT274_DAC1L_GAIN: 286 case RT274_DAC1R_GAIN: 287 case RT274_ADCL_GAIN: 288 case RT274_ADCR_GAIN: 289 case RT274_MIC_GAIN: 290 case RT274_HPOL_GAIN: 291 case RT274_HPOR_GAIN: 292 case RT274_LOUTL_GAIN: 293 case RT274_LOUTR_GAIN: 294 case RT274_DAC_FORMAT: 295 case RT274_ADC_FORMAT: 296 case RT274_COEF_INDEX: 297 case RT274_PROC_COEF: 298 case RT274_SET_AMP_GAIN_ADC_IN1: 299 case RT274_SET_AMP_GAIN_ADC_IN2: 300 case RT274_SET_POWER(RT274_DAC_OUT0): 301 case RT274_SET_POWER(RT274_DAC_OUT1): 302 case RT274_SET_POWER(RT274_ADC_IN1): 303 case RT274_SET_POWER(RT274_ADC_IN2): 304 case RT274_SET_POWER(RT274_DMIC2): 305 case RT274_SET_POWER(RT274_MIC): 306 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0): 307 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0): 308 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0): 309 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0): 310 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0): 311 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0): 312 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0): 313 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0): 314 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0): 315 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0): 316 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0): 317 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0): 318 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0): 319 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0): 320 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0): 321 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0): 322 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0): 323 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0): 324 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0): 325 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0): 326 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0): 327 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0): 328 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0): 329 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0): 330 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0): 331 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0): 332 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0): 333 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0): 334 return true; 335 default: 336 return false; 337 } 338 } 339 340 #ifdef CONFIG_PM 341 static void rt274_index_sync(struct snd_soc_component *component) 342 { 343 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 344 int i; 345 346 for (i = 0; i < INDEX_CACHE_SIZE; i++) { 347 snd_soc_component_write(component, rt274->index_cache[i].reg, 348 rt274->index_cache[i].def); 349 } 350 } 351 #endif 352 353 static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic) 354 { 355 unsigned int buf; 356 int ret; 357 358 *hp = false; 359 *mic = false; 360 361 if (!rt274->component) 362 return -EINVAL; 363 364 ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf); 365 if (ret) 366 return ret; 367 368 *hp = buf & 0x80000000; 369 ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf); 370 if (ret) 371 return ret; 372 373 *mic = buf & 0x80000000; 374 375 pr_debug("*hp = %d *mic = %d\n", *hp, *mic); 376 377 return 0; 378 } 379 380 static void rt274_jack_detect_work(struct work_struct *work) 381 { 382 struct rt274_priv *rt274 = 383 container_of(work, struct rt274_priv, jack_detect_work.work); 384 int status = 0; 385 bool hp = false; 386 bool mic = false; 387 388 if (rt274_jack_detect(rt274, &hp, &mic) < 0) 389 return; 390 391 if (hp) 392 status |= SND_JACK_HEADPHONE; 393 394 if (mic) 395 status |= SND_JACK_MICROPHONE; 396 397 snd_soc_jack_report(rt274->jack, status, 398 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 399 } 400 401 static irqreturn_t rt274_irq(int irq, void *data); 402 403 static int rt274_mic_detect(struct snd_soc_component *component, 404 struct snd_soc_jack *jack, void *data) 405 { 406 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 407 408 rt274->jack = jack; 409 410 if (jack == NULL) { 411 /* Disable jack detection */ 412 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 413 RT274_IRQ_EN, RT274_IRQ_DIS); 414 415 return 0; 416 } 417 418 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 419 RT274_IRQ_EN, RT274_IRQ_EN); 420 421 /* Send an initial report */ 422 rt274_irq(0, rt274); 423 424 return 0; 425 } 426 427 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); 428 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 429 430 static const struct snd_kcontrol_new rt274_snd_controls[] = { 431 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN, 432 RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv), 433 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN, 434 RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv), 435 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN, 436 RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), 437 SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN, 438 RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1), 439 SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN, 440 0, 0x3, 0, mic_vol_tlv), 441 }; 442 443 static const struct snd_kcontrol_new hpol_enable_control = 444 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN, 445 RT274_MUTE_SFT, 1, 1); 446 447 static const struct snd_kcontrol_new hpor_enable_control = 448 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN, 449 RT274_MUTE_SFT, 1, 1); 450 451 static const struct snd_kcontrol_new loutl_enable_control = 452 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN, 453 RT274_MUTE_SFT, 1, 1); 454 455 static const struct snd_kcontrol_new loutr_enable_control = 456 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN, 457 RT274_MUTE_SFT, 1, 1); 458 459 /* ADC0 source */ 460 static const char * const rt274_adc_src[] = { 461 "Mic", "Line1", "Line2", "Dmic" 462 }; 463 464 static SOC_ENUM_SINGLE_DECL( 465 rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT, 466 rt274_adc_src); 467 468 static const struct snd_kcontrol_new rt274_adc0_mux = 469 SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum); 470 471 static SOC_ENUM_SINGLE_DECL( 472 rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT, 473 rt274_adc_src); 474 475 static const struct snd_kcontrol_new rt274_adc1_mux = 476 SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum); 477 478 static const char * const rt274_dac_src[] = { 479 "DAC OUT0", "DAC OUT1" 480 }; 481 /* HP-OUT source */ 482 static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX, 483 0, rt274_dac_src); 484 485 static const struct snd_kcontrol_new rt274_hpo_mux = 486 SOC_DAPM_ENUM("HPO source", rt274_hpo_enum); 487 488 /* Line out source */ 489 static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX, 490 0, rt274_dac_src); 491 492 static const struct snd_kcontrol_new rt274_lout_mux = 493 SOC_DAPM_ENUM("LOUT source", rt274_lout_enum); 494 495 static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = { 496 /* Input Lines */ 497 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 498 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 499 SND_SOC_DAPM_INPUT("MIC"), 500 SND_SOC_DAPM_INPUT("LINE1"), 501 SND_SOC_DAPM_INPUT("LINE2"), 502 503 /* DMIC */ 504 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 505 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 506 507 /* ADCs */ 508 SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0), 509 SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0), 510 511 /* ADC Mux */ 512 SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0, 513 &rt274_adc0_mux), 514 SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0, 515 &rt274_adc1_mux), 516 517 /* Audio Interface */ 518 SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 519 SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0), 520 SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 521 SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0), 522 SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0), 523 SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0), 524 SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0), 525 SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0), 526 527 /* Output Side */ 528 /* DACs */ 529 SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0), 530 SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0), 531 532 /* Output Mux */ 533 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux), 534 SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux), 535 536 SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO, 537 RT274_SET_PIN_SFT, 0, NULL, 0), 538 SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3, 539 RT274_SET_PIN_SFT, 0, NULL, 0), 540 541 /* Output Mixer */ 542 SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0, 543 NULL, 0), 544 SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0, 545 NULL, 0), 546 547 /* Output Pga */ 548 SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0, 549 &loutl_enable_control), 550 SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0, 551 &loutr_enable_control), 552 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, 553 &hpol_enable_control), 554 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, 555 &hpor_enable_control), 556 557 /* Output Lines */ 558 SND_SOC_DAPM_OUTPUT("HPO Pin"), 559 SND_SOC_DAPM_OUTPUT("SPDIF"), 560 SND_SOC_DAPM_OUTPUT("LINE3"), 561 }; 562 563 static const struct snd_soc_dapm_route rt274_dapm_routes[] = { 564 {"DMIC1", NULL, "DMIC1 Pin"}, 565 {"DMIC2", NULL, "DMIC2 Pin"}, 566 567 {"ADC 0 Mux", "Mic", "MIC"}, 568 {"ADC 0 Mux", "Dmic", "DMIC1"}, 569 {"ADC 0 Mux", "Line1", "LINE1"}, 570 {"ADC 0 Mux", "Line2", "LINE2"}, 571 {"ADC 1 Mux", "Mic", "MIC"}, 572 {"ADC 1 Mux", "Dmic", "DMIC2"}, 573 {"ADC 1 Mux", "Line1", "LINE1"}, 574 {"ADC 1 Mux", "Line2", "LINE2"}, 575 576 {"ADC 0", NULL, "ADC 0 Mux"}, 577 {"ADC 1", NULL, "ADC 1 Mux"}, 578 579 {"AIF1TXL", NULL, "ADC 0"}, 580 {"AIF1TXR", NULL, "ADC 0"}, 581 {"AIF2TXL", NULL, "ADC 1"}, 582 {"AIF2TXR", NULL, "ADC 1"}, 583 584 {"DAC 0", NULL, "AIF1RXL"}, 585 {"DAC 0", NULL, "AIF1RXR"}, 586 {"DAC 1", NULL, "AIF2RXL"}, 587 {"DAC 1", NULL, "AIF2RXR"}, 588 589 {"DAC OUT0", NULL, "DAC 0"}, 590 591 {"DAC OUT1", NULL, "DAC 1"}, 592 593 {"LOUT Mux", "DAC OUT0", "DAC OUT0"}, 594 {"LOUT Mux", "DAC OUT1", "DAC OUT1"}, 595 596 {"LOUT L", "Switch", "LOUT Mux"}, 597 {"LOUT R", "Switch", "LOUT Mux"}, 598 {"LOUT L", NULL, "LOUT Power"}, 599 {"LOUT R", NULL, "LOUT Power"}, 600 601 {"LINE3", NULL, "LOUT L"}, 602 {"LINE3", NULL, "LOUT R"}, 603 604 {"HPO Mux", "DAC OUT0", "DAC OUT0"}, 605 {"HPO Mux", "DAC OUT1", "DAC OUT1"}, 606 607 {"HPO L", "Switch", "HPO Mux"}, 608 {"HPO R", "Switch", "HPO Mux"}, 609 {"HPO L", NULL, "HP Power"}, 610 {"HPO R", NULL, "HP Power"}, 611 612 {"HPO Pin", NULL, "HPO L"}, 613 {"HPO Pin", NULL, "HPO R"}, 614 }; 615 616 static int rt274_hw_params(struct snd_pcm_substream *substream, 617 struct snd_pcm_hw_params *params, 618 struct snd_soc_dai *dai) 619 { 620 struct snd_soc_component *component = dai->component; 621 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 622 unsigned int val = 0; 623 int d_len_code = 0, c_len_code = 0; 624 625 switch (params_rate(params)) { 626 /* bit 14 0:48K 1:44.1K */ 627 case 44100: 628 case 48000: 629 break; 630 default: 631 dev_err(component->dev, "Unsupported sample rate %d\n", 632 params_rate(params)); 633 return -EINVAL; 634 } 635 switch (rt274->sys_clk) { 636 case 12288000: 637 case 24576000: 638 if (params_rate(params) != 48000) { 639 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 640 params_rate(params), rt274->sys_clk); 641 return -EINVAL; 642 } 643 break; 644 case 11289600: 645 case 22579200: 646 if (params_rate(params) != 44100) { 647 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", 648 params_rate(params), rt274->sys_clk); 649 return -EINVAL; 650 } 651 break; 652 } 653 654 if (params_channels(params) <= 16) { 655 /* bit 3:0 Number of Channel */ 656 val |= (params_channels(params) - 1); 657 } else { 658 dev_err(component->dev, "Unsupported channels %d\n", 659 params_channels(params)); 660 return -EINVAL; 661 } 662 663 switch (params_width(params)) { 664 /* bit 6:4 Bits per Sample */ 665 case 16: 666 d_len_code = 0; 667 c_len_code = 0; 668 val |= (0x1 << 4); 669 break; 670 case 32: 671 d_len_code = 2; 672 c_len_code = 3; 673 val |= (0x4 << 4); 674 break; 675 case 20: 676 d_len_code = 1; 677 c_len_code = 1; 678 val |= (0x2 << 4); 679 break; 680 case 24: 681 d_len_code = 2; 682 c_len_code = 2; 683 val |= (0x3 << 4); 684 break; 685 case 8: 686 d_len_code = 3; 687 c_len_code = 0; 688 break; 689 default: 690 return -EINVAL; 691 } 692 693 if (rt274->master) 694 c_len_code = 0x3; 695 696 snd_soc_component_update_bits(component, 697 RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14); 698 dev_dbg(component->dev, "format val = 0x%x\n", val); 699 700 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val); 701 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val); 702 703 return 0; 704 } 705 706 static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 707 { 708 struct snd_soc_component *component = dai->component; 709 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 710 711 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 712 case SND_SOC_DAIFMT_CBM_CFM: 713 snd_soc_component_update_bits(component, 714 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M); 715 rt274->master = true; 716 break; 717 case SND_SOC_DAIFMT_CBS_CFS: 718 snd_soc_component_update_bits(component, 719 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S); 720 rt274->master = false; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 727 case SND_SOC_DAIFMT_I2S: 728 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 729 RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S); 730 break; 731 case SND_SOC_DAIFMT_LEFT_J: 732 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 733 RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ); 734 break; 735 case SND_SOC_DAIFMT_DSP_A: 736 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 737 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA); 738 break; 739 case SND_SOC_DAIFMT_DSP_B: 740 snd_soc_component_update_bits(component, RT274_I2S_CTRL1, 741 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB); 742 break; 743 default: 744 return -EINVAL; 745 } 746 /* bit 15 Stream Type 0:PCM 1:Non-PCM */ 747 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0); 748 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0); 749 750 return 0; 751 } 752 753 static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 754 unsigned int freq_in, unsigned int freq_out) 755 { 756 struct snd_soc_component *component = dai->component; 757 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 758 759 switch (source) { 760 case RT274_PLL2_S_MCLK: 761 snd_soc_component_update_bits(component, RT274_PLL2_CTRL, 762 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK); 763 break; 764 default: 765 dev_warn(component->dev, "invalid pll source, use BCLK\n"); 766 /* fall through */ 767 case RT274_PLL2_S_BCLK: 768 snd_soc_component_update_bits(component, RT274_PLL2_CTRL, 769 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK); 770 break; 771 } 772 773 if (source == RT274_PLL2_S_BCLK) { 774 snd_soc_component_update_bits(component, RT274_MCLK_CTRL, 775 (0x3 << 12), (0x3 << 12)); 776 switch (rt274->fs) { 777 case 50: 778 snd_soc_component_write(component, 0x7a, 0xaab6); 779 snd_soc_component_write(component, 0x7b, 0x0301); 780 snd_soc_component_write(component, 0x7c, 0x04fe); 781 break; 782 case 64: 783 snd_soc_component_write(component, 0x7a, 0xaa96); 784 snd_soc_component_write(component, 0x7b, 0x8003); 785 snd_soc_component_write(component, 0x7c, 0x081e); 786 break; 787 case 128: 788 snd_soc_component_write(component, 0x7a, 0xaa96); 789 snd_soc_component_write(component, 0x7b, 0x8003); 790 snd_soc_component_write(component, 0x7c, 0x080e); 791 break; 792 default: 793 dev_warn(component->dev, "invalid freq_in, assume 4.8M\n"); 794 /* fall through */ 795 case 100: 796 snd_soc_component_write(component, 0x7a, 0xaab6); 797 snd_soc_component_write(component, 0x7b, 0x0301); 798 snd_soc_component_write(component, 0x7c, 0x047e); 799 break; 800 } 801 } 802 803 return 0; 804 } 805 806 static int rt274_set_dai_sysclk(struct snd_soc_dai *dai, 807 int clk_id, unsigned int freq, int dir) 808 { 809 struct snd_soc_component *component = dai->component; 810 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 811 unsigned int clk_src, mclk_en; 812 813 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq); 814 815 switch (clk_id) { 816 case RT274_SCLK_S_MCLK: 817 mclk_en = RT274_MCLK_MODE_EN; 818 clk_src = RT274_CLK_SRC_MCLK; 819 break; 820 case RT274_SCLK_S_PLL1: 821 mclk_en = RT274_MCLK_MODE_DIS; 822 clk_src = RT274_CLK_SRC_MCLK; 823 break; 824 case RT274_SCLK_S_PLL2: 825 mclk_en = RT274_MCLK_MODE_EN; 826 clk_src = RT274_CLK_SRC_PLL2; 827 break; 828 default: 829 mclk_en = RT274_MCLK_MODE_DIS; 830 clk_src = RT274_CLK_SRC_MCLK; 831 dev_warn(component->dev, "invalid sysclk source, use PLL1\n"); 832 break; 833 } 834 snd_soc_component_update_bits(component, RT274_MCLK_CTRL, 835 RT274_MCLK_MODE_MASK, mclk_en); 836 snd_soc_component_update_bits(component, RT274_CLK_CTRL, 837 RT274_CLK_SRC_MASK, clk_src); 838 839 switch (freq) { 840 case 19200000: 841 if (clk_id == RT274_SCLK_S_MCLK) { 842 dev_err(component->dev, "Should not use MCLK\n"); 843 return -EINVAL; 844 } 845 snd_soc_component_update_bits(component, 846 RT274_I2S_CTRL2, 0x40, 0x40); 847 break; 848 case 24000000: 849 if (clk_id == RT274_SCLK_S_MCLK) { 850 dev_err(component->dev, "Should not use MCLK\n"); 851 return -EINVAL; 852 } 853 snd_soc_component_update_bits(component, 854 RT274_I2S_CTRL2, 0x40, 0x0); 855 break; 856 case 12288000: 857 case 11289600: 858 snd_soc_component_update_bits(component, 859 RT274_MCLK_CTRL, 0x1fcf, 0x0008); 860 break; 861 case 24576000: 862 case 22579200: 863 snd_soc_component_update_bits(component, 864 RT274_MCLK_CTRL, 0x1fcf, 0x1543); 865 break; 866 default: 867 dev_err(component->dev, "Unsupported system clock\n"); 868 return -EINVAL; 869 } 870 871 rt274->sys_clk = freq; 872 rt274->clk_id = clk_id; 873 874 return 0; 875 } 876 877 static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 878 { 879 struct snd_soc_component *component = dai->component; 880 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 881 882 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 883 rt274->fs = ratio; 884 if ((ratio / 50) == 0) 885 snd_soc_component_update_bits(component, 886 RT274_I2S_CTRL1, 0x1000, 0x1000); 887 else 888 snd_soc_component_update_bits(component, 889 RT274_I2S_CTRL1, 0x1000, 0x0); 890 891 892 return 0; 893 } 894 895 static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 896 unsigned int rx_mask, int slots, int slot_width) 897 898 { 899 struct snd_soc_component *component = dai->component; 900 901 if (rx_mask || tx_mask) { 902 snd_soc_component_update_bits(component, 903 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN); 904 } else { 905 snd_soc_component_update_bits(component, 906 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS); 907 return 0; 908 } 909 910 switch (slots) { 911 case 4: 912 snd_soc_component_update_bits(component, 913 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH); 914 break; 915 case 2: 916 snd_soc_component_update_bits(component, 917 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH); 918 break; 919 default: 920 dev_err(component->dev, 921 "Support 2 or 4 slots TDM only\n"); 922 return -EINVAL; 923 } 924 925 return 0; 926 } 927 928 static int rt274_set_bias_level(struct snd_soc_component *component, 929 enum snd_soc_bias_level level) 930 { 931 switch (level) { 932 case SND_SOC_BIAS_PREPARE: 933 if (SND_SOC_BIAS_STANDBY == 934 snd_soc_component_get_bias_level(component)) { 935 snd_soc_component_write(component, 936 RT274_SET_AUDIO_POWER, AC_PWRST_D0); 937 } 938 break; 939 940 case SND_SOC_BIAS_STANDBY: 941 snd_soc_component_write(component, 942 RT274_SET_AUDIO_POWER, AC_PWRST_D3); 943 break; 944 945 default: 946 break; 947 } 948 949 return 0; 950 } 951 952 static irqreturn_t rt274_irq(int irq, void *data) 953 { 954 struct rt274_priv *rt274 = data; 955 bool hp = false; 956 bool mic = false; 957 int ret, status = 0; 958 959 /* Clear IRQ */ 960 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 961 RT274_IRQ_CLR, RT274_IRQ_CLR); 962 963 ret = rt274_jack_detect(rt274, &hp, &mic); 964 965 if (ret == 0) { 966 if (hp) 967 status |= SND_JACK_HEADPHONE; 968 969 if (mic) 970 status |= SND_JACK_MICROPHONE; 971 972 snd_soc_jack_report(rt274->jack, status, 973 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); 974 975 pm_wakeup_event(&rt274->i2c->dev, 300); 976 } 977 978 return IRQ_HANDLED; 979 } 980 981 static int rt274_probe(struct snd_soc_component *component) 982 { 983 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 984 985 rt274->component = component; 986 987 if (rt274->i2c->irq) { 988 INIT_DELAYED_WORK(&rt274->jack_detect_work, 989 rt274_jack_detect_work); 990 schedule_delayed_work(&rt274->jack_detect_work, 991 msecs_to_jiffies(1250)); 992 } 993 994 return 0; 995 } 996 997 static void rt274_remove(struct snd_soc_component *component) 998 { 999 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 1000 1001 cancel_delayed_work_sync(&rt274->jack_detect_work); 1002 } 1003 1004 #ifdef CONFIG_PM 1005 static int rt274_suspend(struct snd_soc_component *component) 1006 { 1007 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 1008 1009 regcache_cache_only(rt274->regmap, true); 1010 regcache_mark_dirty(rt274->regmap); 1011 1012 return 0; 1013 } 1014 1015 static int rt274_resume(struct snd_soc_component *component) 1016 { 1017 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component); 1018 1019 regcache_cache_only(rt274->regmap, false); 1020 rt274_index_sync(component); 1021 regcache_sync(rt274->regmap); 1022 1023 return 0; 1024 } 1025 #else 1026 #define rt274_suspend NULL 1027 #define rt274_resume NULL 1028 #endif 1029 1030 #define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1031 #define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1032 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1033 1034 static const struct snd_soc_dai_ops rt274_aif_dai_ops = { 1035 .hw_params = rt274_hw_params, 1036 .set_fmt = rt274_set_dai_fmt, 1037 .set_sysclk = rt274_set_dai_sysclk, 1038 .set_pll = rt274_set_dai_pll, 1039 .set_bclk_ratio = rt274_set_bclk_ratio, 1040 .set_tdm_slot = rt274_set_tdm_slot, 1041 }; 1042 1043 static struct snd_soc_dai_driver rt274_dai[] = { 1044 { 1045 .name = "rt274-aif1", 1046 .id = RT274_AIF1, 1047 .playback = { 1048 .stream_name = "AIF1 Playback", 1049 .channels_min = 1, 1050 .channels_max = 2, 1051 .rates = RT274_STEREO_RATES, 1052 .formats = RT274_FORMATS, 1053 }, 1054 .capture = { 1055 .stream_name = "AIF1 Capture", 1056 .channels_min = 1, 1057 .channels_max = 2, 1058 .rates = RT274_STEREO_RATES, 1059 .formats = RT274_FORMATS, 1060 }, 1061 .ops = &rt274_aif_dai_ops, 1062 .symmetric_rates = 1, 1063 }, 1064 }; 1065 1066 static const struct snd_soc_component_driver soc_component_dev_rt274 = { 1067 .probe = rt274_probe, 1068 .remove = rt274_remove, 1069 .suspend = rt274_suspend, 1070 .resume = rt274_resume, 1071 .set_bias_level = rt274_set_bias_level, 1072 .set_jack = rt274_mic_detect, 1073 .controls = rt274_snd_controls, 1074 .num_controls = ARRAY_SIZE(rt274_snd_controls), 1075 .dapm_widgets = rt274_dapm_widgets, 1076 .num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets), 1077 .dapm_routes = rt274_dapm_routes, 1078 .num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes), 1079 .use_pmdown_time = 1, 1080 .endianness = 1, 1081 .non_legacy_dai_naming = 1, 1082 }; 1083 1084 static const struct regmap_config rt274_regmap = { 1085 .reg_bits = 32, 1086 .val_bits = 32, 1087 .max_register = 0x05bfffff, 1088 .volatile_reg = rt274_volatile_register, 1089 .readable_reg = rt274_readable_register, 1090 .reg_write = rl6347a_hw_write, 1091 .reg_read = rl6347a_hw_read, 1092 .cache_type = REGCACHE_RBTREE, 1093 .reg_defaults = rt274_reg, 1094 .num_reg_defaults = ARRAY_SIZE(rt274_reg), 1095 }; 1096 1097 #ifdef CONFIG_OF 1098 static const struct of_device_id rt274_of_match[] = { 1099 {.compatible = "realtek,rt274"}, 1100 {}, 1101 }; 1102 MODULE_DEVICE_TABLE(of, rt274_of_match); 1103 #endif 1104 1105 static const struct i2c_device_id rt274_i2c_id[] = { 1106 {"rt274", 0}, 1107 {} 1108 }; 1109 MODULE_DEVICE_TABLE(i2c, rt274_i2c_id); 1110 1111 static const struct acpi_device_id rt274_acpi_match[] = { 1112 { "10EC0274", 0 }, 1113 { "INT34C2", 0 }, 1114 {}, 1115 }; 1116 MODULE_DEVICE_TABLE(acpi, rt274_acpi_match); 1117 1118 static int rt274_i2c_probe(struct i2c_client *i2c, 1119 const struct i2c_device_id *id) 1120 { 1121 struct rt274_priv *rt274; 1122 1123 int ret; 1124 unsigned int val; 1125 1126 rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274), 1127 GFP_KERNEL); 1128 if (rt274 == NULL) 1129 return -ENOMEM; 1130 1131 rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap); 1132 if (IS_ERR(rt274->regmap)) { 1133 ret = PTR_ERR(rt274->regmap); 1134 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1135 ret); 1136 return ret; 1137 } 1138 1139 ret = regmap_read(rt274->regmap, 1140 RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val); 1141 if (ret) 1142 return ret; 1143 1144 if (val != RT274_VENDOR_ID) { 1145 dev_err(&i2c->dev, 1146 "Device with ID register %#x is not rt274\n", val); 1147 return -ENODEV; 1148 } 1149 1150 rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def, 1151 sizeof(rt274_index_def), GFP_KERNEL); 1152 if (!rt274->index_cache) 1153 return -ENOMEM; 1154 1155 rt274->index_cache_size = INDEX_CACHE_SIZE; 1156 rt274->i2c = i2c; 1157 i2c_set_clientdata(i2c, rt274); 1158 1159 /* reset codec */ 1160 regmap_write(rt274->regmap, RT274_RESET, 0); 1161 regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000); 1162 1163 /* Set Pad PDB is floating */ 1164 regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0); 1165 regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01); 1166 regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540); 1167 regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100); 1168 /* Combo jack auto detect */ 1169 regmap_write(rt274->regmap, 0x4a, 0x201b); 1170 /* Aux mode off */ 1171 regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000); 1172 /* HP DC Calibration */ 1173 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0); 1174 /* Set NID=58h.Index 00h [15]= 1b; */ 1175 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00); 1176 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888); 1177 msleep(500); 1178 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb); 1179 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00); 1180 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888); 1181 /* Set pin widget */ 1182 regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40); 1183 regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40); 1184 regmap_write(rt274->regmap, RT274_SET_MIC, 0x20); 1185 regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20); 1186 1187 regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004); 1188 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL, 1189 RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK); 1190 1191 /* jack detection */ 1192 regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81); 1193 regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82); 1194 1195 if (rt274->i2c->irq) { 1196 ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq, 1197 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274); 1198 if (ret != 0) { 1199 dev_err(&i2c->dev, 1200 "Failed to reguest IRQ: %d\n", ret); 1201 return ret; 1202 } 1203 } 1204 1205 ret = devm_snd_soc_register_component(&i2c->dev, 1206 &soc_component_dev_rt274, 1207 rt274_dai, ARRAY_SIZE(rt274_dai)); 1208 1209 return ret; 1210 } 1211 1212 static int rt274_i2c_remove(struct i2c_client *i2c) 1213 { 1214 struct rt274_priv *rt274 = i2c_get_clientdata(i2c); 1215 1216 if (i2c->irq) 1217 free_irq(i2c->irq, rt274); 1218 1219 return 0; 1220 } 1221 1222 1223 static struct i2c_driver rt274_i2c_driver = { 1224 .driver = { 1225 .name = "rt274", 1226 .acpi_match_table = ACPI_PTR(rt274_acpi_match), 1227 #ifdef CONFIG_OF 1228 .of_match_table = of_match_ptr(rt274_of_match), 1229 #endif 1230 }, 1231 .probe = rt274_i2c_probe, 1232 .remove = rt274_i2c_remove, 1233 .id_table = rt274_i2c_id, 1234 }; 1235 1236 module_i2c_driver(rt274_i2c_driver); 1237 1238 MODULE_DESCRIPTION("ASoC RT274 driver"); 1239 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 1240 MODULE_LICENSE("GPL v2"); 1241