1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2021 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <sound/core.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/sdw.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/initval.h> 20 #include "rt1316-sdw.h" 21 22 static const struct reg_default rt1316_reg_defaults[] = { 23 { 0x3004, 0x00 }, 24 { 0x3005, 0x00 }, 25 { 0x3206, 0x00 }, 26 { 0xc001, 0x00 }, 27 { 0xc002, 0x00 }, 28 { 0xc003, 0x00 }, 29 { 0xc004, 0x00 }, 30 { 0xc005, 0x00 }, 31 { 0xc006, 0x00 }, 32 { 0xc007, 0x00 }, 33 { 0xc008, 0x00 }, 34 { 0xc009, 0x00 }, 35 { 0xc00a, 0x00 }, 36 { 0xc00b, 0x00 }, 37 { 0xc00c, 0x00 }, 38 { 0xc00d, 0x00 }, 39 { 0xc00e, 0x00 }, 40 { 0xc00f, 0x00 }, 41 { 0xc010, 0xa5 }, 42 { 0xc011, 0x00 }, 43 { 0xc012, 0xff }, 44 { 0xc013, 0xff }, 45 { 0xc014, 0x40 }, 46 { 0xc015, 0x00 }, 47 { 0xc016, 0x00 }, 48 { 0xc017, 0x00 }, 49 { 0xc605, 0x30 }, 50 { 0xc700, 0x0a }, 51 { 0xc701, 0xaa }, 52 { 0xc702, 0x1a }, 53 { 0xc703, 0x0a }, 54 { 0xc710, 0x80 }, 55 { 0xc711, 0x00 }, 56 { 0xc712, 0x3e }, 57 { 0xc713, 0x80 }, 58 { 0xc714, 0x80 }, 59 { 0xc715, 0x06 }, 60 { 0xd101, 0x00 }, 61 { 0xd102, 0x30 }, 62 { 0xd103, 0x00 }, 63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 }, 67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 69 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 70 }; 71 72 static const struct reg_sequence rt1316_blind_write[] = { 73 { 0xc710, 0x17 }, 74 { 0xc711, 0x80 }, 75 { 0xc712, 0x26 }, 76 { 0xc713, 0x06 }, 77 { 0xc714, 0x80 }, 78 { 0xc715, 0x06 }, 79 { 0xc702, 0x0a }, 80 { 0xc703, 0x0a }, 81 { 0xc001, 0x45 }, 82 { 0xc003, 0x00 }, 83 { 0xc004, 0x11 }, 84 { 0xc005, 0x00 }, 85 { 0xc006, 0x00 }, 86 { 0xc106, 0x00 }, 87 { 0xc007, 0x11 }, 88 { 0xc008, 0x11 }, 89 { 0xc009, 0x00 }, 90 91 { 0x2f0a, 0x00 }, 92 { 0xd101, 0xf0 }, 93 { 0xd103, 0x9b }, 94 { 0x2f36, 0x8e }, 95 { 0x3206, 0x80 }, 96 { 0x3211, 0x0b }, 97 { 0x3216, 0x06 }, 98 { 0xc614, 0x20 }, 99 { 0xc615, 0x0a }, 100 { 0xc616, 0x02 }, 101 { 0xc617, 0x00 }, 102 { 0xc60b, 0x10 }, 103 { 0xc60e, 0x05 }, 104 { 0xc102, 0x00 }, 105 { 0xc090, 0xb0 }, 106 { 0xc00f, 0x01 }, 107 { 0xc09c, 0x7b }, 108 109 { 0xc602, 0x07 }, 110 { 0xc603, 0x07 }, 111 { 0xc0a3, 0x71 }, 112 { 0xc00b, 0x30 }, 113 { 0xc093, 0x80 }, 114 { 0xc09d, 0x80 }, 115 { 0xc0b0, 0x77 }, 116 { 0xc010, 0xa5 }, 117 { 0xc050, 0x83 }, 118 { 0x2f55, 0x03 }, 119 { 0x3217, 0xb5 }, 120 { 0x3202, 0x02 }, 121 122 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 }, 123 124 /* for IV sense */ 125 { 0x2232, 0x80 }, 126 { 0xc0b0, 0x77 }, 127 { 0xc011, 0x00 }, 128 { 0xc020, 0x00 }, 129 { 0xc023, 0x00 }, 130 { 0x3101, 0x00 }, 131 { 0x3004, 0xa0 }, 132 { 0x3005, 0xb1 }, 133 { 0xc007, 0x11 }, 134 { 0xc008, 0x11 }, 135 { 0xc009, 0x00 }, 136 { 0xc022, 0xd6 }, 137 { 0xc025, 0xd6 }, 138 139 { 0xd001, 0x03 }, 140 { 0xd002, 0xbf }, 141 { 0xd003, 0x03 }, 142 { 0xd004, 0xbf }, 143 }; 144 145 static bool rt1316_readable_register(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case 0x2f0a: 149 case 0x2f36: 150 case 0x3203 ... 0x320e: 151 case 0xc000 ... 0xc7b4: 152 case 0xcf00 ... 0xcf03: 153 case 0xd101 ... 0xd103: 154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0): 155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L): 156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R): 157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 160 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 161 return true; 162 default: 163 return false; 164 } 165 } 166 167 static bool rt1316_volatile_register(struct device *dev, unsigned int reg) 168 { 169 switch (reg) { 170 case 0xc000: 171 case 0xc093: 172 case 0xc09d: 173 case 0xc0a3: 174 case 0xc201: 175 case 0xc427 ... 0xc428: 176 case 0xd102: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static const struct regmap_config rt1316_sdw_regmap = { 184 .reg_bits = 32, 185 .val_bits = 8, 186 .readable_reg = rt1316_readable_register, 187 .volatile_reg = rt1316_volatile_register, 188 .max_register = 0x4108ffff, 189 .reg_defaults = rt1316_reg_defaults, 190 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults), 191 .cache_type = REGCACHE_MAPLE, 192 .use_single_read = true, 193 .use_single_write = true, 194 }; 195 196 static int rt1316_read_prop(struct sdw_slave *slave) 197 { 198 struct sdw_slave_prop *prop = &slave->prop; 199 int nval; 200 int i, j; 201 u32 bit; 202 unsigned long addr; 203 struct sdw_dpn_prop *dpn; 204 205 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 206 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 207 208 prop->paging_support = true; 209 210 /* first we need to allocate memory for set bits in port lists */ 211 prop->source_ports = 0x04; /* BITMAP: 00000100 */ 212 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 213 214 nval = hweight32(prop->source_ports); 215 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 216 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 217 if (!prop->src_dpn_prop) 218 return -ENOMEM; 219 220 i = 0; 221 dpn = prop->src_dpn_prop; 222 addr = prop->source_ports; 223 for_each_set_bit(bit, &addr, 32) { 224 dpn[i].num = bit; 225 dpn[i].type = SDW_DPN_FULL; 226 dpn[i].simple_ch_prep_sm = true; 227 dpn[i].ch_prep_timeout = 10; 228 i++; 229 } 230 231 /* do this again for sink now */ 232 nval = hweight32(prop->sink_ports); 233 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 234 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 235 if (!prop->sink_dpn_prop) 236 return -ENOMEM; 237 238 j = 0; 239 dpn = prop->sink_dpn_prop; 240 addr = prop->sink_ports; 241 for_each_set_bit(bit, &addr, 32) { 242 dpn[j].num = bit; 243 dpn[j].type = SDW_DPN_FULL; 244 dpn[j].simple_ch_prep_sm = true; 245 dpn[j].ch_prep_timeout = 10; 246 j++; 247 } 248 249 /* set the timeout values */ 250 prop->clk_stop_timeout = 20; 251 252 dev_dbg(&slave->dev, "%s\n", __func__); 253 254 return 0; 255 } 256 257 static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316) 258 { 259 unsigned int i, reg, data; 260 261 for (i = 0; i < rt1316->bq_params_cnt; i += 3) { 262 reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8); 263 data = rt1316->bq_params[i + 2]; 264 regmap_write(rt1316->regmap, reg, data); 265 } 266 } 267 268 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave) 269 { 270 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 271 272 if (rt1316->hw_init) 273 return 0; 274 275 if (rt1316->first_hw_init) { 276 regcache_cache_only(rt1316->regmap, false); 277 regcache_cache_bypass(rt1316->regmap, true); 278 } else { 279 /* 280 * PM runtime is only enabled when a Slave reports as Attached 281 */ 282 283 /* set autosuspend parameters */ 284 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 285 pm_runtime_use_autosuspend(&slave->dev); 286 287 /* update count of parent 'active' children */ 288 pm_runtime_set_active(&slave->dev); 289 290 /* make sure the device does not suspend immediately */ 291 pm_runtime_mark_last_busy(&slave->dev); 292 293 pm_runtime_enable(&slave->dev); 294 } 295 296 pm_runtime_get_noresume(&slave->dev); 297 298 /* sw reset */ 299 regmap_write(rt1316->regmap, 0xc000, 0x02); 300 301 /* initial settings - blind write */ 302 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write, 303 ARRAY_SIZE(rt1316_blind_write)); 304 305 if (rt1316->first_hw_init) { 306 regcache_cache_bypass(rt1316->regmap, false); 307 regcache_mark_dirty(rt1316->regmap); 308 } else 309 rt1316->first_hw_init = true; 310 311 /* Mark Slave initialization complete */ 312 rt1316->hw_init = true; 313 314 pm_runtime_mark_last_busy(&slave->dev); 315 pm_runtime_put_autosuspend(&slave->dev); 316 317 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 318 return 0; 319 } 320 321 static int rt1316_update_status(struct sdw_slave *slave, 322 enum sdw_slave_status status) 323 { 324 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 325 326 if (status == SDW_SLAVE_UNATTACHED) 327 rt1316->hw_init = false; 328 329 /* 330 * Perform initialization only if slave status is present and 331 * hw_init flag is false 332 */ 333 if (rt1316->hw_init || status != SDW_SLAVE_ATTACHED) 334 return 0; 335 336 /* perform I/O transfers required for Slave initialization */ 337 return rt1316_io_init(&slave->dev, slave); 338 } 339 340 static int rt1316_classd_event(struct snd_soc_dapm_widget *w, 341 struct snd_kcontrol *kcontrol, int event) 342 { 343 struct snd_soc_component *component = 344 snd_soc_dapm_to_component(w->dapm); 345 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 346 unsigned char ps0 = 0x0, ps3 = 0x3; 347 348 switch (event) { 349 case SND_SOC_DAPM_POST_PMU: 350 regmap_write(rt1316->regmap, 351 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 352 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 353 ps0); 354 regmap_write(rt1316->regmap, 355 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 356 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 357 ps0); 358 regmap_write(rt1316->regmap, 359 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 360 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 361 ps0); 362 break; 363 case SND_SOC_DAPM_PRE_PMD: 364 regmap_write(rt1316->regmap, 365 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 366 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 367 ps3); 368 regmap_write(rt1316->regmap, 369 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 370 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 371 ps3); 372 regmap_write(rt1316->regmap, 373 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 374 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 375 ps3); 376 break; 377 378 default: 379 break; 380 } 381 382 return 0; 383 } 384 385 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w, 386 struct snd_kcontrol *kcontrol, int event) 387 { 388 struct snd_soc_component *component = 389 snd_soc_dapm_to_component(w->dapm); 390 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 391 unsigned char ps0 = 0x0, ps3 = 0x3; 392 393 switch (event) { 394 case SND_SOC_DAPM_POST_PMU: 395 regmap_write(rt1316->regmap, 396 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 397 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 398 ps0); 399 break; 400 case SND_SOC_DAPM_PRE_PMD: 401 regmap_write(rt1316->regmap, 402 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 403 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 404 ps3); 405 break; 406 } 407 return 0; 408 } 409 410 static const char * const rt1316_rx_data_ch_select[] = { 411 "L,R", 412 "L,L", 413 "L,R", 414 "L,L+R", 415 "R,L", 416 "R,R", 417 "R,L+R", 418 "L+R,L", 419 "L+R,R", 420 "L+R,L+R", 421 }; 422 423 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum, 424 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0, 425 rt1316_rx_data_ch_select); 426 427 static const struct snd_kcontrol_new rt1316_snd_controls[] = { 428 429 /* I2S Data Channel Selection */ 430 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum), 431 432 /* XU24 Bypass Control */ 433 SOC_SINGLE("XU24 Bypass Switch", 434 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0), 435 436 /* Left/Right IV tag */ 437 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0), 438 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0), 439 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0), 440 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0), 441 442 /* IV mixer Control */ 443 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1), 444 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1), 445 }; 446 447 static const struct snd_kcontrol_new rt1316_sto_dac = 448 SOC_DAPM_DOUBLE_R("Switch", 449 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 450 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 451 0, 1, 1); 452 453 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = { 454 /* Audio Interface */ 455 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 456 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0), 457 458 /* Digital Interface */ 459 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac), 460 461 /* Output Lines */ 462 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 463 rt1316_classd_event, 464 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 465 SND_SOC_DAPM_OUTPUT("SPOL"), 466 SND_SOC_DAPM_OUTPUT("SPOR"), 467 468 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0, 469 rt1316_pde24_event, 470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 471 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 472 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 473 SND_SOC_DAPM_SIGGEN("I Gen"), 474 SND_SOC_DAPM_SIGGEN("V Gen"), 475 }; 476 477 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = { 478 { "DAC", "Switch", "DP1RX" }, 479 { "CLASS D", NULL, "DAC" }, 480 { "SPOL", NULL, "CLASS D" }, 481 { "SPOR", NULL, "CLASS D" }, 482 483 { "I Sense", NULL, "I Gen" }, 484 { "V Sense", NULL, "V Gen" }, 485 { "I Sense", NULL, "PDE 24" }, 486 { "V Sense", NULL, "PDE 24" }, 487 { "DP2TX", NULL, "I Sense" }, 488 { "DP2TX", NULL, "V Sense" }, 489 }; 490 491 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 492 int direction) 493 { 494 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 495 496 return 0; 497 } 498 499 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream, 500 struct snd_soc_dai *dai) 501 { 502 snd_soc_dai_set_dma_data(dai, substream, NULL); 503 } 504 505 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream, 506 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 507 { 508 struct snd_soc_component *component = dai->component; 509 struct rt1316_sdw_priv *rt1316 = 510 snd_soc_component_get_drvdata(component); 511 struct sdw_stream_config stream_config = {0}; 512 struct sdw_port_config port_config = {0}; 513 struct sdw_stream_runtime *sdw_stream; 514 int retval; 515 516 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 517 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 518 519 if (!sdw_stream) 520 return -EINVAL; 521 522 if (!rt1316->sdw_slave) 523 return -EINVAL; 524 525 /* SoundWire specific configuration */ 526 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 527 528 /* port 1 for playback */ 529 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 530 port_config.num = 1; 531 else 532 port_config.num = 2; 533 534 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config, 535 &port_config, 1, sdw_stream); 536 if (retval) { 537 dev_err(dai->dev, "Unable to configure port\n"); 538 return retval; 539 } 540 541 return 0; 542 } 543 544 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 545 struct snd_soc_dai *dai) 546 { 547 struct snd_soc_component *component = dai->component; 548 struct rt1316_sdw_priv *rt1316 = 549 snd_soc_component_get_drvdata(component); 550 struct sdw_stream_runtime *sdw_stream = 551 snd_soc_dai_get_dma_data(dai, substream); 552 553 if (!rt1316->sdw_slave) 554 return -EINVAL; 555 556 sdw_stream_remove_slave(rt1316->sdw_slave, sdw_stream); 557 return 0; 558 } 559 560 /* 561 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 562 * port_prep are not defined for now 563 */ 564 static const struct sdw_slave_ops rt1316_slave_ops = { 565 .read_prop = rt1316_read_prop, 566 .update_status = rt1316_update_status, 567 }; 568 569 static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev) 570 { 571 int ret = 0; 572 573 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt); 574 if (rt1316->bq_params_cnt) { 575 rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL); 576 if (!rt1316->bq_params) { 577 dev_err(dev, "Could not allocate bq_params memory\n"); 578 ret = -ENOMEM; 579 } else { 580 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt); 581 if (ret < 0) 582 dev_err(dev, "Could not read list of realtek,bq-params\n"); 583 } 584 } 585 586 dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt); 587 return ret; 588 } 589 590 static int rt1316_sdw_component_probe(struct snd_soc_component *component) 591 { 592 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 593 int ret; 594 595 rt1316->component = component; 596 rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev); 597 598 ret = pm_runtime_resume(component->dev); 599 if (ret < 0 && ret != -EACCES) 600 return ret; 601 602 /* apply BQ params */ 603 rt1316_apply_bq_params(rt1316); 604 605 return 0; 606 } 607 608 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = { 609 .probe = rt1316_sdw_component_probe, 610 .controls = rt1316_snd_controls, 611 .num_controls = ARRAY_SIZE(rt1316_snd_controls), 612 .dapm_widgets = rt1316_dapm_widgets, 613 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets), 614 .dapm_routes = rt1316_dapm_routes, 615 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes), 616 .endianness = 1, 617 }; 618 619 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = { 620 .hw_params = rt1316_sdw_hw_params, 621 .hw_free = rt1316_sdw_pcm_hw_free, 622 .set_stream = rt1316_set_sdw_stream, 623 .shutdown = rt1316_sdw_shutdown, 624 }; 625 626 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000 627 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 628 SNDRV_PCM_FMTBIT_S24_LE) 629 630 static struct snd_soc_dai_driver rt1316_sdw_dai[] = { 631 { 632 .name = "rt1316-aif", 633 .playback = { 634 .stream_name = "DP1 Playback", 635 .channels_min = 1, 636 .channels_max = 2, 637 .rates = RT1316_STEREO_RATES, 638 .formats = RT1316_FORMATS, 639 }, 640 .capture = { 641 .stream_name = "DP2 Capture", 642 .channels_min = 1, 643 .channels_max = 2, 644 .rates = RT1316_STEREO_RATES, 645 .formats = RT1316_FORMATS, 646 }, 647 .ops = &rt1316_aif_dai_ops, 648 }, 649 }; 650 651 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap, 652 struct sdw_slave *slave) 653 { 654 struct rt1316_sdw_priv *rt1316; 655 int ret; 656 657 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL); 658 if (!rt1316) 659 return -ENOMEM; 660 661 dev_set_drvdata(dev, rt1316); 662 rt1316->sdw_slave = slave; 663 rt1316->regmap = regmap; 664 665 /* 666 * Mark hw_init to false 667 * HW init will be performed when device reports present 668 */ 669 rt1316->hw_init = false; 670 rt1316->first_hw_init = false; 671 672 ret = devm_snd_soc_register_component(dev, 673 &soc_component_sdw_rt1316, 674 rt1316_sdw_dai, 675 ARRAY_SIZE(rt1316_sdw_dai)); 676 677 dev_dbg(&slave->dev, "%s\n", __func__); 678 679 return ret; 680 } 681 682 static int rt1316_sdw_probe(struct sdw_slave *slave, 683 const struct sdw_device_id *id) 684 { 685 struct regmap *regmap; 686 687 /* Regmap Initialization */ 688 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap); 689 if (IS_ERR(regmap)) 690 return PTR_ERR(regmap); 691 692 return rt1316_sdw_init(&slave->dev, regmap, slave); 693 } 694 695 static int rt1316_sdw_remove(struct sdw_slave *slave) 696 { 697 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 698 699 if (rt1316->first_hw_init) 700 pm_runtime_disable(&slave->dev); 701 702 return 0; 703 } 704 705 static const struct sdw_device_id rt1316_id[] = { 706 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0), 707 {}, 708 }; 709 MODULE_DEVICE_TABLE(sdw, rt1316_id); 710 711 static int __maybe_unused rt1316_dev_suspend(struct device *dev) 712 { 713 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 714 715 if (!rt1316->hw_init) 716 return 0; 717 718 regcache_cache_only(rt1316->regmap, true); 719 720 return 0; 721 } 722 723 #define RT1316_PROBE_TIMEOUT 5000 724 725 static int __maybe_unused rt1316_dev_resume(struct device *dev) 726 { 727 struct sdw_slave *slave = dev_to_sdw_dev(dev); 728 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 729 unsigned long time; 730 731 if (!rt1316->first_hw_init) 732 return 0; 733 734 if (!slave->unattach_request) 735 goto regmap_sync; 736 737 time = wait_for_completion_timeout(&slave->initialization_complete, 738 msecs_to_jiffies(RT1316_PROBE_TIMEOUT)); 739 if (!time) { 740 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 741 sdw_show_ping_status(slave->bus, true); 742 743 return -ETIMEDOUT; 744 } 745 746 regmap_sync: 747 slave->unattach_request = 0; 748 regcache_cache_only(rt1316->regmap, false); 749 regcache_sync(rt1316->regmap); 750 751 return 0; 752 } 753 754 static const struct dev_pm_ops rt1316_pm = { 755 SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume) 756 SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL) 757 }; 758 759 static struct sdw_driver rt1316_sdw_driver = { 760 .driver = { 761 .name = "rt1316-sdca", 762 .owner = THIS_MODULE, 763 .pm = &rt1316_pm, 764 }, 765 .probe = rt1316_sdw_probe, 766 .remove = rt1316_sdw_remove, 767 .ops = &rt1316_slave_ops, 768 .id_table = rt1316_id, 769 }; 770 module_sdw_driver(rt1316_sdw_driver); 771 772 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW"); 773 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 774 MODULE_LICENSE("GPL"); 775