1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2021 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <sound/core.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/sdw.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/initval.h> 20 #include "rt1316-sdw.h" 21 22 static const struct reg_default rt1316_reg_defaults[] = { 23 { 0x3004, 0x00 }, 24 { 0x3005, 0x00 }, 25 { 0x3206, 0x00 }, 26 { 0xc001, 0x00 }, 27 { 0xc002, 0x00 }, 28 { 0xc003, 0x00 }, 29 { 0xc004, 0x00 }, 30 { 0xc005, 0x00 }, 31 { 0xc006, 0x00 }, 32 { 0xc007, 0x00 }, 33 { 0xc008, 0x00 }, 34 { 0xc009, 0x00 }, 35 { 0xc00a, 0x00 }, 36 { 0xc00b, 0x00 }, 37 { 0xc00c, 0x00 }, 38 { 0xc00d, 0x00 }, 39 { 0xc00e, 0x00 }, 40 { 0xc00f, 0x00 }, 41 { 0xc010, 0xa5 }, 42 { 0xc011, 0x00 }, 43 { 0xc012, 0xff }, 44 { 0xc013, 0xff }, 45 { 0xc014, 0x40 }, 46 { 0xc015, 0x00 }, 47 { 0xc016, 0x00 }, 48 { 0xc017, 0x00 }, 49 { 0xc605, 0x30 }, 50 { 0xc700, 0x0a }, 51 { 0xc701, 0xaa }, 52 { 0xc702, 0x1a }, 53 { 0xc703, 0x0a }, 54 { 0xc710, 0x80 }, 55 { 0xc711, 0x00 }, 56 { 0xc712, 0x3e }, 57 { 0xc713, 0x80 }, 58 { 0xc714, 0x80 }, 59 { 0xc715, 0x06 }, 60 { 0xd101, 0x00 }, 61 { 0xd102, 0x30 }, 62 { 0xd103, 0x00 }, 63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 }, 67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 69 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 70 }; 71 72 static const struct reg_sequence rt1316_blind_write[] = { 73 { 0xc710, 0x17 }, 74 { 0xc711, 0x80 }, 75 { 0xc712, 0x26 }, 76 { 0xc713, 0x06 }, 77 { 0xc714, 0x80 }, 78 { 0xc715, 0x06 }, 79 { 0xc702, 0x0a }, 80 { 0xc703, 0x0a }, 81 { 0xc001, 0x45 }, 82 { 0xc003, 0x00 }, 83 { 0xc004, 0x11 }, 84 { 0xc005, 0x00 }, 85 { 0xc006, 0x00 }, 86 { 0xc106, 0x00 }, 87 { 0xc007, 0x11 }, 88 { 0xc008, 0x11 }, 89 { 0xc009, 0x00 }, 90 91 { 0x2f0a, 0x00 }, 92 { 0xd101, 0xf0 }, 93 { 0xd103, 0x9b }, 94 { 0x2f36, 0x8e }, 95 { 0x3206, 0x80 }, 96 { 0x3211, 0x0b }, 97 { 0x3216, 0x06 }, 98 { 0xc614, 0x20 }, 99 { 0xc615, 0x0a }, 100 { 0xc616, 0x02 }, 101 { 0xc617, 0x00 }, 102 { 0xc60b, 0x10 }, 103 { 0xc60e, 0x05 }, 104 { 0xc102, 0x00 }, 105 { 0xc090, 0xb0 }, 106 { 0xc00f, 0x01 }, 107 { 0xc09c, 0x7b }, 108 109 { 0xc602, 0x07 }, 110 { 0xc603, 0x07 }, 111 { 0xc0a3, 0x71 }, 112 { 0xc00b, 0x30 }, 113 { 0xc093, 0x80 }, 114 { 0xc09d, 0x80 }, 115 { 0xc0b0, 0x77 }, 116 { 0xc010, 0xa5 }, 117 { 0xc050, 0x83 }, 118 { 0x2f55, 0x03 }, 119 { 0x3217, 0xb5 }, 120 { 0x3202, 0x02 }, 121 122 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 }, 123 124 /* for IV sense */ 125 { 0x2232, 0x80 }, 126 { 0xc0b0, 0x77 }, 127 { 0xc011, 0x00 }, 128 { 0xc020, 0x00 }, 129 { 0xc023, 0x00 }, 130 { 0x3101, 0x00 }, 131 { 0x3004, 0xa0 }, 132 { 0x3005, 0xb1 }, 133 { 0xc007, 0x11 }, 134 { 0xc008, 0x11 }, 135 { 0xc009, 0x00 }, 136 { 0xc022, 0xd6 }, 137 { 0xc025, 0xd6 }, 138 139 { 0xd001, 0x03 }, 140 { 0xd002, 0xbf }, 141 { 0xd003, 0x03 }, 142 { 0xd004, 0xbf }, 143 }; 144 145 static bool rt1316_readable_register(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case 0x2f0a: 149 case 0x2f36: 150 case 0x3203 ... 0x320e: 151 case 0xc000 ... 0xc7b4: 152 case 0xcf00 ... 0xcf03: 153 case 0xd101 ... 0xd103: 154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0): 155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L): 156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R): 157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 160 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 161 return true; 162 default: 163 return false; 164 } 165 } 166 167 static bool rt1316_volatile_register(struct device *dev, unsigned int reg) 168 { 169 switch (reg) { 170 case 0xc000: 171 case 0xc093: 172 case 0xc09d: 173 case 0xc0a3: 174 case 0xc201: 175 case 0xc427 ... 0xc428: 176 case 0xd102: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static const struct regmap_config rt1316_sdw_regmap = { 184 .reg_bits = 32, 185 .val_bits = 8, 186 .readable_reg = rt1316_readable_register, 187 .volatile_reg = rt1316_volatile_register, 188 .max_register = 0x4108ffff, 189 .reg_defaults = rt1316_reg_defaults, 190 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults), 191 .cache_type = REGCACHE_RBTREE, 192 .use_single_read = true, 193 .use_single_write = true, 194 }; 195 196 static int rt1316_read_prop(struct sdw_slave *slave) 197 { 198 struct sdw_slave_prop *prop = &slave->prop; 199 int nval; 200 int i, j; 201 u32 bit; 202 unsigned long addr; 203 struct sdw_dpn_prop *dpn; 204 205 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 206 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 207 208 prop->paging_support = true; 209 210 /* first we need to allocate memory for set bits in port lists */ 211 prop->source_ports = 0x04; /* BITMAP: 00000100 */ 212 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 213 214 nval = hweight32(prop->source_ports); 215 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 216 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 217 if (!prop->src_dpn_prop) 218 return -ENOMEM; 219 220 i = 0; 221 dpn = prop->src_dpn_prop; 222 addr = prop->source_ports; 223 for_each_set_bit(bit, &addr, 32) { 224 dpn[i].num = bit; 225 dpn[i].type = SDW_DPN_FULL; 226 dpn[i].simple_ch_prep_sm = true; 227 dpn[i].ch_prep_timeout = 10; 228 i++; 229 } 230 231 /* do this again for sink now */ 232 nval = hweight32(prop->sink_ports); 233 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 234 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 235 if (!prop->sink_dpn_prop) 236 return -ENOMEM; 237 238 j = 0; 239 dpn = prop->sink_dpn_prop; 240 addr = prop->sink_ports; 241 for_each_set_bit(bit, &addr, 32) { 242 dpn[j].num = bit; 243 dpn[j].type = SDW_DPN_FULL; 244 dpn[j].simple_ch_prep_sm = true; 245 dpn[j].ch_prep_timeout = 10; 246 j++; 247 } 248 249 /* set the timeout values */ 250 prop->clk_stop_timeout = 20; 251 252 dev_dbg(&slave->dev, "%s\n", __func__); 253 254 return 0; 255 } 256 257 static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316) 258 { 259 unsigned int i, reg, data; 260 261 for (i = 0; i < rt1316->bq_params_cnt; i += 3) { 262 reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8); 263 data = rt1316->bq_params[i + 2]; 264 regmap_write(rt1316->regmap, reg, data); 265 } 266 } 267 268 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave) 269 { 270 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 271 272 if (rt1316->hw_init) 273 return 0; 274 275 if (rt1316->first_hw_init) { 276 regcache_cache_only(rt1316->regmap, false); 277 regcache_cache_bypass(rt1316->regmap, true); 278 } else { 279 /* 280 * PM runtime is only enabled when a Slave reports as Attached 281 */ 282 283 /* set autosuspend parameters */ 284 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 285 pm_runtime_use_autosuspend(&slave->dev); 286 287 /* update count of parent 'active' children */ 288 pm_runtime_set_active(&slave->dev); 289 290 /* make sure the device does not suspend immediately */ 291 pm_runtime_mark_last_busy(&slave->dev); 292 293 pm_runtime_enable(&slave->dev); 294 } 295 296 pm_runtime_get_noresume(&slave->dev); 297 298 /* sw reset */ 299 regmap_write(rt1316->regmap, 0xc000, 0x02); 300 301 /* initial settings - blind write */ 302 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write, 303 ARRAY_SIZE(rt1316_blind_write)); 304 305 if (rt1316->first_hw_init) { 306 regcache_cache_bypass(rt1316->regmap, false); 307 regcache_mark_dirty(rt1316->regmap); 308 } else 309 rt1316->first_hw_init = true; 310 311 /* Mark Slave initialization complete */ 312 rt1316->hw_init = true; 313 314 pm_runtime_mark_last_busy(&slave->dev); 315 pm_runtime_put_autosuspend(&slave->dev); 316 317 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 318 return 0; 319 } 320 321 static int rt1316_update_status(struct sdw_slave *slave, 322 enum sdw_slave_status status) 323 { 324 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 325 326 /* Update the status */ 327 rt1316->status = status; 328 329 if (status == SDW_SLAVE_UNATTACHED) 330 rt1316->hw_init = false; 331 332 /* 333 * Perform initialization only if slave status is present and 334 * hw_init flag is false 335 */ 336 if (rt1316->hw_init || rt1316->status != SDW_SLAVE_ATTACHED) 337 return 0; 338 339 /* perform I/O transfers required for Slave initialization */ 340 return rt1316_io_init(&slave->dev, slave); 341 } 342 343 static int rt1316_classd_event(struct snd_soc_dapm_widget *w, 344 struct snd_kcontrol *kcontrol, int event) 345 { 346 struct snd_soc_component *component = 347 snd_soc_dapm_to_component(w->dapm); 348 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 349 unsigned char ps0 = 0x0, ps3 = 0x3; 350 351 switch (event) { 352 case SND_SOC_DAPM_POST_PMU: 353 regmap_write(rt1316->regmap, 354 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 355 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 356 ps0); 357 regmap_write(rt1316->regmap, 358 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 359 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 360 ps0); 361 regmap_write(rt1316->regmap, 362 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 363 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 364 ps0); 365 break; 366 case SND_SOC_DAPM_PRE_PMD: 367 regmap_write(rt1316->regmap, 368 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 369 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 370 ps3); 371 regmap_write(rt1316->regmap, 372 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 373 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 374 ps3); 375 regmap_write(rt1316->regmap, 376 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 377 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 378 ps3); 379 break; 380 381 default: 382 break; 383 } 384 385 return 0; 386 } 387 388 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w, 389 struct snd_kcontrol *kcontrol, int event) 390 { 391 struct snd_soc_component *component = 392 snd_soc_dapm_to_component(w->dapm); 393 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 394 unsigned char ps0 = 0x0, ps3 = 0x3; 395 396 switch (event) { 397 case SND_SOC_DAPM_POST_PMU: 398 regmap_write(rt1316->regmap, 399 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 400 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 401 ps0); 402 break; 403 case SND_SOC_DAPM_PRE_PMD: 404 regmap_write(rt1316->regmap, 405 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 406 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 407 ps3); 408 break; 409 } 410 return 0; 411 } 412 413 static const char * const rt1316_rx_data_ch_select[] = { 414 "L,R", 415 "L,L", 416 "L,R", 417 "L,L+R", 418 "R,L", 419 "R,R", 420 "R,L+R", 421 "L+R,L", 422 "L+R,R", 423 "L+R,L+R", 424 }; 425 426 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum, 427 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0, 428 rt1316_rx_data_ch_select); 429 430 static const struct snd_kcontrol_new rt1316_snd_controls[] = { 431 432 /* I2S Data Channel Selection */ 433 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum), 434 435 /* XU24 Bypass Control */ 436 SOC_SINGLE("XU24 Bypass Switch", 437 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0), 438 439 /* Left/Right IV tag */ 440 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0), 441 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0), 442 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0), 443 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0), 444 445 /* IV mixer Control */ 446 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1), 447 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1), 448 }; 449 450 static const struct snd_kcontrol_new rt1316_sto_dac = 451 SOC_DAPM_DOUBLE_R("Switch", 452 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 453 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 454 0, 1, 1); 455 456 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = { 457 /* Audio Interface */ 458 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 459 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0), 460 461 /* Digital Interface */ 462 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac), 463 464 /* Output Lines */ 465 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 466 rt1316_classd_event, 467 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 468 SND_SOC_DAPM_OUTPUT("SPOL"), 469 SND_SOC_DAPM_OUTPUT("SPOR"), 470 471 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0, 472 rt1316_pde24_event, 473 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 474 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 475 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 476 SND_SOC_DAPM_SIGGEN("I Gen"), 477 SND_SOC_DAPM_SIGGEN("V Gen"), 478 }; 479 480 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = { 481 { "DAC", "Switch", "DP1RX" }, 482 { "CLASS D", NULL, "DAC" }, 483 { "SPOL", NULL, "CLASS D" }, 484 { "SPOR", NULL, "CLASS D" }, 485 486 { "I Sense", NULL, "I Gen" }, 487 { "V Sense", NULL, "V Gen" }, 488 { "I Sense", NULL, "PDE 24" }, 489 { "V Sense", NULL, "PDE 24" }, 490 { "DP2TX", NULL, "I Sense" }, 491 { "DP2TX", NULL, "V Sense" }, 492 }; 493 494 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 495 int direction) 496 { 497 struct sdw_stream_data *stream; 498 499 if (!sdw_stream) 500 return 0; 501 502 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 503 if (!stream) 504 return -ENOMEM; 505 506 stream->sdw_stream = sdw_stream; 507 508 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 509 snd_soc_dai_dma_data_set(dai, direction, stream); 510 511 return 0; 512 } 513 514 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream, 515 struct snd_soc_dai *dai) 516 { 517 struct sdw_stream_data *stream; 518 519 stream = snd_soc_dai_get_dma_data(dai, substream); 520 snd_soc_dai_set_dma_data(dai, substream, NULL); 521 kfree(stream); 522 } 523 524 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream, 525 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 526 { 527 struct snd_soc_component *component = dai->component; 528 struct rt1316_sdw_priv *rt1316 = 529 snd_soc_component_get_drvdata(component); 530 struct sdw_stream_config stream_config = {0}; 531 struct sdw_port_config port_config = {0}; 532 struct sdw_stream_data *stream; 533 int retval; 534 535 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 536 stream = snd_soc_dai_get_dma_data(dai, substream); 537 538 if (!stream) 539 return -EINVAL; 540 541 if (!rt1316->sdw_slave) 542 return -EINVAL; 543 544 /* SoundWire specific configuration */ 545 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 546 547 /* port 1 for playback */ 548 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 549 port_config.num = 1; 550 else 551 port_config.num = 2; 552 553 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config, 554 &port_config, 1, stream->sdw_stream); 555 if (retval) { 556 dev_err(dai->dev, "Unable to configure port\n"); 557 return retval; 558 } 559 560 return 0; 561 } 562 563 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 564 struct snd_soc_dai *dai) 565 { 566 struct snd_soc_component *component = dai->component; 567 struct rt1316_sdw_priv *rt1316 = 568 snd_soc_component_get_drvdata(component); 569 struct sdw_stream_data *stream = 570 snd_soc_dai_get_dma_data(dai, substream); 571 572 if (!rt1316->sdw_slave) 573 return -EINVAL; 574 575 sdw_stream_remove_slave(rt1316->sdw_slave, stream->sdw_stream); 576 return 0; 577 } 578 579 /* 580 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 581 * port_prep are not defined for now 582 */ 583 static const struct sdw_slave_ops rt1316_slave_ops = { 584 .read_prop = rt1316_read_prop, 585 .update_status = rt1316_update_status, 586 }; 587 588 static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev) 589 { 590 int ret = 0; 591 592 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt); 593 if (rt1316->bq_params_cnt) { 594 rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL); 595 if (!rt1316->bq_params) { 596 dev_err(dev, "Could not allocate bq_params memory\n"); 597 ret = -ENOMEM; 598 } else { 599 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt); 600 if (ret < 0) 601 dev_err(dev, "Could not read list of realtek,bq-params\n"); 602 } 603 } 604 605 dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt); 606 return ret; 607 } 608 609 static int rt1316_sdw_component_probe(struct snd_soc_component *component) 610 { 611 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 612 int ret; 613 614 rt1316->component = component; 615 rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev); 616 617 ret = pm_runtime_resume(component->dev); 618 if (ret < 0 && ret != -EACCES) 619 return ret; 620 621 /* apply BQ params */ 622 rt1316_apply_bq_params(rt1316); 623 624 return 0; 625 } 626 627 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = { 628 .probe = rt1316_sdw_component_probe, 629 .controls = rt1316_snd_controls, 630 .num_controls = ARRAY_SIZE(rt1316_snd_controls), 631 .dapm_widgets = rt1316_dapm_widgets, 632 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets), 633 .dapm_routes = rt1316_dapm_routes, 634 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes), 635 .endianness = 1, 636 }; 637 638 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = { 639 .hw_params = rt1316_sdw_hw_params, 640 .hw_free = rt1316_sdw_pcm_hw_free, 641 .set_stream = rt1316_set_sdw_stream, 642 .shutdown = rt1316_sdw_shutdown, 643 }; 644 645 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000 646 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 647 SNDRV_PCM_FMTBIT_S24_LE) 648 649 static struct snd_soc_dai_driver rt1316_sdw_dai[] = { 650 { 651 .name = "rt1316-aif", 652 .playback = { 653 .stream_name = "DP1 Playback", 654 .channels_min = 1, 655 .channels_max = 2, 656 .rates = RT1316_STEREO_RATES, 657 .formats = RT1316_FORMATS, 658 }, 659 .capture = { 660 .stream_name = "DP2 Capture", 661 .channels_min = 1, 662 .channels_max = 2, 663 .rates = RT1316_STEREO_RATES, 664 .formats = RT1316_FORMATS, 665 }, 666 .ops = &rt1316_aif_dai_ops, 667 }, 668 }; 669 670 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap, 671 struct sdw_slave *slave) 672 { 673 struct rt1316_sdw_priv *rt1316; 674 int ret; 675 676 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL); 677 if (!rt1316) 678 return -ENOMEM; 679 680 dev_set_drvdata(dev, rt1316); 681 rt1316->sdw_slave = slave; 682 rt1316->regmap = regmap; 683 684 /* 685 * Mark hw_init to false 686 * HW init will be performed when device reports present 687 */ 688 rt1316->hw_init = false; 689 rt1316->first_hw_init = false; 690 691 ret = devm_snd_soc_register_component(dev, 692 &soc_component_sdw_rt1316, 693 rt1316_sdw_dai, 694 ARRAY_SIZE(rt1316_sdw_dai)); 695 696 dev_dbg(&slave->dev, "%s\n", __func__); 697 698 return ret; 699 } 700 701 static int rt1316_sdw_probe(struct sdw_slave *slave, 702 const struct sdw_device_id *id) 703 { 704 struct regmap *regmap; 705 706 /* Regmap Initialization */ 707 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap); 708 if (IS_ERR(regmap)) 709 return PTR_ERR(regmap); 710 711 return rt1316_sdw_init(&slave->dev, regmap, slave); 712 } 713 714 static int rt1316_sdw_remove(struct sdw_slave *slave) 715 { 716 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 717 718 if (rt1316->first_hw_init) 719 pm_runtime_disable(&slave->dev); 720 721 return 0; 722 } 723 724 static const struct sdw_device_id rt1316_id[] = { 725 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0), 726 {}, 727 }; 728 MODULE_DEVICE_TABLE(sdw, rt1316_id); 729 730 static int __maybe_unused rt1316_dev_suspend(struct device *dev) 731 { 732 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 733 734 if (!rt1316->hw_init) 735 return 0; 736 737 regcache_cache_only(rt1316->regmap, true); 738 739 return 0; 740 } 741 742 #define RT1316_PROBE_TIMEOUT 5000 743 744 static int __maybe_unused rt1316_dev_resume(struct device *dev) 745 { 746 struct sdw_slave *slave = dev_to_sdw_dev(dev); 747 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 748 unsigned long time; 749 750 if (!rt1316->first_hw_init) 751 return 0; 752 753 if (!slave->unattach_request) 754 goto regmap_sync; 755 756 time = wait_for_completion_timeout(&slave->initialization_complete, 757 msecs_to_jiffies(RT1316_PROBE_TIMEOUT)); 758 if (!time) { 759 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 760 sdw_show_ping_status(slave->bus, true); 761 762 return -ETIMEDOUT; 763 } 764 765 regmap_sync: 766 slave->unattach_request = 0; 767 regcache_cache_only(rt1316->regmap, false); 768 regcache_sync(rt1316->regmap); 769 770 return 0; 771 } 772 773 static const struct dev_pm_ops rt1316_pm = { 774 SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume) 775 SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL) 776 }; 777 778 static struct sdw_driver rt1316_sdw_driver = { 779 .driver = { 780 .name = "rt1316-sdca", 781 .owner = THIS_MODULE, 782 .pm = &rt1316_pm, 783 }, 784 .probe = rt1316_sdw_probe, 785 .remove = rt1316_sdw_remove, 786 .ops = &rt1316_slave_ops, 787 .id_table = rt1316_id, 788 }; 789 module_sdw_driver(rt1316_sdw_driver); 790 791 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW"); 792 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 793 MODULE_LICENSE("GPL"); 794