1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2021 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <sound/core.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/sdw.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/initval.h> 20 #include "rt1316-sdw.h" 21 22 static const struct reg_default rt1316_reg_defaults[] = { 23 { 0x3004, 0x00 }, 24 { 0x3005, 0x00 }, 25 { 0x3206, 0x00 }, 26 { 0xc001, 0x00 }, 27 { 0xc002, 0x00 }, 28 { 0xc003, 0x00 }, 29 { 0xc004, 0x00 }, 30 { 0xc005, 0x00 }, 31 { 0xc006, 0x00 }, 32 { 0xc007, 0x00 }, 33 { 0xc008, 0x00 }, 34 { 0xc009, 0x00 }, 35 { 0xc00a, 0x00 }, 36 { 0xc00b, 0x00 }, 37 { 0xc00c, 0x00 }, 38 { 0xc00d, 0x00 }, 39 { 0xc00e, 0x00 }, 40 { 0xc00f, 0x00 }, 41 { 0xc010, 0xa5 }, 42 { 0xc011, 0x00 }, 43 { 0xc012, 0xff }, 44 { 0xc013, 0xff }, 45 { 0xc014, 0x40 }, 46 { 0xc015, 0x00 }, 47 { 0xc016, 0x00 }, 48 { 0xc017, 0x00 }, 49 { 0xc605, 0x30 }, 50 { 0xc700, 0x0a }, 51 { 0xc701, 0xaa }, 52 { 0xc702, 0x1a }, 53 { 0xc703, 0x0a }, 54 { 0xc710, 0x80 }, 55 { 0xc711, 0x00 }, 56 { 0xc712, 0x3e }, 57 { 0xc713, 0x80 }, 58 { 0xc714, 0x80 }, 59 { 0xc715, 0x06 }, 60 { 0xd101, 0x00 }, 61 { 0xd102, 0x30 }, 62 { 0xd103, 0x00 }, 63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 }, 67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 69 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 70 }; 71 72 static const struct reg_sequence rt1316_blind_write[] = { 73 { 0xc710, 0x17 }, 74 { 0xc711, 0x80 }, 75 { 0xc712, 0x26 }, 76 { 0xc713, 0x06 }, 77 { 0xc714, 0x80 }, 78 { 0xc715, 0x06 }, 79 { 0xc702, 0x0a }, 80 { 0xc703, 0x0a }, 81 { 0xc001, 0x45 }, 82 { 0xc003, 0x00 }, 83 { 0xc004, 0x11 }, 84 { 0xc005, 0x00 }, 85 { 0xc006, 0x00 }, 86 { 0xc106, 0x00 }, 87 { 0xc007, 0x11 }, 88 { 0xc008, 0x11 }, 89 { 0xc009, 0x00 }, 90 91 { 0x2f0a, 0x00 }, 92 { 0xd101, 0xf0 }, 93 { 0xd103, 0x9b }, 94 { 0x2f36, 0x8e }, 95 { 0x3206, 0x80 }, 96 { 0x3211, 0x0b }, 97 { 0x3216, 0x06 }, 98 { 0xc614, 0x20 }, 99 { 0xc615, 0x0a }, 100 { 0xc616, 0x02 }, 101 { 0xc617, 0x00 }, 102 { 0xc60b, 0x10 }, 103 { 0xc60e, 0x05 }, 104 { 0xc102, 0x00 }, 105 { 0xc090, 0xb0 }, 106 { 0xc00f, 0x01 }, 107 { 0xc09c, 0x7b }, 108 109 { 0xc602, 0x07 }, 110 { 0xc603, 0x07 }, 111 { 0xc0a3, 0x71 }, 112 { 0xc00b, 0x30 }, 113 { 0xc093, 0x80 }, 114 { 0xc09d, 0x80 }, 115 { 0xc0b0, 0x77 }, 116 { 0xc010, 0xa5 }, 117 { 0xc050, 0x83 }, 118 { 0x2f55, 0x03 }, 119 { 0x3217, 0xb5 }, 120 { 0x3202, 0x02 }, 121 122 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 }, 123 124 /* for IV sense */ 125 { 0x2232, 0x80 }, 126 { 0xc0b0, 0x77 }, 127 { 0xc011, 0x00 }, 128 { 0xc020, 0x00 }, 129 { 0xc023, 0x00 }, 130 { 0x3101, 0x00 }, 131 { 0x3004, 0xa0 }, 132 { 0x3005, 0xb1 }, 133 { 0xc007, 0x11 }, 134 { 0xc008, 0x11 }, 135 { 0xc009, 0x00 }, 136 { 0xc022, 0xd6 }, 137 { 0xc025, 0xd6 }, 138 139 { 0xd001, 0x03 }, 140 { 0xd002, 0xbf }, 141 { 0xd003, 0x03 }, 142 { 0xd004, 0xbf }, 143 }; 144 145 static bool rt1316_readable_register(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case 0x2f0a: 149 case 0x2f36: 150 case 0x3203 ... 0x320e: 151 case 0xc000 ... 0xc7b4: 152 case 0xcf00 ... 0xcf03: 153 case 0xd101 ... 0xd103: 154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0): 155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L): 156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R): 157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 160 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 161 return true; 162 default: 163 return false; 164 } 165 } 166 167 static bool rt1316_volatile_register(struct device *dev, unsigned int reg) 168 { 169 switch (reg) { 170 case 0xc000: 171 case 0xc093: 172 case 0xc09d: 173 case 0xc0a3: 174 case 0xc201: 175 case 0xc427 ... 0xc428: 176 case 0xd102: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static const struct regmap_config rt1316_sdw_regmap = { 184 .reg_bits = 32, 185 .val_bits = 8, 186 .readable_reg = rt1316_readable_register, 187 .volatile_reg = rt1316_volatile_register, 188 .max_register = 0x4108ffff, 189 .reg_defaults = rt1316_reg_defaults, 190 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults), 191 .cache_type = REGCACHE_RBTREE, 192 .use_single_read = true, 193 .use_single_write = true, 194 }; 195 196 static int rt1316_read_prop(struct sdw_slave *slave) 197 { 198 struct sdw_slave_prop *prop = &slave->prop; 199 int nval; 200 int i, j; 201 u32 bit; 202 unsigned long addr; 203 struct sdw_dpn_prop *dpn; 204 205 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 206 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 207 prop->is_sdca = true; 208 209 prop->paging_support = true; 210 211 /* first we need to allocate memory for set bits in port lists */ 212 prop->source_ports = 0x04; /* BITMAP: 00000100 */ 213 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 214 215 nval = hweight32(prop->source_ports); 216 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 217 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 218 if (!prop->src_dpn_prop) 219 return -ENOMEM; 220 221 i = 0; 222 dpn = prop->src_dpn_prop; 223 addr = prop->source_ports; 224 for_each_set_bit(bit, &addr, 32) { 225 dpn[i].num = bit; 226 dpn[i].type = SDW_DPN_FULL; 227 dpn[i].simple_ch_prep_sm = true; 228 dpn[i].ch_prep_timeout = 10; 229 i++; 230 } 231 232 /* do this again for sink now */ 233 nval = hweight32(prop->sink_ports); 234 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 235 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 236 if (!prop->sink_dpn_prop) 237 return -ENOMEM; 238 239 j = 0; 240 dpn = prop->sink_dpn_prop; 241 addr = prop->sink_ports; 242 for_each_set_bit(bit, &addr, 32) { 243 dpn[j].num = bit; 244 dpn[j].type = SDW_DPN_FULL; 245 dpn[j].simple_ch_prep_sm = true; 246 dpn[j].ch_prep_timeout = 10; 247 j++; 248 } 249 250 /* set the timeout values */ 251 prop->clk_stop_timeout = 20; 252 253 dev_dbg(&slave->dev, "%s\n", __func__); 254 255 return 0; 256 } 257 258 static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316) 259 { 260 unsigned int i, reg, data; 261 262 for (i = 0; i < rt1316->bq_params_cnt; i += 3) { 263 reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8); 264 data = rt1316->bq_params[i + 2]; 265 regmap_write(rt1316->regmap, reg, data); 266 } 267 } 268 269 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave) 270 { 271 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 272 273 if (rt1316->hw_init) 274 return 0; 275 276 if (rt1316->first_hw_init) { 277 regcache_cache_only(rt1316->regmap, false); 278 regcache_cache_bypass(rt1316->regmap, true); 279 } else { 280 /* 281 * PM runtime is only enabled when a Slave reports as Attached 282 */ 283 284 /* set autosuspend parameters */ 285 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 286 pm_runtime_use_autosuspend(&slave->dev); 287 288 /* update count of parent 'active' children */ 289 pm_runtime_set_active(&slave->dev); 290 291 /* make sure the device does not suspend immediately */ 292 pm_runtime_mark_last_busy(&slave->dev); 293 294 pm_runtime_enable(&slave->dev); 295 } 296 297 pm_runtime_get_noresume(&slave->dev); 298 299 /* sw reset */ 300 regmap_write(rt1316->regmap, 0xc000, 0x02); 301 302 /* initial settings - blind write */ 303 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write, 304 ARRAY_SIZE(rt1316_blind_write)); 305 306 if (rt1316->first_hw_init) { 307 regcache_cache_bypass(rt1316->regmap, false); 308 regcache_mark_dirty(rt1316->regmap); 309 } else 310 rt1316->first_hw_init = true; 311 312 /* Mark Slave initialization complete */ 313 rt1316->hw_init = true; 314 315 pm_runtime_mark_last_busy(&slave->dev); 316 pm_runtime_put_autosuspend(&slave->dev); 317 318 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 319 return 0; 320 } 321 322 static int rt1316_update_status(struct sdw_slave *slave, 323 enum sdw_slave_status status) 324 { 325 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 326 327 /* Update the status */ 328 rt1316->status = status; 329 330 if (status == SDW_SLAVE_UNATTACHED) 331 rt1316->hw_init = false; 332 333 /* 334 * Perform initialization only if slave status is present and 335 * hw_init flag is false 336 */ 337 if (rt1316->hw_init || rt1316->status != SDW_SLAVE_ATTACHED) 338 return 0; 339 340 /* perform I/O transfers required for Slave initialization */ 341 return rt1316_io_init(&slave->dev, slave); 342 } 343 344 static int rt1316_classd_event(struct snd_soc_dapm_widget *w, 345 struct snd_kcontrol *kcontrol, int event) 346 { 347 struct snd_soc_component *component = 348 snd_soc_dapm_to_component(w->dapm); 349 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 350 unsigned char ps0 = 0x0, ps3 = 0x3; 351 352 switch (event) { 353 case SND_SOC_DAPM_POST_PMU: 354 regmap_write(rt1316->regmap, 355 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 356 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 357 ps0); 358 regmap_write(rt1316->regmap, 359 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 360 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 361 ps0); 362 regmap_write(rt1316->regmap, 363 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 364 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 365 ps0); 366 break; 367 case SND_SOC_DAPM_PRE_PMD: 368 regmap_write(rt1316->regmap, 369 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 370 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 371 ps3); 372 regmap_write(rt1316->regmap, 373 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 374 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 375 ps3); 376 regmap_write(rt1316->regmap, 377 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 378 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 379 ps3); 380 break; 381 382 default: 383 break; 384 } 385 386 return 0; 387 } 388 389 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w, 390 struct snd_kcontrol *kcontrol, int event) 391 { 392 struct snd_soc_component *component = 393 snd_soc_dapm_to_component(w->dapm); 394 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 395 unsigned char ps0 = 0x0, ps3 = 0x3; 396 397 switch (event) { 398 case SND_SOC_DAPM_POST_PMU: 399 regmap_write(rt1316->regmap, 400 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 401 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 402 ps0); 403 break; 404 case SND_SOC_DAPM_PRE_PMD: 405 regmap_write(rt1316->regmap, 406 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 407 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 408 ps3); 409 break; 410 } 411 return 0; 412 } 413 414 static const char * const rt1316_rx_data_ch_select[] = { 415 "L,R", 416 "L,L", 417 "L,R", 418 "L,L+R", 419 "R,L", 420 "R,R", 421 "R,L+R", 422 "L+R,L", 423 "L+R,R", 424 "L+R,L+R", 425 }; 426 427 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum, 428 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0, 429 rt1316_rx_data_ch_select); 430 431 static const struct snd_kcontrol_new rt1316_snd_controls[] = { 432 433 /* I2S Data Channel Selection */ 434 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum), 435 436 /* XU24 Bypass Control */ 437 SOC_SINGLE("XU24 Bypass Switch", 438 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0), 439 440 /* Left/Right IV tag */ 441 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0), 442 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0), 443 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0), 444 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0), 445 446 /* IV mixer Control */ 447 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1), 448 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1), 449 }; 450 451 static const struct snd_kcontrol_new rt1316_sto_dac = 452 SOC_DAPM_DOUBLE_R("Switch", 453 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 454 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 455 0, 1, 1); 456 457 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = { 458 /* Audio Interface */ 459 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 460 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0), 461 462 /* Digital Interface */ 463 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac), 464 465 /* Output Lines */ 466 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 467 rt1316_classd_event, 468 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 469 SND_SOC_DAPM_OUTPUT("SPOL"), 470 SND_SOC_DAPM_OUTPUT("SPOR"), 471 472 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0, 473 rt1316_pde24_event, 474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 475 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 476 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 477 SND_SOC_DAPM_SIGGEN("I Gen"), 478 SND_SOC_DAPM_SIGGEN("V Gen"), 479 }; 480 481 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = { 482 { "DAC", "Switch", "DP1RX" }, 483 { "CLASS D", NULL, "DAC" }, 484 { "SPOL", NULL, "CLASS D" }, 485 { "SPOR", NULL, "CLASS D" }, 486 487 { "I Sense", NULL, "I Gen" }, 488 { "V Sense", NULL, "V Gen" }, 489 { "I Sense", NULL, "PDE 24" }, 490 { "V Sense", NULL, "PDE 24" }, 491 { "DP2TX", NULL, "I Sense" }, 492 { "DP2TX", NULL, "V Sense" }, 493 }; 494 495 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 496 int direction) 497 { 498 struct sdw_stream_data *stream; 499 500 if (!sdw_stream) 501 return 0; 502 503 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 504 if (!stream) 505 return -ENOMEM; 506 507 stream->sdw_stream = sdw_stream; 508 509 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 510 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 511 dai->playback_dma_data = stream; 512 else 513 dai->capture_dma_data = stream; 514 515 return 0; 516 } 517 518 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream, 519 struct snd_soc_dai *dai) 520 { 521 struct sdw_stream_data *stream; 522 523 stream = snd_soc_dai_get_dma_data(dai, substream); 524 snd_soc_dai_set_dma_data(dai, substream, NULL); 525 kfree(stream); 526 } 527 528 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream, 529 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 530 { 531 struct snd_soc_component *component = dai->component; 532 struct rt1316_sdw_priv *rt1316 = 533 snd_soc_component_get_drvdata(component); 534 struct sdw_stream_config stream_config = {0}; 535 struct sdw_port_config port_config = {0}; 536 struct sdw_stream_data *stream; 537 int retval; 538 539 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 540 stream = snd_soc_dai_get_dma_data(dai, substream); 541 542 if (!stream) 543 return -EINVAL; 544 545 if (!rt1316->sdw_slave) 546 return -EINVAL; 547 548 /* SoundWire specific configuration */ 549 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 550 551 /* port 1 for playback */ 552 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 553 port_config.num = 1; 554 else 555 port_config.num = 2; 556 557 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config, 558 &port_config, 1, stream->sdw_stream); 559 if (retval) { 560 dev_err(dai->dev, "Unable to configure port\n"); 561 return retval; 562 } 563 564 return 0; 565 } 566 567 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 568 struct snd_soc_dai *dai) 569 { 570 struct snd_soc_component *component = dai->component; 571 struct rt1316_sdw_priv *rt1316 = 572 snd_soc_component_get_drvdata(component); 573 struct sdw_stream_data *stream = 574 snd_soc_dai_get_dma_data(dai, substream); 575 576 if (!rt1316->sdw_slave) 577 return -EINVAL; 578 579 sdw_stream_remove_slave(rt1316->sdw_slave, stream->sdw_stream); 580 return 0; 581 } 582 583 /* 584 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 585 * port_prep are not defined for now 586 */ 587 static struct sdw_slave_ops rt1316_slave_ops = { 588 .read_prop = rt1316_read_prop, 589 .update_status = rt1316_update_status, 590 }; 591 592 static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev) 593 { 594 int ret = 0; 595 596 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt); 597 if (rt1316->bq_params_cnt) { 598 rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL); 599 if (!rt1316->bq_params) { 600 dev_err(dev, "Could not allocate bq_params memory\n"); 601 ret = -ENOMEM; 602 } else { 603 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt); 604 if (ret < 0) 605 dev_err(dev, "Could not read list of realtek,bq-params\n"); 606 } 607 } 608 609 dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt); 610 return ret; 611 } 612 613 static int rt1316_sdw_component_probe(struct snd_soc_component *component) 614 { 615 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 616 int ret; 617 618 rt1316->component = component; 619 rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev); 620 621 ret = pm_runtime_resume(component->dev); 622 if (ret < 0 && ret != -EACCES) 623 return ret; 624 625 /* apply BQ params */ 626 rt1316_apply_bq_params(rt1316); 627 628 return 0; 629 } 630 631 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = { 632 .probe = rt1316_sdw_component_probe, 633 .controls = rt1316_snd_controls, 634 .num_controls = ARRAY_SIZE(rt1316_snd_controls), 635 .dapm_widgets = rt1316_dapm_widgets, 636 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets), 637 .dapm_routes = rt1316_dapm_routes, 638 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes), 639 .endianness = 1, 640 }; 641 642 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = { 643 .hw_params = rt1316_sdw_hw_params, 644 .hw_free = rt1316_sdw_pcm_hw_free, 645 .set_stream = rt1316_set_sdw_stream, 646 .shutdown = rt1316_sdw_shutdown, 647 }; 648 649 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000 650 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 651 SNDRV_PCM_FMTBIT_S24_LE) 652 653 static struct snd_soc_dai_driver rt1316_sdw_dai[] = { 654 { 655 .name = "rt1316-aif", 656 .playback = { 657 .stream_name = "DP1 Playback", 658 .channels_min = 1, 659 .channels_max = 2, 660 .rates = RT1316_STEREO_RATES, 661 .formats = RT1316_FORMATS, 662 }, 663 .capture = { 664 .stream_name = "DP2 Capture", 665 .channels_min = 1, 666 .channels_max = 2, 667 .rates = RT1316_STEREO_RATES, 668 .formats = RT1316_FORMATS, 669 }, 670 .ops = &rt1316_aif_dai_ops, 671 }, 672 }; 673 674 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap, 675 struct sdw_slave *slave) 676 { 677 struct rt1316_sdw_priv *rt1316; 678 int ret; 679 680 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL); 681 if (!rt1316) 682 return -ENOMEM; 683 684 dev_set_drvdata(dev, rt1316); 685 rt1316->sdw_slave = slave; 686 rt1316->regmap = regmap; 687 688 /* 689 * Mark hw_init to false 690 * HW init will be performed when device reports present 691 */ 692 rt1316->hw_init = false; 693 rt1316->first_hw_init = false; 694 695 ret = devm_snd_soc_register_component(dev, 696 &soc_component_sdw_rt1316, 697 rt1316_sdw_dai, 698 ARRAY_SIZE(rt1316_sdw_dai)); 699 700 dev_dbg(&slave->dev, "%s\n", __func__); 701 702 return ret; 703 } 704 705 static int rt1316_sdw_probe(struct sdw_slave *slave, 706 const struct sdw_device_id *id) 707 { 708 struct regmap *regmap; 709 710 /* Regmap Initialization */ 711 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap); 712 if (IS_ERR(regmap)) 713 return PTR_ERR(regmap); 714 715 return rt1316_sdw_init(&slave->dev, regmap, slave); 716 } 717 718 static int rt1316_sdw_remove(struct sdw_slave *slave) 719 { 720 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 721 722 if (rt1316->first_hw_init) 723 pm_runtime_disable(&slave->dev); 724 725 return 0; 726 } 727 728 static const struct sdw_device_id rt1316_id[] = { 729 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0), 730 {}, 731 }; 732 MODULE_DEVICE_TABLE(sdw, rt1316_id); 733 734 static int __maybe_unused rt1316_dev_suspend(struct device *dev) 735 { 736 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 737 738 if (!rt1316->hw_init) 739 return 0; 740 741 regcache_cache_only(rt1316->regmap, true); 742 743 return 0; 744 } 745 746 #define RT1316_PROBE_TIMEOUT 5000 747 748 static int __maybe_unused rt1316_dev_resume(struct device *dev) 749 { 750 struct sdw_slave *slave = dev_to_sdw_dev(dev); 751 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 752 unsigned long time; 753 754 if (!rt1316->first_hw_init) 755 return 0; 756 757 if (!slave->unattach_request) 758 goto regmap_sync; 759 760 time = wait_for_completion_timeout(&slave->initialization_complete, 761 msecs_to_jiffies(RT1316_PROBE_TIMEOUT)); 762 if (!time) { 763 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 764 sdw_show_ping_status(slave->bus, true); 765 766 return -ETIMEDOUT; 767 } 768 769 regmap_sync: 770 slave->unattach_request = 0; 771 regcache_cache_only(rt1316->regmap, false); 772 regcache_sync(rt1316->regmap); 773 774 return 0; 775 } 776 777 static const struct dev_pm_ops rt1316_pm = { 778 SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume) 779 SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL) 780 }; 781 782 static struct sdw_driver rt1316_sdw_driver = { 783 .driver = { 784 .name = "rt1316-sdca", 785 .owner = THIS_MODULE, 786 .pm = &rt1316_pm, 787 }, 788 .probe = rt1316_sdw_probe, 789 .remove = rt1316_sdw_remove, 790 .ops = &rt1316_slave_ops, 791 .id_table = rt1316_id, 792 }; 793 module_sdw_driver(rt1316_sdw_driver); 794 795 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW"); 796 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 797 MODULE_LICENSE("GPL"); 798