1 /* 2 * rt1308.c -- RT1308 ALSA SoC amplifier component driver 3 * 4 * Copyright 2019 Realtek Semiconductor Corp. 5 * Author: Derek Fang <derek.fang@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/gpio.h> 18 #include <linux/i2c.h> 19 #include <linux/regmap.h> 20 #include <linux/of_gpio.h> 21 #include <linux/acpi.h> 22 #include <linux/platform_device.h> 23 #include <linux/firmware.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 32 #include "rl6231.h" 33 #include "rt1308.h" 34 35 static const struct reg_sequence init_list[] = { 36 37 { RT1308_I2C_I2S_SDW_SET, 0x01014005 }, 38 { RT1308_CLASS_D_SET_2, 0x227f5501 }, 39 { RT1308_PADS_1, 0x50150505 }, 40 { RT1308_VREF, 0x18100000 }, 41 { RT1308_IV_SENSE, 0x87010000 }, 42 { RT1308_DUMMY_REG, 0x00000200 }, 43 { RT1308_SIL_DET, 0xe1c30000 }, 44 { RT1308_DC_CAL_2, 0x00ffff00 }, 45 { RT1308_CLK_DET, 0x01000000 }, 46 { RT1308_POWER_STATUS, 0x08800000 }, 47 { RT1308_DAC_SET, 0xafaf0700 }, 48 49 }; 50 #define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list) 51 52 struct rt1308_priv { 53 struct snd_soc_component *component; 54 struct regmap *regmap; 55 56 int sysclk; 57 int sysclk_src; 58 int lrck; 59 int bclk; 60 int master; 61 62 int pll_src; 63 int pll_in; 64 int pll_out; 65 }; 66 67 static const struct reg_default rt1308_reg[] = { 68 69 { 0x01, 0x1f3f5f00 }, 70 { 0x02, 0x07000000 }, 71 { 0x03, 0x80003e00 }, 72 { 0x04, 0x80800600 }, 73 { 0x05, 0x0aaa1a0a }, 74 { 0x06, 0x52000000 }, 75 { 0x07, 0x00000000 }, 76 { 0x08, 0x00600000 }, 77 { 0x09, 0xe1030000 }, 78 { 0x0a, 0x00000000 }, 79 { 0x0b, 0x30000000 }, 80 { 0x0c, 0x7fff7000 }, 81 { 0x10, 0xffff0700 }, 82 { 0x11, 0x0a000000 }, 83 { 0x12, 0x60040000 }, 84 { 0x13, 0x00000000 }, 85 { 0x14, 0x0f300000 }, 86 { 0x15, 0x00000022 }, 87 { 0x16, 0x02000000 }, 88 { 0x17, 0x01004045 }, 89 { 0x18, 0x00000000 }, 90 { 0x19, 0x00000000 }, 91 { 0x1a, 0x80000000 }, 92 { 0x1b, 0x10325476 }, 93 { 0x1c, 0x1d1d0000 }, 94 { 0x20, 0xd2101300 }, 95 { 0x21, 0xf3ffff00 }, 96 { 0x22, 0x00000000 }, 97 { 0x23, 0x00000000 }, 98 { 0x24, 0x00000000 }, 99 { 0x25, 0x00000000 }, 100 { 0x26, 0x00000000 }, 101 { 0x27, 0x00000000 }, 102 { 0x28, 0x00000000 }, 103 { 0x29, 0x00000000 }, 104 { 0x2a, 0x00000000 }, 105 { 0x2b, 0x00000000 }, 106 { 0x2c, 0x00000000 }, 107 { 0x2d, 0x00000000 }, 108 { 0x2e, 0x00000000 }, 109 { 0x2f, 0x00000000 }, 110 { 0x30, 0x01000000 }, 111 { 0x31, 0x20025501 }, 112 { 0x32, 0x00000000 }, 113 { 0x33, 0x105a0000 }, 114 { 0x34, 0x10100000 }, 115 { 0x35, 0x2aaa52aa }, 116 { 0x36, 0x00c00000 }, 117 { 0x37, 0x20046100 }, 118 { 0x50, 0x10022f00 }, 119 { 0x51, 0x003c0000 }, 120 { 0x54, 0x04000000 }, 121 { 0x55, 0x01000000 }, 122 { 0x56, 0x02000000 }, 123 { 0x57, 0x02000000 }, 124 { 0x58, 0x02000000 }, 125 { 0x59, 0x02000000 }, 126 { 0x5b, 0x02000000 }, 127 { 0x5c, 0x00000000 }, 128 { 0x5d, 0x00000000 }, 129 { 0x5e, 0x00000000 }, 130 { 0x5f, 0x00000000 }, 131 { 0x60, 0x02000000 }, 132 { 0x61, 0x00000000 }, 133 { 0x62, 0x00000000 }, 134 { 0x63, 0x00000000 }, 135 { 0x64, 0x00000000 }, 136 { 0x65, 0x02000000 }, 137 { 0x66, 0x00000000 }, 138 { 0x67, 0x00000000 }, 139 { 0x68, 0x00000000 }, 140 { 0x69, 0x00000000 }, 141 { 0x6a, 0x02000000 }, 142 { 0x6c, 0x00000000 }, 143 { 0x6d, 0x00000000 }, 144 { 0x6e, 0x00000000 }, 145 { 0x70, 0x10EC1308 }, 146 { 0x71, 0x00000000 }, 147 { 0x72, 0x00000000 }, 148 { 0x73, 0x00000000 }, 149 { 0x74, 0x00000000 }, 150 { 0x75, 0x00000000 }, 151 { 0x76, 0x00000000 }, 152 { 0x77, 0x00000000 }, 153 { 0x78, 0x00000000 }, 154 { 0x79, 0x00000000 }, 155 { 0x7a, 0x00000000 }, 156 { 0x7b, 0x00000000 }, 157 { 0x7c, 0x00000000 }, 158 { 0x7d, 0x00000000 }, 159 { 0x7e, 0x00000000 }, 160 { 0x7f, 0x00020f00 }, 161 { 0x80, 0x00000000 }, 162 { 0x81, 0x00000000 }, 163 { 0x82, 0x00000000 }, 164 { 0x83, 0x00000000 }, 165 { 0x84, 0x00000000 }, 166 { 0x85, 0x00000000 }, 167 { 0x86, 0x00000000 }, 168 { 0x87, 0x00000000 }, 169 { 0x88, 0x00000000 }, 170 { 0x89, 0x00000000 }, 171 { 0x8a, 0x00000000 }, 172 { 0x8b, 0x00000000 }, 173 { 0x8c, 0x00000000 }, 174 { 0x8d, 0x00000000 }, 175 { 0x8e, 0x00000000 }, 176 { 0x90, 0x50250905 }, 177 { 0x91, 0x15050000 }, 178 { 0xa0, 0x00000000 }, 179 { 0xa1, 0x00000000 }, 180 { 0xa2, 0x00000000 }, 181 { 0xa3, 0x00000000 }, 182 { 0xa4, 0x00000000 }, 183 { 0xb0, 0x00000000 }, 184 { 0xb1, 0x00000000 }, 185 { 0xb2, 0x00000000 }, 186 { 0xb3, 0x00000000 }, 187 { 0xb4, 0x00000000 }, 188 { 0xb5, 0x00000000 }, 189 { 0xb6, 0x00000000 }, 190 { 0xb7, 0x00000000 }, 191 { 0xb8, 0x00000000 }, 192 { 0xb9, 0x00000000 }, 193 { 0xba, 0x00000000 }, 194 { 0xbb, 0x00000000 }, 195 { 0xc0, 0x01000000 }, 196 { 0xc1, 0x00000000 }, 197 { 0xf0, 0x00000000 }, 198 }; 199 200 static int rt1308_reg_init(struct snd_soc_component *component) 201 { 202 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 203 204 return regmap_multi_reg_write(rt1308->regmap, init_list, 205 RT1308_INIT_REG_LEN); 206 } 207 208 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 209 { 210 switch (reg) { 211 case RT1308_RESET: 212 case RT1308_RESET_N: 213 case RT1308_CLK_2: 214 case RT1308_SIL_DET: 215 case RT1308_CLK_DET: 216 case RT1308_DC_DET: 217 case RT1308_DAC_SET: 218 case RT1308_DAC_BUF: 219 case RT1308_SDW_REG_RDATA: 220 case RT1308_DC_CAL_1: 221 case RT1308_PVDD_OFFSET_CTL: 222 case RT1308_CAL_OFFSET_DAC_PBTL: 223 case RT1308_CAL_OFFSET_DAC_L: 224 case RT1308_CAL_OFFSET_DAC_R: 225 case RT1308_CAL_OFFSET_PWM_L: 226 case RT1308_CAL_OFFSET_PWM_R: 227 case RT1308_CAL_PWM_VOS_ADC_L: 228 case RT1308_CAL_PWM_VOS_ADC_R: 229 case RT1308_MBIAS: 230 case RT1308_POWER_STATUS: 231 case RT1308_POWER_INT: 232 case RT1308_SINE_TONE_GEN_2: 233 case RT1308_BQ_SET: 234 case RT1308_BQ_PARA_UPDATE: 235 case RT1308_VEN_DEV_ID: 236 case RT1308_VERSION_ID: 237 case RT1308_EFUSE_1: 238 case RT1308_EFUSE_READ_PVDD_L: 239 case RT1308_EFUSE_READ_PVDD_R: 240 case RT1308_EFUSE_READ_PVDD_PTBL: 241 case RT1308_EFUSE_READ_DEV: 242 case RT1308_EFUSE_READ_R0: 243 case RT1308_EFUSE_READ_ADC_L: 244 case RT1308_EFUSE_READ_ADC_R: 245 case RT1308_EFUSE_READ_ADC_PBTL: 246 case RT1308_EFUSE_RESERVE: 247 case RT1308_EFUSE_DATA_0_MSB: 248 case RT1308_EFUSE_DATA_0_LSB: 249 case RT1308_EFUSE_DATA_1_MSB: 250 case RT1308_EFUSE_DATA_1_LSB: 251 case RT1308_EFUSE_DATA_2_MSB: 252 case RT1308_EFUSE_DATA_2_LSB: 253 case RT1308_EFUSE_DATA_3_MSB: 254 case RT1308_EFUSE_DATA_3_LSB: 255 case RT1308_EFUSE_STATUS_1: 256 case RT1308_EFUSE_STATUS_2: 257 case RT1308_DUMMY_REG: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 265 { 266 switch (reg) { 267 case RT1308_RESET: 268 case RT1308_RESET_N: 269 case RT1308_CLK_GATING ... RT1308_DC_DET_THRES: 270 case RT1308_DAC_SET ... RT1308_AD_FILTER_SET: 271 case RT1308_DC_CAL_1 ... RT1308_POWER_INT: 272 case RT1308_SINE_TONE_GEN_1: 273 case RT1308_SINE_TONE_GEN_2: 274 case RT1308_BQ_SET: 275 case RT1308_BQ_PARA_UPDATE: 276 case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R: 277 case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2: 278 case RT1308_VEN_DEV_ID: 279 case RT1308_VERSION_ID: 280 case RT1308_SPK_BOUND: 281 case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3: 282 case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE: 283 case RT1308_PADS_1: 284 case RT1308_PADS_2: 285 case RT1308_TEST_MODE: 286 case RT1308_TEST_1: 287 case RT1308_TEST_2: 288 case RT1308_TEST_3: 289 case RT1308_TEST_4: 290 case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2: 291 case RT1308_TCON_1: 292 case RT1308_TCON_2: 293 case RT1308_DUMMY_REG: 294 case RT1308_MAX_REG: 295 return true; 296 default: 297 return false; 298 } 299 } 300 301 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 302 struct snd_kcontrol *kcontrol, int event) 303 { 304 struct snd_soc_component *component = 305 snd_soc_dapm_to_component(w->dapm); 306 307 switch (event) { 308 case SND_SOC_DAPM_POST_PMU: 309 msleep(30); 310 snd_soc_component_update_bits(component, RT1308_POWER_STATUS, 311 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 312 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT); 313 msleep(40); 314 break; 315 case SND_SOC_DAPM_PRE_PMD: 316 snd_soc_component_update_bits(component, RT1308_POWER_STATUS, 317 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0); 318 usleep_range(150000, 200000); 319 break; 320 321 default: 322 break; 323 } 324 325 return 0; 326 } 327 328 static const char * const rt1308_rx_data_ch_select[] = { 329 "LR", 330 "LL", 331 "RL", 332 "RR", 333 }; 334 335 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24, 336 rt1308_rx_data_ch_select); 337 338 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 339 340 /* I2S Data Channel Selection */ 341 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 342 }; 343 344 static const struct snd_kcontrol_new rt1308_sto_dac_l = 345 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET, 346 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 347 348 static const struct snd_kcontrol_new rt1308_sto_dac_r = 349 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET, 350 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 351 352 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 353 /* Audio Interface */ 354 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 355 356 /* Supply Widgets */ 357 SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER, 358 RT1308_POW_MBIAS20U_BIT, 0, NULL, 0), 359 SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER, 360 RT1308_POW_ALDO_BIT, 0, NULL, 0), 361 SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER, 362 RT1308_POW_DBG_BIT, 0, NULL, 0), 363 SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER, 364 RT1308_POW_DACL_BIT, 0, NULL, 0), 365 SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER, 366 RT1308_POW_CLK25M_BIT, 0, NULL, 0), 367 SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER, 368 RT1308_POW_ADC_R_BIT, 0, NULL, 0), 369 SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER, 370 RT1308_POW_ADC_L_BIT, 0, NULL, 0), 371 SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER, 372 RT1308_POW_DLDO_BIT, 0, NULL, 0), 373 SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER, 374 RT1308_POW_VREF_BIT, 0, NULL, 0), 375 SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER, 376 RT1308_POW_MIXER_R_BIT, 0, NULL, 0), 377 SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER, 378 RT1308_POW_MIXER_L_BIT, 0, NULL, 0), 379 SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER, 380 RT1308_POW_MBIAS4U_BIT, 0, NULL, 0), 381 SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER, 382 RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0), 383 SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER, 384 RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0), 385 SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER, 386 RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0), 387 SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER, 388 RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0), 389 SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER, 390 RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0), 391 392 /* Digital Interface */ 393 SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER, 394 RT1308_POW_DAC1_BIT, 0, NULL, 0), 395 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 396 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 397 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 398 399 /* Output Lines */ 400 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 401 rt1308_classd_event, 402 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 403 SND_SOC_DAPM_OUTPUT("SPOL"), 404 SND_SOC_DAPM_OUTPUT("SPOR"), 405 }; 406 407 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 408 409 { "DAC", NULL, "AIF1RX" }, 410 411 { "DAC", NULL, "MBIAS20U" }, 412 { "DAC", NULL, "ALDO" }, 413 { "DAC", NULL, "DBG" }, 414 { "DAC", NULL, "DACL" }, 415 { "DAC", NULL, "CLK25M" }, 416 { "DAC", NULL, "ADC_R" }, 417 { "DAC", NULL, "ADC_L" }, 418 { "DAC", NULL, "DLDO" }, 419 { "DAC", NULL, "VREF" }, 420 { "DAC", NULL, "MIXER_R" }, 421 { "DAC", NULL, "MIXER_L" }, 422 { "DAC", NULL, "MBIAS4U" }, 423 { "DAC", NULL, "PLL2_LDO" }, 424 { "DAC", NULL, "PLL2B" }, 425 { "DAC", NULL, "PLL2F" }, 426 { "DAC", NULL, "PLL2F2" }, 427 { "DAC", NULL, "PLL2B2" }, 428 429 { "DAC L", "Switch", "DAC" }, 430 { "DAC R", "Switch", "DAC" }, 431 { "DAC L", NULL, "DAC Power" }, 432 { "DAC R", NULL, "DAC Power" }, 433 434 { "CLASS D", NULL, "DAC L" }, 435 { "CLASS D", NULL, "DAC R" }, 436 { "SPOL", NULL, "CLASS D" }, 437 { "SPOR", NULL, "CLASS D" }, 438 }; 439 440 static int rt1308_get_clk_info(int sclk, int rate) 441 { 442 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; 443 444 if (sclk <= 0 || rate <= 0) 445 return -EINVAL; 446 447 rate = rate << 8; 448 for (i = 0; i < ARRAY_SIZE(pd); i++) 449 if (sclk == rate * pd[i]) 450 return i; 451 452 return -EINVAL; 453 } 454 455 static int rt1308_hw_params(struct snd_pcm_substream *substream, 456 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 457 { 458 struct snd_soc_component *component = dai->component; 459 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 460 unsigned int val_len = 0, val_clk, mask_clk; 461 int pre_div, bclk_ms, frame_size; 462 463 rt1308->lrck = params_rate(params); 464 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck); 465 if (pre_div < 0) { 466 dev_err(component->dev, 467 "Unsupported clock setting %d\n", rt1308->lrck); 468 return -EINVAL; 469 } 470 471 frame_size = snd_soc_params_to_frame_size(params); 472 if (frame_size < 0) { 473 dev_err(component->dev, "Unsupported frame size: %d\n", 474 frame_size); 475 return -EINVAL; 476 } 477 478 bclk_ms = frame_size > 32; 479 rt1308->bclk = rt1308->lrck * (32 << bclk_ms); 480 481 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 482 bclk_ms, pre_div, dai->id); 483 484 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 485 rt1308->lrck, pre_div, dai->id); 486 487 switch (params_width(params)) { 488 case 16: 489 val_len |= RT1308_I2S_DL_SEL_16B; 490 break; 491 case 20: 492 val_len |= RT1308_I2S_DL_SEL_20B; 493 break; 494 case 24: 495 val_len |= RT1308_I2S_DL_SEL_24B; 496 break; 497 case 8: 498 val_len |= RT1308_I2S_DL_SEL_8B; 499 break; 500 default: 501 return -EINVAL; 502 } 503 504 switch (dai->id) { 505 case RT1308_AIF1: 506 mask_clk = RT1308_DIV_FS_SYS_MASK; 507 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT; 508 snd_soc_component_update_bits(component, 509 RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK, 510 val_len); 511 break; 512 default: 513 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 514 return -EINVAL; 515 } 516 517 snd_soc_component_update_bits(component, RT1308_CLK_1, 518 mask_clk, val_clk); 519 520 return 0; 521 } 522 523 static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 524 { 525 struct snd_soc_component *component = dai->component; 526 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 527 unsigned int reg_val = 0, reg1_val = 0; 528 529 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 530 case SND_SOC_DAIFMT_CBS_CFS: 531 rt1308->master = 0; 532 break; 533 default: 534 return -EINVAL; 535 } 536 537 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 538 case SND_SOC_DAIFMT_I2S: 539 break; 540 case SND_SOC_DAIFMT_LEFT_J: 541 reg_val |= RT1308_I2S_DF_SEL_LEFT; 542 break; 543 case SND_SOC_DAIFMT_DSP_A: 544 reg_val |= RT1308_I2S_DF_SEL_PCM_A; 545 break; 546 case SND_SOC_DAIFMT_DSP_B: 547 reg_val |= RT1308_I2S_DF_SEL_PCM_B; 548 break; 549 default: 550 return -EINVAL; 551 } 552 553 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 554 case SND_SOC_DAIFMT_NB_NF: 555 break; 556 case SND_SOC_DAIFMT_IB_NF: 557 reg1_val |= RT1308_I2S_BCLK_INV; 558 break; 559 default: 560 return -EINVAL; 561 } 562 563 switch (dai->id) { 564 case RT1308_AIF1: 565 snd_soc_component_update_bits(component, 566 RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK, 567 reg_val); 568 snd_soc_component_update_bits(component, 569 RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK, 570 reg1_val); 571 break; 572 default: 573 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 574 return -EINVAL; 575 } 576 return 0; 577 } 578 579 static int rt1308_set_component_sysclk(struct snd_soc_component *component, 580 int clk_id, int source, unsigned int freq, int dir) 581 { 582 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 583 unsigned int reg_val = 0; 584 585 if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src) 586 return 0; 587 588 switch (clk_id) { 589 case RT1308_FS_SYS_S_MCLK: 590 reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK; 591 snd_soc_component_update_bits(component, 592 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK, 593 RT1308_MCLK_DET_EN); 594 break; 595 case RT1308_FS_SYS_S_BCLK: 596 reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK; 597 break; 598 case RT1308_FS_SYS_S_PLL: 599 reg_val |= RT1308_SEL_FS_SYS_SRC_PLL; 600 break; 601 case RT1308_FS_SYS_S_RCCLK: 602 reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK; 603 break; 604 default: 605 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 606 return -EINVAL; 607 } 608 snd_soc_component_update_bits(component, RT1308_CLK_1, 609 RT1308_SEL_FS_SYS_MASK, reg_val); 610 rt1308->sysclk = freq; 611 rt1308->sysclk_src = clk_id; 612 613 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 614 freq, clk_id); 615 616 return 0; 617 } 618 619 static int rt1308_set_component_pll(struct snd_soc_component *component, 620 int pll_id, int source, unsigned int freq_in, 621 unsigned int freq_out) 622 { 623 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 624 struct rl6231_pll_code pll_code; 625 int ret; 626 627 if (source == rt1308->pll_src && freq_in == rt1308->pll_in && 628 freq_out == rt1308->pll_out) 629 return 0; 630 631 if (!freq_in || !freq_out) { 632 dev_dbg(component->dev, "PLL disabled\n"); 633 634 rt1308->pll_in = 0; 635 rt1308->pll_out = 0; 636 snd_soc_component_update_bits(component, 637 RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK, 638 RT1308_SEL_FS_SYS_SRC_MCLK); 639 return 0; 640 } 641 642 switch (source) { 643 case RT1308_PLL_S_MCLK: 644 snd_soc_component_update_bits(component, 645 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK, 646 RT1308_SEL_PLL_SRC_MCLK); 647 snd_soc_component_update_bits(component, 648 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK, 649 RT1308_MCLK_DET_EN); 650 break; 651 case RT1308_PLL_S_BCLK: 652 snd_soc_component_update_bits(component, 653 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK, 654 RT1308_SEL_PLL_SRC_BCLK); 655 break; 656 case RT1308_PLL_S_RCCLK: 657 snd_soc_component_update_bits(component, 658 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK, 659 RT1308_SEL_PLL_SRC_RCCLK); 660 freq_in = 25000000; 661 break; 662 default: 663 dev_err(component->dev, "Unknown PLL Source %d\n", source); 664 return -EINVAL; 665 } 666 667 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 668 if (ret < 0) { 669 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 670 return ret; 671 } 672 673 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 674 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 675 pll_code.n_code, pll_code.k_code); 676 677 snd_soc_component_write(component, RT1308_PLL_1, 678 pll_code.k_code << RT1308_PLL1_K_SFT | 679 pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT | 680 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT | 681 pll_code.n_code << RT1308_PLL1_N_SFT); 682 683 rt1308->pll_in = freq_in; 684 rt1308->pll_out = freq_out; 685 rt1308->pll_src = source; 686 687 return 0; 688 } 689 690 static int rt1308_probe(struct snd_soc_component *component) 691 { 692 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 693 694 rt1308->component = component; 695 696 return rt1308_reg_init(component); 697 } 698 699 static void rt1308_remove(struct snd_soc_component *component) 700 { 701 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 702 703 regmap_write(rt1308->regmap, RT1308_RESET, 0); 704 } 705 706 #ifdef CONFIG_PM 707 static int rt1308_suspend(struct snd_soc_component *component) 708 { 709 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 710 711 regcache_cache_only(rt1308->regmap, true); 712 regcache_mark_dirty(rt1308->regmap); 713 714 return 0; 715 } 716 717 static int rt1308_resume(struct snd_soc_component *component) 718 { 719 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component); 720 721 regcache_cache_only(rt1308->regmap, false); 722 regcache_sync(rt1308->regmap); 723 724 return 0; 725 } 726 #else 727 #define rt1308_suspend NULL 728 #define rt1308_resume NULL 729 #endif 730 731 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 732 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 733 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 734 SNDRV_PCM_FMTBIT_S24_LE) 735 736 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 737 .hw_params = rt1308_hw_params, 738 .set_fmt = rt1308_set_dai_fmt, 739 }; 740 741 static struct snd_soc_dai_driver rt1308_dai[] = { 742 { 743 .name = "rt1308-aif", 744 .playback = { 745 .stream_name = "AIF1 Playback", 746 .channels_min = 1, 747 .channels_max = 2, 748 .rates = RT1308_STEREO_RATES, 749 .formats = RT1308_FORMATS, 750 }, 751 .ops = &rt1308_aif_dai_ops, 752 }, 753 }; 754 755 static const struct snd_soc_component_driver soc_component_dev_rt1308 = { 756 .probe = rt1308_probe, 757 .remove = rt1308_remove, 758 .suspend = rt1308_suspend, 759 .resume = rt1308_resume, 760 .controls = rt1308_snd_controls, 761 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 762 .dapm_widgets = rt1308_dapm_widgets, 763 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 764 .dapm_routes = rt1308_dapm_routes, 765 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 766 .set_sysclk = rt1308_set_component_sysclk, 767 .set_pll = rt1308_set_component_pll, 768 .use_pmdown_time = 1, 769 .endianness = 1, 770 .non_legacy_dai_naming = 1, 771 }; 772 773 static const struct regmap_config rt1308_regmap = { 774 .reg_bits = 8, 775 .val_bits = 32, 776 .max_register = RT1308_MAX_REG, 777 .volatile_reg = rt1308_volatile_register, 778 .readable_reg = rt1308_readable_register, 779 .cache_type = REGCACHE_RBTREE, 780 .reg_defaults = rt1308_reg, 781 .num_reg_defaults = ARRAY_SIZE(rt1308_reg), 782 .use_single_read = true, 783 .use_single_write = true, 784 }; 785 786 #ifdef CONFIG_OF 787 static const struct of_device_id rt1308_of_match[] = { 788 { .compatible = "realtek,rt1308", }, 789 { }, 790 }; 791 MODULE_DEVICE_TABLE(of, rt1308_of_match); 792 #endif 793 794 #ifdef CONFIG_ACPI 795 static struct acpi_device_id rt1308_acpi_match[] = { 796 { "10EC1308", 0, }, 797 { }, 798 }; 799 MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match); 800 #endif 801 802 static const struct i2c_device_id rt1308_i2c_id[] = { 803 { "rt1308", 0 }, 804 { } 805 }; 806 MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id); 807 808 static void rt1308_efuse(struct rt1308_priv *rt1308) 809 { 810 regmap_write(rt1308->regmap, RT1308_RESET, 0); 811 812 regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000); 813 msleep(100); 814 regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00); 815 msleep(20); 816 regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000); 817 } 818 819 static int rt1308_i2c_probe(struct i2c_client *i2c, 820 const struct i2c_device_id *id) 821 { 822 struct rt1308_priv *rt1308; 823 int ret; 824 unsigned int val; 825 826 rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv), 827 GFP_KERNEL); 828 if (rt1308 == NULL) 829 return -ENOMEM; 830 831 i2c_set_clientdata(i2c, rt1308); 832 833 rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap); 834 if (IS_ERR(rt1308->regmap)) { 835 ret = PTR_ERR(rt1308->regmap); 836 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 837 ret); 838 return ret; 839 } 840 841 regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val); 842 /* ignore last byte difference */ 843 if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) { 844 dev_err(&i2c->dev, 845 "Device with ID register %x is not rt1308\n", val); 846 return -ENODEV; 847 } 848 849 rt1308_efuse(rt1308); 850 851 return devm_snd_soc_register_component(&i2c->dev, 852 &soc_component_dev_rt1308, 853 rt1308_dai, ARRAY_SIZE(rt1308_dai)); 854 } 855 856 static void rt1308_i2c_shutdown(struct i2c_client *client) 857 { 858 struct rt1308_priv *rt1308 = i2c_get_clientdata(client); 859 860 regmap_write(rt1308->regmap, RT1308_RESET, 0); 861 } 862 863 static struct i2c_driver rt1308_i2c_driver = { 864 .driver = { 865 .name = "rt1308", 866 .of_match_table = of_match_ptr(rt1308_of_match), 867 .acpi_match_table = ACPI_PTR(rt1308_acpi_match), 868 }, 869 .probe = rt1308_i2c_probe, 870 .shutdown = rt1308_i2c_shutdown, 871 .id_table = rt1308_i2c_id, 872 }; 873 module_i2c_driver(rt1308_i2c_driver); 874 875 MODULE_DESCRIPTION("ASoC RT1308 amplifier driver"); 876 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>"); 877 MODULE_LICENSE("GPL v2"); 878