1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/initval.h> 23 24 #include "rt1308.h" 25 #include "rt1308-sdw.h" 26 27 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 28 { 29 switch (reg) { 30 case 0x00e0: 31 case 0x00f0: 32 case 0x2f01 ... 0x2f07: 33 case 0x3000 ... 0x3001: 34 case 0x3004 ... 0x3005: 35 case 0x3008: 36 case 0x300a: 37 case 0xc000 ... 0xcff3: 38 return true; 39 default: 40 return false; 41 } 42 } 43 44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 45 { 46 switch (reg) { 47 case 0x2f01 ... 0x2f07: 48 case 0x3000 ... 0x3001: 49 case 0x3004 ... 0x3005: 50 case 0x3008: 51 case 0x300a: 52 case 0xc000: 53 return true; 54 default: 55 return false; 56 } 57 } 58 59 static const struct regmap_config rt1308_sdw_regmap = { 60 .reg_bits = 32, 61 .val_bits = 8, 62 .readable_reg = rt1308_readable_register, 63 .volatile_reg = rt1308_volatile_register, 64 .max_register = 0xcfff, 65 .reg_defaults = rt1308_reg_defaults, 66 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 67 .cache_type = REGCACHE_RBTREE, 68 .use_single_read = true, 69 .use_single_write = true, 70 }; 71 72 /* Bus clock frequency */ 73 #define RT1308_CLK_FREQ_9600000HZ 9600000 74 #define RT1308_CLK_FREQ_12000000HZ 12000000 75 #define RT1308_CLK_FREQ_6000000HZ 6000000 76 #define RT1308_CLK_FREQ_4800000HZ 4800000 77 #define RT1308_CLK_FREQ_2400000HZ 2400000 78 #define RT1308_CLK_FREQ_12288000HZ 12288000 79 80 static int rt1308_clock_config(struct device *dev) 81 { 82 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 83 unsigned int clk_freq, value; 84 85 clk_freq = (rt1308->params.curr_dr_freq >> 1); 86 87 switch (clk_freq) { 88 case RT1308_CLK_FREQ_12000000HZ: 89 value = 0x0; 90 break; 91 case RT1308_CLK_FREQ_6000000HZ: 92 value = 0x1; 93 break; 94 case RT1308_CLK_FREQ_9600000HZ: 95 value = 0x2; 96 break; 97 case RT1308_CLK_FREQ_4800000HZ: 98 value = 0x3; 99 break; 100 case RT1308_CLK_FREQ_2400000HZ: 101 value = 0x4; 102 break; 103 case RT1308_CLK_FREQ_12288000HZ: 104 value = 0x5; 105 break; 106 default: 107 return -EINVAL; 108 } 109 110 regmap_write(rt1308->regmap, 0xe0, value); 111 regmap_write(rt1308->regmap, 0xf0, value); 112 113 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 114 115 return 0; 116 } 117 118 static int rt1308_read_prop(struct sdw_slave *slave) 119 { 120 struct sdw_slave_prop *prop = &slave->prop; 121 int nval, i, num_of_ports = 1; 122 u32 bit; 123 unsigned long addr; 124 struct sdw_dpn_prop *dpn; 125 126 prop->paging_support = true; 127 128 /* first we need to allocate memory for set bits in port lists */ 129 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 130 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 131 132 /* for sink */ 133 nval = hweight32(prop->sink_ports); 134 num_of_ports += nval; 135 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 136 sizeof(*prop->sink_dpn_prop), 137 GFP_KERNEL); 138 if (!prop->sink_dpn_prop) 139 return -ENOMEM; 140 141 i = 0; 142 dpn = prop->sink_dpn_prop; 143 addr = prop->sink_ports; 144 for_each_set_bit(bit, &addr, 32) { 145 dpn[i].num = bit; 146 dpn[i].type = SDW_DPN_FULL; 147 dpn[i].simple_ch_prep_sm = true; 148 dpn[i].ch_prep_timeout = 10; 149 i++; 150 } 151 152 /* Allocate port_ready based on num_of_ports */ 153 slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports, 154 sizeof(*slave->port_ready), 155 GFP_KERNEL); 156 if (!slave->port_ready) 157 return -ENOMEM; 158 159 /* Initialize completion */ 160 for (i = 0; i < num_of_ports; i++) 161 init_completion(&slave->port_ready[i]); 162 163 /* set the timeout values */ 164 prop->clk_stop_timeout = 20; 165 166 dev_dbg(&slave->dev, "%s\n", __func__); 167 168 return 0; 169 } 170 171 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 172 { 173 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 174 int ret = 0; 175 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 176 unsigned int efuse_c_btl_l, efuse_c_btl_r; 177 178 if (rt1308->hw_init) 179 return 0; 180 181 if (rt1308->first_hw_init) { 182 regcache_cache_only(rt1308->regmap, false); 183 regcache_cache_bypass(rt1308->regmap, true); 184 } 185 186 /* 187 * PM runtime is only enabled when a Slave reports as Attached 188 */ 189 if (!rt1308->first_hw_init) { 190 /* set autosuspend parameters */ 191 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 192 pm_runtime_use_autosuspend(&slave->dev); 193 194 /* update count of parent 'active' children */ 195 pm_runtime_set_active(&slave->dev); 196 197 /* make sure the device does not suspend immediately */ 198 pm_runtime_mark_last_busy(&slave->dev); 199 200 pm_runtime_enable(&slave->dev); 201 } 202 203 pm_runtime_get_noresume(&slave->dev); 204 205 /* sw reset */ 206 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 207 208 /* read efuse */ 209 regmap_write(rt1308->regmap, 0xc360, 0x01); 210 regmap_write(rt1308->regmap, 0xc361, 0x80); 211 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 212 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 213 msleep(100); 214 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 215 msleep(20); 216 regmap_write(rt1308->regmap, 0xc240, 0x10); 217 218 regmap_read(rt1308->regmap, 0xc861, &tmp); 219 efuse_m_btl_l = tmp; 220 regmap_read(rt1308->regmap, 0xc860, &tmp); 221 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 222 regmap_read(rt1308->regmap, 0xc863, &tmp); 223 efuse_c_btl_l = tmp; 224 regmap_read(rt1308->regmap, 0xc862, &tmp); 225 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 226 regmap_read(rt1308->regmap, 0xc871, &tmp); 227 efuse_m_btl_r = tmp; 228 regmap_read(rt1308->regmap, 0xc870, &tmp); 229 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 230 regmap_read(rt1308->regmap, 0xc873, &tmp); 231 efuse_c_btl_r = tmp; 232 regmap_read(rt1308->regmap, 0xc872, &tmp); 233 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 234 dev_dbg(&slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 235 efuse_m_btl_l, efuse_m_btl_r); 236 dev_dbg(&slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 237 efuse_c_btl_l, efuse_c_btl_r); 238 239 /* initial settings */ 240 regmap_write(rt1308->regmap, 0xc103, 0xc0); 241 regmap_write(rt1308->regmap, 0xc030, 0x17); 242 regmap_write(rt1308->regmap, 0xc031, 0x81); 243 regmap_write(rt1308->regmap, 0xc032, 0x26); 244 regmap_write(rt1308->regmap, 0xc040, 0x80); 245 regmap_write(rt1308->regmap, 0xc041, 0x80); 246 regmap_write(rt1308->regmap, 0xc042, 0x06); 247 regmap_write(rt1308->regmap, 0xc052, 0x0a); 248 regmap_write(rt1308->regmap, 0xc080, 0x0a); 249 regmap_write(rt1308->regmap, 0xc060, 0x02); 250 regmap_write(rt1308->regmap, 0xc061, 0x75); 251 regmap_write(rt1308->regmap, 0xc062, 0x05); 252 regmap_write(rt1308->regmap, 0xc171, 0x07); 253 regmap_write(rt1308->regmap, 0xc173, 0x0d); 254 regmap_write(rt1308->regmap, 0xc311, 0x7f); 255 regmap_write(rt1308->regmap, 0xc900, 0x90); 256 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 257 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 258 regmap_write(rt1308->regmap, 0xc360, 0x78); 259 regmap_write(rt1308->regmap, 0xc361, 0x87); 260 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 261 regmap_write(rt1308->regmap, 0xc210, 0x00); 262 regmap_write(rt1308->regmap, 0xc070, 0x00); 263 regmap_write(rt1308->regmap, 0xc100, 0xd7); 264 regmap_write(rt1308->regmap, 0xc101, 0xd7); 265 regmap_write(rt1308->regmap, 0xc300, 0x09); 266 267 if (rt1308->first_hw_init) { 268 regcache_cache_bypass(rt1308->regmap, false); 269 regcache_mark_dirty(rt1308->regmap); 270 } else 271 rt1308->first_hw_init = true; 272 273 /* Mark Slave initialization complete */ 274 rt1308->hw_init = true; 275 276 pm_runtime_mark_last_busy(&slave->dev); 277 pm_runtime_put_autosuspend(&slave->dev); 278 279 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 280 281 return ret; 282 } 283 284 static int rt1308_update_status(struct sdw_slave *slave, 285 enum sdw_slave_status status) 286 { 287 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 288 289 /* Update the status */ 290 rt1308->status = status; 291 292 if (status == SDW_SLAVE_UNATTACHED) 293 rt1308->hw_init = false; 294 295 /* 296 * Perform initialization only if slave status is present and 297 * hw_init flag is false 298 */ 299 if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED) 300 return 0; 301 302 /* perform I/O transfers required for Slave initialization */ 303 return rt1308_io_init(&slave->dev, slave); 304 } 305 306 static int rt1308_bus_config(struct sdw_slave *slave, 307 struct sdw_bus_params *params) 308 { 309 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 310 int ret; 311 312 memcpy(&rt1308->params, params, sizeof(*params)); 313 314 ret = rt1308_clock_config(&slave->dev); 315 if (ret < 0) 316 dev_err(&slave->dev, "Invalid clk config"); 317 318 return ret; 319 } 320 321 static int rt1308_interrupt_callback(struct sdw_slave *slave, 322 struct sdw_slave_intr_status *status) 323 { 324 dev_dbg(&slave->dev, 325 "%s control_port_stat=%x", __func__, status->control_port); 326 327 return 0; 328 } 329 330 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 331 struct snd_kcontrol *kcontrol, int event) 332 { 333 struct snd_soc_component *component = 334 snd_soc_dapm_to_component(w->dapm); 335 336 switch (event) { 337 case SND_SOC_DAPM_POST_PMU: 338 msleep(30); 339 snd_soc_component_update_bits(component, 340 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 341 0x3, 0x3); 342 msleep(40); 343 break; 344 case SND_SOC_DAPM_PRE_PMD: 345 snd_soc_component_update_bits(component, 346 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 347 0x3, 0); 348 usleep_range(150000, 200000); 349 break; 350 351 default: 352 break; 353 } 354 355 return 0; 356 } 357 358 static const char * const rt1308_rx_data_ch_select[] = { 359 "LR", 360 "LL", 361 "RL", 362 "RR", 363 }; 364 365 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 366 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 367 rt1308_rx_data_ch_select); 368 369 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 370 371 /* I2S Data Channel Selection */ 372 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 373 }; 374 375 static const struct snd_kcontrol_new rt1308_sto_dac_l = 376 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 377 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 378 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 379 380 static const struct snd_kcontrol_new rt1308_sto_dac_r = 381 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 382 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 383 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 384 385 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 386 /* Audio Interface */ 387 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 388 389 /* Supply Widgets */ 390 SND_SOC_DAPM_SUPPLY("MBIAS20U", 391 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 392 SND_SOC_DAPM_SUPPLY("ALDO", 393 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 394 SND_SOC_DAPM_SUPPLY("DBG", 395 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 396 SND_SOC_DAPM_SUPPLY("DACL", 397 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 398 SND_SOC_DAPM_SUPPLY("CLK25M", 399 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 400 SND_SOC_DAPM_SUPPLY("ADC_R", 401 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 402 SND_SOC_DAPM_SUPPLY("ADC_L", 403 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 404 SND_SOC_DAPM_SUPPLY("DAC Power", 405 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 406 407 SND_SOC_DAPM_SUPPLY("DLDO", 408 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 409 SND_SOC_DAPM_SUPPLY("VREF", 410 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 411 SND_SOC_DAPM_SUPPLY("MIXER_R", 412 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 413 SND_SOC_DAPM_SUPPLY("MIXER_L", 414 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 415 SND_SOC_DAPM_SUPPLY("MBIAS4U", 416 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 417 418 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 419 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 420 SND_SOC_DAPM_SUPPLY("PLL2B", 421 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 422 SND_SOC_DAPM_SUPPLY("PLL2F", 423 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 424 SND_SOC_DAPM_SUPPLY("PLL2F2", 425 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 426 SND_SOC_DAPM_SUPPLY("PLL2B2", 427 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 428 429 /* Digital Interface */ 430 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 431 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 432 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 433 434 /* Output Lines */ 435 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 436 rt1308_classd_event, 437 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 438 SND_SOC_DAPM_OUTPUT("SPOL"), 439 SND_SOC_DAPM_OUTPUT("SPOR"), 440 }; 441 442 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 443 444 { "DAC", NULL, "AIF1RX" }, 445 446 { "DAC", NULL, "MBIAS20U" }, 447 { "DAC", NULL, "ALDO" }, 448 { "DAC", NULL, "DBG" }, 449 { "DAC", NULL, "DACL" }, 450 { "DAC", NULL, "CLK25M" }, 451 { "DAC", NULL, "ADC_R" }, 452 { "DAC", NULL, "ADC_L" }, 453 { "DAC", NULL, "DLDO" }, 454 { "DAC", NULL, "VREF" }, 455 { "DAC", NULL, "MIXER_R" }, 456 { "DAC", NULL, "MIXER_L" }, 457 { "DAC", NULL, "MBIAS4U" }, 458 { "DAC", NULL, "PLL2_LDO" }, 459 { "DAC", NULL, "PLL2B" }, 460 { "DAC", NULL, "PLL2F" }, 461 { "DAC", NULL, "PLL2F2" }, 462 { "DAC", NULL, "PLL2B2" }, 463 464 { "DAC L", "Switch", "DAC" }, 465 { "DAC R", "Switch", "DAC" }, 466 { "DAC L", NULL, "DAC Power" }, 467 { "DAC R", NULL, "DAC Power" }, 468 469 { "CLASS D", NULL, "DAC L" }, 470 { "CLASS D", NULL, "DAC R" }, 471 { "SPOL", NULL, "CLASS D" }, 472 { "SPOR", NULL, "CLASS D" }, 473 }; 474 475 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 476 int direction) 477 { 478 struct sdw_stream_data *stream; 479 480 if (!sdw_stream) 481 return 0; 482 483 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 484 if (!stream) 485 return -ENOMEM; 486 487 stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream; 488 489 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 490 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 491 dai->playback_dma_data = stream; 492 else 493 dai->capture_dma_data = stream; 494 495 return 0; 496 } 497 498 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 499 struct snd_soc_dai *dai) 500 { 501 struct sdw_stream_data *stream; 502 503 stream = snd_soc_dai_get_dma_data(dai, substream); 504 snd_soc_dai_set_dma_data(dai, substream, NULL); 505 kfree(stream); 506 } 507 508 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 509 unsigned int tx_mask, 510 unsigned int rx_mask, 511 int slots, int slot_width) 512 { 513 struct snd_soc_component *component = dai->component; 514 struct rt1308_sdw_priv *rt1308 = 515 snd_soc_component_get_drvdata(component); 516 517 if (tx_mask) 518 return -EINVAL; 519 520 if (slots > 2) 521 return -EINVAL; 522 523 rt1308->rx_mask = rx_mask; 524 rt1308->slots = slots; 525 /* slot_width is not used since it's irrelevant for SoundWire */ 526 527 return 0; 528 } 529 530 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 531 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 532 { 533 struct snd_soc_component *component = dai->component; 534 struct rt1308_sdw_priv *rt1308 = 535 snd_soc_component_get_drvdata(component); 536 struct sdw_stream_config stream_config; 537 struct sdw_port_config port_config; 538 enum sdw_data_direction direction; 539 struct sdw_stream_data *stream; 540 int retval, port, num_channels, ch_mask; 541 542 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 543 stream = snd_soc_dai_get_dma_data(dai, substream); 544 545 if (!stream) 546 return -EINVAL; 547 548 if (!rt1308->sdw_slave) 549 return -EINVAL; 550 551 /* SoundWire specific configuration */ 552 /* port 1 for playback */ 553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 554 direction = SDW_DATA_DIR_RX; 555 port = 1; 556 } else { 557 return -EINVAL; 558 } 559 560 if (rt1308->slots) { 561 num_channels = rt1308->slots; 562 ch_mask = rt1308->rx_mask; 563 } else { 564 num_channels = params_channels(params); 565 ch_mask = (1 << num_channels) - 1; 566 } 567 568 stream_config.frame_rate = params_rate(params); 569 stream_config.ch_count = num_channels; 570 stream_config.bps = snd_pcm_format_width(params_format(params)); 571 stream_config.direction = direction; 572 573 port_config.ch_mask = ch_mask; 574 port_config.num = port; 575 576 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 577 &port_config, 1, stream->sdw_stream); 578 if (retval) { 579 dev_err(dai->dev, "Unable to configure port\n"); 580 return retval; 581 } 582 583 return retval; 584 } 585 586 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 587 struct snd_soc_dai *dai) 588 { 589 struct snd_soc_component *component = dai->component; 590 struct rt1308_sdw_priv *rt1308 = 591 snd_soc_component_get_drvdata(component); 592 struct sdw_stream_data *stream = 593 snd_soc_dai_get_dma_data(dai, substream); 594 595 if (!rt1308->sdw_slave) 596 return -EINVAL; 597 598 sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream); 599 return 0; 600 } 601 602 /* 603 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 604 * port_prep are not defined for now 605 */ 606 static struct sdw_slave_ops rt1308_slave_ops = { 607 .read_prop = rt1308_read_prop, 608 .interrupt_callback = rt1308_interrupt_callback, 609 .update_status = rt1308_update_status, 610 .bus_config = rt1308_bus_config, 611 }; 612 613 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 614 .controls = rt1308_snd_controls, 615 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 616 .dapm_widgets = rt1308_dapm_widgets, 617 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 618 .dapm_routes = rt1308_dapm_routes, 619 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 620 }; 621 622 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 623 .hw_params = rt1308_sdw_hw_params, 624 .hw_free = rt1308_sdw_pcm_hw_free, 625 .set_sdw_stream = rt1308_set_sdw_stream, 626 .shutdown = rt1308_sdw_shutdown, 627 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 628 }; 629 630 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 631 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 632 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 633 SNDRV_PCM_FMTBIT_S24_LE) 634 635 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 636 { 637 .name = "rt1308-aif", 638 .playback = { 639 .stream_name = "DP1 Playback", 640 .channels_min = 1, 641 .channels_max = 2, 642 .rates = RT1308_STEREO_RATES, 643 .formats = RT1308_FORMATS, 644 }, 645 .ops = &rt1308_aif_dai_ops, 646 }, 647 }; 648 649 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 650 struct sdw_slave *slave) 651 { 652 struct rt1308_sdw_priv *rt1308; 653 int ret; 654 655 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 656 if (!rt1308) 657 return -ENOMEM; 658 659 dev_set_drvdata(dev, rt1308); 660 rt1308->sdw_slave = slave; 661 rt1308->regmap = regmap; 662 663 /* 664 * Mark hw_init to false 665 * HW init will be performed when device reports present 666 */ 667 rt1308->hw_init = false; 668 rt1308->first_hw_init = false; 669 670 ret = devm_snd_soc_register_component(dev, 671 &soc_component_sdw_rt1308, 672 rt1308_sdw_dai, 673 ARRAY_SIZE(rt1308_sdw_dai)); 674 675 dev_dbg(&slave->dev, "%s\n", __func__); 676 677 return ret; 678 } 679 680 static int rt1308_sdw_probe(struct sdw_slave *slave, 681 const struct sdw_device_id *id) 682 { 683 struct regmap *regmap; 684 685 /* Regmap Initialization */ 686 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 687 if (!regmap) 688 return -EINVAL; 689 690 rt1308_sdw_init(&slave->dev, regmap, slave); 691 692 return 0; 693 } 694 695 static const struct sdw_device_id rt1308_id[] = { 696 SDW_SLAVE_ENTRY(0x025d, 0x1308, 0), 697 {}, 698 }; 699 MODULE_DEVICE_TABLE(sdw, rt1308_id); 700 701 static int __maybe_unused rt1308_dev_suspend(struct device *dev) 702 { 703 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 704 705 if (!rt1308->hw_init) 706 return 0; 707 708 regcache_cache_only(rt1308->regmap, true); 709 710 return 0; 711 } 712 713 #define RT1308_PROBE_TIMEOUT 2000 714 715 static int __maybe_unused rt1308_dev_resume(struct device *dev) 716 { 717 struct sdw_slave *slave = dev_to_sdw_dev(dev); 718 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 719 unsigned long time; 720 721 if (!rt1308->hw_init) 722 return 0; 723 724 if (!slave->unattach_request) 725 goto regmap_sync; 726 727 time = wait_for_completion_timeout(&slave->initialization_complete, 728 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 729 if (!time) { 730 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 731 return -ETIMEDOUT; 732 } 733 734 regmap_sync: 735 slave->unattach_request = 0; 736 regcache_cache_only(rt1308->regmap, false); 737 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 738 739 return 0; 740 } 741 742 static const struct dev_pm_ops rt1308_pm = { 743 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 744 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 745 }; 746 747 static struct sdw_driver rt1308_sdw_driver = { 748 .driver = { 749 .name = "rt1308", 750 .owner = THIS_MODULE, 751 .pm = &rt1308_pm, 752 }, 753 .probe = rt1308_sdw_probe, 754 .ops = &rt1308_slave_ops, 755 .id_table = rt1308_id, 756 }; 757 module_sdw_driver(rt1308_sdw_driver); 758 759 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 760 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 761 MODULE_LICENSE("GPL v2"); 762