1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/sdw.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/initval.h> 24 25 #include "rt1308.h" 26 #include "rt1308-sdw.h" 27 28 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 29 { 30 switch (reg) { 31 case 0x00e0: 32 case 0x00f0: 33 case 0x2f01 ... 0x2f07: 34 case 0x3000 ... 0x3001: 35 case 0x3004 ... 0x3005: 36 case 0x3008: 37 case 0x300a: 38 case 0xc000 ... 0xcff3: 39 return true; 40 default: 41 return false; 42 } 43 } 44 45 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 46 { 47 switch (reg) { 48 case 0x2f01 ... 0x2f07: 49 case 0x3000 ... 0x3001: 50 case 0x3004 ... 0x3005: 51 case 0x3008: 52 case 0x300a: 53 case 0xc000: 54 case 0xc710: 55 case 0xcf01: 56 case 0xc860 ... 0xc863: 57 case 0xc870 ... 0xc873: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static const struct regmap_config rt1308_sdw_regmap = { 65 .reg_bits = 32, 66 .val_bits = 8, 67 .readable_reg = rt1308_readable_register, 68 .volatile_reg = rt1308_volatile_register, 69 .max_register = 0xcfff, 70 .reg_defaults = rt1308_reg_defaults, 71 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 72 .cache_type = REGCACHE_MAPLE, 73 .use_single_read = true, 74 .use_single_write = true, 75 }; 76 77 /* Bus clock frequency */ 78 #define RT1308_CLK_FREQ_9600000HZ 9600000 79 #define RT1308_CLK_FREQ_12000000HZ 12000000 80 #define RT1308_CLK_FREQ_6000000HZ 6000000 81 #define RT1308_CLK_FREQ_4800000HZ 4800000 82 #define RT1308_CLK_FREQ_2400000HZ 2400000 83 #define RT1308_CLK_FREQ_12288000HZ 12288000 84 85 static int rt1308_clock_config(struct device *dev) 86 { 87 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 88 unsigned int clk_freq, value; 89 90 clk_freq = (rt1308->params.curr_dr_freq >> 1); 91 92 switch (clk_freq) { 93 case RT1308_CLK_FREQ_12000000HZ: 94 value = 0x0; 95 break; 96 case RT1308_CLK_FREQ_6000000HZ: 97 value = 0x1; 98 break; 99 case RT1308_CLK_FREQ_9600000HZ: 100 value = 0x2; 101 break; 102 case RT1308_CLK_FREQ_4800000HZ: 103 value = 0x3; 104 break; 105 case RT1308_CLK_FREQ_2400000HZ: 106 value = 0x4; 107 break; 108 case RT1308_CLK_FREQ_12288000HZ: 109 value = 0x5; 110 break; 111 default: 112 return -EINVAL; 113 } 114 115 regmap_write(rt1308->regmap, 0xe0, value); 116 regmap_write(rt1308->regmap, 0xf0, value); 117 118 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 119 120 return 0; 121 } 122 123 static int rt1308_read_prop(struct sdw_slave *slave) 124 { 125 struct sdw_slave_prop *prop = &slave->prop; 126 int nval, i; 127 u32 bit; 128 unsigned long addr; 129 struct sdw_dpn_prop *dpn; 130 131 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 132 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 133 134 prop->paging_support = true; 135 136 /* first we need to allocate memory for set bits in port lists */ 137 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 138 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 139 140 /* for sink */ 141 nval = hweight32(prop->sink_ports); 142 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 143 sizeof(*prop->sink_dpn_prop), 144 GFP_KERNEL); 145 if (!prop->sink_dpn_prop) 146 return -ENOMEM; 147 148 i = 0; 149 dpn = prop->sink_dpn_prop; 150 addr = prop->sink_ports; 151 for_each_set_bit(bit, &addr, 32) { 152 dpn[i].num = bit; 153 dpn[i].type = SDW_DPN_FULL; 154 dpn[i].simple_ch_prep_sm = true; 155 dpn[i].ch_prep_timeout = 10; 156 i++; 157 } 158 159 /* set the timeout values */ 160 prop->clk_stop_timeout = 20; 161 162 dev_dbg(&slave->dev, "%s\n", __func__); 163 164 return 0; 165 } 166 167 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308) 168 { 169 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 170 unsigned int efuse_c_btl_l, efuse_c_btl_r; 171 172 /* read efuse to apply calibration parameters */ 173 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 174 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 175 msleep(100); 176 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 177 msleep(20); 178 regmap_write(rt1308->regmap, 0xc240, 0x10); 179 180 regmap_read(rt1308->regmap, 0xc861, &tmp); 181 efuse_m_btl_l = tmp; 182 regmap_read(rt1308->regmap, 0xc860, &tmp); 183 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 184 regmap_read(rt1308->regmap, 0xc863, &tmp); 185 efuse_c_btl_l = tmp; 186 regmap_read(rt1308->regmap, 0xc862, &tmp); 187 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 188 regmap_read(rt1308->regmap, 0xc871, &tmp); 189 efuse_m_btl_r = tmp; 190 regmap_read(rt1308->regmap, 0xc870, &tmp); 191 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 192 regmap_read(rt1308->regmap, 0xc873, &tmp); 193 efuse_c_btl_r = tmp; 194 regmap_read(rt1308->regmap, 0xc872, &tmp); 195 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 196 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 197 efuse_m_btl_l, efuse_m_btl_r); 198 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 199 efuse_c_btl_l, efuse_c_btl_r); 200 } 201 202 static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308) 203 { 204 unsigned int i, reg, data; 205 206 for (i = 0; i < rt1308->bq_params_cnt; i += 3) { 207 reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8); 208 data = rt1308->bq_params[i + 2]; 209 regmap_write(rt1308->regmap, reg, data); 210 } 211 } 212 213 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 214 { 215 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 216 int ret = 0; 217 unsigned int tmp, hibernation_flag; 218 219 if (rt1308->hw_init) 220 return 0; 221 222 if (rt1308->first_hw_init) { 223 regcache_cache_only(rt1308->regmap, false); 224 regcache_cache_bypass(rt1308->regmap, true); 225 } 226 227 /* 228 * PM runtime is only enabled when a Slave reports as Attached 229 */ 230 if (!rt1308->first_hw_init) { 231 /* set autosuspend parameters */ 232 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 233 pm_runtime_use_autosuspend(&slave->dev); 234 235 /* update count of parent 'active' children */ 236 pm_runtime_set_active(&slave->dev); 237 238 /* make sure the device does not suspend immediately */ 239 pm_runtime_mark_last_busy(&slave->dev); 240 241 pm_runtime_enable(&slave->dev); 242 } 243 244 pm_runtime_get_noresume(&slave->dev); 245 246 regmap_read(rt1308->regmap, 0xcf01, &hibernation_flag); 247 if ((hibernation_flag != 0x00) && rt1308->first_hw_init) 248 goto _preset_ready_; 249 250 /* sw reset */ 251 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 252 253 regmap_read(rt1308->regmap, 0xc710, &tmp); 254 rt1308->hw_ver = tmp; 255 dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver); 256 257 /* initial settings */ 258 regmap_write(rt1308->regmap, 0xc103, 0xc0); 259 regmap_write(rt1308->regmap, 0xc030, 0x17); 260 regmap_write(rt1308->regmap, 0xc031, 0x81); 261 regmap_write(rt1308->regmap, 0xc032, 0x26); 262 regmap_write(rt1308->regmap, 0xc040, 0x80); 263 regmap_write(rt1308->regmap, 0xc041, 0x80); 264 regmap_write(rt1308->regmap, 0xc042, 0x06); 265 regmap_write(rt1308->regmap, 0xc052, 0x0a); 266 regmap_write(rt1308->regmap, 0xc080, 0x0a); 267 regmap_write(rt1308->regmap, 0xc060, 0x02); 268 regmap_write(rt1308->regmap, 0xc061, 0x75); 269 regmap_write(rt1308->regmap, 0xc062, 0x05); 270 regmap_write(rt1308->regmap, 0xc171, 0x07); 271 regmap_write(rt1308->regmap, 0xc173, 0x0d); 272 if (rt1308->hw_ver == RT1308_VER_C) { 273 regmap_write(rt1308->regmap, 0xc311, 0x7f); 274 regmap_write(rt1308->regmap, 0xc300, 0x09); 275 } else { 276 regmap_write(rt1308->regmap, 0xc311, 0x4f); 277 regmap_write(rt1308->regmap, 0xc300, 0x0b); 278 } 279 regmap_write(rt1308->regmap, 0xc900, 0x5a); 280 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 281 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 282 regmap_write(rt1308->regmap, 0xc360, 0x78); 283 regmap_write(rt1308->regmap, 0xc361, 0x87); 284 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 285 regmap_write(rt1308->regmap, 0xc210, 0x00); 286 regmap_write(rt1308->regmap, 0xc070, 0x00); 287 regmap_write(rt1308->regmap, 0xc100, 0xd7); 288 regmap_write(rt1308->regmap, 0xc101, 0xd7); 289 290 /* apply BQ params */ 291 rt1308_apply_bq_params(rt1308); 292 293 regmap_write(rt1308->regmap, 0xcf01, 0x01); 294 295 _preset_ready_: 296 if (rt1308->first_hw_init) { 297 regcache_cache_bypass(rt1308->regmap, false); 298 regcache_mark_dirty(rt1308->regmap); 299 } else 300 rt1308->first_hw_init = true; 301 302 /* Mark Slave initialization complete */ 303 rt1308->hw_init = true; 304 305 pm_runtime_mark_last_busy(&slave->dev); 306 pm_runtime_put_autosuspend(&slave->dev); 307 308 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 309 310 return ret; 311 } 312 313 static int rt1308_update_status(struct sdw_slave *slave, 314 enum sdw_slave_status status) 315 { 316 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 317 318 if (status == SDW_SLAVE_UNATTACHED) 319 rt1308->hw_init = false; 320 321 /* 322 * Perform initialization only if slave status is present and 323 * hw_init flag is false 324 */ 325 if (rt1308->hw_init || status != SDW_SLAVE_ATTACHED) 326 return 0; 327 328 /* perform I/O transfers required for Slave initialization */ 329 return rt1308_io_init(&slave->dev, slave); 330 } 331 332 static int rt1308_bus_config(struct sdw_slave *slave, 333 struct sdw_bus_params *params) 334 { 335 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 336 int ret; 337 338 memcpy(&rt1308->params, params, sizeof(*params)); 339 340 ret = rt1308_clock_config(&slave->dev); 341 if (ret < 0) 342 dev_err(&slave->dev, "Invalid clk config"); 343 344 return ret; 345 } 346 347 static int rt1308_interrupt_callback(struct sdw_slave *slave, 348 struct sdw_slave_intr_status *status) 349 { 350 dev_dbg(&slave->dev, 351 "%s control_port_stat=%x", __func__, status->control_port); 352 353 return 0; 354 } 355 356 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 357 struct snd_kcontrol *kcontrol, int event) 358 { 359 struct snd_soc_component *component = 360 snd_soc_dapm_to_component(w->dapm); 361 struct rt1308_sdw_priv *rt1308 = 362 snd_soc_component_get_drvdata(component); 363 364 switch (event) { 365 case SND_SOC_DAPM_POST_PMU: 366 msleep(30); 367 snd_soc_component_update_bits(component, 368 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 369 0x3, 0x3); 370 msleep(40); 371 rt1308_apply_calib_params(rt1308); 372 break; 373 case SND_SOC_DAPM_PRE_PMD: 374 snd_soc_component_update_bits(component, 375 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 376 0x3, 0); 377 usleep_range(150000, 200000); 378 break; 379 380 default: 381 break; 382 } 383 384 return 0; 385 } 386 387 static const char * const rt1308_rx_data_ch_select[] = { 388 "LR", 389 "LL", 390 "RL", 391 "RR", 392 }; 393 394 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 395 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 396 rt1308_rx_data_ch_select); 397 398 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 399 400 /* I2S Data Channel Selection */ 401 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 402 }; 403 404 static const struct snd_kcontrol_new rt1308_sto_dac_l = 405 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 406 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 407 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 408 409 static const struct snd_kcontrol_new rt1308_sto_dac_r = 410 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 411 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 412 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 413 414 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 415 /* Audio Interface */ 416 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 417 418 /* Supply Widgets */ 419 SND_SOC_DAPM_SUPPLY("MBIAS20U", 420 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 421 SND_SOC_DAPM_SUPPLY("ALDO", 422 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 423 SND_SOC_DAPM_SUPPLY("DBG", 424 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 425 SND_SOC_DAPM_SUPPLY("DACL", 426 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 427 SND_SOC_DAPM_SUPPLY("CLK25M", 428 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 429 SND_SOC_DAPM_SUPPLY("ADC_R", 430 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 431 SND_SOC_DAPM_SUPPLY("ADC_L", 432 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 433 SND_SOC_DAPM_SUPPLY("DAC Power", 434 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 435 436 SND_SOC_DAPM_SUPPLY("DLDO", 437 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 438 SND_SOC_DAPM_SUPPLY("VREF", 439 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 440 SND_SOC_DAPM_SUPPLY("MIXER_R", 441 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 442 SND_SOC_DAPM_SUPPLY("MIXER_L", 443 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 444 SND_SOC_DAPM_SUPPLY("MBIAS4U", 445 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 446 447 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 448 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 449 SND_SOC_DAPM_SUPPLY("PLL2B", 450 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 451 SND_SOC_DAPM_SUPPLY("PLL2F", 452 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 453 SND_SOC_DAPM_SUPPLY("PLL2F2", 454 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 455 SND_SOC_DAPM_SUPPLY("PLL2B2", 456 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 457 458 /* Digital Interface */ 459 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 460 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 461 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 462 463 /* Output Lines */ 464 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 465 rt1308_classd_event, 466 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 467 SND_SOC_DAPM_OUTPUT("SPOL"), 468 SND_SOC_DAPM_OUTPUT("SPOR"), 469 }; 470 471 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 472 473 { "DAC", NULL, "AIF1RX" }, 474 475 { "DAC", NULL, "MBIAS20U" }, 476 { "DAC", NULL, "ALDO" }, 477 { "DAC", NULL, "DBG" }, 478 { "DAC", NULL, "DACL" }, 479 { "DAC", NULL, "CLK25M" }, 480 { "DAC", NULL, "ADC_R" }, 481 { "DAC", NULL, "ADC_L" }, 482 { "DAC", NULL, "DLDO" }, 483 { "DAC", NULL, "VREF" }, 484 { "DAC", NULL, "MIXER_R" }, 485 { "DAC", NULL, "MIXER_L" }, 486 { "DAC", NULL, "MBIAS4U" }, 487 { "DAC", NULL, "PLL2_LDO" }, 488 { "DAC", NULL, "PLL2B" }, 489 { "DAC", NULL, "PLL2F" }, 490 { "DAC", NULL, "PLL2F2" }, 491 { "DAC", NULL, "PLL2B2" }, 492 493 { "DAC L", "Switch", "DAC" }, 494 { "DAC R", "Switch", "DAC" }, 495 { "DAC L", NULL, "DAC Power" }, 496 { "DAC R", NULL, "DAC Power" }, 497 498 { "CLASS D", NULL, "DAC L" }, 499 { "CLASS D", NULL, "DAC R" }, 500 { "SPOL", NULL, "CLASS D" }, 501 { "SPOR", NULL, "CLASS D" }, 502 }; 503 504 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 505 int direction) 506 { 507 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 508 509 return 0; 510 } 511 512 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 513 struct snd_soc_dai *dai) 514 { 515 snd_soc_dai_set_dma_data(dai, substream, NULL); 516 } 517 518 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 519 unsigned int tx_mask, 520 unsigned int rx_mask, 521 int slots, int slot_width) 522 { 523 struct snd_soc_component *component = dai->component; 524 struct rt1308_sdw_priv *rt1308 = 525 snd_soc_component_get_drvdata(component); 526 527 if (tx_mask) 528 return -EINVAL; 529 530 if (slots > 2) 531 return -EINVAL; 532 533 rt1308->rx_mask = rx_mask; 534 rt1308->slots = slots; 535 /* slot_width is not used since it's irrelevant for SoundWire */ 536 537 return 0; 538 } 539 540 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 541 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 542 { 543 struct snd_soc_component *component = dai->component; 544 struct rt1308_sdw_priv *rt1308 = 545 snd_soc_component_get_drvdata(component); 546 struct sdw_stream_config stream_config = {0}; 547 struct sdw_port_config port_config = {0}; 548 struct sdw_stream_runtime *sdw_stream; 549 int retval; 550 551 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 552 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 553 554 if (!sdw_stream) 555 return -EINVAL; 556 557 if (!rt1308->sdw_slave) 558 return -EINVAL; 559 560 /* SoundWire specific configuration */ 561 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 562 563 /* port 1 for playback */ 564 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 565 port_config.num = 1; 566 else 567 return -EINVAL; 568 569 if (rt1308->slots) { 570 stream_config.ch_count = rt1308->slots; 571 port_config.ch_mask = rt1308->rx_mask; 572 } 573 574 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 575 &port_config, 1, sdw_stream); 576 if (retval) { 577 dev_err(dai->dev, "Unable to configure port\n"); 578 return retval; 579 } 580 581 return retval; 582 } 583 584 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 585 struct snd_soc_dai *dai) 586 { 587 struct snd_soc_component *component = dai->component; 588 struct rt1308_sdw_priv *rt1308 = 589 snd_soc_component_get_drvdata(component); 590 struct sdw_stream_runtime *sdw_stream = 591 snd_soc_dai_get_dma_data(dai, substream); 592 593 if (!rt1308->sdw_slave) 594 return -EINVAL; 595 596 sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream); 597 return 0; 598 } 599 600 /* 601 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 602 * port_prep are not defined for now 603 */ 604 static const struct sdw_slave_ops rt1308_slave_ops = { 605 .read_prop = rt1308_read_prop, 606 .interrupt_callback = rt1308_interrupt_callback, 607 .update_status = rt1308_update_status, 608 .bus_config = rt1308_bus_config, 609 }; 610 611 static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev) 612 { 613 int ret = 0; 614 615 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt); 616 if (rt1308->bq_params_cnt) { 617 rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL); 618 if (!rt1308->bq_params) { 619 dev_err(dev, "Could not allocate bq_params memory\n"); 620 ret = -ENOMEM; 621 } else { 622 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt); 623 if (ret < 0) 624 dev_err(dev, "Could not read list of realtek,bq-params\n"); 625 } 626 } 627 628 dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt); 629 return ret; 630 } 631 632 static int rt1308_sdw_component_probe(struct snd_soc_component *component) 633 { 634 struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component); 635 int ret; 636 637 rt1308->component = component; 638 rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev); 639 640 ret = pm_runtime_resume(component->dev); 641 if (ret < 0 && ret != -EACCES) 642 return ret; 643 644 /* apply BQ params */ 645 rt1308_apply_bq_params(rt1308); 646 647 return 0; 648 } 649 650 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 651 .probe = rt1308_sdw_component_probe, 652 .controls = rt1308_snd_controls, 653 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 654 .dapm_widgets = rt1308_dapm_widgets, 655 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 656 .dapm_routes = rt1308_dapm_routes, 657 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 658 .endianness = 1, 659 }; 660 661 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 662 .hw_params = rt1308_sdw_hw_params, 663 .hw_free = rt1308_sdw_pcm_hw_free, 664 .set_stream = rt1308_set_sdw_stream, 665 .shutdown = rt1308_sdw_shutdown, 666 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 667 }; 668 669 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 670 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 671 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 672 SNDRV_PCM_FMTBIT_S24_LE) 673 674 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 675 { 676 .name = "rt1308-aif", 677 .playback = { 678 .stream_name = "DP1 Playback", 679 .channels_min = 1, 680 .channels_max = 2, 681 .rates = RT1308_STEREO_RATES, 682 .formats = RT1308_FORMATS, 683 }, 684 .ops = &rt1308_aif_dai_ops, 685 }, 686 }; 687 688 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 689 struct sdw_slave *slave) 690 { 691 struct rt1308_sdw_priv *rt1308; 692 int ret; 693 694 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 695 if (!rt1308) 696 return -ENOMEM; 697 698 dev_set_drvdata(dev, rt1308); 699 rt1308->sdw_slave = slave; 700 rt1308->regmap = regmap; 701 702 /* 703 * Mark hw_init to false 704 * HW init will be performed when device reports present 705 */ 706 rt1308->hw_init = false; 707 rt1308->first_hw_init = false; 708 709 ret = devm_snd_soc_register_component(dev, 710 &soc_component_sdw_rt1308, 711 rt1308_sdw_dai, 712 ARRAY_SIZE(rt1308_sdw_dai)); 713 714 dev_dbg(&slave->dev, "%s\n", __func__); 715 716 return ret; 717 } 718 719 static int rt1308_sdw_probe(struct sdw_slave *slave, 720 const struct sdw_device_id *id) 721 { 722 struct regmap *regmap; 723 724 /* Regmap Initialization */ 725 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 726 if (IS_ERR(regmap)) 727 return PTR_ERR(regmap); 728 729 rt1308_sdw_init(&slave->dev, regmap, slave); 730 731 return 0; 732 } 733 734 static int rt1308_sdw_remove(struct sdw_slave *slave) 735 { 736 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 737 738 if (rt1308->first_hw_init) 739 pm_runtime_disable(&slave->dev); 740 741 return 0; 742 } 743 744 static const struct sdw_device_id rt1308_id[] = { 745 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0), 746 {}, 747 }; 748 MODULE_DEVICE_TABLE(sdw, rt1308_id); 749 750 static int __maybe_unused rt1308_dev_suspend(struct device *dev) 751 { 752 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 753 754 if (!rt1308->hw_init) 755 return 0; 756 757 regcache_cache_only(rt1308->regmap, true); 758 759 return 0; 760 } 761 762 #define RT1308_PROBE_TIMEOUT 5000 763 764 static int __maybe_unused rt1308_dev_resume(struct device *dev) 765 { 766 struct sdw_slave *slave = dev_to_sdw_dev(dev); 767 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 768 unsigned long time; 769 770 if (!rt1308->first_hw_init) 771 return 0; 772 773 if (!slave->unattach_request) 774 goto regmap_sync; 775 776 time = wait_for_completion_timeout(&slave->initialization_complete, 777 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 778 if (!time) { 779 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 780 sdw_show_ping_status(slave->bus, true); 781 782 return -ETIMEDOUT; 783 } 784 785 regmap_sync: 786 slave->unattach_request = 0; 787 regcache_cache_only(rt1308->regmap, false); 788 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 789 790 return 0; 791 } 792 793 static const struct dev_pm_ops rt1308_pm = { 794 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 795 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 796 }; 797 798 static struct sdw_driver rt1308_sdw_driver = { 799 .driver = { 800 .name = "rt1308", 801 .owner = THIS_MODULE, 802 .pm = &rt1308_pm, 803 }, 804 .probe = rt1308_sdw_probe, 805 .remove = rt1308_sdw_remove, 806 .ops = &rt1308_slave_ops, 807 .id_table = rt1308_id, 808 }; 809 module_sdw_driver(rt1308_sdw_driver); 810 811 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 812 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 813 MODULE_LICENSE("GPL v2"); 814