1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/sdw.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/initval.h> 24 25 #include "rt1308.h" 26 #include "rt1308-sdw.h" 27 28 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 29 { 30 switch (reg) { 31 case 0x00e0: 32 case 0x00f0: 33 case 0x2f01 ... 0x2f07: 34 case 0x3000 ... 0x3001: 35 case 0x3004 ... 0x3005: 36 case 0x3008: 37 case 0x300a: 38 case 0xc000 ... 0xcff3: 39 return true; 40 default: 41 return false; 42 } 43 } 44 45 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 46 { 47 switch (reg) { 48 case 0x2f01 ... 0x2f07: 49 case 0x3000 ... 0x3001: 50 case 0x3004 ... 0x3005: 51 case 0x3008: 52 case 0x300a: 53 case 0xc000: 54 case 0xc710: 55 case 0xc860 ... 0xc863: 56 case 0xc870 ... 0xc873: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static const struct regmap_config rt1308_sdw_regmap = { 64 .reg_bits = 32, 65 .val_bits = 8, 66 .readable_reg = rt1308_readable_register, 67 .volatile_reg = rt1308_volatile_register, 68 .max_register = 0xcfff, 69 .reg_defaults = rt1308_reg_defaults, 70 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 71 .cache_type = REGCACHE_RBTREE, 72 .use_single_read = true, 73 .use_single_write = true, 74 }; 75 76 /* Bus clock frequency */ 77 #define RT1308_CLK_FREQ_9600000HZ 9600000 78 #define RT1308_CLK_FREQ_12000000HZ 12000000 79 #define RT1308_CLK_FREQ_6000000HZ 6000000 80 #define RT1308_CLK_FREQ_4800000HZ 4800000 81 #define RT1308_CLK_FREQ_2400000HZ 2400000 82 #define RT1308_CLK_FREQ_12288000HZ 12288000 83 84 static int rt1308_clock_config(struct device *dev) 85 { 86 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 87 unsigned int clk_freq, value; 88 89 clk_freq = (rt1308->params.curr_dr_freq >> 1); 90 91 switch (clk_freq) { 92 case RT1308_CLK_FREQ_12000000HZ: 93 value = 0x0; 94 break; 95 case RT1308_CLK_FREQ_6000000HZ: 96 value = 0x1; 97 break; 98 case RT1308_CLK_FREQ_9600000HZ: 99 value = 0x2; 100 break; 101 case RT1308_CLK_FREQ_4800000HZ: 102 value = 0x3; 103 break; 104 case RT1308_CLK_FREQ_2400000HZ: 105 value = 0x4; 106 break; 107 case RT1308_CLK_FREQ_12288000HZ: 108 value = 0x5; 109 break; 110 default: 111 return -EINVAL; 112 } 113 114 regmap_write(rt1308->regmap, 0xe0, value); 115 regmap_write(rt1308->regmap, 0xf0, value); 116 117 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 118 119 return 0; 120 } 121 122 static int rt1308_read_prop(struct sdw_slave *slave) 123 { 124 struct sdw_slave_prop *prop = &slave->prop; 125 int nval, i; 126 u32 bit; 127 unsigned long addr; 128 struct sdw_dpn_prop *dpn; 129 130 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 131 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 132 133 prop->paging_support = true; 134 135 /* first we need to allocate memory for set bits in port lists */ 136 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 137 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 138 139 /* for sink */ 140 nval = hweight32(prop->sink_ports); 141 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 142 sizeof(*prop->sink_dpn_prop), 143 GFP_KERNEL); 144 if (!prop->sink_dpn_prop) 145 return -ENOMEM; 146 147 i = 0; 148 dpn = prop->sink_dpn_prop; 149 addr = prop->sink_ports; 150 for_each_set_bit(bit, &addr, 32) { 151 dpn[i].num = bit; 152 dpn[i].type = SDW_DPN_FULL; 153 dpn[i].simple_ch_prep_sm = true; 154 dpn[i].ch_prep_timeout = 10; 155 i++; 156 } 157 158 /* set the timeout values */ 159 prop->clk_stop_timeout = 20; 160 161 dev_dbg(&slave->dev, "%s\n", __func__); 162 163 return 0; 164 } 165 166 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308) 167 { 168 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 169 unsigned int efuse_c_btl_l, efuse_c_btl_r; 170 171 /* read efuse to apply calibration parameters */ 172 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 173 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 174 msleep(100); 175 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 176 msleep(20); 177 regmap_write(rt1308->regmap, 0xc240, 0x10); 178 179 regmap_read(rt1308->regmap, 0xc861, &tmp); 180 efuse_m_btl_l = tmp; 181 regmap_read(rt1308->regmap, 0xc860, &tmp); 182 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 183 regmap_read(rt1308->regmap, 0xc863, &tmp); 184 efuse_c_btl_l = tmp; 185 regmap_read(rt1308->regmap, 0xc862, &tmp); 186 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 187 regmap_read(rt1308->regmap, 0xc871, &tmp); 188 efuse_m_btl_r = tmp; 189 regmap_read(rt1308->regmap, 0xc870, &tmp); 190 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 191 regmap_read(rt1308->regmap, 0xc873, &tmp); 192 efuse_c_btl_r = tmp; 193 regmap_read(rt1308->regmap, 0xc872, &tmp); 194 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 195 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 196 efuse_m_btl_l, efuse_m_btl_r); 197 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 198 efuse_c_btl_l, efuse_c_btl_r); 199 } 200 201 static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308) 202 { 203 unsigned int i, reg, data; 204 205 for (i = 0; i < rt1308->bq_params_cnt; i += 3) { 206 reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8); 207 data = rt1308->bq_params[i + 2]; 208 regmap_write(rt1308->regmap, reg, data); 209 } 210 } 211 212 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 213 { 214 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 215 int ret = 0; 216 unsigned int tmp; 217 218 if (rt1308->hw_init) 219 return 0; 220 221 if (rt1308->first_hw_init) { 222 regcache_cache_only(rt1308->regmap, false); 223 regcache_cache_bypass(rt1308->regmap, true); 224 } 225 226 /* 227 * PM runtime is only enabled when a Slave reports as Attached 228 */ 229 if (!rt1308->first_hw_init) { 230 /* set autosuspend parameters */ 231 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 232 pm_runtime_use_autosuspend(&slave->dev); 233 234 /* update count of parent 'active' children */ 235 pm_runtime_set_active(&slave->dev); 236 237 /* make sure the device does not suspend immediately */ 238 pm_runtime_mark_last_busy(&slave->dev); 239 240 pm_runtime_enable(&slave->dev); 241 } 242 243 pm_runtime_get_noresume(&slave->dev); 244 245 /* sw reset */ 246 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 247 248 regmap_read(rt1308->regmap, 0xc710, &tmp); 249 rt1308->hw_ver = tmp; 250 dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver); 251 252 /* initial settings */ 253 regmap_write(rt1308->regmap, 0xc103, 0xc0); 254 regmap_write(rt1308->regmap, 0xc030, 0x17); 255 regmap_write(rt1308->regmap, 0xc031, 0x81); 256 regmap_write(rt1308->regmap, 0xc032, 0x26); 257 regmap_write(rt1308->regmap, 0xc040, 0x80); 258 regmap_write(rt1308->regmap, 0xc041, 0x80); 259 regmap_write(rt1308->regmap, 0xc042, 0x06); 260 regmap_write(rt1308->regmap, 0xc052, 0x0a); 261 regmap_write(rt1308->regmap, 0xc080, 0x0a); 262 regmap_write(rt1308->regmap, 0xc060, 0x02); 263 regmap_write(rt1308->regmap, 0xc061, 0x75); 264 regmap_write(rt1308->regmap, 0xc062, 0x05); 265 regmap_write(rt1308->regmap, 0xc171, 0x07); 266 regmap_write(rt1308->regmap, 0xc173, 0x0d); 267 if (rt1308->hw_ver == RT1308_VER_C) { 268 regmap_write(rt1308->regmap, 0xc311, 0x7f); 269 regmap_write(rt1308->regmap, 0xc300, 0x09); 270 } else { 271 regmap_write(rt1308->regmap, 0xc311, 0x4f); 272 regmap_write(rt1308->regmap, 0xc300, 0x0b); 273 } 274 regmap_write(rt1308->regmap, 0xc900, 0x5a); 275 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 276 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 277 regmap_write(rt1308->regmap, 0xc360, 0x78); 278 regmap_write(rt1308->regmap, 0xc361, 0x87); 279 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 280 regmap_write(rt1308->regmap, 0xc210, 0x00); 281 regmap_write(rt1308->regmap, 0xc070, 0x00); 282 regmap_write(rt1308->regmap, 0xc100, 0xd7); 283 regmap_write(rt1308->regmap, 0xc101, 0xd7); 284 285 if (rt1308->first_hw_init) { 286 regcache_cache_bypass(rt1308->regmap, false); 287 regcache_mark_dirty(rt1308->regmap); 288 } else 289 rt1308->first_hw_init = true; 290 291 /* Mark Slave initialization complete */ 292 rt1308->hw_init = true; 293 294 pm_runtime_mark_last_busy(&slave->dev); 295 pm_runtime_put_autosuspend(&slave->dev); 296 297 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 298 299 return ret; 300 } 301 302 static int rt1308_update_status(struct sdw_slave *slave, 303 enum sdw_slave_status status) 304 { 305 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 306 307 /* Update the status */ 308 rt1308->status = status; 309 310 if (status == SDW_SLAVE_UNATTACHED) 311 rt1308->hw_init = false; 312 313 /* 314 * Perform initialization only if slave status is present and 315 * hw_init flag is false 316 */ 317 if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED) 318 return 0; 319 320 /* perform I/O transfers required for Slave initialization */ 321 return rt1308_io_init(&slave->dev, slave); 322 } 323 324 static int rt1308_bus_config(struct sdw_slave *slave, 325 struct sdw_bus_params *params) 326 { 327 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 328 int ret; 329 330 memcpy(&rt1308->params, params, sizeof(*params)); 331 332 ret = rt1308_clock_config(&slave->dev); 333 if (ret < 0) 334 dev_err(&slave->dev, "Invalid clk config"); 335 336 return ret; 337 } 338 339 static int rt1308_interrupt_callback(struct sdw_slave *slave, 340 struct sdw_slave_intr_status *status) 341 { 342 dev_dbg(&slave->dev, 343 "%s control_port_stat=%x", __func__, status->control_port); 344 345 return 0; 346 } 347 348 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 349 struct snd_kcontrol *kcontrol, int event) 350 { 351 struct snd_soc_component *component = 352 snd_soc_dapm_to_component(w->dapm); 353 struct rt1308_sdw_priv *rt1308 = 354 snd_soc_component_get_drvdata(component); 355 356 switch (event) { 357 case SND_SOC_DAPM_POST_PMU: 358 msleep(30); 359 snd_soc_component_update_bits(component, 360 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 361 0x3, 0x3); 362 msleep(40); 363 rt1308_apply_calib_params(rt1308); 364 break; 365 case SND_SOC_DAPM_PRE_PMD: 366 snd_soc_component_update_bits(component, 367 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 368 0x3, 0); 369 usleep_range(150000, 200000); 370 break; 371 372 default: 373 break; 374 } 375 376 return 0; 377 } 378 379 static const char * const rt1308_rx_data_ch_select[] = { 380 "LR", 381 "LL", 382 "RL", 383 "RR", 384 }; 385 386 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 387 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 388 rt1308_rx_data_ch_select); 389 390 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 391 392 /* I2S Data Channel Selection */ 393 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 394 }; 395 396 static const struct snd_kcontrol_new rt1308_sto_dac_l = 397 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 398 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 399 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 400 401 static const struct snd_kcontrol_new rt1308_sto_dac_r = 402 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 403 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 404 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 405 406 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 407 /* Audio Interface */ 408 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 409 410 /* Supply Widgets */ 411 SND_SOC_DAPM_SUPPLY("MBIAS20U", 412 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 413 SND_SOC_DAPM_SUPPLY("ALDO", 414 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 415 SND_SOC_DAPM_SUPPLY("DBG", 416 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 417 SND_SOC_DAPM_SUPPLY("DACL", 418 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 419 SND_SOC_DAPM_SUPPLY("CLK25M", 420 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 421 SND_SOC_DAPM_SUPPLY("ADC_R", 422 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 423 SND_SOC_DAPM_SUPPLY("ADC_L", 424 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 425 SND_SOC_DAPM_SUPPLY("DAC Power", 426 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 427 428 SND_SOC_DAPM_SUPPLY("DLDO", 429 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 430 SND_SOC_DAPM_SUPPLY("VREF", 431 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 432 SND_SOC_DAPM_SUPPLY("MIXER_R", 433 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 434 SND_SOC_DAPM_SUPPLY("MIXER_L", 435 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 436 SND_SOC_DAPM_SUPPLY("MBIAS4U", 437 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 438 439 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 440 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 441 SND_SOC_DAPM_SUPPLY("PLL2B", 442 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 443 SND_SOC_DAPM_SUPPLY("PLL2F", 444 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 445 SND_SOC_DAPM_SUPPLY("PLL2F2", 446 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 447 SND_SOC_DAPM_SUPPLY("PLL2B2", 448 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 449 450 /* Digital Interface */ 451 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 452 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 453 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 454 455 /* Output Lines */ 456 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 457 rt1308_classd_event, 458 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 459 SND_SOC_DAPM_OUTPUT("SPOL"), 460 SND_SOC_DAPM_OUTPUT("SPOR"), 461 }; 462 463 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 464 465 { "DAC", NULL, "AIF1RX" }, 466 467 { "DAC", NULL, "MBIAS20U" }, 468 { "DAC", NULL, "ALDO" }, 469 { "DAC", NULL, "DBG" }, 470 { "DAC", NULL, "DACL" }, 471 { "DAC", NULL, "CLK25M" }, 472 { "DAC", NULL, "ADC_R" }, 473 { "DAC", NULL, "ADC_L" }, 474 { "DAC", NULL, "DLDO" }, 475 { "DAC", NULL, "VREF" }, 476 { "DAC", NULL, "MIXER_R" }, 477 { "DAC", NULL, "MIXER_L" }, 478 { "DAC", NULL, "MBIAS4U" }, 479 { "DAC", NULL, "PLL2_LDO" }, 480 { "DAC", NULL, "PLL2B" }, 481 { "DAC", NULL, "PLL2F" }, 482 { "DAC", NULL, "PLL2F2" }, 483 { "DAC", NULL, "PLL2B2" }, 484 485 { "DAC L", "Switch", "DAC" }, 486 { "DAC R", "Switch", "DAC" }, 487 { "DAC L", NULL, "DAC Power" }, 488 { "DAC R", NULL, "DAC Power" }, 489 490 { "CLASS D", NULL, "DAC L" }, 491 { "CLASS D", NULL, "DAC R" }, 492 { "SPOL", NULL, "CLASS D" }, 493 { "SPOR", NULL, "CLASS D" }, 494 }; 495 496 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 497 int direction) 498 { 499 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 500 501 return 0; 502 } 503 504 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 505 struct snd_soc_dai *dai) 506 { 507 snd_soc_dai_set_dma_data(dai, substream, NULL); 508 } 509 510 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 511 unsigned int tx_mask, 512 unsigned int rx_mask, 513 int slots, int slot_width) 514 { 515 struct snd_soc_component *component = dai->component; 516 struct rt1308_sdw_priv *rt1308 = 517 snd_soc_component_get_drvdata(component); 518 519 if (tx_mask) 520 return -EINVAL; 521 522 if (slots > 2) 523 return -EINVAL; 524 525 rt1308->rx_mask = rx_mask; 526 rt1308->slots = slots; 527 /* slot_width is not used since it's irrelevant for SoundWire */ 528 529 return 0; 530 } 531 532 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 533 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 534 { 535 struct snd_soc_component *component = dai->component; 536 struct rt1308_sdw_priv *rt1308 = 537 snd_soc_component_get_drvdata(component); 538 struct sdw_stream_config stream_config = {0}; 539 struct sdw_port_config port_config = {0}; 540 struct sdw_stream_runtime *sdw_stream; 541 int retval; 542 543 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 544 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 545 546 if (!sdw_stream) 547 return -EINVAL; 548 549 if (!rt1308->sdw_slave) 550 return -EINVAL; 551 552 /* SoundWire specific configuration */ 553 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 554 555 /* port 1 for playback */ 556 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 557 port_config.num = 1; 558 else 559 return -EINVAL; 560 561 if (rt1308->slots) { 562 stream_config.ch_count = rt1308->slots; 563 port_config.ch_mask = rt1308->rx_mask; 564 } 565 566 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 567 &port_config, 1, sdw_stream); 568 if (retval) { 569 dev_err(dai->dev, "Unable to configure port\n"); 570 return retval; 571 } 572 573 return retval; 574 } 575 576 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 577 struct snd_soc_dai *dai) 578 { 579 struct snd_soc_component *component = dai->component; 580 struct rt1308_sdw_priv *rt1308 = 581 snd_soc_component_get_drvdata(component); 582 struct sdw_stream_runtime *sdw_stream = 583 snd_soc_dai_get_dma_data(dai, substream); 584 585 if (!rt1308->sdw_slave) 586 return -EINVAL; 587 588 sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream); 589 return 0; 590 } 591 592 /* 593 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 594 * port_prep are not defined for now 595 */ 596 static const struct sdw_slave_ops rt1308_slave_ops = { 597 .read_prop = rt1308_read_prop, 598 .interrupt_callback = rt1308_interrupt_callback, 599 .update_status = rt1308_update_status, 600 .bus_config = rt1308_bus_config, 601 }; 602 603 static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev) 604 { 605 int ret = 0; 606 607 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt); 608 if (rt1308->bq_params_cnt) { 609 rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL); 610 if (!rt1308->bq_params) { 611 dev_err(dev, "Could not allocate bq_params memory\n"); 612 ret = -ENOMEM; 613 } else { 614 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt); 615 if (ret < 0) 616 dev_err(dev, "Could not read list of realtek,bq-params\n"); 617 } 618 } 619 620 dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt); 621 return ret; 622 } 623 624 static int rt1308_sdw_component_probe(struct snd_soc_component *component) 625 { 626 struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component); 627 int ret; 628 629 rt1308->component = component; 630 rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev); 631 632 ret = pm_runtime_resume(component->dev); 633 if (ret < 0 && ret != -EACCES) 634 return ret; 635 636 /* apply BQ params */ 637 rt1308_apply_bq_params(rt1308); 638 639 return 0; 640 } 641 642 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 643 .probe = rt1308_sdw_component_probe, 644 .controls = rt1308_snd_controls, 645 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 646 .dapm_widgets = rt1308_dapm_widgets, 647 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 648 .dapm_routes = rt1308_dapm_routes, 649 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 650 .endianness = 1, 651 }; 652 653 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 654 .hw_params = rt1308_sdw_hw_params, 655 .hw_free = rt1308_sdw_pcm_hw_free, 656 .set_stream = rt1308_set_sdw_stream, 657 .shutdown = rt1308_sdw_shutdown, 658 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 659 }; 660 661 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 662 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 663 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 664 SNDRV_PCM_FMTBIT_S24_LE) 665 666 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 667 { 668 .name = "rt1308-aif", 669 .playback = { 670 .stream_name = "DP1 Playback", 671 .channels_min = 1, 672 .channels_max = 2, 673 .rates = RT1308_STEREO_RATES, 674 .formats = RT1308_FORMATS, 675 }, 676 .ops = &rt1308_aif_dai_ops, 677 }, 678 }; 679 680 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 681 struct sdw_slave *slave) 682 { 683 struct rt1308_sdw_priv *rt1308; 684 int ret; 685 686 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 687 if (!rt1308) 688 return -ENOMEM; 689 690 dev_set_drvdata(dev, rt1308); 691 rt1308->sdw_slave = slave; 692 rt1308->regmap = regmap; 693 694 /* 695 * Mark hw_init to false 696 * HW init will be performed when device reports present 697 */ 698 rt1308->hw_init = false; 699 rt1308->first_hw_init = false; 700 701 ret = devm_snd_soc_register_component(dev, 702 &soc_component_sdw_rt1308, 703 rt1308_sdw_dai, 704 ARRAY_SIZE(rt1308_sdw_dai)); 705 706 dev_dbg(&slave->dev, "%s\n", __func__); 707 708 return ret; 709 } 710 711 static int rt1308_sdw_probe(struct sdw_slave *slave, 712 const struct sdw_device_id *id) 713 { 714 struct regmap *regmap; 715 716 /* Regmap Initialization */ 717 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 718 if (IS_ERR(regmap)) 719 return PTR_ERR(regmap); 720 721 rt1308_sdw_init(&slave->dev, regmap, slave); 722 723 return 0; 724 } 725 726 static int rt1308_sdw_remove(struct sdw_slave *slave) 727 { 728 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 729 730 if (rt1308->first_hw_init) 731 pm_runtime_disable(&slave->dev); 732 733 return 0; 734 } 735 736 static const struct sdw_device_id rt1308_id[] = { 737 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0), 738 {}, 739 }; 740 MODULE_DEVICE_TABLE(sdw, rt1308_id); 741 742 static int __maybe_unused rt1308_dev_suspend(struct device *dev) 743 { 744 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 745 746 if (!rt1308->hw_init) 747 return 0; 748 749 regcache_cache_only(rt1308->regmap, true); 750 751 return 0; 752 } 753 754 #define RT1308_PROBE_TIMEOUT 5000 755 756 static int __maybe_unused rt1308_dev_resume(struct device *dev) 757 { 758 struct sdw_slave *slave = dev_to_sdw_dev(dev); 759 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 760 unsigned long time; 761 762 if (!rt1308->first_hw_init) 763 return 0; 764 765 if (!slave->unattach_request) 766 goto regmap_sync; 767 768 time = wait_for_completion_timeout(&slave->initialization_complete, 769 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 770 if (!time) { 771 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 772 sdw_show_ping_status(slave->bus, true); 773 774 return -ETIMEDOUT; 775 } 776 777 regmap_sync: 778 slave->unattach_request = 0; 779 regcache_cache_only(rt1308->regmap, false); 780 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 781 782 return 0; 783 } 784 785 static const struct dev_pm_ops rt1308_pm = { 786 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 787 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 788 }; 789 790 static struct sdw_driver rt1308_sdw_driver = { 791 .driver = { 792 .name = "rt1308", 793 .owner = THIS_MODULE, 794 .pm = &rt1308_pm, 795 }, 796 .probe = rt1308_sdw_probe, 797 .remove = rt1308_sdw_remove, 798 .ops = &rt1308_slave_ops, 799 .id_table = rt1308_id, 800 }; 801 module_sdw_driver(rt1308_sdw_driver); 802 803 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 804 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 805 MODULE_LICENSE("GPL v2"); 806