1 /* 2 * RT1305.h -- RT1305 ALSA SoC amplifier component driver 3 * 4 * Copyright 2018 Realtek Semiconductor Corp. 5 * Author: Shuming Fan <shumingf@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _RT1305_H_ 13 #define _RT1305_H_ 14 15 #define RT1305_DEVICE_ID_NUM 0x6251 16 17 #define RT1305_RESET 0x00 18 #define RT1305_CLK_1 0x04 19 #define RT1305_CLK_2 0x05 20 #define RT1305_CLK_3 0x06 21 #define RT1305_DFLL_REG 0x07 22 #define RT1305_CAL_EFUSE_CLOCK 0x08 23 #define RT1305_PLL0_1 0x0a 24 #define RT1305_PLL0_2 0x0b 25 #define RT1305_PLL1_1 0x0c 26 #define RT1305_PLL1_2 0x0d 27 #define RT1305_MIXER_CTRL_1 0x10 28 #define RT1305_MIXER_CTRL_2 0x11 29 #define RT1305_DAC_SET_1 0x12 30 #define RT1305_DAC_SET_2 0x14 31 #define RT1305_ADC_SET_1 0x16 32 #define RT1305_ADC_SET_2 0x17 33 #define RT1305_ADC_SET_3 0x18 34 #define RT1305_PATH_SET 0x20 35 #define RT1305_SPDIF_IN_SET_1 0x22 36 #define RT1305_SPDIF_IN_SET_2 0x24 37 #define RT1305_SPDIF_IN_SET_3 0x26 38 #define RT1305_SPDIF_OUT_SET_1 0x28 39 #define RT1305_SPDIF_OUT_SET_2 0x2a 40 #define RT1305_SPDIF_OUT_SET_3 0x2b 41 #define RT1305_I2S_SET_1 0x2d 42 #define RT1305_I2S_SET_2 0x2e 43 #define RT1305_PBTL_MONO_MODE_SRC 0x2f 44 #define RT1305_MANUALLY_I2C_DEVICE 0x32 45 #define RT1305_POWER_STATUS 0x39 46 #define RT1305_POWER_CTRL_1 0x3a 47 #define RT1305_POWER_CTRL_2 0x3b 48 #define RT1305_POWER_CTRL_3 0x3c 49 #define RT1305_POWER_CTRL_4 0x3d 50 #define RT1305_POWER_CTRL_5 0x3e 51 #define RT1305_CLOCK_DETECT 0x3f 52 #define RT1305_BIQUAD_SET_1 0x40 53 #define RT1305_BIQUAD_SET_2 0x42 54 #define RT1305_ADJUSTED_HPF_1 0x46 55 #define RT1305_ADJUSTED_HPF_2 0x47 56 #define RT1305_EQ_SET_1 0x4b 57 #define RT1305_EQ_SET_2 0x4c 58 #define RT1305_SPK_TEMP_PROTECTION_0 0x4f 59 #define RT1305_SPK_TEMP_PROTECTION_1 0x50 60 #define RT1305_SPK_TEMP_PROTECTION_2 0x51 61 #define RT1305_SPK_TEMP_PROTECTION_3 0x52 62 #define RT1305_SPK_DC_DETECT_1 0x53 63 #define RT1305_SPK_DC_DETECT_2 0x54 64 #define RT1305_LOUDNESS 0x58 65 #define RT1305_THERMAL_FOLD_BACK_1 0x5e 66 #define RT1305_THERMAL_FOLD_BACK_2 0x5f 67 #define RT1305_SILENCE_DETECT 0x60 68 #define RT1305_ALC_DRC_1 0x62 69 #define RT1305_ALC_DRC_2 0x63 70 #define RT1305_ALC_DRC_3 0x64 71 #define RT1305_ALC_DRC_4 0x65 72 #define RT1305_PRIV_INDEX 0x6a 73 #define RT1305_PRIV_DATA 0x6c 74 #define RT1305_SPK_EXCURSION_LIMITER_7 0x76 75 #define RT1305_VERSION_ID 0x7a 76 #define RT1305_VENDOR_ID 0x7c 77 #define RT1305_DEVICE_ID 0x7e 78 #define RT1305_EFUSE_1 0x80 79 #define RT1305_EFUSE_2 0x81 80 #define RT1305_EFUSE_3 0x82 81 #define RT1305_DC_CALIB_1 0x90 82 #define RT1305_DC_CALIB_2 0x91 83 #define RT1305_DC_CALIB_3 0x92 84 #define RT1305_DAC_OFFSET_1 0x93 85 #define RT1305_DAC_OFFSET_2 0x94 86 #define RT1305_DAC_OFFSET_3 0x95 87 #define RT1305_DAC_OFFSET_4 0x96 88 #define RT1305_DAC_OFFSET_5 0x97 89 #define RT1305_DAC_OFFSET_6 0x98 90 #define RT1305_DAC_OFFSET_7 0x99 91 #define RT1305_DAC_OFFSET_8 0x9a 92 #define RT1305_DAC_OFFSET_9 0x9b 93 #define RT1305_DAC_OFFSET_10 0x9c 94 #define RT1305_DAC_OFFSET_11 0x9d 95 #define RT1305_DAC_OFFSET_12 0x9e 96 #define RT1305_DAC_OFFSET_13 0x9f 97 #define RT1305_DAC_OFFSET_14 0xa0 98 #define RT1305_TRIM_1 0xb0 99 #define RT1305_TRIM_2 0xb1 100 #define RT1305_TUNE_INTERNAL_OSC 0xb2 101 #define RT1305_BIQUAD1_H0_L_28_16 0xc0 102 #define RT1305_BIQUAD3_A2_R_15_0 0xfb 103 #define RT1305_MAX_REG 0xff 104 105 /* CLOCK-1 (0x04) */ 106 #define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15) 107 #define RT1305_SEL_PLL_SRC_2_SFT 15 108 #define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15) 109 #define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15) 110 #define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13) 111 #define RT1305_DIV_PLL_SRC_2_SFT 13 112 #define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10) 113 #define RT1305_SEL_PLL_SRC_1_SFT 10 114 #define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10) 115 #define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10) 116 #define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10) 117 #define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8) 118 #define RT1305_SEL_FS_SYS_PRE_SFT 8 119 #define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8) 120 #define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8) 121 #define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8) 122 #define RT1305_DIV_FS_SYS_MASK (0x7 << 4) 123 #define RT1305_DIV_FS_SYS_SFT 4 124 125 /* PLL1M/N/K Code-1 (0x0c) */ 126 #define RT1305_PLL_1_M_SFT 12 127 #define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11) 128 #define RT1305_PLL_1_M_BYPASS_SFT 11 129 #define RT1305_PLL_1_M_BYPASS (0x1 << 11) 130 #define RT1305_PLL_1_N_MASK (0x1ff << 0) 131 132 /* DAC Setting (0x14) */ 133 #define RT1305_DVOL_MUTE_L_EN_SFT 15 134 #define RT1305_DVOL_MUTE_R_EN_SFT 14 135 136 /* I2S Setting-1 (0x2d) */ 137 #define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15) 138 #define RT1305_SEL_I2S_OUT_MODE_SFT 15 139 #define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15) 140 #define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15) 141 142 /* I2S Setting-2 (0x2e) */ 143 #define RT1305_I2S_DF_SEL_MASK (0x3 << 12) 144 #define RT1305_I2S_DF_SEL_SFT 12 145 #define RT1305_I2S_DF_SEL_I2S (0x0 << 12) 146 #define RT1305_I2S_DF_SEL_LEFT (0x1 << 12) 147 #define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12) 148 #define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12) 149 #define RT1305_I2S_DL_SEL_MASK (0x3 << 10) 150 #define RT1305_I2S_DL_SEL_SFT 10 151 #define RT1305_I2S_DL_SEL_16B (0x0 << 10) 152 #define RT1305_I2S_DL_SEL_20B (0x1 << 10) 153 #define RT1305_I2S_DL_SEL_24B (0x2 << 10) 154 #define RT1305_I2S_DL_SEL_8B (0x3 << 10) 155 #define RT1305_I2S_BCLK_MASK (0x1 << 9) 156 #define RT1305_I2S_BCLK_SFT 9 157 #define RT1305_I2S_BCLK_NORMAL (0x0 << 9) 158 #define RT1305_I2S_BCLK_INV (0x1 << 9) 159 160 /* Power Control-1 (0x3a) */ 161 #define RT1305_POW_PDB_JD_MASK (0x1 << 12) 162 #define RT1305_POW_PDB_JD (0x1 << 12) 163 #define RT1305_POW_PDB_JD_BIT 12 164 #define RT1305_POW_PLL0_EN (0x1 << 11) 165 #define RT1305_POW_PLL0_EN_BIT 11 166 #define RT1305_POW_PLL1_EN (0x1 << 10) 167 #define RT1305_POW_PLL1_EN_BIT 10 168 #define RT1305_POW_PDB_JD_POLARITY (0x1 << 9) 169 #define RT1305_POW_PDB_JD_POLARITY_BIT 9 170 #define RT1305_POW_MBIAS_LV (0x1 << 8) 171 #define RT1305_POW_MBIAS_LV_BIT 8 172 #define RT1305_POW_BG_MBIAS_LV (0x1 << 7) 173 #define RT1305_POW_BG_MBIAS_LV_BIT 7 174 #define RT1305_POW_LDO2 (0x1 << 6) 175 #define RT1305_POW_LDO2_BIT 6 176 #define RT1305_POW_BG2 (0x1 << 5) 177 #define RT1305_POW_BG2_BIT 5 178 #define RT1305_POW_LDO2_IB2 (0x1 << 4) 179 #define RT1305_POW_LDO2_IB2_BIT 4 180 #define RT1305_POW_VREF (0x1 << 3) 181 #define RT1305_POW_VREF_BIT 3 182 #define RT1305_POW_VREF1 (0x1 << 2) 183 #define RT1305_POW_VREF1_BIT 2 184 #define RT1305_POW_VREF2 (0x1 << 1) 185 #define RT1305_POW_VREF2_BIT 1 186 187 /* Power Control-2 (0x3b) */ 188 #define RT1305_POW_DISC_VREF (1 << 15) 189 #define RT1305_POW_DISC_VREF_BIT 15 190 #define RT1305_POW_FASTB_VREF (1 << 14) 191 #define RT1305_POW_FASTB_VREF_BIT 14 192 #define RT1305_POW_ULTRA_FAST_VREF (1 << 13) 193 #define RT1305_POW_ULTRA_FAST_VREF_BIT 13 194 #define RT1305_POW_CKXEN_DAC (1 << 12) 195 #define RT1305_POW_CKXEN_DAC_BIT 12 196 #define RT1305_POW_EN_CKGEN_DAC (1 << 11) 197 #define RT1305_POW_EN_CKGEN_DAC_BIT 11 198 #define RT1305_POW_DAC1_L (1 << 10) 199 #define RT1305_POW_DAC1_L_BIT 10 200 #define RT1305_POW_DAC1_R (1 << 9) 201 #define RT1305_POW_DAC1_R_BIT 9 202 #define RT1305_POW_CLAMP (1 << 8) 203 #define RT1305_POW_CLAMP_BIT 8 204 #define RT1305_POW_BUFL (1 << 7) 205 #define RT1305_POW_BUFL_BIT 7 206 #define RT1305_POW_BUFR (1 << 6) 207 #define RT1305_POW_BUFR_BIT 6 208 #define RT1305_POW_EN_CKGEN_ADC (1 << 5) 209 #define RT1305_POW_EN_CKGEN_ADC_BIT 5 210 #define RT1305_POW_ADC3_L (1 << 4) 211 #define RT1305_POW_ADC3_L_BIT 4 212 #define RT1305_POW_ADC3_R (1 << 3) 213 #define RT1305_POW_ADC3_R_BIT 3 214 #define RT1305_POW_TRIOSC (1 << 2) 215 #define RT1305_POW_TRIOSC_BIT 2 216 #define RT1305_POR_AVDD1 (1 << 1) 217 #define RT1305_POR_AVDD1_BIT 1 218 #define RT1305_POR_AVDD2 (1 << 0) 219 #define RT1305_POR_AVDD2_BIT 0 220 221 /* Power Control-3 (0x3c) */ 222 #define RT1305_POW_VSENSE_RCH (1 << 15) 223 #define RT1305_POW_VSENSE_RCH_BIT 15 224 #define RT1305_POW_VSENSE_LCH (1 << 14) 225 #define RT1305_POW_VSENSE_LCH_BIT 14 226 #define RT1305_POW_ISENSE_RCH (1 << 13) 227 #define RT1305_POW_ISENSE_RCH_BIT 13 228 #define RT1305_POW_ISENSE_LCH (1 << 12) 229 #define RT1305_POW_ISENSE_LCH_BIT 12 230 #define RT1305_POW_POR_AVDD1 (1 << 11) 231 #define RT1305_POW_POR_AVDD1_BIT 11 232 #define RT1305_POW_POR_AVDD2 (1 << 10) 233 #define RT1305_POW_POR_AVDD2_BIT 10 234 #define RT1305_EN_K_HV (1 << 9) 235 #define RT1305_EN_K_HV_BIT 9 236 #define RT1305_EN_PRE_K_HV (1 << 8) 237 #define RT1305_EN_PRE_K_HV_BIT 8 238 #define RT1305_EN_EFUSE_1P8V (1 << 7) 239 #define RT1305_EN_EFUSE_1P8V_BIT 7 240 #define RT1305_EN_EFUSE_5V (1 << 6) 241 #define RT1305_EN_EFUSE_5V_BIT 6 242 #define RT1305_EN_VCM_6172 (1 << 5) 243 #define RT1305_EN_VCM_6172_BIT 5 244 #define RT1305_POR_EFUSE (1 << 4) 245 #define RT1305_POR_EFUSE_BIT 4 246 247 /* Clock Detect (0x3f) */ 248 #define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12) 249 #define RT1305_SEL_CLK_DET_SRC_SFT 12 250 #define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12) 251 #define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12) 252 253 254 /* System Clock Source */ 255 enum { 256 RT1305_FS_SYS_PRE_S_MCLK, 257 RT1305_FS_SYS_PRE_S_PLL1, 258 RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */ 259 }; 260 261 /* PLL Source 1/2 */ 262 enum { 263 RT1305_PLL1_S_BCLK, 264 RT1305_PLL2_S_MCLK, 265 RT1305_PLL2_S_RCCLK, /* 98.304M Hz */ 266 }; 267 268 enum { 269 RT1305_AIF1, 270 RT1305_AIFS 271 }; 272 273 #define R0_UPPER 0x2E8BA2 //5.5 ohm 274 #define R0_LOWER 0x666666 //2.5 ohm 275 276 #endif /* end of _RT1305_H_ */ 277