1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1019.c -- RT1019 ALSA SoC audio amplifier driver 4 // Author: Jack Yu <jack.yu@realtek.com> 5 // 6 // Copyright(c) 2021 Realtek Semiconductor Corp. 7 // 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/fs.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/regmap.h> 18 #include <linux/i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/gpio.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt1019.h" 32 33 static const struct reg_default rt1019_reg[] = { 34 { 0x0000, 0x00 }, 35 { 0x0011, 0x04 }, 36 { 0x0013, 0x00 }, 37 { 0x0019, 0x30 }, 38 { 0x001b, 0x01 }, 39 { 0x005c, 0x00 }, 40 { 0x005e, 0x10 }, 41 { 0x005f, 0xec }, 42 { 0x0061, 0x10 }, 43 { 0x0062, 0x19 }, 44 { 0x0066, 0x08 }, 45 { 0x0100, 0x80 }, 46 { 0x0100, 0x51 }, 47 { 0x0102, 0x23 }, 48 { 0x0311, 0x00 }, 49 { 0x0312, 0x3e }, 50 { 0x0313, 0x86 }, 51 { 0x0400, 0x03 }, 52 { 0x0401, 0x02 }, 53 { 0x0402, 0x01 }, 54 { 0x0504, 0xff }, 55 { 0x0505, 0x24 }, 56 { 0x0b00, 0x50 }, 57 { 0x0b01, 0xc3 }, 58 }; 59 60 static bool rt1019_volatile_register(struct device *dev, unsigned int reg) 61 { 62 switch (reg) { 63 case RT1019_PWR_STRP_2: 64 case RT1019_VER_ID: 65 case RT1019_VEND_ID_1: 66 case RT1019_VEND_ID_2: 67 case RT1019_DEV_ID_1: 68 case RT1019_DEV_ID_2: 69 return true; 70 71 default: 72 return false; 73 } 74 } 75 76 static bool rt1019_readable_register(struct device *dev, unsigned int reg) 77 { 78 switch (reg) { 79 case RT1019_RESET: 80 case RT1019_IDS_CTRL: 81 case RT1019_ASEL_CTRL: 82 case RT1019_PWR_STRP_2: 83 case RT1019_BEEP_TONE: 84 case RT1019_VER_ID: 85 case RT1019_VEND_ID_1: 86 case RT1019_VEND_ID_2: 87 case RT1019_DEV_ID_1: 88 case RT1019_DEV_ID_2: 89 case RT1019_SDB_CTRL: 90 case RT1019_CLK_TREE_1: 91 case RT1019_CLK_TREE_2: 92 case RT1019_CLK_TREE_3: 93 case RT1019_PLL_1: 94 case RT1019_PLL_2: 95 case RT1019_PLL_3: 96 case RT1019_TDM_1: 97 case RT1019_TDM_2: 98 case RT1019_TDM_3: 99 case RT1019_DMIX_MONO_1: 100 case RT1019_DMIX_MONO_2: 101 case RT1019_BEEP_1: 102 case RT1019_BEEP_2: 103 return true; 104 default: 105 return false; 106 } 107 } 108 109 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 110 111 static const char * const rt1019_din_source_select[] = { 112 "Left", 113 "Right", 114 "Left + Right average", 115 }; 116 117 static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0, 118 rt1019_din_source_select); 119 120 static const struct snd_kcontrol_new rt1019_snd_controls[] = { 121 SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0, 122 127, 0, dac_vol_tlv), 123 SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel), 124 }; 125 126 static int r1019_dac_event(struct snd_soc_dapm_widget *w, 127 struct snd_kcontrol *kcontrol, int event) 128 { 129 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 130 131 switch (event) { 132 case SND_SOC_DAPM_PRE_PMU: 133 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb); 134 break; 135 case SND_SOC_DAPM_POST_PMD: 136 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); 137 break; 138 default: 139 break; 140 } 141 142 return 0; 143 } 144 145 static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = { 146 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 147 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, 148 r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 149 SND_SOC_DAPM_OUTPUT("SPO"), 150 }; 151 152 static const struct snd_soc_dapm_route rt1019_dapm_routes[] = { 153 { "DAC", NULL, "AIFRX" }, 154 { "SPO", NULL, "DAC" }, 155 }; 156 157 static int rt1019_hw_params(struct snd_pcm_substream *substream, 158 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 159 { 160 struct snd_soc_component *component = dai->component; 161 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 162 int pre_div, bclk_ms, frame_size; 163 unsigned int val_len = 0, sys_div_da_filter = 0; 164 unsigned int sys_dac_osr = 0, sys_fifo_clk = 0; 165 unsigned int sys_clk_cal = 0, sys_asrc_in = 0; 166 167 rt1019->lrck = params_rate(params); 168 pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck); 169 if (pre_div < 0) { 170 dev_err(component->dev, "Unsupported clock setting\n"); 171 return -EINVAL; 172 } 173 174 frame_size = snd_soc_params_to_frame_size(params); 175 if (frame_size < 0) { 176 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 177 return -EINVAL; 178 } 179 180 bclk_ms = frame_size > 32; 181 rt1019->bclk = rt1019->lrck * (32 << bclk_ms); 182 183 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 184 rt1019->bclk, rt1019->lrck); 185 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 186 bclk_ms, pre_div, dai->id); 187 188 switch (pre_div) { 189 case 0: 190 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1; 191 sys_dac_osr = RT1019_SYS_DA_OSR_DIV1; 192 sys_asrc_in = RT1019_ASRC_256FS_DIV1; 193 sys_fifo_clk = RT1019_SEL_FIFO_DIV1; 194 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1; 195 break; 196 case 1: 197 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2; 198 sys_dac_osr = RT1019_SYS_DA_OSR_DIV2; 199 sys_asrc_in = RT1019_ASRC_256FS_DIV2; 200 sys_fifo_clk = RT1019_SEL_FIFO_DIV2; 201 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2; 202 break; 203 case 3: 204 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4; 205 sys_dac_osr = RT1019_SYS_DA_OSR_DIV4; 206 sys_asrc_in = RT1019_ASRC_256FS_DIV4; 207 sys_fifo_clk = RT1019_SEL_FIFO_DIV4; 208 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4; 209 break; 210 default: 211 return -EINVAL; 212 } 213 214 switch (params_width(params)) { 215 case 16: 216 break; 217 case 20: 218 val_len = RT1019_I2S_DL_20; 219 break; 220 case 24: 221 val_len = RT1019_I2S_DL_24; 222 break; 223 case 32: 224 val_len = RT1019_I2S_DL_32; 225 break; 226 case 8: 227 val_len = RT1019_I2S_DL_8; 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK, 234 val_len); 235 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 236 RT1019_SEL_FIFO_MASK, sys_fifo_clk); 237 snd_soc_component_update_bits(component, RT1019_CLK_TREE_2, 238 RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK | 239 RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr | 240 sys_asrc_in); 241 snd_soc_component_update_bits(component, RT1019_CLK_TREE_3, 242 RT1019_SEL_CLK_CAL_MASK, sys_clk_cal); 243 244 return 0; 245 } 246 247 static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 248 { 249 struct snd_soc_component *component = dai->component; 250 unsigned int reg_val = 0, reg_val2 = 0; 251 252 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 253 case SND_SOC_DAIFMT_NB_NF: 254 break; 255 case SND_SOC_DAIFMT_IB_NF: 256 reg_val2 |= RT1019_TDM_BCLK_INV; 257 break; 258 default: 259 return -EINVAL; 260 } 261 262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 263 case SND_SOC_DAIFMT_I2S: 264 break; 265 266 case SND_SOC_DAIFMT_LEFT_J: 267 reg_val |= RT1019_I2S_DF_LEFT; 268 break; 269 270 case SND_SOC_DAIFMT_DSP_A: 271 reg_val |= RT1019_I2S_DF_PCM_A_R; 272 break; 273 274 case SND_SOC_DAIFMT_DSP_B: 275 reg_val |= RT1019_I2S_DF_PCM_B_R; 276 break; 277 278 default: 279 return -EINVAL; 280 } 281 282 snd_soc_component_update_bits(component, RT1019_TDM_2, 283 RT1019_I2S_DF_MASK, reg_val); 284 snd_soc_component_update_bits(component, RT1019_TDM_1, 285 RT1019_TDM_BCLK_MASK, reg_val2); 286 287 return 0; 288 } 289 290 static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai, 291 int clk_id, unsigned int freq, int dir) 292 { 293 struct snd_soc_component *component = dai->component; 294 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 295 unsigned int reg_val = 0; 296 297 if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src) 298 return 0; 299 300 switch (clk_id) { 301 case RT1019_SCLK_S_BCLK: 302 reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK; 303 break; 304 305 case RT1019_SCLK_S_PLL: 306 reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL; 307 break; 308 309 default: 310 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 311 return -EINVAL; 312 } 313 314 rt1019->sysclk = freq; 315 rt1019->sysclk_src = clk_id; 316 317 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 318 319 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 320 RT1019_CLK_SYS_PRE_SEL_MASK, reg_val); 321 322 return 0; 323 } 324 325 static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 326 unsigned int freq_in, unsigned int freq_out) 327 { 328 struct snd_soc_component *component = dai->component; 329 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 330 struct rl6231_pll_code pll_code; 331 int ret; 332 333 if (!freq_in || !freq_out) { 334 dev_dbg(component->dev, "PLL disabled\n"); 335 rt1019->pll_in = 0; 336 rt1019->pll_out = 0; 337 return 0; 338 } 339 340 if (source == rt1019->pll_src && freq_in == rt1019->pll_in && 341 freq_out == rt1019->pll_out) 342 return 0; 343 344 switch (source) { 345 case RT1019_PLL_S_BCLK: 346 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 347 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK); 348 break; 349 350 case RT1019_PLL_S_RC25M: 351 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 352 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC); 353 break; 354 355 default: 356 dev_err(component->dev, "Unknown PLL source %d\n", source); 357 return -EINVAL; 358 } 359 360 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 361 if (ret < 0) { 362 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 363 return ret; 364 } 365 366 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 367 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 368 pll_code.n_code, pll_code.k_code); 369 370 snd_soc_component_update_bits(component, RT1019_PWR_STRP_2, 371 RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK, 372 RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU); 373 snd_soc_component_update_bits(component, RT1019_PLL_1, 374 RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK, 375 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT) | 376 (pll_code.m_bp << RT1019_PLL_M_BP_SFT) | 377 ((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK)); 378 snd_soc_component_update_bits(component, RT1019_PLL_2, 379 RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK); 380 snd_soc_component_update_bits(component, RT1019_PLL_3, 381 RT1019_PLL_K_MASK, pll_code.k_code); 382 383 rt1019->pll_in = freq_in; 384 rt1019->pll_out = freq_out; 385 rt1019->pll_src = source; 386 387 return 0; 388 } 389 390 static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 391 unsigned int rx_mask, int slots, int slot_width) 392 { 393 struct snd_soc_component *component = dai->component; 394 unsigned int cn = 0, cl = 0, rx_slotnum; 395 int ret = 0, first_bit; 396 397 switch (slots) { 398 case 4: 399 cn = RT1019_I2S_TX_4CH; 400 break; 401 case 6: 402 cn = RT1019_I2S_TX_6CH; 403 break; 404 case 8: 405 cn = RT1019_I2S_TX_8CH; 406 break; 407 case 2: 408 break; 409 default: 410 return -EINVAL; 411 } 412 413 switch (slot_width) { 414 case 20: 415 cl = RT1019_TDM_CL_20; 416 break; 417 case 24: 418 cl = RT1019_TDM_CL_24; 419 break; 420 case 32: 421 cl = RT1019_TDM_CL_32; 422 break; 423 case 8: 424 cl = RT1019_TDM_CL_8; 425 break; 426 case 16: 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 /* Rx slot configuration */ 433 rx_slotnum = hweight_long(rx_mask); 434 if (rx_slotnum != 1) { 435 ret = -EINVAL; 436 dev_err(component->dev, "too many rx slots or zero slot\n"); 437 goto _set_tdm_err_; 438 } 439 /* This is an assumption that the system sends stereo audio to the 440 * amplifier typically. And the stereo audio is placed in slot 0/2/4/6 441 * as the starting slot. The users could select the channel from 442 * L/R/L+R by "Mono LR Select" control. 443 */ 444 first_bit = __ffs(rx_mask); 445 switch (first_bit) { 446 case 0: 447 case 2: 448 case 4: 449 case 6: 450 snd_soc_component_update_bits(component, 451 RT1019_TDM_3, 452 RT1019_TDM_I2S_TX_L_DAC1_1_MASK | 453 RT1019_TDM_I2S_TX_R_DAC1_1_MASK, 454 (first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | 455 ((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); 456 break; 457 case 1: 458 case 3: 459 case 5: 460 case 7: 461 snd_soc_component_update_bits(component, 462 RT1019_TDM_3, 463 RT1019_TDM_I2S_TX_L_DAC1_1_MASK | 464 RT1019_TDM_I2S_TX_R_DAC1_1_MASK, 465 ((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | 466 (first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); 467 break; 468 default: 469 ret = -EINVAL; 470 goto _set_tdm_err_; 471 } 472 473 snd_soc_component_update_bits(component, RT1019_TDM_1, 474 RT1019_TDM_CL_MASK, cl); 475 snd_soc_component_update_bits(component, RT1019_TDM_2, 476 RT1019_I2S_CH_TX_MASK, cn); 477 478 _set_tdm_err_: 479 return ret; 480 } 481 482 static int rt1019_probe(struct snd_soc_component *component) 483 { 484 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 485 486 rt1019->component = component; 487 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); 488 489 return 0; 490 } 491 492 #define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000 493 #define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 494 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 495 496 static const struct snd_soc_dai_ops rt1019_aif_dai_ops = { 497 .hw_params = rt1019_hw_params, 498 .set_fmt = rt1019_set_dai_fmt, 499 .set_sysclk = rt1019_set_dai_sysclk, 500 .set_pll = rt1019_set_dai_pll, 501 .set_tdm_slot = rt1019_set_tdm_slot, 502 }; 503 504 static struct snd_soc_dai_driver rt1019_dai[] = { 505 { 506 .name = "rt1019-aif", 507 .id = 0, 508 .playback = { 509 .stream_name = "AIF Playback", 510 .channels_min = 1, 511 .channels_max = 2, 512 .rates = RT1019_STEREO_RATES, 513 .formats = RT1019_FORMATS, 514 }, 515 .ops = &rt1019_aif_dai_ops, 516 } 517 }; 518 519 static const struct snd_soc_component_driver soc_component_dev_rt1019 = { 520 .probe = rt1019_probe, 521 .controls = rt1019_snd_controls, 522 .num_controls = ARRAY_SIZE(rt1019_snd_controls), 523 .dapm_widgets = rt1019_dapm_widgets, 524 .num_dapm_widgets = ARRAY_SIZE(rt1019_dapm_widgets), 525 .dapm_routes = rt1019_dapm_routes, 526 .num_dapm_routes = ARRAY_SIZE(rt1019_dapm_routes), 527 .endianness = 1, 528 }; 529 530 static const struct regmap_config rt1019_regmap = { 531 .reg_bits = 16, 532 .val_bits = 8, 533 .use_single_read = true, 534 .use_single_write = true, 535 .max_register = RT1019_BEEP_2, 536 .volatile_reg = rt1019_volatile_register, 537 .readable_reg = rt1019_readable_register, 538 .cache_type = REGCACHE_RBTREE, 539 .reg_defaults = rt1019_reg, 540 .num_reg_defaults = ARRAY_SIZE(rt1019_reg), 541 }; 542 543 static const struct i2c_device_id rt1019_i2c_id[] = { 544 { "rt1019", 0 }, 545 { } 546 }; 547 MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id); 548 549 static const struct of_device_id rt1019_of_match[] = { 550 { .compatible = "realtek,rt1019", }, 551 {}, 552 }; 553 MODULE_DEVICE_TABLE(of, rt1019_of_match); 554 555 #ifdef CONFIG_ACPI 556 static const struct acpi_device_id rt1019_acpi_match[] = { 557 { "10EC1019", 0}, 558 { }, 559 }; 560 MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match); 561 #endif 562 563 static int rt1019_i2c_probe(struct i2c_client *i2c) 564 { 565 struct rt1019_priv *rt1019; 566 int ret; 567 unsigned int val, val2, dev_id; 568 569 rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv), 570 GFP_KERNEL); 571 if (!rt1019) 572 return -ENOMEM; 573 574 i2c_set_clientdata(i2c, rt1019); 575 576 rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap); 577 if (IS_ERR(rt1019->regmap)) { 578 ret = PTR_ERR(rt1019->regmap); 579 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 580 ret); 581 return ret; 582 } 583 584 regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val); 585 regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2); 586 dev_id = val << 8 | val2; 587 if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) { 588 dev_err(&i2c->dev, 589 "Device with ID register 0x%x is not rt1019\n", dev_id); 590 return -ENODEV; 591 } 592 593 return devm_snd_soc_register_component(&i2c->dev, 594 &soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai)); 595 } 596 597 static struct i2c_driver rt1019_i2c_driver = { 598 .driver = { 599 .name = "rt1019", 600 .of_match_table = of_match_ptr(rt1019_of_match), 601 .acpi_match_table = ACPI_PTR(rt1019_acpi_match), 602 }, 603 .probe_new = rt1019_i2c_probe, 604 .id_table = rt1019_i2c_id, 605 }; 606 module_i2c_driver(rt1019_i2c_driver); 607 608 MODULE_DESCRIPTION("ASoC RT1019 driver"); 609 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 610 MODULE_LICENSE("GPL v2"); 611