1*2b7aecd5SDerek Fang /* SPDX-License-Identifier: GPL-2.0-only */ 2*2b7aecd5SDerek Fang /* 3*2b7aecd5SDerek Fang * rt1017-sdca-sdw.h -- RT1017 SDCA ALSA SoC audio driver header 4*2b7aecd5SDerek Fang * 5*2b7aecd5SDerek Fang * Copyright(c) 2023 Realtek Semiconductor Corp. 6*2b7aecd5SDerek Fang */ 7*2b7aecd5SDerek Fang 8*2b7aecd5SDerek Fang #ifndef __RT1017_SDW_H__ 9*2b7aecd5SDerek Fang #define __RT1017_SDW_H__ 10*2b7aecd5SDerek Fang 11*2b7aecd5SDerek Fang #include <linux/regmap.h> 12*2b7aecd5SDerek Fang #include <linux/soundwire/sdw.h> 13*2b7aecd5SDerek Fang #include <linux/soundwire/sdw_type.h> 14*2b7aecd5SDerek Fang #include <linux/soundwire/sdw_registers.h> 15*2b7aecd5SDerek Fang #include <sound/soc.h> 16*2b7aecd5SDerek Fang 17*2b7aecd5SDerek Fang /* RT1017 SDCA Control - function number */ 18*2b7aecd5SDerek Fang #define FUNC_NUM_SMART_AMP 0x04 19*2b7aecd5SDerek Fang 20*2b7aecd5SDerek Fang /* RT1017 SDCA entity */ 21*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_PDE23 0x31 22*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_PDE22 0x33 23*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_CS21 0x21 24*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_SAPU29 0x29 25*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_XU22 0x22 26*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_FU 0x03 27*2b7aecd5SDerek Fang #define RT1017_SDCA_ENT_UDMPU21 0x02 28*2b7aecd5SDerek Fang 29*2b7aecd5SDerek Fang /* RT1017 SDCA control */ 30*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_FS_INDEX 0x10 31*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_REQ_POWER_STATE 0x01 32*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_PROT_STAT 0x11 33*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_BYPASS 0x01 34*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_FU_MUTE 0x01 35*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_FU_VOLUME 0x02 36*2b7aecd5SDerek Fang #define RT1017_SDCA_CTL_UDMPU_CLUSTER 0x10 37*2b7aecd5SDerek Fang 38*2b7aecd5SDerek Fang 39*2b7aecd5SDerek Fang #define RT1017_CLASSD_INT_1 0xd300 40*2b7aecd5SDerek Fang #define RT1017_PWM_TRIM_1 0xd370 41*2b7aecd5SDerek Fang 42*2b7aecd5SDerek Fang 43*2b7aecd5SDerek Fang #define RT1017_PWM_FREQ_CTL_SRC_SEL_MASK (0x3 << 2) 44*2b7aecd5SDerek Fang #define RT1017_PWM_FREQ_CTL_SRC_SEL_EFUSE (0x2 << 2) 45*2b7aecd5SDerek Fang #define RT1017_PWM_FREQ_CTL_SRC_SEL_REG (0x0 << 2) 46*2b7aecd5SDerek Fang 47*2b7aecd5SDerek Fang enum { 48*2b7aecd5SDerek Fang RT1017_SDCA_RATE_44100HZ = 0x8, 49*2b7aecd5SDerek Fang RT1017_SDCA_RATE_48000HZ = 0x9, 50*2b7aecd5SDerek Fang RT1017_SDCA_RATE_96000HZ = 0xb, 51*2b7aecd5SDerek Fang RT1017_SDCA_RATE_192000HZ = 0xd, 52*2b7aecd5SDerek Fang }; 53*2b7aecd5SDerek Fang 54*2b7aecd5SDerek Fang struct rt1017_sdca_priv { 55*2b7aecd5SDerek Fang struct snd_soc_component *component; 56*2b7aecd5SDerek Fang struct regmap *regmap; 57*2b7aecd5SDerek Fang struct sdw_slave *sdw_slave; 58*2b7aecd5SDerek Fang struct sdw_bus_params params; 59*2b7aecd5SDerek Fang bool hw_init; 60*2b7aecd5SDerek Fang bool first_hw_init; 61*2b7aecd5SDerek Fang }; 62*2b7aecd5SDerek Fang 63*2b7aecd5SDerek Fang static const struct reg_default rt1017_sdca_reg_defaults[] = { 64*2b7aecd5SDerek Fang { 0x3206, 0x00 }, 65*2b7aecd5SDerek Fang { 0xc001, 0x43 }, 66*2b7aecd5SDerek Fang { 0xc030, 0x54 }, 67*2b7aecd5SDerek Fang { 0xc104, 0x8a }, 68*2b7aecd5SDerek Fang { 0xc10b, 0x2f }, 69*2b7aecd5SDerek Fang { 0xc10c, 0x2f }, 70*2b7aecd5SDerek Fang { 0xc110, 0x49 }, 71*2b7aecd5SDerek Fang { 0xc112, 0x10 }, 72*2b7aecd5SDerek Fang { 0xc300, 0xff }, 73*2b7aecd5SDerek Fang { 0xc301, 0xdd }, 74*2b7aecd5SDerek Fang { 0xc318, 0x40 }, 75*2b7aecd5SDerek Fang { 0xc325, 0x00 }, 76*2b7aecd5SDerek Fang { 0xc326, 0x00 }, 77*2b7aecd5SDerek Fang { 0xc327, 0x00 }, 78*2b7aecd5SDerek Fang { 0xc328, 0x02 }, 79*2b7aecd5SDerek Fang { 0xc331, 0xb2 }, 80*2b7aecd5SDerek Fang { 0xc340, 0x02 }, 81*2b7aecd5SDerek Fang { 0xc350, 0x21 }, 82*2b7aecd5SDerek Fang { 0xc500, 0x00 }, 83*2b7aecd5SDerek Fang { 0xc502, 0x00 }, 84*2b7aecd5SDerek Fang { 0xc504, 0x3f }, 85*2b7aecd5SDerek Fang { 0xc507, 0x1f }, 86*2b7aecd5SDerek Fang { 0xc509, 0x1f }, 87*2b7aecd5SDerek Fang { 0xc510, 0x40 }, 88*2b7aecd5SDerek Fang { 0xc512, 0x00 }, 89*2b7aecd5SDerek Fang { 0xc518, 0x02 }, 90*2b7aecd5SDerek Fang { 0xc51b, 0x7f }, 91*2b7aecd5SDerek Fang { 0xc51d, 0x0f }, 92*2b7aecd5SDerek Fang { 0xc520, 0x00 }, 93*2b7aecd5SDerek Fang { 0xc540, 0x80 }, 94*2b7aecd5SDerek Fang { 0xc541, 0x00 }, 95*2b7aecd5SDerek Fang { 0xc542, 0x0a }, 96*2b7aecd5SDerek Fang { 0xc550, 0x80 }, 97*2b7aecd5SDerek Fang { 0xc551, 0x0f }, 98*2b7aecd5SDerek Fang { 0xc552, 0xff }, 99*2b7aecd5SDerek Fang { 0xc600, 0x10 }, 100*2b7aecd5SDerek Fang { 0xc602, 0x83 }, 101*2b7aecd5SDerek Fang { 0xc612, 0x40 }, 102*2b7aecd5SDerek Fang { 0xc622, 0x40 }, 103*2b7aecd5SDerek Fang { 0xc632, 0x40 }, 104*2b7aecd5SDerek Fang { 0xc642, 0x40 }, 105*2b7aecd5SDerek Fang { 0xc651, 0x00 }, 106*2b7aecd5SDerek Fang { 0xca00, 0xc1 }, 107*2b7aecd5SDerek Fang { 0xca09, 0x00 }, 108*2b7aecd5SDerek Fang { 0xca0a, 0x51 }, 109*2b7aecd5SDerek Fang { 0xca0b, 0xeb }, 110*2b7aecd5SDerek Fang { 0xca0c, 0x85 }, 111*2b7aecd5SDerek Fang { 0xca0e, 0x00 }, 112*2b7aecd5SDerek Fang { 0xca0f, 0x10 }, 113*2b7aecd5SDerek Fang { 0xca10, 0x62 }, 114*2b7aecd5SDerek Fang { 0xca11, 0x4d }, 115*2b7aecd5SDerek Fang { 0xca16, 0x0f }, 116*2b7aecd5SDerek Fang { 0xca17, 0x00 }, 117*2b7aecd5SDerek Fang { 0xcb00, 0x10 }, 118*2b7aecd5SDerek Fang { 0xcc00, 0x10 }, 119*2b7aecd5SDerek Fang { 0xcc02, 0x0b }, 120*2b7aecd5SDerek Fang { 0xd017, 0x09 }, 121*2b7aecd5SDerek Fang { 0xd01a, 0x00 }, 122*2b7aecd5SDerek Fang { 0xd01b, 0x00 }, 123*2b7aecd5SDerek Fang { 0xd01c, 0x00 }, 124*2b7aecd5SDerek Fang { 0xd101, 0xa0 }, 125*2b7aecd5SDerek Fang { 0xd20c, 0x14 }, 126*2b7aecd5SDerek Fang { 0xd300, 0x0f }, 127*2b7aecd5SDerek Fang { 0xd370, 0x18 }, 128*2b7aecd5SDerek Fang { 0xd500, 0x00 }, 129*2b7aecd5SDerek Fang { 0xd545, 0x0b }, 130*2b7aecd5SDerek Fang { 0xd546, 0xf9 }, 131*2b7aecd5SDerek Fang { 0xd547, 0xb2 }, 132*2b7aecd5SDerek Fang { 0xd548, 0xa9 }, 133*2b7aecd5SDerek Fang { 0xd5a5, 0x00 }, 134*2b7aecd5SDerek Fang { 0xd5a6, 0x00 }, 135*2b7aecd5SDerek Fang { 0xd5a7, 0x00 }, 136*2b7aecd5SDerek Fang { 0xd5a8, 0x00 }, 137*2b7aecd5SDerek Fang { 0xd5aa, 0x00 }, 138*2b7aecd5SDerek Fang { 0xd5ab, 0x00 }, 139*2b7aecd5SDerek Fang { 0xd5ac, 0x00 }, 140*2b7aecd5SDerek Fang { 0xd5ad, 0x00 }, 141*2b7aecd5SDerek Fang { 0xda04, 0x03 }, 142*2b7aecd5SDerek Fang { 0xda05, 0x33 }, 143*2b7aecd5SDerek Fang { 0xda06, 0x33 }, 144*2b7aecd5SDerek Fang { 0xda07, 0x33 }, 145*2b7aecd5SDerek Fang { 0xda09, 0x5d }, 146*2b7aecd5SDerek Fang { 0xda0a, 0xc0 }, 147*2b7aecd5SDerek Fang { 0xda0c, 0x00 }, 148*2b7aecd5SDerek Fang { 0xda0d, 0x01 }, 149*2b7aecd5SDerek Fang { 0xda0e, 0x5d }, 150*2b7aecd5SDerek Fang { 0xda0f, 0x86 }, 151*2b7aecd5SDerek Fang { 0xda11, 0x20 }, 152*2b7aecd5SDerek Fang { 0xda12, 0x00 }, 153*2b7aecd5SDerek Fang { 0xda13, 0x00 }, 154*2b7aecd5SDerek Fang { 0xda14, 0x00 }, 155*2b7aecd5SDerek Fang { 0xda16, 0x7f }, 156*2b7aecd5SDerek Fang { 0xda17, 0xff }, 157*2b7aecd5SDerek Fang { 0xda18, 0xff }, 158*2b7aecd5SDerek Fang { 0xda19, 0xff }, 159*2b7aecd5SDerek Fang { 0xdab6, 0x00 }, 160*2b7aecd5SDerek Fang { 0xdab7, 0x01 }, 161*2b7aecd5SDerek Fang { 0xdab8, 0x00 }, 162*2b7aecd5SDerek Fang { 0xdab9, 0x01 }, 163*2b7aecd5SDerek Fang { 0xdaba, 0x00 }, 164*2b7aecd5SDerek Fang { 0xdabb, 0x01 }, 165*2b7aecd5SDerek Fang { 0xdb09, 0x0f }, 166*2b7aecd5SDerek Fang { 0xdb0a, 0xff }, 167*2b7aecd5SDerek Fang { 0xdb14, 0x00 }, 168*2b7aecd5SDerek Fang 169*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21, 170*2b7aecd5SDerek Fang RT1017_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 171*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU, 172*2b7aecd5SDerek Fang RT1017_SDCA_CTL_FU_MUTE, 0x01), 0x01 }, 173*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_XU22, 174*2b7aecd5SDerek Fang RT1017_SDCA_CTL_BYPASS, 0), 0x01 }, 175*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21, 176*2b7aecd5SDerek Fang RT1017_SDCA_CTL_FS_INDEX, 0), 0x09 }, 177*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23, 178*2b7aecd5SDerek Fang RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 179*2b7aecd5SDerek Fang { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE22, 180*2b7aecd5SDerek Fang RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 181*2b7aecd5SDerek Fang }; 182*2b7aecd5SDerek Fang 183*2b7aecd5SDerek Fang #endif /* __RT1017_SDW_H__ */ 184