1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1015.h -- RT1015 ALSA SoC audio amplifier driver 4 // 5 // Copyright 2019 Realtek Semiconductor Corp. 6 // Author: Jack Yu <jack.yu@realtek.com> 7 // 8 // This program is free software; you can redistribute it and/or modify 9 // it under the terms of the GNU General Public License version 2 as 10 // published by the Free Software Foundation. 11 // 12 13 #ifndef __RT1015_H__ 14 #define __RT1015_H__ 15 16 #define RT1015_DEVICE_ID_VAL 0x1011 17 #define RT1015_DEVICE_ID_VAL2 0x1015 18 19 #define RT1015_RESET 0x0000 20 #define RT1015_CLK2 0x0004 21 #define RT1015_CLK3 0x0006 22 #define RT1015_PLL1 0x000a 23 #define RT1015_PLL2 0x000c 24 #define RT1015_CLK_DET 0x0020 25 #define RT1015_SIL_DET 0x0022 26 #define RT1015_CUSTOMER_ID 0x0076 27 #define RT1015_PCODE_FWVER 0x0078 28 #define RT1015_VER_ID 0x007a 29 #define RT1015_VENDOR_ID 0x007c 30 #define RT1015_DEVICE_ID 0x007d 31 #define RT1015_PAD_DRV1 0x00f0 32 #define RT1015_PAD_DRV2 0x00f2 33 #define RT1015_GAT_BOOST 0x00f3 34 #define RT1015_PRO_ALT 0x00f4 35 #define RT1015_MAN_I2C 0x0100 36 #define RT1015_DAC1 0x0102 37 #define RT1015_DAC2 0x0104 38 #define RT1015_DAC3 0x0106 39 #define RT1015_ADC1 0x010c 40 #define RT1015_ADC2 0x010e 41 #define RT1015_TDM_MASTER 0x0111 42 #define RT1015_TDM_TCON 0x0112 43 #define RT1015_TDM1_1 0x0114 44 #define RT1015_TDM1_2 0x0116 45 #define RT1015_TDM1_3 0x0118 46 #define RT1015_TDM1_4 0x011a 47 #define RT1015_TDM1_5 0x011c 48 #define RT1015_MIXER1 0x0300 49 #define RT1015_MIXER2 0x0302 50 #define RT1015_ANA_PROTECT1 0x0311 51 #define RT1015_ANA_CTRL_SEQ1 0x0313 52 #define RT1015_ANA_CTRL_SEQ2 0x0314 53 #define RT1015_VBAT_DET_DEB 0x031a 54 #define RT1015_VBAT_VOLT_DET1 0x031c 55 #define RT1015_VBAT_VOLT_DET2 0x031d 56 #define RT1015_VBAT_TEST_OUT1 0x031e 57 #define RT1015_VBAT_TEST_OUT2 0x031f 58 #define RT1015_VBAT_PROT_ATT 0x0320 59 #define RT1015_VBAT_DET_CODE 0x0321 60 #define RT1015_PWR1 0x0322 61 #define RT1015_PWR4 0x0328 62 #define RT1015_PWR5 0x0329 63 #define RT1015_PWR6 0x032a 64 #define RT1015_PWR7 0x032b 65 #define RT1015_PWR8 0x032c 66 #define RT1015_PWR9 0x032d 67 #define RT1015_CLASSD_SEQ 0x032e 68 #define RT1015_SMART_BST_CTRL1 0x0330 69 #define RT1015_SMART_BST_CTRL2 0x0332 70 #define RT1015_ANA_CTRL1 0x0334 71 #define RT1015_ANA_CTRL2 0x0336 72 #define RT1015_PWR_STATE_CTRL 0x0338 73 #define RT1015_SPK_VOL 0x0506 74 #define RT1015_SHORT_DETTOP1 0x0508 75 #define RT1015_SHORT_DETTOP2 0x050a 76 #define RT1015_SPK_DC_DETECT1 0x0519 77 #define RT1015_SPK_DC_DETECT2 0x051a 78 #define RT1015_SPK_DC_DETECT3 0x051b 79 #define RT1015_SPK_DC_DETECT4 0x051d 80 #define RT1015_SPK_DC_DETECT5 0x051f 81 #define RT1015_BAT_RPO_STEP1 0x0536 82 #define RT1015_BAT_RPO_STEP2 0x0538 83 #define RT1015_BAT_RPO_STEP3 0x053a 84 #define RT1015_BAT_RPO_STEP4 0x053c 85 #define RT1015_BAT_RPO_STEP5 0x053d 86 #define RT1015_BAT_RPO_STEP6 0x053e 87 #define RT1015_BAT_RPO_STEP7 0x053f 88 #define RT1015_BAT_RPO_STEP8 0x0540 89 #define RT1015_BAT_RPO_STEP9 0x0541 90 #define RT1015_BAT_RPO_STEP10 0x0542 91 #define RT1015_BAT_RPO_STEP11 0x0543 92 #define RT1015_BAT_RPO_STEP12 0x0544 93 #define RT1015_SPREAD_SPEC1 0x0568 94 #define RT1015_SPREAD_SPEC2 0x056a 95 #define RT1015_PAD_STATUS 0x1000 96 #define RT1015_PADS_PULLING_CTRL1 0x1002 97 #define RT1015_PADS_DRIVING 0x1006 98 #define RT1015_SYS_RST1 0x1007 99 #define RT1015_SYS_RST2 0x1009 100 #define RT1015_SYS_GATING1 0x100a 101 #define RT1015_TEST_MODE1 0x100c 102 #define RT1015_TEST_MODE2 0x100d 103 #define RT1015_TIMING_CTRL1 0x100e 104 #define RT1015_PLL_INT 0x1010 105 #define RT1015_TEST_OUT1 0x1020 106 #define RT1015_DC_CALIB_CLSD1 0x1200 107 #define RT1015_DC_CALIB_CLSD2 0x1202 108 #define RT1015_DC_CALIB_CLSD3 0x1204 109 #define RT1015_DC_CALIB_CLSD4 0x1206 110 #define RT1015_DC_CALIB_CLSD5 0x1208 111 #define RT1015_DC_CALIB_CLSD6 0x120a 112 #define RT1015_DC_CALIB_CLSD7 0x120c 113 #define RT1015_DC_CALIB_CLSD8 0x120e 114 #define RT1015_DC_CALIB_CLSD9 0x1210 115 #define RT1015_DC_CALIB_CLSD10 0x1212 116 #define RT1015_CLSD_INTERNAL1 0x1300 117 #define RT1015_CLSD_INTERNAL2 0x1302 118 #define RT1015_CLSD_INTERNAL3 0x1304 119 #define RT1015_CLSD_INTERNAL4 0x1305 120 #define RT1015_CLSD_INTERNAL5 0x1306 121 #define RT1015_CLSD_INTERNAL6 0x1308 122 #define RT1015_CLSD_INTERNAL7 0x130a 123 #define RT1015_CLSD_INTERNAL8 0x130c 124 #define RT1015_CLSD_INTERNAL9 0x130e 125 #define RT1015_CLSD_OCP_CTRL 0x130f 126 #define RT1015_VREF_LV 0x1310 127 #define RT1015_MBIAS1 0x1312 128 #define RT1015_MBIAS2 0x1314 129 #define RT1015_MBIAS3 0x1316 130 #define RT1015_MBIAS4 0x1318 131 #define RT1015_VREF_LV1 0x131a 132 #define RT1015_S_BST_TIMING_INTER1 0x1322 133 #define RT1015_S_BST_TIMING_INTER2 0x1323 134 #define RT1015_S_BST_TIMING_INTER3 0x1324 135 #define RT1015_S_BST_TIMING_INTER4 0x1325 136 #define RT1015_S_BST_TIMING_INTER5 0x1326 137 #define RT1015_S_BST_TIMING_INTER6 0x1327 138 #define RT1015_S_BST_TIMING_INTER7 0x1328 139 #define RT1015_S_BST_TIMING_INTER8 0x1329 140 #define RT1015_S_BST_TIMING_INTER9 0x132a 141 #define RT1015_S_BST_TIMING_INTER10 0x132b 142 #define RT1015_S_BST_TIMING_INTER11 0x1330 143 #define RT1015_S_BST_TIMING_INTER12 0x1331 144 #define RT1015_S_BST_TIMING_INTER13 0x1332 145 #define RT1015_S_BST_TIMING_INTER14 0x1333 146 #define RT1015_S_BST_TIMING_INTER15 0x1334 147 #define RT1015_S_BST_TIMING_INTER16 0x1335 148 #define RT1015_S_BST_TIMING_INTER17 0x1336 149 #define RT1015_S_BST_TIMING_INTER18 0x1337 150 #define RT1015_S_BST_TIMING_INTER19 0x1338 151 #define RT1015_S_BST_TIMING_INTER20 0x1339 152 #define RT1015_S_BST_TIMING_INTER21 0x133a 153 #define RT1015_S_BST_TIMING_INTER22 0x133b 154 #define RT1015_S_BST_TIMING_INTER23 0x133c 155 #define RT1015_S_BST_TIMING_INTER24 0x133d 156 #define RT1015_S_BST_TIMING_INTER25 0x133e 157 #define RT1015_S_BST_TIMING_INTER26 0x133f 158 #define RT1015_S_BST_TIMING_INTER27 0x1340 159 #define RT1015_S_BST_TIMING_INTER28 0x1341 160 #define RT1015_S_BST_TIMING_INTER29 0x1342 161 #define RT1015_S_BST_TIMING_INTER30 0x1343 162 #define RT1015_S_BST_TIMING_INTER31 0x1344 163 #define RT1015_S_BST_TIMING_INTER32 0x1345 164 #define RT1015_S_BST_TIMING_INTER33 0x1346 165 #define RT1015_S_BST_TIMING_INTER34 0x1347 166 #define RT1015_S_BST_TIMING_INTER35 0x1348 167 #define RT1015_S_BST_TIMING_INTER36 0x1349 168 169 /* 0x0004 */ 170 #define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14) 171 #define RT1015_CLK_SYS_PRE_SEL_SFT 14 172 #define RT1015_CLK_SYS_PRE_SEL_MCLK (0x0 << 14) 173 #define RT1015_CLK_SYS_PRE_SEL_PLL (0x2 << 14) 174 #define RT1015_PLL_SEL_MASK (0x1 << 13) 175 #define RT1015_PLL_SEL_SFT 13 176 #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13) 177 #define RT1015_PLL_SEL_BCLK (0x1 << 13) 178 #define RT1015_FS_PD_MASK (0x7 << 4) 179 #define RT1015_FS_PD_SFT 4 180 181 /* 0x000a */ 182 #define RT1015_PLL_M_MAX 0xf 183 #define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12) 184 #define RT1015_PLL_M_SFT 12 185 #define RT1015_PLL_M_BP (0x1 << 11) 186 #define RT1015_PLL_M_BP_SFT 11 187 #define RT1015_PLL_N_MAX 0x1ff 188 #define RT1015_PLL_N_MASK (RT1015_PLL_N_MAX << 0) 189 #define RT1015_PLL_N_SFT 0 190 191 /* 0x000c */ 192 #define RT1015_PLL_BPK_MASK (0x1 << 5) 193 #define RT1015_PLL_BPK (0x0 << 5) 194 #define RT1015_PLL_K_MAX 0x1f 195 #define RT1015_PLL_K_MASK (RT1015_PLL_K_MAX) 196 #define RT1015_PLL_K_SFT 0 197 198 /* 0x007a */ 199 #define RT1015_ID_MASK 0xff 200 #define RT1015_ID_VERA 0x0 201 #define RT1015_ID_VERB 0x1 202 203 /* 0x0102 */ 204 #define RT1015_DAC_VOL_MASK (0x7f << 9) 205 #define RT1015_DAC_VOL_SFT 9 206 207 /* 0x0104 */ 208 #define RT1015_DAC_CLK (0x1 << 13) 209 #define RT1015_DAC_CLK_BIT 13 210 211 /* 0x0106 */ 212 #define RT1015_DAC_MUTE_MASK (0x1 << 15) 213 #define RT1015_DA_MUTE_SFT 15 214 #define RT1015_DVOL_MUTE_FLAG_SFT 12 215 216 /* 0x0111 */ 217 #define RT1015_TCON_TDM_MS_MASK (0x1 << 14) 218 #define RT1015_TCON_TDM_MS_SFT 14 219 #define RT1015_TCON_TDM_MS_S (0x0 << 14) 220 #define RT1015_TCON_TDM_MS_M (0x1 << 14) 221 #define RT1015_I2S_DL_MASK (0x7 << 8) 222 #define RT1015_I2S_DL_SFT 8 223 #define RT1015_I2S_DL_16 (0x0 << 8) 224 #define RT1015_I2S_DL_20 (0x1 << 8) 225 #define RT1015_I2S_DL_24 (0x2 << 8) 226 #define RT1015_I2S_DL_8 (0x3 << 8) 227 #define RT1015_I2S_M_DF_MASK (0x7 << 0) 228 #define RT1015_I2S_M_DF_SFT 0 229 #define RT1015_I2S_M_DF_I2S (0x0) 230 #define RT1015_I2S_M_DF_LEFT (0x1) 231 #define RT1015_I2S_M_DF_PCM_A (0x2) 232 #define RT1015_I2S_M_DF_PCM_B (0x3) 233 #define RT1015_I2S_M_DF_PCM_A_N (0x6) 234 #define RT1015_I2S_M_DF_PCM_B_N (0x7) 235 236 /* TDM_tcon Setting (0x0112) */ 237 #define RT1015_I2S_TCON_DF_MASK (0x7 << 13) 238 #define RT1015_I2S_TCON_DF_SFT 13 239 #define RT1015_I2S_TCON_DF_I2S (0x0 << 13) 240 #define RT1015_I2S_TCON_DF_LEFT (0x1 << 13) 241 #define RT1015_I2S_TCON_DF_PCM_A (0x2 << 13) 242 #define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13) 243 #define RT1015_I2S_TCON_DF_PCM_A_N (0x6 << 13) 244 #define RT1015_I2S_TCON_DF_PCM_B_N (0x7 << 13) 245 #define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10) 246 #define RT1015_TCON_BCLK_SEL_SFT 10 247 #define RT1015_TCON_BCLK_SEL_32FS (0x0 << 10) 248 #define RT1015_TCON_BCLK_SEL_64FS (0x1 << 10) 249 #define RT1015_TCON_BCLK_SEL_128FS (0x2 << 10) 250 #define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10) 251 #define RT1015_TCON_CH_LEN_MASK (0x3 << 5) 252 #define RT1015_TCON_CH_LEN_SFT 5 253 #define RT1015_TCON_CH_LEN_16B (0x0 << 5) 254 #define RT1015_TCON_CH_LEN_20B (0x1 << 5) 255 #define RT1015_TCON_CH_LEN_24B (0x2 << 5) 256 #define RT1015_TCON_CH_LEN_32B (0x3 << 5) 257 #define RT1015_TCON_BCLK_MST_MASK (0x1 << 4) 258 #define RT1015_TCON_BCLK_MST_SFT 4 259 #define RT1015_TCON_BCLK_MST_INV (0x1 << 4) 260 261 /* TDM1 Setting-1 (0x0114) */ 262 #define RT1015_TDM_INV_BCLK_MASK (0x1 << 15) 263 #define RT1015_TDM_INV_BCLK_SFT 15 264 #define RT1015_TDM_INV_BCLK (0x1 << 15) 265 266 /* 0x0330 */ 267 #define RT1015_ABST_AUTO_EN_MASK (0x1 << 13) 268 #define RT1015_ABST_AUTO_MODE (0x1 << 13) 269 #define RT1015_ABST_REG_MODE (0x0 << 13) 270 #define RT1015_ABST_FIX_TGT_MASK (0x1 << 12) 271 #define RT1015_ABST_FIX_TGT_EN (0x1 << 12) 272 #define RT1015_ABST_FIX_TGT_DIS (0x0 << 12) 273 #define RT1015_BYPASS_SWR_REG_MASK (0x1 << 7) 274 #define RT1015_BYPASS_SWRREG_BYPASS (0x1 << 7) 275 #define RT1015_BYPASS_SWRREG_PASS (0x0 << 7) 276 277 /* 0x0322 */ 278 #define RT1015_PWR_LDO2 (0x1 << 15) 279 #define RT1015_PWR_LDO2_BIT 15 280 #define RT1015_PWR_DAC (0x1 << 14) 281 #define RT1015_PWR_DAC_BIT 14 282 #define RT1015_PWR_INTCLK (0x1 << 13) 283 #define RT1015_PWR_INTCLK_BIT 13 284 #define RT1015_PWR_ISENSE (0x1 << 12) 285 #define RT1015_PWR_ISENSE_BIT 12 286 #define RT1015_PWR_VSENSE (0x1 << 10) 287 #define RT1015_PWR_VSENSE_BIT 10 288 #define RT1015_PWR_PLL (0x1 << 9) 289 #define RT1015_PWR_PLL_BIT 9 290 #define RT1015_PWR_BG_1_2 (0x1 << 8) 291 #define RT1015_PWR_BG_1_2_BIT 8 292 #define RT1015_PWR_MBIAS_BG (0x1 << 7) 293 #define RT1015_PWR_MBIAS_BG_BIT 7 294 #define RT1015_PWR_VBAT (0x1 << 6) 295 #define RT1015_PWR_VBAT_BIT 6 296 #define RT1015_PWR_MBIAS (0x1 << 4) 297 #define RT1015_PWR_MBIAS_BIT 4 298 #define RT1015_PWR_ADCV (0x1 << 3) 299 #define RT1015_PWR_ADCV_BIT 3 300 #define RT1015_PWR_MIXERV (0x1 << 2) 301 #define RT1015_PWR_MIXERV_BIT 2 302 #define RT1015_PWR_SUMV (0x1 << 1) 303 #define RT1015_PWR_SUMV_BIT 1 304 #define RT1015_PWR_VREFLV (0x1 << 0) 305 #define RT1015_PWR_VREFLV_BIT 0 306 307 /* 0x0324 */ 308 #define RT1015_PWR_BASIC (0x1 << 15) 309 #define RT1015_PWR_BASIC_BIT 15 310 #define RT1015_PWR_SD (0x1 << 14) 311 #define RT1015_PWR_SD_BIT 14 312 #define RT1015_PWR_IBIAS (0x1 << 13) 313 #define RT1015_PWR_IBIAS_BIT 13 314 #define RT1015_PWR_VCM (0x1 << 11) 315 #define RT1015_PWR_VCM_BIT 11 316 317 /* 0x0328 */ 318 #define RT1015_PWR_SWR (0x1 << 12) 319 #define RT1015_PWR_SWR_BIT 12 320 321 /* 0x1300 */ 322 #define RT1015_PWR_CLSD (0x1 << 12) 323 #define RT1015_PWR_CLSD_BIT 12 324 325 /* 0x007a */ 326 #define RT1015_ID_MASK 0xff 327 #define RT1015_ID_VERA 0x0 328 #define RT1015_ID_VERB 0x1 329 330 /* System Clock Source */ 331 enum { 332 RT1015_SCLK_S_MCLK, 333 RT1015_SCLK_S_PLL, 334 }; 335 336 /* PLL1 Source */ 337 enum { 338 RT1015_PLL_S_MCLK, 339 RT1015_PLL_S_BCLK, 340 }; 341 342 enum { 343 RT1015_AIF1, 344 RT1015_AIFS, 345 }; 346 347 enum { 348 RT1015_VERA, 349 RT1015_VERB, 350 }; 351 352 enum { 353 BYPASS, 354 ADAPTIVE, 355 FIXED_ADAPTIVE, 356 }; 357 358 struct rt1015_priv { 359 struct snd_soc_component *component; 360 struct regmap *regmap; 361 int sysclk; 362 int sysclk_src; 363 int lrck; 364 int bclk; 365 int id; 366 int pll_src; 367 int pll_in; 368 int pll_out; 369 int boost_mode; 370 int bypass_boost; 371 int amp_ver; 372 int dac_is_used; 373 }; 374 375 #endif /* __RT1015_H__ */ 376