1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver 4 // 5 // Copyright 2019 Realtek Semiconductor Corp. 6 // 7 // Author: Jack Yu <jack.yu@realtek.com> 8 // 9 // 10 11 #include <linux/acpi.h> 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/fs.h> 15 #include <linux/gpio.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/regmap.h> 23 #include <sound/core.h> 24 #include <sound/initval.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/soc.h> 29 #include <sound/tlv.h> 30 #include <sound/rt1015.h> 31 32 #include "rl6231.h" 33 #include "rt1015.h" 34 35 static const struct rt1015_platform_data i2s_default_platform_data = { 36 .power_up_delay_ms = 50, 37 }; 38 39 static const struct reg_default rt1015_reg[] = { 40 { 0x0000, 0x0000 }, 41 { 0x0004, 0xa000 }, 42 { 0x0006, 0x0003 }, 43 { 0x000a, 0x081e }, 44 { 0x000c, 0x0006 }, 45 { 0x000e, 0x0000 }, 46 { 0x0010, 0x0000 }, 47 { 0x0012, 0x0000 }, 48 { 0x0014, 0x0000 }, 49 { 0x0016, 0x0000 }, 50 { 0x0018, 0x0000 }, 51 { 0x0020, 0x8000 }, 52 { 0x0022, 0x8043 }, 53 { 0x0076, 0x0000 }, 54 { 0x0078, 0x0000 }, 55 { 0x007a, 0x0002 }, 56 { 0x007c, 0x10ec }, 57 { 0x007d, 0x1015 }, 58 { 0x00f0, 0x5000 }, 59 { 0x00f2, 0x004c }, 60 { 0x00f3, 0xecfe }, 61 { 0x00f4, 0x0000 }, 62 { 0x00f6, 0x0400 }, 63 { 0x0100, 0x0028 }, 64 { 0x0102, 0xff02 }, 65 { 0x0104, 0xa213 }, 66 { 0x0106, 0x200c }, 67 { 0x010c, 0x0000 }, 68 { 0x010e, 0x0058 }, 69 { 0x0111, 0x0200 }, 70 { 0x0112, 0x0400 }, 71 { 0x0114, 0x0022 }, 72 { 0x0116, 0x0000 }, 73 { 0x0118, 0x0000 }, 74 { 0x011a, 0x0123 }, 75 { 0x011c, 0x4567 }, 76 { 0x0300, 0x203d }, 77 { 0x0302, 0x001e }, 78 { 0x0311, 0x0000 }, 79 { 0x0313, 0x6014 }, 80 { 0x0314, 0x00a2 }, 81 { 0x031a, 0x00a0 }, 82 { 0x031c, 0x001f }, 83 { 0x031d, 0xffff }, 84 { 0x031e, 0x0000 }, 85 { 0x031f, 0x0000 }, 86 { 0x0320, 0x0000 }, 87 { 0x0321, 0x0000 }, 88 { 0x0322, 0xd7df }, 89 { 0x0328, 0x10b2 }, 90 { 0x0329, 0x0175 }, 91 { 0x032a, 0x36ad }, 92 { 0x032b, 0x7e55 }, 93 { 0x032c, 0x0520 }, 94 { 0x032d, 0xaa00 }, 95 { 0x032e, 0x570e }, 96 { 0x0330, 0xe180 }, 97 { 0x0332, 0x0034 }, 98 { 0x0334, 0x0001 }, 99 { 0x0336, 0x0010 }, 100 { 0x0338, 0x0000 }, 101 { 0x04fa, 0x0030 }, 102 { 0x04fc, 0x35c8 }, 103 { 0x04fe, 0x0800 }, 104 { 0x0500, 0x0400 }, 105 { 0x0502, 0x1000 }, 106 { 0x0504, 0x0000 }, 107 { 0x0506, 0x04ff }, 108 { 0x0508, 0x0010 }, 109 { 0x050a, 0x001a }, 110 { 0x0519, 0x1c68 }, 111 { 0x051a, 0x0ccc }, 112 { 0x051b, 0x0666 }, 113 { 0x051d, 0x0000 }, 114 { 0x051f, 0x0000 }, 115 { 0x0536, 0x061c }, 116 { 0x0538, 0x0000 }, 117 { 0x053a, 0x0000 }, 118 { 0x053c, 0x0000 }, 119 { 0x053d, 0x0000 }, 120 { 0x053e, 0x0000 }, 121 { 0x053f, 0x0000 }, 122 { 0x0540, 0x0000 }, 123 { 0x0541, 0x0000 }, 124 { 0x0542, 0x0000 }, 125 { 0x0543, 0x0000 }, 126 { 0x0544, 0x0000 }, 127 { 0x0568, 0x0000 }, 128 { 0x056a, 0x0000 }, 129 { 0x1000, 0x0040 }, 130 { 0x1002, 0x5405 }, 131 { 0x1006, 0x5515 }, 132 { 0x1007, 0x05f7 }, 133 { 0x1009, 0x0b0a }, 134 { 0x100a, 0x00ef }, 135 { 0x100d, 0x0003 }, 136 { 0x1010, 0xa433 }, 137 { 0x1020, 0x0000 }, 138 { 0x1200, 0x5a01 }, 139 { 0x1202, 0x6524 }, 140 { 0x1204, 0x1f00 }, 141 { 0x1206, 0x0000 }, 142 { 0x1208, 0x0000 }, 143 { 0x120a, 0x0000 }, 144 { 0x120c, 0x0000 }, 145 { 0x120e, 0x0000 }, 146 { 0x1210, 0x0000 }, 147 { 0x1212, 0x0000 }, 148 { 0x1300, 0x10a1 }, 149 { 0x1302, 0x12ff }, 150 { 0x1304, 0x0400 }, 151 { 0x1305, 0x0844 }, 152 { 0x1306, 0x4611 }, 153 { 0x1308, 0x555e }, 154 { 0x130a, 0x0000 }, 155 { 0x130c, 0x2000 }, 156 { 0x130e, 0x0100 }, 157 { 0x130f, 0x0001 }, 158 { 0x1310, 0x0000 }, 159 { 0x1312, 0x0000 }, 160 { 0x1314, 0x0000 }, 161 { 0x1316, 0x0000 }, 162 { 0x1318, 0x0000 }, 163 { 0x131a, 0x0000 }, 164 { 0x1322, 0x0029 }, 165 { 0x1323, 0x4a52 }, 166 { 0x1324, 0x002c }, 167 { 0x1325, 0x0b02 }, 168 { 0x1326, 0x002d }, 169 { 0x1327, 0x6b5a }, 170 { 0x1328, 0x002e }, 171 { 0x1329, 0xcbb2 }, 172 { 0x132a, 0x0030 }, 173 { 0x132b, 0x2c0b }, 174 { 0x1330, 0x0031 }, 175 { 0x1331, 0x8c63 }, 176 { 0x1332, 0x0032 }, 177 { 0x1333, 0xecbb }, 178 { 0x1334, 0x0034 }, 179 { 0x1335, 0x4d13 }, 180 { 0x1336, 0x0037 }, 181 { 0x1337, 0x0dc3 }, 182 { 0x1338, 0x003d }, 183 { 0x1339, 0xef7b }, 184 { 0x133a, 0x0044 }, 185 { 0x133b, 0xd134 }, 186 { 0x133c, 0x0047 }, 187 { 0x133d, 0x91e4 }, 188 { 0x133e, 0x004d }, 189 { 0x133f, 0xc370 }, 190 { 0x1340, 0x0053 }, 191 { 0x1341, 0xf4fd }, 192 { 0x1342, 0x0060 }, 193 { 0x1343, 0x5816 }, 194 { 0x1344, 0x006c }, 195 { 0x1345, 0xbb2e }, 196 { 0x1346, 0x0072 }, 197 { 0x1347, 0xecbb }, 198 { 0x1348, 0x0076 }, 199 { 0x1349, 0x5d97 }, 200 }; 201 202 static bool rt1015_volatile_register(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case RT1015_RESET: 206 case RT1015_CLK_DET: 207 case RT1015_SIL_DET: 208 case RT1015_VER_ID: 209 case RT1015_VENDOR_ID: 210 case RT1015_DEVICE_ID: 211 case RT1015_PRO_ALT: 212 case RT1015_DAC3: 213 case RT1015_VBAT_TEST_OUT1: 214 case RT1015_VBAT_TEST_OUT2: 215 case RT1015_VBAT_PROT_ATT: 216 case RT1015_VBAT_DET_CODE: 217 case RT1015_SMART_BST_CTRL1: 218 case RT1015_SPK_DC_DETECT1: 219 case RT1015_SPK_DC_DETECT4: 220 case RT1015_SPK_DC_DETECT5: 221 case RT1015_DC_CALIB_CLSD1: 222 case RT1015_DC_CALIB_CLSD5: 223 case RT1015_DC_CALIB_CLSD6: 224 case RT1015_DC_CALIB_CLSD7: 225 case RT1015_DC_CALIB_CLSD8: 226 case RT1015_S_BST_TIMING_INTER1: 227 case RT1015_OSCK_STA: 228 case RT1015_MONO_DYNA_CTRL1: 229 case RT1015_MONO_DYNA_CTRL5: 230 return true; 231 232 default: 233 return false; 234 } 235 } 236 237 static bool rt1015_readable_register(struct device *dev, unsigned int reg) 238 { 239 switch (reg) { 240 case RT1015_RESET: 241 case RT1015_CLK2: 242 case RT1015_CLK3: 243 case RT1015_PLL1: 244 case RT1015_PLL2: 245 case RT1015_DUM_RW1: 246 case RT1015_DUM_RW2: 247 case RT1015_DUM_RW3: 248 case RT1015_DUM_RW4: 249 case RT1015_DUM_RW5: 250 case RT1015_DUM_RW6: 251 case RT1015_CLK_DET: 252 case RT1015_SIL_DET: 253 case RT1015_CUSTOMER_ID: 254 case RT1015_PCODE_FWVER: 255 case RT1015_VER_ID: 256 case RT1015_VENDOR_ID: 257 case RT1015_DEVICE_ID: 258 case RT1015_PAD_DRV1: 259 case RT1015_PAD_DRV2: 260 case RT1015_GAT_BOOST: 261 case RT1015_PRO_ALT: 262 case RT1015_OSCK_STA: 263 case RT1015_MAN_I2C: 264 case RT1015_DAC1: 265 case RT1015_DAC2: 266 case RT1015_DAC3: 267 case RT1015_ADC1: 268 case RT1015_ADC2: 269 case RT1015_TDM_MASTER: 270 case RT1015_TDM_TCON: 271 case RT1015_TDM1_1: 272 case RT1015_TDM1_2: 273 case RT1015_TDM1_3: 274 case RT1015_TDM1_4: 275 case RT1015_TDM1_5: 276 case RT1015_MIXER1: 277 case RT1015_MIXER2: 278 case RT1015_ANA_PROTECT1: 279 case RT1015_ANA_CTRL_SEQ1: 280 case RT1015_ANA_CTRL_SEQ2: 281 case RT1015_VBAT_DET_DEB: 282 case RT1015_VBAT_VOLT_DET1: 283 case RT1015_VBAT_VOLT_DET2: 284 case RT1015_VBAT_TEST_OUT1: 285 case RT1015_VBAT_TEST_OUT2: 286 case RT1015_VBAT_PROT_ATT: 287 case RT1015_VBAT_DET_CODE: 288 case RT1015_PWR1: 289 case RT1015_PWR4: 290 case RT1015_PWR5: 291 case RT1015_PWR6: 292 case RT1015_PWR7: 293 case RT1015_PWR8: 294 case RT1015_PWR9: 295 case RT1015_CLASSD_SEQ: 296 case RT1015_SMART_BST_CTRL1: 297 case RT1015_SMART_BST_CTRL2: 298 case RT1015_ANA_CTRL1: 299 case RT1015_ANA_CTRL2: 300 case RT1015_PWR_STATE_CTRL: 301 case RT1015_MONO_DYNA_CTRL: 302 case RT1015_MONO_DYNA_CTRL1: 303 case RT1015_MONO_DYNA_CTRL2: 304 case RT1015_MONO_DYNA_CTRL3: 305 case RT1015_MONO_DYNA_CTRL4: 306 case RT1015_MONO_DYNA_CTRL5: 307 case RT1015_SPK_VOL: 308 case RT1015_SHORT_DETTOP1: 309 case RT1015_SHORT_DETTOP2: 310 case RT1015_SPK_DC_DETECT1: 311 case RT1015_SPK_DC_DETECT2: 312 case RT1015_SPK_DC_DETECT3: 313 case RT1015_SPK_DC_DETECT4: 314 case RT1015_SPK_DC_DETECT5: 315 case RT1015_BAT_RPO_STEP1: 316 case RT1015_BAT_RPO_STEP2: 317 case RT1015_BAT_RPO_STEP3: 318 case RT1015_BAT_RPO_STEP4: 319 case RT1015_BAT_RPO_STEP5: 320 case RT1015_BAT_RPO_STEP6: 321 case RT1015_BAT_RPO_STEP7: 322 case RT1015_BAT_RPO_STEP8: 323 case RT1015_BAT_RPO_STEP9: 324 case RT1015_BAT_RPO_STEP10: 325 case RT1015_BAT_RPO_STEP11: 326 case RT1015_BAT_RPO_STEP12: 327 case RT1015_SPREAD_SPEC1: 328 case RT1015_SPREAD_SPEC2: 329 case RT1015_PAD_STATUS: 330 case RT1015_PADS_PULLING_CTRL1: 331 case RT1015_PADS_DRIVING: 332 case RT1015_SYS_RST1: 333 case RT1015_SYS_RST2: 334 case RT1015_SYS_GATING1: 335 case RT1015_TEST_MODE1: 336 case RT1015_TEST_MODE2: 337 case RT1015_TIMING_CTRL1: 338 case RT1015_PLL_INT: 339 case RT1015_TEST_OUT1: 340 case RT1015_DC_CALIB_CLSD1: 341 case RT1015_DC_CALIB_CLSD2: 342 case RT1015_DC_CALIB_CLSD3: 343 case RT1015_DC_CALIB_CLSD4: 344 case RT1015_DC_CALIB_CLSD5: 345 case RT1015_DC_CALIB_CLSD6: 346 case RT1015_DC_CALIB_CLSD7: 347 case RT1015_DC_CALIB_CLSD8: 348 case RT1015_DC_CALIB_CLSD9: 349 case RT1015_DC_CALIB_CLSD10: 350 case RT1015_CLSD_INTERNAL1: 351 case RT1015_CLSD_INTERNAL2: 352 case RT1015_CLSD_INTERNAL3: 353 case RT1015_CLSD_INTERNAL4: 354 case RT1015_CLSD_INTERNAL5: 355 case RT1015_CLSD_INTERNAL6: 356 case RT1015_CLSD_INTERNAL7: 357 case RT1015_CLSD_INTERNAL8: 358 case RT1015_CLSD_INTERNAL9: 359 case RT1015_CLSD_OCP_CTRL: 360 case RT1015_VREF_LV: 361 case RT1015_MBIAS1: 362 case RT1015_MBIAS2: 363 case RT1015_MBIAS3: 364 case RT1015_MBIAS4: 365 case RT1015_VREF_LV1: 366 case RT1015_S_BST_TIMING_INTER1: 367 case RT1015_S_BST_TIMING_INTER2: 368 case RT1015_S_BST_TIMING_INTER3: 369 case RT1015_S_BST_TIMING_INTER4: 370 case RT1015_S_BST_TIMING_INTER5: 371 case RT1015_S_BST_TIMING_INTER6: 372 case RT1015_S_BST_TIMING_INTER7: 373 case RT1015_S_BST_TIMING_INTER8: 374 case RT1015_S_BST_TIMING_INTER9: 375 case RT1015_S_BST_TIMING_INTER10: 376 case RT1015_S_BST_TIMING_INTER11: 377 case RT1015_S_BST_TIMING_INTER12: 378 case RT1015_S_BST_TIMING_INTER13: 379 case RT1015_S_BST_TIMING_INTER14: 380 case RT1015_S_BST_TIMING_INTER15: 381 case RT1015_S_BST_TIMING_INTER16: 382 case RT1015_S_BST_TIMING_INTER17: 383 case RT1015_S_BST_TIMING_INTER18: 384 case RT1015_S_BST_TIMING_INTER19: 385 case RT1015_S_BST_TIMING_INTER20: 386 case RT1015_S_BST_TIMING_INTER21: 387 case RT1015_S_BST_TIMING_INTER22: 388 case RT1015_S_BST_TIMING_INTER23: 389 case RT1015_S_BST_TIMING_INTER24: 390 case RT1015_S_BST_TIMING_INTER25: 391 case RT1015_S_BST_TIMING_INTER26: 392 case RT1015_S_BST_TIMING_INTER27: 393 case RT1015_S_BST_TIMING_INTER28: 394 case RT1015_S_BST_TIMING_INTER29: 395 case RT1015_S_BST_TIMING_INTER30: 396 case RT1015_S_BST_TIMING_INTER31: 397 case RT1015_S_BST_TIMING_INTER32: 398 case RT1015_S_BST_TIMING_INTER33: 399 case RT1015_S_BST_TIMING_INTER34: 400 case RT1015_S_BST_TIMING_INTER35: 401 case RT1015_S_BST_TIMING_INTER36: 402 return true; 403 404 default: 405 return false; 406 } 407 } 408 409 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 410 411 static const char * const rt1015_din_source_select[] = { 412 "Left", 413 "Right", 414 "Left + Right average", 415 }; 416 417 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4, 418 rt1015_din_source_select); 419 420 static const char * const rt1015_boost_mode[] = { 421 "Bypass", "Adaptive", "Fixed Adaptive" 422 }; 423 424 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0, 425 rt1015_boost_mode); 426 427 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol, 428 struct snd_ctl_elem_value *ucontrol) 429 { 430 struct snd_soc_component *component = 431 snd_soc_kcontrol_component(kcontrol); 432 struct rt1015_priv *rt1015 = 433 snd_soc_component_get_drvdata(component); 434 435 ucontrol->value.integer.value[0] = rt1015->boost_mode; 436 437 return 0; 438 } 439 440 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol, 441 struct snd_ctl_elem_value *ucontrol) 442 { 443 struct snd_soc_component *component = 444 snd_soc_kcontrol_component(kcontrol); 445 struct rt1015_priv *rt1015 = 446 snd_soc_component_get_drvdata(component); 447 448 rt1015->boost_mode = ucontrol->value.integer.value[0]; 449 450 switch (rt1015->boost_mode) { 451 case BYPASS: 452 snd_soc_component_update_bits(component, 453 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 454 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 455 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS | 456 RT1015_BYPASS_SWRREG_BYPASS); 457 break; 458 case ADAPTIVE: 459 snd_soc_component_update_bits(component, 460 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 461 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 462 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS | 463 RT1015_BYPASS_SWRREG_PASS); 464 break; 465 case FIXED_ADAPTIVE: 466 snd_soc_component_update_bits(component, 467 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 468 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 469 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN | 470 RT1015_BYPASS_SWRREG_PASS); 471 break; 472 default: 473 dev_err(component->dev, "Unknown boost control.\n"); 474 } 475 476 return 0; 477 } 478 479 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol, 480 struct snd_ctl_elem_value *ucontrol) 481 { 482 struct snd_soc_component *component = 483 snd_soc_kcontrol_component(kcontrol); 484 struct rt1015_priv *rt1015 = 485 snd_soc_component_get_drvdata(component); 486 487 ucontrol->value.integer.value[0] = rt1015->bypass_boost; 488 489 return 0; 490 } 491 492 static void rt1015_calibrate(struct rt1015_priv *rt1015) 493 { 494 struct snd_soc_component *component = rt1015->component; 495 struct regmap *regmap = rt1015->regmap; 496 497 snd_soc_dapm_mutex_lock(&component->dapm); 498 regcache_cache_bypass(regmap, true); 499 500 regmap_write(regmap, RT1015_PWR1, 0xd7df); 501 regmap_write(regmap, RT1015_PWR4, 0x00b2); 502 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2008); 503 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140); 504 regmap_write(regmap, RT1015_GAT_BOOST, 0x0efe); 505 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000d); 506 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000e); 507 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a00); 508 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a01); 509 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a05); 510 msleep(500); 511 regmap_write(regmap, RT1015_PWR1, 0x0); 512 513 regcache_cache_bypass(regmap, false); 514 regcache_mark_dirty(regmap); 515 regcache_sync(regmap); 516 snd_soc_dapm_mutex_unlock(&component->dapm); 517 } 518 519 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol, 520 struct snd_ctl_elem_value *ucontrol) 521 { 522 struct snd_soc_component *component = 523 snd_soc_kcontrol_component(kcontrol); 524 struct rt1015_priv *rt1015 = 525 snd_soc_component_get_drvdata(component); 526 527 if (!rt1015->dac_is_used) { 528 rt1015->bypass_boost = ucontrol->value.integer.value[0]; 529 if (rt1015->bypass_boost == RT1015_Bypass_Boost && 530 !rt1015->cali_done) { 531 rt1015_calibrate(rt1015); 532 rt1015->cali_done = 1; 533 534 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010); 535 } 536 } else 537 dev_err(component->dev, "DAC is being used!\n"); 538 539 return 0; 540 } 541 542 static void rt1015_flush_work(struct work_struct *work) 543 { 544 struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv, 545 flush_work.work); 546 struct snd_soc_component *component = rt1015->component; 547 unsigned int val, i = 0, count = 200; 548 549 while (i < count) { 550 usleep_range(1000, 1500); 551 dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i); 552 regmap_read(rt1015->regmap, RT1015_CLK_DET, &val); 553 if (val & 0x800) 554 break; 555 i++; 556 } 557 558 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597); 559 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7); 560 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028); 561 562 if (val & 0x800) 563 dev_dbg(component->dev, "Flush DAC completed.\n"); 564 else 565 dev_warn(component->dev, "Fail to flush DAC data.\n"); 566 } 567 568 static const struct snd_kcontrol_new rt1015_snd_controls[] = { 569 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT, 570 127, 0, dac_vol_tlv), 571 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3, 572 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1), 573 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum, 574 rt1015_boost_mode_get, rt1015_boost_mode_put), 575 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel), 576 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0, 577 rt1015_bypass_boost_get, rt1015_bypass_boost_put), 578 }; 579 580 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 581 struct snd_soc_dapm_widget *sink) 582 { 583 struct snd_soc_component *component = 584 snd_soc_dapm_to_component(source->dapm); 585 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 586 587 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL) 588 return 1; 589 else 590 return 0; 591 } 592 593 static int r1015_dac_event(struct snd_soc_dapm_widget *w, 594 struct snd_kcontrol *kcontrol, int event) 595 { 596 struct snd_soc_component *component = 597 snd_soc_dapm_to_component(w->dapm); 598 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 599 600 switch (event) { 601 case SND_SOC_DAPM_PRE_PMU: 602 rt1015->dac_is_used = 1; 603 if (rt1015->bypass_boost == RT1015_Enable_Boost) { 604 snd_soc_component_write(component, 605 RT1015_SYS_RST1, 0x05f7); 606 snd_soc_component_write(component, 607 RT1015_GAT_BOOST, 0xacfe); 608 snd_soc_component_write(component, 609 RT1015_PWR9, 0xaa00); 610 snd_soc_component_write(component, 611 RT1015_GAT_BOOST, 0xecfe); 612 } else { 613 snd_soc_component_write(component, 614 RT1015_SYS_RST1, 0x05f7); 615 snd_soc_component_write(component, 616 RT1015_PWR_STATE_CTRL, 0x026e); 617 } 618 break; 619 620 case SND_SOC_DAPM_POST_PMU: 621 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8); 622 break; 623 624 case SND_SOC_DAPM_POST_PMD: 625 if (rt1015->bypass_boost == RT1015_Enable_Boost) { 626 snd_soc_component_write(component, 627 RT1015_PWR9, 0xa800); 628 snd_soc_component_write(component, 629 RT1015_SYS_RST1, 0x05f5); 630 } else { 631 snd_soc_component_write(component, 632 RT1015_PWR_STATE_CTRL, 0x0268); 633 snd_soc_component_write(component, 634 RT1015_SYS_RST1, 0x05f5); 635 } 636 rt1015->dac_is_used = 0; 637 638 cancel_delayed_work_sync(&rt1015->flush_work); 639 break; 640 641 default: 642 break; 643 } 644 return 0; 645 } 646 647 static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w, 648 struct snd_kcontrol *kcontrol, int event) 649 { 650 struct snd_soc_component *component = 651 snd_soc_dapm_to_component(w->dapm); 652 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 653 654 switch (event) { 655 case SND_SOC_DAPM_POST_PMU: 656 if (rt1015->hw_config == RT1015_HW_28) 657 schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10)); 658 msleep(rt1015->pdata.power_up_delay_ms); 659 break; 660 default: 661 break; 662 } 663 return 0; 664 } 665 666 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = { 667 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0, 668 NULL, 0), 669 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT, 670 0, NULL, 0), 671 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0, 672 NULL, 0), 673 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0, 674 NULL, 0), 675 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0, 676 NULL, 0), 677 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0, 678 NULL, 0), 679 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0, 680 NULL, 0), 681 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL, 682 0), 683 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0, 684 NULL, 0), 685 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL, 686 0), 687 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0, 688 NULL, 0), 689 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL, 690 0), 691 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0, 692 NULL, 0), 693 694 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 695 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0, 696 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 697 SND_SOC_DAPM_POST_PMD), 698 699 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0, 700 rt1015_amp_drv_event, SND_SOC_DAPM_POST_PMU), 701 SND_SOC_DAPM_OUTPUT("SPO"), 702 }; 703 704 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = { 705 { "DAC", NULL, "AIFRX" }, 706 { "DAC", NULL, "LDO2" }, 707 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll}, 708 { "DAC", NULL, "INT RC CLK" }, 709 { "DAC", NULL, "ISENSE" }, 710 { "DAC", NULL, "VSENSE" }, 711 { "DAC", NULL, "BG1 BG2" }, 712 { "DAC", NULL, "MBIAS BG" }, 713 { "DAC", NULL, "VBAT" }, 714 { "DAC", NULL, "MBIAS" }, 715 { "DAC", NULL, "ADCV" }, 716 { "DAC", NULL, "MIXERV" }, 717 { "DAC", NULL, "SUMV" }, 718 { "DAC", NULL, "VREFLV" }, 719 { "Amp Drv", NULL, "DAC" }, 720 { "SPO", NULL, "Amp Drv" }, 721 }; 722 723 static int rt1015_hw_params(struct snd_pcm_substream *substream, 724 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 725 { 726 struct snd_soc_component *component = dai->component; 727 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 728 int pre_div, bclk_ms, frame_size; 729 unsigned int val_len = 0; 730 731 rt1015->lrck = params_rate(params); 732 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck); 733 if (pre_div < 0) { 734 dev_err(component->dev, "Unsupported clock rate\n"); 735 return -EINVAL; 736 } 737 738 frame_size = snd_soc_params_to_frame_size(params); 739 if (frame_size < 0) { 740 dev_err(component->dev, "Unsupported frame size: %d\n", 741 frame_size); 742 return -EINVAL; 743 } 744 745 bclk_ms = frame_size > 32; 746 rt1015->bclk = rt1015->lrck * (32 << bclk_ms); 747 748 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 749 bclk_ms, pre_div, dai->id); 750 751 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 752 rt1015->lrck, pre_div, dai->id); 753 754 switch (params_width(params)) { 755 case 16: 756 break; 757 case 20: 758 val_len = RT1015_I2S_DL_20; 759 break; 760 case 24: 761 val_len = RT1015_I2S_DL_24; 762 break; 763 case 8: 764 val_len = RT1015_I2S_DL_8; 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 771 RT1015_I2S_DL_MASK, val_len); 772 snd_soc_component_update_bits(component, RT1015_CLK2, 773 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT); 774 775 return 0; 776 } 777 778 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 779 { 780 struct snd_soc_component *component = dai->component; 781 unsigned int reg_val = 0, reg_val2 = 0; 782 783 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 784 case SND_SOC_DAIFMT_CBM_CFM: 785 reg_val |= RT1015_TCON_TDM_MS_M; 786 break; 787 case SND_SOC_DAIFMT_CBS_CFS: 788 reg_val |= RT1015_TCON_TDM_MS_S; 789 break; 790 default: 791 return -EINVAL; 792 } 793 794 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 795 case SND_SOC_DAIFMT_NB_NF: 796 break; 797 case SND_SOC_DAIFMT_IB_NF: 798 reg_val2 |= RT1015_TDM_INV_BCLK; 799 break; 800 default: 801 return -EINVAL; 802 } 803 804 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 805 case SND_SOC_DAIFMT_I2S: 806 break; 807 808 case SND_SOC_DAIFMT_LEFT_J: 809 reg_val |= RT1015_I2S_M_DF_LEFT; 810 break; 811 812 case SND_SOC_DAIFMT_DSP_A: 813 reg_val |= RT1015_I2S_M_DF_PCM_A; 814 break; 815 816 case SND_SOC_DAIFMT_DSP_B: 817 reg_val |= RT1015_I2S_M_DF_PCM_B; 818 break; 819 820 default: 821 return -EINVAL; 822 } 823 824 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 825 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK, 826 reg_val); 827 snd_soc_component_update_bits(component, RT1015_TDM1_1, 828 RT1015_TDM_INV_BCLK_MASK, reg_val2); 829 830 return 0; 831 } 832 833 static int rt1015_set_component_sysclk(struct snd_soc_component *component, 834 int clk_id, int source, unsigned int freq, int dir) 835 { 836 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 837 unsigned int reg_val = 0; 838 839 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src) 840 return 0; 841 842 switch (clk_id) { 843 case RT1015_SCLK_S_MCLK: 844 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK; 845 break; 846 847 case RT1015_SCLK_S_PLL: 848 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL; 849 break; 850 851 default: 852 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 853 return -EINVAL; 854 } 855 856 rt1015->sysclk = freq; 857 rt1015->sysclk_src = clk_id; 858 859 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 860 freq, clk_id); 861 862 snd_soc_component_update_bits(component, RT1015_CLK2, 863 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val); 864 865 return 0; 866 } 867 868 static int rt1015_set_component_pll(struct snd_soc_component *component, 869 int pll_id, int source, unsigned int freq_in, 870 unsigned int freq_out) 871 { 872 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 873 struct rl6231_pll_code pll_code; 874 int ret; 875 876 if (!freq_in || !freq_out) { 877 dev_dbg(component->dev, "PLL disabled\n"); 878 879 rt1015->pll_in = 0; 880 rt1015->pll_out = 0; 881 882 return 0; 883 } 884 885 if (source == rt1015->pll_src && freq_in == rt1015->pll_in && 886 freq_out == rt1015->pll_out) 887 return 0; 888 889 if (source == RT1015_PLL_S_BCLK) { 890 if (rt1015->bclk_ratio == 0) { 891 dev_err(component->dev, 892 "Can not support bclk ratio as 0.\n"); 893 return -EINVAL; 894 } 895 } 896 897 switch (source) { 898 case RT1015_PLL_S_MCLK: 899 snd_soc_component_update_bits(component, RT1015_CLK2, 900 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2); 901 break; 902 903 case RT1015_PLL_S_BCLK: 904 snd_soc_component_update_bits(component, RT1015_CLK2, 905 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK); 906 break; 907 908 default: 909 dev_err(component->dev, "Unknown PLL Source %d\n", source); 910 return -EINVAL; 911 } 912 913 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 914 if (ret < 0) { 915 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 916 return ret; 917 } 918 919 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 920 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 921 pll_code.n_code, pll_code.k_code); 922 923 snd_soc_component_write(component, RT1015_PLL1, 924 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT | 925 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code); 926 snd_soc_component_write(component, RT1015_PLL2, 927 pll_code.k_code); 928 929 rt1015->pll_in = freq_in; 930 rt1015->pll_out = freq_out; 931 rt1015->pll_src = source; 932 933 return 0; 934 } 935 936 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 937 { 938 struct snd_soc_component *component = dai->component; 939 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 940 941 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 942 943 rt1015->bclk_ratio = ratio; 944 945 if (ratio == 50) { 946 dev_dbg(component->dev, "Unsupport bclk ratio\n"); 947 return -EINVAL; 948 } 949 950 return 0; 951 } 952 953 static int rt1015_probe(struct snd_soc_component *component) 954 { 955 struct rt1015_priv *rt1015 = 956 snd_soc_component_get_drvdata(component); 957 958 rt1015->component = component; 959 rt1015->bclk_ratio = 0; 960 rt1015->cali_done = 0; 961 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c); 962 963 INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work); 964 965 return 0; 966 } 967 968 static void rt1015_remove(struct snd_soc_component *component) 969 { 970 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 971 972 cancel_delayed_work_sync(&rt1015->flush_work); 973 regmap_write(rt1015->regmap, RT1015_RESET, 0); 974 } 975 976 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000 977 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 978 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 979 980 static struct snd_soc_dai_ops rt1015_aif_dai_ops = { 981 .hw_params = rt1015_hw_params, 982 .set_fmt = rt1015_set_dai_fmt, 983 .set_bclk_ratio = rt1015_set_bclk_ratio, 984 }; 985 986 static struct snd_soc_dai_driver rt1015_dai[] = { 987 { 988 .name = "rt1015-aif", 989 .id = 0, 990 .playback = { 991 .stream_name = "AIF Playback", 992 .channels_min = 1, 993 .channels_max = 4, 994 .rates = RT1015_STEREO_RATES, 995 .formats = RT1015_FORMATS, 996 }, 997 .ops = &rt1015_aif_dai_ops, 998 } 999 }; 1000 1001 #ifdef CONFIG_PM 1002 static int rt1015_suspend(struct snd_soc_component *component) 1003 { 1004 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 1005 1006 regcache_cache_only(rt1015->regmap, true); 1007 regcache_mark_dirty(rt1015->regmap); 1008 1009 return 0; 1010 } 1011 1012 static int rt1015_resume(struct snd_soc_component *component) 1013 { 1014 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 1015 1016 regcache_cache_only(rt1015->regmap, false); 1017 regcache_sync(rt1015->regmap); 1018 return 0; 1019 } 1020 #else 1021 #define rt1015_suspend NULL 1022 #define rt1015_resume NULL 1023 #endif 1024 1025 static const struct snd_soc_component_driver soc_component_dev_rt1015 = { 1026 .probe = rt1015_probe, 1027 .remove = rt1015_remove, 1028 .suspend = rt1015_suspend, 1029 .resume = rt1015_resume, 1030 .controls = rt1015_snd_controls, 1031 .num_controls = ARRAY_SIZE(rt1015_snd_controls), 1032 .dapm_widgets = rt1015_dapm_widgets, 1033 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets), 1034 .dapm_routes = rt1015_dapm_routes, 1035 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes), 1036 .set_sysclk = rt1015_set_component_sysclk, 1037 .set_pll = rt1015_set_component_pll, 1038 .use_pmdown_time = 1, 1039 .endianness = 1, 1040 .non_legacy_dai_naming = 1, 1041 }; 1042 1043 static const struct regmap_config rt1015_regmap = { 1044 .reg_bits = 16, 1045 .val_bits = 16, 1046 .max_register = RT1015_S_BST_TIMING_INTER36, 1047 .volatile_reg = rt1015_volatile_register, 1048 .readable_reg = rt1015_readable_register, 1049 .cache_type = REGCACHE_RBTREE, 1050 .reg_defaults = rt1015_reg, 1051 .num_reg_defaults = ARRAY_SIZE(rt1015_reg), 1052 }; 1053 1054 static const struct i2c_device_id rt1015_i2c_id[] = { 1055 { "rt1015", 0 }, 1056 { } 1057 }; 1058 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id); 1059 1060 #if defined(CONFIG_OF) 1061 static const struct of_device_id rt1015_of_match[] = { 1062 { .compatible = "realtek,rt1015", }, 1063 {}, 1064 }; 1065 MODULE_DEVICE_TABLE(of, rt1015_of_match); 1066 #endif 1067 1068 #ifdef CONFIG_ACPI 1069 static struct acpi_device_id rt1015_acpi_match[] = { 1070 {"10EC1015", 0,}, 1071 {}, 1072 }; 1073 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match); 1074 #endif 1075 1076 static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev) 1077 { 1078 device_property_read_u32(dev, "realtek,power-up-delay-ms", 1079 &rt1015->pdata.power_up_delay_ms); 1080 } 1081 1082 static int rt1015_i2c_probe(struct i2c_client *i2c, 1083 const struct i2c_device_id *id) 1084 { 1085 struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev); 1086 struct rt1015_priv *rt1015; 1087 int ret; 1088 unsigned int val; 1089 1090 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv), 1091 GFP_KERNEL); 1092 if (rt1015 == NULL) 1093 return -ENOMEM; 1094 1095 i2c_set_clientdata(i2c, rt1015); 1096 1097 rt1015->pdata = i2s_default_platform_data; 1098 1099 if (pdata) 1100 rt1015->pdata = *pdata; 1101 else 1102 rt1015_parse_dt(rt1015, &i2c->dev); 1103 1104 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap); 1105 if (IS_ERR(rt1015->regmap)) { 1106 ret = PTR_ERR(rt1015->regmap); 1107 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1108 ret); 1109 return ret; 1110 } 1111 1112 rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28; 1113 1114 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val); 1115 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) { 1116 dev_err(&i2c->dev, 1117 "Device with ID register %x is not rt1015\n", val); 1118 return -ENODEV; 1119 } 1120 1121 return devm_snd_soc_register_component(&i2c->dev, 1122 &soc_component_dev_rt1015, 1123 rt1015_dai, ARRAY_SIZE(rt1015_dai)); 1124 } 1125 1126 static void rt1015_i2c_shutdown(struct i2c_client *client) 1127 { 1128 struct rt1015_priv *rt1015 = i2c_get_clientdata(client); 1129 1130 regmap_write(rt1015->regmap, RT1015_RESET, 0); 1131 } 1132 1133 static struct i2c_driver rt1015_i2c_driver = { 1134 .driver = { 1135 .name = "rt1015", 1136 .of_match_table = of_match_ptr(rt1015_of_match), 1137 .acpi_match_table = ACPI_PTR(rt1015_acpi_match), 1138 }, 1139 .probe = rt1015_i2c_probe, 1140 .shutdown = rt1015_i2c_shutdown, 1141 .id_table = rt1015_i2c_id, 1142 }; 1143 module_i2c_driver(rt1015_i2c_driver); 1144 1145 MODULE_DESCRIPTION("ASoC RT1015 driver"); 1146 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1147 MODULE_LICENSE("GPL v2"); 1148