1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver 4 // 5 // Copyright 2019 Realtek Semiconductor Corp. 6 // 7 // Author: Jack Yu <jack.yu@realtek.com> 8 // 9 // 10 11 #include <linux/fs.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/regmap.h> 18 #include <linux/i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/gpio.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt1015.h" 32 33 static const struct reg_default rt1015_reg[] = { 34 { 0x0000, 0x0000 }, 35 { 0x0004, 0xa000 }, 36 { 0x0006, 0x0003 }, 37 { 0x000a, 0x081e }, 38 { 0x000c, 0x0006 }, 39 { 0x000e, 0x0000 }, 40 { 0x0010, 0x0000 }, 41 { 0x0012, 0x0000 }, 42 { 0x0014, 0x0000 }, 43 { 0x0016, 0x0000 }, 44 { 0x0018, 0x0000 }, 45 { 0x0020, 0x8000 }, 46 { 0x0022, 0x8043 }, 47 { 0x0076, 0x0000 }, 48 { 0x0078, 0x0000 }, 49 { 0x007a, 0x0002 }, 50 { 0x007c, 0x10ec }, 51 { 0x007d, 0x1015 }, 52 { 0x00f0, 0x5000 }, 53 { 0x00f2, 0x004c }, 54 { 0x00f3, 0xecfe }, 55 { 0x00f4, 0x0000 }, 56 { 0x00f6, 0x0400 }, 57 { 0x0100, 0x0028 }, 58 { 0x0102, 0xff02 }, 59 { 0x0104, 0xa213 }, 60 { 0x0106, 0x200c }, 61 { 0x010c, 0x0000 }, 62 { 0x010e, 0x0058 }, 63 { 0x0111, 0x0200 }, 64 { 0x0112, 0x0400 }, 65 { 0x0114, 0x0022 }, 66 { 0x0116, 0x0000 }, 67 { 0x0118, 0x0000 }, 68 { 0x011a, 0x0123 }, 69 { 0x011c, 0x4567 }, 70 { 0x0300, 0x203d }, 71 { 0x0302, 0x001e }, 72 { 0x0311, 0x0000 }, 73 { 0x0313, 0x6014 }, 74 { 0x0314, 0x00a2 }, 75 { 0x031a, 0x00a0 }, 76 { 0x031c, 0x001f }, 77 { 0x031d, 0xffff }, 78 { 0x031e, 0x0000 }, 79 { 0x031f, 0x0000 }, 80 { 0x0320, 0x0000 }, 81 { 0x0321, 0x0000 }, 82 { 0x0322, 0xd7df }, 83 { 0x0328, 0x10b2 }, 84 { 0x0329, 0x0175 }, 85 { 0x032a, 0x36ad }, 86 { 0x032b, 0x7e55 }, 87 { 0x032c, 0x0520 }, 88 { 0x032d, 0xaa00 }, 89 { 0x032e, 0x570e }, 90 { 0x0330, 0xe180 }, 91 { 0x0332, 0x0034 }, 92 { 0x0334, 0x0001 }, 93 { 0x0336, 0x0010 }, 94 { 0x0338, 0x0000 }, 95 { 0x04fa, 0x0030 }, 96 { 0x04fc, 0x35c8 }, 97 { 0x04fe, 0x0800 }, 98 { 0x0500, 0x0400 }, 99 { 0x0502, 0x1000 }, 100 { 0x0504, 0x0000 }, 101 { 0x0506, 0x04ff }, 102 { 0x0508, 0x0010 }, 103 { 0x050a, 0x001a }, 104 { 0x0519, 0x1c68 }, 105 { 0x051a, 0x0ccc }, 106 { 0x051b, 0x0666 }, 107 { 0x051d, 0x0000 }, 108 { 0x051f, 0x0000 }, 109 { 0x0536, 0x061c }, 110 { 0x0538, 0x0000 }, 111 { 0x053a, 0x0000 }, 112 { 0x053c, 0x0000 }, 113 { 0x053d, 0x0000 }, 114 { 0x053e, 0x0000 }, 115 { 0x053f, 0x0000 }, 116 { 0x0540, 0x0000 }, 117 { 0x0541, 0x0000 }, 118 { 0x0542, 0x0000 }, 119 { 0x0543, 0x0000 }, 120 { 0x0544, 0x0000 }, 121 { 0x0568, 0x0000 }, 122 { 0x056a, 0x0000 }, 123 { 0x1000, 0x0040 }, 124 { 0x1002, 0x5405 }, 125 { 0x1006, 0x5515 }, 126 { 0x1007, 0x05f7 }, 127 { 0x1009, 0x0b0a }, 128 { 0x100a, 0x00ef }, 129 { 0x100d, 0x0003 }, 130 { 0x1010, 0xa433 }, 131 { 0x1020, 0x0000 }, 132 { 0x1200, 0x5a01 }, 133 { 0x1202, 0x6524 }, 134 { 0x1204, 0x1f00 }, 135 { 0x1206, 0x0000 }, 136 { 0x1208, 0x0000 }, 137 { 0x120a, 0x0000 }, 138 { 0x120c, 0x0000 }, 139 { 0x120e, 0x0000 }, 140 { 0x1210, 0x0000 }, 141 { 0x1212, 0x0000 }, 142 { 0x1300, 0x10a1 }, 143 { 0x1302, 0x12ff }, 144 { 0x1304, 0x0400 }, 145 { 0x1305, 0x0844 }, 146 { 0x1306, 0x4611 }, 147 { 0x1308, 0x555e }, 148 { 0x130a, 0x0000 }, 149 { 0x130c, 0x2000 }, 150 { 0x130e, 0x0100 }, 151 { 0x130f, 0x0001 }, 152 { 0x1310, 0x0000 }, 153 { 0x1312, 0x0000 }, 154 { 0x1314, 0x0000 }, 155 { 0x1316, 0x0000 }, 156 { 0x1318, 0x0000 }, 157 { 0x131a, 0x0000 }, 158 { 0x1322, 0x0029 }, 159 { 0x1323, 0x4a52 }, 160 { 0x1324, 0x002c }, 161 { 0x1325, 0x0b02 }, 162 { 0x1326, 0x002d }, 163 { 0x1327, 0x6b5a }, 164 { 0x1328, 0x002e }, 165 { 0x1329, 0xcbb2 }, 166 { 0x132a, 0x0030 }, 167 { 0x132b, 0x2c0b }, 168 { 0x1330, 0x0031 }, 169 { 0x1331, 0x8c63 }, 170 { 0x1332, 0x0032 }, 171 { 0x1333, 0xecbb }, 172 { 0x1334, 0x0034 }, 173 { 0x1335, 0x4d13 }, 174 { 0x1336, 0x0037 }, 175 { 0x1337, 0x0dc3 }, 176 { 0x1338, 0x003d }, 177 { 0x1339, 0xef7b }, 178 { 0x133a, 0x0044 }, 179 { 0x133b, 0xd134 }, 180 { 0x133c, 0x0047 }, 181 { 0x133d, 0x91e4 }, 182 { 0x133e, 0x004d }, 183 { 0x133f, 0xc370 }, 184 { 0x1340, 0x0053 }, 185 { 0x1341, 0xf4fd }, 186 { 0x1342, 0x0060 }, 187 { 0x1343, 0x5816 }, 188 { 0x1344, 0x006c }, 189 { 0x1345, 0xbb2e }, 190 { 0x1346, 0x0072 }, 191 { 0x1347, 0xecbb }, 192 { 0x1348, 0x0076 }, 193 { 0x1349, 0x5d97 }, 194 }; 195 196 static bool rt1015_volatile_register(struct device *dev, unsigned int reg) 197 { 198 switch (reg) { 199 case RT1015_RESET: 200 case RT1015_CLK_DET: 201 case RT1015_SIL_DET: 202 case RT1015_VER_ID: 203 case RT1015_VENDOR_ID: 204 case RT1015_DEVICE_ID: 205 case RT1015_PRO_ALT: 206 case RT1015_DAC3: 207 case RT1015_VBAT_TEST_OUT1: 208 case RT1015_VBAT_TEST_OUT2: 209 case RT1015_VBAT_PROT_ATT: 210 case RT1015_VBAT_DET_CODE: 211 case RT1015_SMART_BST_CTRL1: 212 case RT1015_SPK_DC_DETECT1: 213 case RT1015_SPK_DC_DETECT4: 214 case RT1015_SPK_DC_DETECT5: 215 case RT1015_DC_CALIB_CLSD1: 216 case RT1015_DC_CALIB_CLSD5: 217 case RT1015_DC_CALIB_CLSD6: 218 case RT1015_DC_CALIB_CLSD7: 219 case RT1015_DC_CALIB_CLSD8: 220 case RT1015_S_BST_TIMING_INTER1: 221 case RT1015_OSCK_STA: 222 case RT1015_MONO_DYNA_CTRL1: 223 case RT1015_MONO_DYNA_CTRL5: 224 return true; 225 226 default: 227 return false; 228 } 229 } 230 231 static bool rt1015_readable_register(struct device *dev, unsigned int reg) 232 { 233 switch (reg) { 234 case RT1015_RESET: 235 case RT1015_CLK2: 236 case RT1015_CLK3: 237 case RT1015_PLL1: 238 case RT1015_PLL2: 239 case RT1015_DUM_RW1: 240 case RT1015_DUM_RW2: 241 case RT1015_DUM_RW3: 242 case RT1015_DUM_RW4: 243 case RT1015_DUM_RW5: 244 case RT1015_DUM_RW6: 245 case RT1015_CLK_DET: 246 case RT1015_SIL_DET: 247 case RT1015_CUSTOMER_ID: 248 case RT1015_PCODE_FWVER: 249 case RT1015_VER_ID: 250 case RT1015_VENDOR_ID: 251 case RT1015_DEVICE_ID: 252 case RT1015_PAD_DRV1: 253 case RT1015_PAD_DRV2: 254 case RT1015_GAT_BOOST: 255 case RT1015_PRO_ALT: 256 case RT1015_OSCK_STA: 257 case RT1015_MAN_I2C: 258 case RT1015_DAC1: 259 case RT1015_DAC2: 260 case RT1015_DAC3: 261 case RT1015_ADC1: 262 case RT1015_ADC2: 263 case RT1015_TDM_MASTER: 264 case RT1015_TDM_TCON: 265 case RT1015_TDM1_1: 266 case RT1015_TDM1_2: 267 case RT1015_TDM1_3: 268 case RT1015_TDM1_4: 269 case RT1015_TDM1_5: 270 case RT1015_MIXER1: 271 case RT1015_MIXER2: 272 case RT1015_ANA_PROTECT1: 273 case RT1015_ANA_CTRL_SEQ1: 274 case RT1015_ANA_CTRL_SEQ2: 275 case RT1015_VBAT_DET_DEB: 276 case RT1015_VBAT_VOLT_DET1: 277 case RT1015_VBAT_VOLT_DET2: 278 case RT1015_VBAT_TEST_OUT1: 279 case RT1015_VBAT_TEST_OUT2: 280 case RT1015_VBAT_PROT_ATT: 281 case RT1015_VBAT_DET_CODE: 282 case RT1015_PWR1: 283 case RT1015_PWR4: 284 case RT1015_PWR5: 285 case RT1015_PWR6: 286 case RT1015_PWR7: 287 case RT1015_PWR8: 288 case RT1015_PWR9: 289 case RT1015_CLASSD_SEQ: 290 case RT1015_SMART_BST_CTRL1: 291 case RT1015_SMART_BST_CTRL2: 292 case RT1015_ANA_CTRL1: 293 case RT1015_ANA_CTRL2: 294 case RT1015_PWR_STATE_CTRL: 295 case RT1015_MONO_DYNA_CTRL: 296 case RT1015_MONO_DYNA_CTRL1: 297 case RT1015_MONO_DYNA_CTRL2: 298 case RT1015_MONO_DYNA_CTRL3: 299 case RT1015_MONO_DYNA_CTRL4: 300 case RT1015_MONO_DYNA_CTRL5: 301 case RT1015_SPK_VOL: 302 case RT1015_SHORT_DETTOP1: 303 case RT1015_SHORT_DETTOP2: 304 case RT1015_SPK_DC_DETECT1: 305 case RT1015_SPK_DC_DETECT2: 306 case RT1015_SPK_DC_DETECT3: 307 case RT1015_SPK_DC_DETECT4: 308 case RT1015_SPK_DC_DETECT5: 309 case RT1015_BAT_RPO_STEP1: 310 case RT1015_BAT_RPO_STEP2: 311 case RT1015_BAT_RPO_STEP3: 312 case RT1015_BAT_RPO_STEP4: 313 case RT1015_BAT_RPO_STEP5: 314 case RT1015_BAT_RPO_STEP6: 315 case RT1015_BAT_RPO_STEP7: 316 case RT1015_BAT_RPO_STEP8: 317 case RT1015_BAT_RPO_STEP9: 318 case RT1015_BAT_RPO_STEP10: 319 case RT1015_BAT_RPO_STEP11: 320 case RT1015_BAT_RPO_STEP12: 321 case RT1015_SPREAD_SPEC1: 322 case RT1015_SPREAD_SPEC2: 323 case RT1015_PAD_STATUS: 324 case RT1015_PADS_PULLING_CTRL1: 325 case RT1015_PADS_DRIVING: 326 case RT1015_SYS_RST1: 327 case RT1015_SYS_RST2: 328 case RT1015_SYS_GATING1: 329 case RT1015_TEST_MODE1: 330 case RT1015_TEST_MODE2: 331 case RT1015_TIMING_CTRL1: 332 case RT1015_PLL_INT: 333 case RT1015_TEST_OUT1: 334 case RT1015_DC_CALIB_CLSD1: 335 case RT1015_DC_CALIB_CLSD2: 336 case RT1015_DC_CALIB_CLSD3: 337 case RT1015_DC_CALIB_CLSD4: 338 case RT1015_DC_CALIB_CLSD5: 339 case RT1015_DC_CALIB_CLSD6: 340 case RT1015_DC_CALIB_CLSD7: 341 case RT1015_DC_CALIB_CLSD8: 342 case RT1015_DC_CALIB_CLSD9: 343 case RT1015_DC_CALIB_CLSD10: 344 case RT1015_CLSD_INTERNAL1: 345 case RT1015_CLSD_INTERNAL2: 346 case RT1015_CLSD_INTERNAL3: 347 case RT1015_CLSD_INTERNAL4: 348 case RT1015_CLSD_INTERNAL5: 349 case RT1015_CLSD_INTERNAL6: 350 case RT1015_CLSD_INTERNAL7: 351 case RT1015_CLSD_INTERNAL8: 352 case RT1015_CLSD_INTERNAL9: 353 case RT1015_CLSD_OCP_CTRL: 354 case RT1015_VREF_LV: 355 case RT1015_MBIAS1: 356 case RT1015_MBIAS2: 357 case RT1015_MBIAS3: 358 case RT1015_MBIAS4: 359 case RT1015_VREF_LV1: 360 case RT1015_S_BST_TIMING_INTER1: 361 case RT1015_S_BST_TIMING_INTER2: 362 case RT1015_S_BST_TIMING_INTER3: 363 case RT1015_S_BST_TIMING_INTER4: 364 case RT1015_S_BST_TIMING_INTER5: 365 case RT1015_S_BST_TIMING_INTER6: 366 case RT1015_S_BST_TIMING_INTER7: 367 case RT1015_S_BST_TIMING_INTER8: 368 case RT1015_S_BST_TIMING_INTER9: 369 case RT1015_S_BST_TIMING_INTER10: 370 case RT1015_S_BST_TIMING_INTER11: 371 case RT1015_S_BST_TIMING_INTER12: 372 case RT1015_S_BST_TIMING_INTER13: 373 case RT1015_S_BST_TIMING_INTER14: 374 case RT1015_S_BST_TIMING_INTER15: 375 case RT1015_S_BST_TIMING_INTER16: 376 case RT1015_S_BST_TIMING_INTER17: 377 case RT1015_S_BST_TIMING_INTER18: 378 case RT1015_S_BST_TIMING_INTER19: 379 case RT1015_S_BST_TIMING_INTER20: 380 case RT1015_S_BST_TIMING_INTER21: 381 case RT1015_S_BST_TIMING_INTER22: 382 case RT1015_S_BST_TIMING_INTER23: 383 case RT1015_S_BST_TIMING_INTER24: 384 case RT1015_S_BST_TIMING_INTER25: 385 case RT1015_S_BST_TIMING_INTER26: 386 case RT1015_S_BST_TIMING_INTER27: 387 case RT1015_S_BST_TIMING_INTER28: 388 case RT1015_S_BST_TIMING_INTER29: 389 case RT1015_S_BST_TIMING_INTER30: 390 case RT1015_S_BST_TIMING_INTER31: 391 case RT1015_S_BST_TIMING_INTER32: 392 case RT1015_S_BST_TIMING_INTER33: 393 case RT1015_S_BST_TIMING_INTER34: 394 case RT1015_S_BST_TIMING_INTER35: 395 case RT1015_S_BST_TIMING_INTER36: 396 return true; 397 398 default: 399 return false; 400 } 401 } 402 403 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 404 405 static const char * const rt1015_din_source_select[] = { 406 "Left", 407 "Right", 408 "Left + Right average", 409 }; 410 411 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4, 412 rt1015_din_source_select); 413 414 static const char * const rt1015_boost_mode[] = { 415 "Bypass", "Adaptive", "Fixed Adaptive" 416 }; 417 418 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0, 419 rt1015_boost_mode); 420 421 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol, 422 struct snd_ctl_elem_value *ucontrol) 423 { 424 struct snd_soc_component *component = 425 snd_soc_kcontrol_component(kcontrol); 426 struct rt1015_priv *rt1015 = 427 snd_soc_component_get_drvdata(component); 428 429 ucontrol->value.integer.value[0] = rt1015->boost_mode; 430 431 return 0; 432 } 433 434 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol, 435 struct snd_ctl_elem_value *ucontrol) 436 { 437 struct snd_soc_component *component = 438 snd_soc_kcontrol_component(kcontrol); 439 struct rt1015_priv *rt1015 = 440 snd_soc_component_get_drvdata(component); 441 442 rt1015->boost_mode = ucontrol->value.integer.value[0]; 443 444 switch (rt1015->boost_mode) { 445 case BYPASS: 446 snd_soc_component_update_bits(component, 447 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 448 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 449 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS | 450 RT1015_BYPASS_SWRREG_BYPASS); 451 break; 452 case ADAPTIVE: 453 snd_soc_component_update_bits(component, 454 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 455 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 456 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS | 457 RT1015_BYPASS_SWRREG_PASS); 458 break; 459 case FIXED_ADAPTIVE: 460 snd_soc_component_update_bits(component, 461 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 462 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 463 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN | 464 RT1015_BYPASS_SWRREG_PASS); 465 break; 466 default: 467 dev_err(component->dev, "Unknown boost control.\n"); 468 } 469 470 return 0; 471 } 472 473 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol, 474 struct snd_ctl_elem_value *ucontrol) 475 { 476 struct snd_soc_component *component = 477 snd_soc_kcontrol_component(kcontrol); 478 struct rt1015_priv *rt1015 = 479 snd_soc_component_get_drvdata(component); 480 481 ucontrol->value.integer.value[0] = rt1015->bypass_boost; 482 483 return 0; 484 } 485 486 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol, 487 struct snd_ctl_elem_value *ucontrol) 488 { 489 struct snd_soc_component *component = 490 snd_soc_kcontrol_component(kcontrol); 491 struct rt1015_priv *rt1015 = 492 snd_soc_component_get_drvdata(component); 493 494 if (!rt1015->dac_is_used) { 495 rt1015->bypass_boost = ucontrol->value.integer.value[0]; 496 if (rt1015->bypass_boost == 1) { 497 snd_soc_component_write(component, 498 RT1015_PWR4, 0x00b2); 499 snd_soc_component_write(component, 500 RT1015_CLSD_INTERNAL8, 0x2008); 501 snd_soc_component_write(component, 502 RT1015_CLSD_INTERNAL9, 0x0140); 503 snd_soc_component_write(component, 504 RT1015_GAT_BOOST, 0x0efe); 505 snd_soc_component_write(component, 506 RT1015_PWR_STATE_CTRL, 0x000d); 507 msleep(500); 508 snd_soc_component_write(component, 509 RT1015_PWR_STATE_CTRL, 0x000e); 510 } 511 } else 512 dev_err(component->dev, "DAC is being used!\n"); 513 514 return 0; 515 } 516 517 static const struct snd_kcontrol_new rt1015_snd_controls[] = { 518 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT, 519 127, 0, dac_vol_tlv), 520 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3, 521 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1), 522 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum, 523 rt1015_boost_mode_get, rt1015_boost_mode_put), 524 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel), 525 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0, 526 rt1015_bypass_boost_get, rt1015_bypass_boost_put), 527 }; 528 529 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 530 struct snd_soc_dapm_widget *sink) 531 { 532 struct snd_soc_component *component = 533 snd_soc_dapm_to_component(source->dapm); 534 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 535 536 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL) 537 return 1; 538 else 539 return 0; 540 } 541 542 static int r1015_dac_event(struct snd_soc_dapm_widget *w, 543 struct snd_kcontrol *kcontrol, int event) 544 { 545 struct snd_soc_component *component = 546 snd_soc_dapm_to_component(w->dapm); 547 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 548 549 switch (event) { 550 case SND_SOC_DAPM_PRE_PMU: 551 rt1015->dac_is_used = 1; 552 if (rt1015->bypass_boost == 0) { 553 snd_soc_component_write(component, 554 RT1015_SYS_RST1, 0x05f7); 555 snd_soc_component_write(component, 556 RT1015_GAT_BOOST, 0xacfe); 557 snd_soc_component_write(component, 558 RT1015_PWR9, 0xaa00); 559 snd_soc_component_write(component, 560 RT1015_GAT_BOOST, 0xecfe); 561 } else { 562 snd_soc_component_write(component, 563 RT1015_SYS_RST1, 0x05f7); 564 snd_soc_component_write(component, 565 RT1015_PWR_STATE_CTRL, 0x026e); 566 } 567 break; 568 569 case SND_SOC_DAPM_POST_PMD: 570 if (rt1015->bypass_boost == 0) { 571 snd_soc_component_write(component, 572 RT1015_PWR9, 0xa800); 573 snd_soc_component_write(component, 574 RT1015_SYS_RST1, 0x05f5); 575 } else { 576 snd_soc_component_write(component, 577 RT1015_PWR_STATE_CTRL, 0x0268); 578 snd_soc_component_write(component, 579 RT1015_SYS_RST1, 0x05f5); 580 } 581 rt1015->dac_is_used = 0; 582 break; 583 584 default: 585 break; 586 } 587 return 0; 588 } 589 590 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = { 591 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0, 592 NULL, 0), 593 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT, 594 0, NULL, 0), 595 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0, 596 NULL, 0), 597 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0, 598 NULL, 0), 599 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0, 600 NULL, 0), 601 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0, 602 NULL, 0), 603 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0, 604 NULL, 0), 605 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL, 606 0), 607 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0, 608 NULL, 0), 609 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL, 610 0), 611 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0, 612 NULL, 0), 613 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL, 614 0), 615 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0, 616 NULL, 0), 617 618 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 619 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0, 620 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 621 622 SND_SOC_DAPM_OUTPUT("SPO"), 623 }; 624 625 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = { 626 { "DAC", NULL, "AIFRX" }, 627 { "DAC", NULL, "LDO2" }, 628 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll}, 629 { "DAC", NULL, "INT RC CLK" }, 630 { "DAC", NULL, "ISENSE" }, 631 { "DAC", NULL, "VSENSE" }, 632 { "DAC", NULL, "BG1 BG2" }, 633 { "DAC", NULL, "MBIAS BG" }, 634 { "DAC", NULL, "VBAT" }, 635 { "DAC", NULL, "MBIAS" }, 636 { "DAC", NULL, "ADCV" }, 637 { "DAC", NULL, "MIXERV" }, 638 { "DAC", NULL, "SUMV" }, 639 { "DAC", NULL, "VREFLV" }, 640 { "SPO", NULL, "DAC" }, 641 }; 642 643 static int rt1015_hw_params(struct snd_pcm_substream *substream, 644 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 645 { 646 struct snd_soc_component *component = dai->component; 647 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 648 int pre_div, bclk_ms, frame_size; 649 unsigned int val_len = 0; 650 651 rt1015->lrck = params_rate(params); 652 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck); 653 if (pre_div < 0) { 654 dev_err(component->dev, "Unsupported clock rate\n"); 655 return -EINVAL; 656 } 657 658 frame_size = snd_soc_params_to_frame_size(params); 659 if (frame_size < 0) { 660 dev_err(component->dev, "Unsupported frame size: %d\n", 661 frame_size); 662 return -EINVAL; 663 } 664 665 bclk_ms = frame_size > 32; 666 rt1015->bclk = rt1015->lrck * (32 << bclk_ms); 667 668 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 669 bclk_ms, pre_div, dai->id); 670 671 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 672 rt1015->lrck, pre_div, dai->id); 673 674 switch (params_width(params)) { 675 case 16: 676 break; 677 case 20: 678 val_len = RT1015_I2S_DL_20; 679 break; 680 case 24: 681 val_len = RT1015_I2S_DL_24; 682 break; 683 case 8: 684 val_len = RT1015_I2S_DL_8; 685 break; 686 default: 687 return -EINVAL; 688 } 689 690 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 691 RT1015_I2S_DL_MASK, val_len); 692 snd_soc_component_update_bits(component, RT1015_CLK2, 693 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT); 694 695 return 0; 696 } 697 698 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 699 { 700 struct snd_soc_component *component = dai->component; 701 unsigned int reg_val = 0, reg_val2 = 0; 702 703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 704 case SND_SOC_DAIFMT_CBM_CFM: 705 reg_val |= RT1015_TCON_TDM_MS_M; 706 break; 707 case SND_SOC_DAIFMT_CBS_CFS: 708 reg_val |= RT1015_TCON_TDM_MS_S; 709 break; 710 default: 711 return -EINVAL; 712 } 713 714 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 715 case SND_SOC_DAIFMT_NB_NF: 716 break; 717 case SND_SOC_DAIFMT_IB_NF: 718 reg_val2 |= RT1015_TDM_INV_BCLK; 719 break; 720 default: 721 return -EINVAL; 722 } 723 724 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 725 case SND_SOC_DAIFMT_I2S: 726 break; 727 728 case SND_SOC_DAIFMT_LEFT_J: 729 reg_val |= RT1015_I2S_M_DF_LEFT; 730 break; 731 732 case SND_SOC_DAIFMT_DSP_A: 733 reg_val |= RT1015_I2S_M_DF_PCM_A; 734 break; 735 736 case SND_SOC_DAIFMT_DSP_B: 737 reg_val |= RT1015_I2S_M_DF_PCM_B; 738 break; 739 740 default: 741 return -EINVAL; 742 } 743 744 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 745 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK, 746 reg_val); 747 snd_soc_component_update_bits(component, RT1015_TDM1_1, 748 RT1015_TDM_INV_BCLK_MASK, reg_val2); 749 750 return 0; 751 } 752 753 static int rt1015_set_component_sysclk(struct snd_soc_component *component, 754 int clk_id, int source, unsigned int freq, int dir) 755 { 756 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 757 unsigned int reg_val = 0; 758 759 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src) 760 return 0; 761 762 switch (clk_id) { 763 case RT1015_SCLK_S_MCLK: 764 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK; 765 break; 766 767 case RT1015_SCLK_S_PLL: 768 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL; 769 break; 770 771 default: 772 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 773 return -EINVAL; 774 } 775 776 rt1015->sysclk = freq; 777 rt1015->sysclk_src = clk_id; 778 779 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 780 freq, clk_id); 781 782 snd_soc_component_update_bits(component, RT1015_CLK2, 783 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val); 784 785 return 0; 786 } 787 788 static int rt1015_set_component_pll(struct snd_soc_component *component, 789 int pll_id, int source, unsigned int freq_in, 790 unsigned int freq_out) 791 { 792 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 793 struct rl6231_pll_code pll_code; 794 int ret; 795 796 if (!freq_in || !freq_out) { 797 dev_dbg(component->dev, "PLL disabled\n"); 798 799 rt1015->pll_in = 0; 800 rt1015->pll_out = 0; 801 802 return 0; 803 } 804 805 if (source == rt1015->pll_src && freq_in == rt1015->pll_in && 806 freq_out == rt1015->pll_out) 807 return 0; 808 809 if (source == RT1015_PLL_S_BCLK) { 810 if (rt1015->bclk_ratio == 0) { 811 dev_err(component->dev, 812 "Can not support bclk ratio as 0.\n"); 813 return -EINVAL; 814 } 815 } 816 817 switch (source) { 818 case RT1015_PLL_S_MCLK: 819 snd_soc_component_update_bits(component, RT1015_CLK2, 820 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2); 821 break; 822 823 case RT1015_PLL_S_BCLK: 824 snd_soc_component_update_bits(component, RT1015_CLK2, 825 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK); 826 break; 827 828 default: 829 dev_err(component->dev, "Unknown PLL Source %d\n", source); 830 return -EINVAL; 831 } 832 833 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 834 if (ret < 0) { 835 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 836 return ret; 837 } 838 839 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 840 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 841 pll_code.n_code, pll_code.k_code); 842 843 snd_soc_component_write(component, RT1015_PLL1, 844 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT | 845 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code); 846 snd_soc_component_write(component, RT1015_PLL2, 847 pll_code.k_code); 848 849 rt1015->pll_in = freq_in; 850 rt1015->pll_out = freq_out; 851 rt1015->pll_src = source; 852 853 return 0; 854 } 855 856 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 857 { 858 struct snd_soc_component *component = dai->component; 859 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 860 861 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 862 863 rt1015->bclk_ratio = ratio; 864 865 if (ratio == 50) { 866 dev_dbg(component->dev, "Unsupport bclk ratio\n"); 867 return -EINVAL; 868 } 869 870 return 0; 871 } 872 873 static int rt1015_probe(struct snd_soc_component *component) 874 { 875 struct rt1015_priv *rt1015 = 876 snd_soc_component_get_drvdata(component); 877 878 rt1015->component = component; 879 rt1015->bclk_ratio = 0; 880 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c); 881 882 return 0; 883 } 884 885 static void rt1015_remove(struct snd_soc_component *component) 886 { 887 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 888 889 regmap_write(rt1015->regmap, RT1015_RESET, 0); 890 } 891 892 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000 893 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 894 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 895 896 static struct snd_soc_dai_ops rt1015_aif_dai_ops = { 897 .hw_params = rt1015_hw_params, 898 .set_fmt = rt1015_set_dai_fmt, 899 .set_bclk_ratio = rt1015_set_bclk_ratio, 900 }; 901 902 static struct snd_soc_dai_driver rt1015_dai[] = { 903 { 904 .name = "rt1015-aif", 905 .id = 0, 906 .playback = { 907 .stream_name = "AIF Playback", 908 .channels_min = 1, 909 .channels_max = 4, 910 .rates = RT1015_STEREO_RATES, 911 .formats = RT1015_FORMATS, 912 }, 913 .ops = &rt1015_aif_dai_ops, 914 } 915 }; 916 917 #ifdef CONFIG_PM 918 static int rt1015_suspend(struct snd_soc_component *component) 919 { 920 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 921 922 regcache_cache_only(rt1015->regmap, true); 923 regcache_mark_dirty(rt1015->regmap); 924 925 return 0; 926 } 927 928 static int rt1015_resume(struct snd_soc_component *component) 929 { 930 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 931 932 regcache_cache_only(rt1015->regmap, false); 933 regcache_sync(rt1015->regmap); 934 return 0; 935 } 936 #else 937 #define rt1015_suspend NULL 938 #define rt1015_resume NULL 939 #endif 940 941 static const struct snd_soc_component_driver soc_component_dev_rt1015 = { 942 .probe = rt1015_probe, 943 .remove = rt1015_remove, 944 .suspend = rt1015_suspend, 945 .resume = rt1015_resume, 946 .controls = rt1015_snd_controls, 947 .num_controls = ARRAY_SIZE(rt1015_snd_controls), 948 .dapm_widgets = rt1015_dapm_widgets, 949 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets), 950 .dapm_routes = rt1015_dapm_routes, 951 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes), 952 .set_sysclk = rt1015_set_component_sysclk, 953 .set_pll = rt1015_set_component_pll, 954 .use_pmdown_time = 1, 955 .endianness = 1, 956 .non_legacy_dai_naming = 1, 957 }; 958 959 static const struct regmap_config rt1015_regmap = { 960 .reg_bits = 16, 961 .val_bits = 16, 962 .max_register = RT1015_S_BST_TIMING_INTER36, 963 .volatile_reg = rt1015_volatile_register, 964 .readable_reg = rt1015_readable_register, 965 .cache_type = REGCACHE_RBTREE, 966 .reg_defaults = rt1015_reg, 967 .num_reg_defaults = ARRAY_SIZE(rt1015_reg), 968 }; 969 970 static const struct i2c_device_id rt1015_i2c_id[] = { 971 { "rt1015", 0 }, 972 { } 973 }; 974 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id); 975 976 #if defined(CONFIG_OF) 977 static const struct of_device_id rt1015_of_match[] = { 978 { .compatible = "realtek,rt1015", }, 979 {}, 980 }; 981 MODULE_DEVICE_TABLE(of, rt1015_of_match); 982 #endif 983 984 #ifdef CONFIG_ACPI 985 static struct acpi_device_id rt1015_acpi_match[] = { 986 {"10EC1015", 0,}, 987 {}, 988 }; 989 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match); 990 #endif 991 992 static int rt1015_i2c_probe(struct i2c_client *i2c, 993 const struct i2c_device_id *id) 994 { 995 struct rt1015_priv *rt1015; 996 int ret; 997 unsigned int val; 998 999 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv), 1000 GFP_KERNEL); 1001 if (rt1015 == NULL) 1002 return -ENOMEM; 1003 1004 i2c_set_clientdata(i2c, rt1015); 1005 1006 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap); 1007 if (IS_ERR(rt1015->regmap)) { 1008 ret = PTR_ERR(rt1015->regmap); 1009 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1010 ret); 1011 return ret; 1012 } 1013 1014 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val); 1015 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) { 1016 dev_err(&i2c->dev, 1017 "Device with ID register %x is not rt1015\n", val); 1018 return -ENODEV; 1019 } 1020 1021 return devm_snd_soc_register_component(&i2c->dev, 1022 &soc_component_dev_rt1015, 1023 rt1015_dai, ARRAY_SIZE(rt1015_dai)); 1024 } 1025 1026 static void rt1015_i2c_shutdown(struct i2c_client *client) 1027 { 1028 struct rt1015_priv *rt1015 = i2c_get_clientdata(client); 1029 1030 regmap_write(rt1015->regmap, RT1015_RESET, 0); 1031 } 1032 1033 static struct i2c_driver rt1015_i2c_driver = { 1034 .driver = { 1035 .name = "rt1015", 1036 .of_match_table = of_match_ptr(rt1015_of_match), 1037 .acpi_match_table = ACPI_PTR(rt1015_acpi_match), 1038 }, 1039 .probe = rt1015_i2c_probe, 1040 .shutdown = rt1015_i2c_shutdown, 1041 .id_table = rt1015_i2c_id, 1042 }; 1043 module_i2c_driver(rt1015_i2c_driver); 1044 1045 MODULE_DESCRIPTION("ASoC RT1015 driver"); 1046 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1047 MODULE_LICENSE("GPL v2"); 1048