1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver 4 // 5 // Copyright 2019 Realtek Semiconductor Corp. 6 // 7 // Author: Jack Yu <jack.yu@realtek.com> 8 // 9 // 10 11 #include <linux/fs.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/regmap.h> 18 #include <linux/i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/gpio.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt1015.h" 32 33 static const struct reg_default rt1015_reg[] = { 34 { 0x0000, 0x0000 }, 35 { 0x0004, 0xa000 }, 36 { 0x0006, 0x0003 }, 37 { 0x000a, 0x0802 }, 38 { 0x000c, 0x0020 }, 39 { 0x000e, 0x0000 }, 40 { 0x0010, 0x0000 }, 41 { 0x0012, 0x0000 }, 42 { 0x0020, 0x8000 }, 43 { 0x0022, 0x471b }, 44 { 0x006a, 0x0000 }, 45 { 0x006c, 0x4020 }, 46 { 0x0076, 0x0000 }, 47 { 0x0078, 0x0000 }, 48 { 0x007a, 0x0000 }, 49 { 0x007c, 0x10ec }, 50 { 0x007d, 0x1015 }, 51 { 0x00f0, 0x5000 }, 52 { 0x00f2, 0x0774 }, 53 { 0x00f3, 0x8400 }, 54 { 0x00f4, 0x0000 }, 55 { 0x0100, 0x0028 }, 56 { 0x0102, 0xff02 }, 57 { 0x0104, 0x8232 }, 58 { 0x0106, 0x200c }, 59 { 0x010c, 0x002f }, 60 { 0x010e, 0xc000 }, 61 { 0x0111, 0x0200 }, 62 { 0x0112, 0x0400 }, 63 { 0x0114, 0x0022 }, 64 { 0x0116, 0x0000 }, 65 { 0x0118, 0x0000 }, 66 { 0x011a, 0x0123 }, 67 { 0x011c, 0x4567 }, 68 { 0x0300, 0xdddd }, 69 { 0x0302, 0x0000 }, 70 { 0x0311, 0x9330 }, 71 { 0x0313, 0x0000 }, 72 { 0x0314, 0x0000 }, 73 { 0x031a, 0x00a0 }, 74 { 0x031c, 0x001f }, 75 { 0x031d, 0xffff }, 76 { 0x031e, 0x0000 }, 77 { 0x031f, 0x0000 }, 78 { 0x0321, 0x0000 }, 79 { 0x0322, 0x0000 }, 80 { 0x0328, 0x0000 }, 81 { 0x0329, 0x0000 }, 82 { 0x032a, 0x0000 }, 83 { 0x032b, 0x0000 }, 84 { 0x032c, 0x0000 }, 85 { 0x032d, 0x0000 }, 86 { 0x032e, 0x030e }, 87 { 0x0330, 0x0080 }, 88 { 0x0332, 0x0034 }, 89 { 0x0334, 0x0000 }, 90 { 0x0336, 0x0000 }, 91 { 0x0506, 0x04ff }, 92 { 0x0508, 0x0030 }, 93 { 0x050a, 0x0018 }, 94 { 0x0519, 0x307f }, 95 { 0x051a, 0xffff }, 96 { 0x051b, 0x4000 }, 97 { 0x051d, 0x0000 }, 98 { 0x051f, 0x0000 }, 99 { 0x0536, 0x1000 }, 100 { 0x0538, 0x0000 }, 101 { 0x053a, 0x0000 }, 102 { 0x053c, 0x0000 }, 103 { 0x053d, 0x0000 }, 104 { 0x053e, 0x0000 }, 105 { 0x053f, 0x0000 }, 106 { 0x0540, 0x0000 }, 107 { 0x0541, 0x0000 }, 108 { 0x0542, 0x0000 }, 109 { 0x0543, 0x0000 }, 110 { 0x0544, 0x0000 }, 111 { 0x0568, 0x0000 }, 112 { 0x056a, 0x0000 }, 113 { 0x1000, 0x0000 }, 114 { 0x1002, 0x6505 }, 115 { 0x1006, 0x5515 }, 116 { 0x1007, 0x003f }, 117 { 0x1009, 0x770f }, 118 { 0x100a, 0x01ff }, 119 { 0x100c, 0x0000 }, 120 { 0x100d, 0x0003 }, 121 { 0x1010, 0xa433 }, 122 { 0x1020, 0x0000 }, 123 { 0x1200, 0x3d02 }, 124 { 0x1202, 0x0813 }, 125 { 0x1204, 0x0211 }, 126 { 0x1206, 0x0000 }, 127 { 0x1208, 0x0000 }, 128 { 0x120a, 0x0000 }, 129 { 0x120c, 0x0000 }, 130 { 0x120e, 0x0000 }, 131 { 0x1210, 0x0000 }, 132 { 0x1212, 0x0000 }, 133 { 0x1300, 0x0701 }, 134 { 0x1302, 0x12f9 }, 135 { 0x1304, 0x3405 }, 136 { 0x1305, 0x0844 }, 137 { 0x1306, 0x1611 }, 138 { 0x1308, 0x555e }, 139 { 0x130a, 0x0000 }, 140 { 0x130c, 0x2400}, 141 { 0x130e, 0x7700 }, 142 { 0x130f, 0x0000 }, 143 { 0x1310, 0x0000 }, 144 { 0x1312, 0x0000 }, 145 { 0x1314, 0x0000 }, 146 { 0x1316, 0x0000 }, 147 { 0x1318, 0x0000 }, 148 { 0x131a, 0x0000 }, 149 { 0x1322, 0x0029 }, 150 { 0x1323, 0x4a52 }, 151 { 0x1324, 0x002c }, 152 { 0x1325, 0x0b02 }, 153 { 0x1326, 0x002d }, 154 { 0x1327, 0x6b5a }, 155 { 0x1328, 0x002e }, 156 { 0x1329, 0xcbb2 }, 157 { 0x132a, 0x0030 }, 158 { 0x132b, 0x2c0b }, 159 { 0x1330, 0x0031 }, 160 { 0x1331, 0x8c63 }, 161 { 0x1332, 0x0032 }, 162 { 0x1333, 0xecbb }, 163 { 0x1334, 0x0034 }, 164 { 0x1335, 0x4d13 }, 165 { 0x1336, 0x0037 }, 166 { 0x1337, 0x0dc3 }, 167 { 0x1338, 0x003d }, 168 { 0x1339, 0xef7b }, 169 { 0x133a, 0x0044 }, 170 { 0x133b, 0xd134 }, 171 { 0x133c, 0x0047 }, 172 { 0x133d, 0x91e4 }, 173 { 0x133e, 0x004d }, 174 { 0x133f, 0xc370 }, 175 { 0x1340, 0x0053 }, 176 { 0x1341, 0xf4fd }, 177 { 0x1342, 0x0060 }, 178 { 0x1343, 0x5816 }, 179 { 0x1344, 0x006c }, 180 { 0x1345, 0xbb2e }, 181 { 0x1346, 0x0072 }, 182 { 0x1347, 0xecbb }, 183 { 0x1348, 0x0076 }, 184 { 0x1349, 0x5d97 }, 185 }; 186 187 static bool rt1015_volatile_register(struct device *dev, unsigned int reg) 188 { 189 switch (reg) { 190 case RT1015_RESET: 191 case RT1015_CLK_DET: 192 case RT1015_SIL_DET: 193 case RT1015_VER_ID: 194 case RT1015_VENDOR_ID: 195 case RT1015_DEVICE_ID: 196 case RT1015_PRO_ALT: 197 case RT1015_DAC3: 198 case RT1015_VBAT_TEST_OUT1: 199 case RT1015_VBAT_TEST_OUT2: 200 case RT1015_VBAT_PROT_ATT: 201 case RT1015_VBAT_DET_CODE: 202 case RT1015_SMART_BST_CTRL1: 203 case RT1015_SPK_DC_DETECT1: 204 case RT1015_SPK_DC_DETECT4: 205 case RT1015_SPK_DC_DETECT5: 206 case RT1015_DC_CALIB_CLSD1: 207 case RT1015_DC_CALIB_CLSD5: 208 case RT1015_DC_CALIB_CLSD6: 209 case RT1015_DC_CALIB_CLSD7: 210 case RT1015_DC_CALIB_CLSD8: 211 case RT1015_S_BST_TIMING_INTER1: 212 return true; 213 214 default: 215 return false; 216 } 217 } 218 219 static bool rt1015_readable_register(struct device *dev, unsigned int reg) 220 { 221 switch (reg) { 222 case RT1015_RESET: 223 case RT1015_CLK2: 224 case RT1015_CLK3: 225 case RT1015_PLL1: 226 case RT1015_PLL2: 227 case RT1015_CLK_DET: 228 case RT1015_SIL_DET: 229 case RT1015_CUSTOMER_ID: 230 case RT1015_PCODE_FWVER: 231 case RT1015_VER_ID: 232 case RT1015_VENDOR_ID: 233 case RT1015_DEVICE_ID: 234 case RT1015_PAD_DRV1: 235 case RT1015_PAD_DRV2: 236 case RT1015_GAT_BOOST: 237 case RT1015_PRO_ALT: 238 case RT1015_MAN_I2C: 239 case RT1015_DAC1: 240 case RT1015_DAC2: 241 case RT1015_DAC3: 242 case RT1015_ADC1: 243 case RT1015_ADC2: 244 case RT1015_TDM_MASTER: 245 case RT1015_TDM_TCON: 246 case RT1015_TDM1_1: 247 case RT1015_TDM1_2: 248 case RT1015_TDM1_3: 249 case RT1015_TDM1_4: 250 case RT1015_TDM1_5: 251 case RT1015_MIXER1: 252 case RT1015_MIXER2: 253 case RT1015_ANA_PROTECT1: 254 case RT1015_ANA_CTRL_SEQ1: 255 case RT1015_ANA_CTRL_SEQ2: 256 case RT1015_VBAT_DET_DEB: 257 case RT1015_VBAT_VOLT_DET1: 258 case RT1015_VBAT_VOLT_DET2: 259 case RT1015_VBAT_TEST_OUT1: 260 case RT1015_VBAT_TEST_OUT2: 261 case RT1015_VBAT_PROT_ATT: 262 case RT1015_VBAT_DET_CODE: 263 case RT1015_PWR1: 264 case RT1015_PWR4: 265 case RT1015_PWR5: 266 case RT1015_PWR6: 267 case RT1015_PWR7: 268 case RT1015_PWR8: 269 case RT1015_PWR9: 270 case RT1015_CLASSD_SEQ: 271 case RT1015_SMART_BST_CTRL1: 272 case RT1015_SMART_BST_CTRL2: 273 case RT1015_ANA_CTRL1: 274 case RT1015_ANA_CTRL2: 275 case RT1015_SPK_VOL: 276 case RT1015_SHORT_DETTOP1: 277 case RT1015_SHORT_DETTOP2: 278 case RT1015_SPK_DC_DETECT1: 279 case RT1015_SPK_DC_DETECT2: 280 case RT1015_SPK_DC_DETECT3: 281 case RT1015_SPK_DC_DETECT4: 282 case RT1015_SPK_DC_DETECT5: 283 case RT1015_BAT_RPO_STEP1: 284 case RT1015_BAT_RPO_STEP2: 285 case RT1015_BAT_RPO_STEP3: 286 case RT1015_BAT_RPO_STEP4: 287 case RT1015_BAT_RPO_STEP5: 288 case RT1015_BAT_RPO_STEP6: 289 case RT1015_BAT_RPO_STEP7: 290 case RT1015_BAT_RPO_STEP8: 291 case RT1015_BAT_RPO_STEP9: 292 case RT1015_BAT_RPO_STEP10: 293 case RT1015_BAT_RPO_STEP11: 294 case RT1015_BAT_RPO_STEP12: 295 case RT1015_SPREAD_SPEC1: 296 case RT1015_SPREAD_SPEC2: 297 case RT1015_PAD_STATUS: 298 case RT1015_PADS_PULLING_CTRL1: 299 case RT1015_PADS_DRIVING: 300 case RT1015_SYS_RST1: 301 case RT1015_SYS_RST2: 302 case RT1015_SYS_GATING1: 303 case RT1015_TEST_MODE1: 304 case RT1015_TEST_MODE2: 305 case RT1015_TIMING_CTRL1: 306 case RT1015_PLL_INT: 307 case RT1015_TEST_OUT1: 308 case RT1015_DC_CALIB_CLSD1: 309 case RT1015_DC_CALIB_CLSD2: 310 case RT1015_DC_CALIB_CLSD3: 311 case RT1015_DC_CALIB_CLSD4: 312 case RT1015_DC_CALIB_CLSD5: 313 case RT1015_DC_CALIB_CLSD6: 314 case RT1015_DC_CALIB_CLSD7: 315 case RT1015_DC_CALIB_CLSD8: 316 case RT1015_DC_CALIB_CLSD9: 317 case RT1015_DC_CALIB_CLSD10: 318 case RT1015_CLSD_INTERNAL1: 319 case RT1015_CLSD_INTERNAL2: 320 case RT1015_CLSD_INTERNAL3: 321 case RT1015_CLSD_INTERNAL4: 322 case RT1015_CLSD_INTERNAL5: 323 case RT1015_CLSD_INTERNAL6: 324 case RT1015_CLSD_INTERNAL7: 325 case RT1015_CLSD_INTERNAL8: 326 case RT1015_CLSD_INTERNAL9: 327 case RT1015_CLSD_OCP_CTRL: 328 case RT1015_VREF_LV: 329 case RT1015_MBIAS1: 330 case RT1015_MBIAS2: 331 case RT1015_MBIAS3: 332 case RT1015_MBIAS4: 333 case RT1015_VREF_LV1: 334 case RT1015_S_BST_TIMING_INTER1: 335 case RT1015_S_BST_TIMING_INTER2: 336 case RT1015_S_BST_TIMING_INTER3: 337 case RT1015_S_BST_TIMING_INTER4: 338 case RT1015_S_BST_TIMING_INTER5: 339 case RT1015_S_BST_TIMING_INTER6: 340 case RT1015_S_BST_TIMING_INTER7: 341 case RT1015_S_BST_TIMING_INTER8: 342 case RT1015_S_BST_TIMING_INTER9: 343 case RT1015_S_BST_TIMING_INTER10: 344 case RT1015_S_BST_TIMING_INTER11: 345 case RT1015_S_BST_TIMING_INTER12: 346 case RT1015_S_BST_TIMING_INTER13: 347 case RT1015_S_BST_TIMING_INTER14: 348 case RT1015_S_BST_TIMING_INTER15: 349 case RT1015_S_BST_TIMING_INTER16: 350 case RT1015_S_BST_TIMING_INTER17: 351 case RT1015_S_BST_TIMING_INTER18: 352 case RT1015_S_BST_TIMING_INTER19: 353 case RT1015_S_BST_TIMING_INTER20: 354 case RT1015_S_BST_TIMING_INTER21: 355 case RT1015_S_BST_TIMING_INTER22: 356 case RT1015_S_BST_TIMING_INTER23: 357 case RT1015_S_BST_TIMING_INTER24: 358 case RT1015_S_BST_TIMING_INTER25: 359 case RT1015_S_BST_TIMING_INTER26: 360 case RT1015_S_BST_TIMING_INTER27: 361 case RT1015_S_BST_TIMING_INTER28: 362 case RT1015_S_BST_TIMING_INTER29: 363 case RT1015_S_BST_TIMING_INTER30: 364 case RT1015_S_BST_TIMING_INTER31: 365 case RT1015_S_BST_TIMING_INTER32: 366 case RT1015_S_BST_TIMING_INTER33: 367 case RT1015_S_BST_TIMING_INTER34: 368 case RT1015_S_BST_TIMING_INTER35: 369 case RT1015_S_BST_TIMING_INTER36: 370 return true; 371 372 default: 373 return false; 374 } 375 } 376 377 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 378 379 static const char * const rt1015_din_source_select[] = { 380 "Left", 381 "Right", 382 "Left + Right average", 383 }; 384 385 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4, 386 rt1015_din_source_select); 387 388 static const char * const rt1015_boost_mode[] = { 389 "Bypass", "Adaptive", "Fixed Adaptive" 390 }; 391 392 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0, 393 rt1015_boost_mode); 394 395 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol, 396 struct snd_ctl_elem_value *ucontrol) 397 { 398 struct snd_soc_component *component = 399 snd_soc_kcontrol_component(kcontrol); 400 struct rt1015_priv *rt1015 = 401 snd_soc_component_get_drvdata(component); 402 403 ucontrol->value.integer.value[0] = rt1015->boost_mode; 404 405 return 0; 406 } 407 408 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol, 409 struct snd_ctl_elem_value *ucontrol) 410 { 411 struct snd_soc_component *component = 412 snd_soc_kcontrol_component(kcontrol); 413 struct rt1015_priv *rt1015 = 414 snd_soc_component_get_drvdata(component); 415 416 rt1015->boost_mode = ucontrol->value.integer.value[0]; 417 418 switch (rt1015->boost_mode) { 419 case BYPASS: 420 snd_soc_component_update_bits(component, 421 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 422 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 423 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS | 424 RT1015_BYPASS_SWRREG_BYPASS); 425 break; 426 case ADAPTIVE: 427 snd_soc_component_update_bits(component, 428 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 429 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 430 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS | 431 RT1015_BYPASS_SWRREG_PASS); 432 break; 433 case FIXED_ADAPTIVE: 434 snd_soc_component_update_bits(component, 435 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 436 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 437 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN | 438 RT1015_BYPASS_SWRREG_PASS); 439 break; 440 default: 441 dev_err(component->dev, "Unknown boost control.\n"); 442 } 443 444 return 0; 445 } 446 447 static int rt5518_bypass_boost_get(struct snd_kcontrol *kcontrol, 448 struct snd_ctl_elem_value *ucontrol) 449 { 450 struct snd_soc_component *component = 451 snd_soc_kcontrol_component(kcontrol); 452 struct rt1015_priv *rt1015 = 453 snd_soc_component_get_drvdata(component); 454 455 ucontrol->value.integer.value[0] = rt1015->bypass_boost; 456 457 return 0; 458 } 459 460 static int rt5518_bypass_boost_put(struct snd_kcontrol *kcontrol, 461 struct snd_ctl_elem_value *ucontrol) 462 { 463 struct snd_soc_component *component = 464 snd_soc_kcontrol_component(kcontrol); 465 struct rt1015_priv *rt1015 = 466 snd_soc_component_get_drvdata(component); 467 468 if (!rt1015->dac_is_used) { 469 rt1015->bypass_boost = ucontrol->value.integer.value[0]; 470 if (rt1015->bypass_boost == 1) { 471 snd_soc_component_write(component, 472 RT1015_PWR4, 0x00b2); 473 snd_soc_component_write(component, 474 RT1015_CLSD_INTERNAL8, 0x2008); 475 snd_soc_component_write(component, 476 RT1015_CLSD_INTERNAL9, 0x0140); 477 snd_soc_component_write(component, 478 RT1015_GAT_BOOST, 0x00fe); 479 snd_soc_component_write(component, 480 RT1015_PWR_STATE_CTRL, 0x000d); 481 msleep(500); 482 snd_soc_component_write(component, 483 RT1015_PWR_STATE_CTRL, 0x000e); 484 } 485 } else 486 dev_err(component->dev, "DAC is being used!\n"); 487 488 return 0; 489 } 490 491 static const struct snd_kcontrol_new rt1015_snd_controls[] = { 492 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT, 493 127, 0, dac_vol_tlv), 494 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3, 495 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1), 496 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum, 497 rt1015_boost_mode_get, rt1015_boost_mode_put), 498 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel), 499 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0, 500 rt5518_bypass_boost_get, rt5518_bypass_boost_put), 501 }; 502 503 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 504 struct snd_soc_dapm_widget *sink) 505 { 506 struct snd_soc_component *component = 507 snd_soc_dapm_to_component(source->dapm); 508 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 509 510 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL) 511 return 1; 512 else 513 return 0; 514 } 515 516 static int r1015_dac_event(struct snd_soc_dapm_widget *w, 517 struct snd_kcontrol *kcontrol, int event) 518 { 519 struct snd_soc_component *component = 520 snd_soc_dapm_to_component(w->dapm); 521 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 522 523 switch (event) { 524 case SND_SOC_DAPM_PRE_PMU: 525 rt1015->dac_is_used = 1; 526 if (rt1015->bypass_boost == 0) { 527 snd_soc_component_write(component, 528 RT1015_SYS_RST1, 0x05f7); 529 snd_soc_component_write(component, 530 RT1015_GAT_BOOST, 0xacfe); 531 snd_soc_component_write(component, 532 RT1015_PWR9, 0xaa00); 533 snd_soc_component_write(component, 534 RT1015_GAT_BOOST, 0xecfe); 535 } else { 536 snd_soc_component_write(component, 537 RT1015_SYS_RST1, 0x05f7); 538 snd_soc_component_write(component, 539 RT1015_PWR_STATE_CTRL, 0x026e); 540 } 541 break; 542 543 case SND_SOC_DAPM_POST_PMD: 544 if (rt1015->bypass_boost == 0) { 545 snd_soc_component_write(component, 546 RT1015_PWR9, 0xa800); 547 snd_soc_component_write(component, 548 RT1015_SYS_RST1, 0x05f5); 549 } else { 550 snd_soc_component_write(component, 551 RT1015_PWR_STATE_CTRL, 0x0268); 552 snd_soc_component_write(component, 553 RT1015_SYS_RST1, 0x05f5); 554 } 555 rt1015->dac_is_used = 0; 556 break; 557 558 default: 559 break; 560 } 561 return 0; 562 } 563 564 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = { 565 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0, 566 NULL, 0), 567 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT, 568 0, NULL, 0), 569 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0, 570 NULL, 0), 571 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0, 572 NULL, 0), 573 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0, 574 NULL, 0), 575 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0, 576 NULL, 0), 577 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0, 578 NULL, 0), 579 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL, 580 0), 581 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0, 582 NULL, 0), 583 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL, 584 0), 585 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0, 586 NULL, 0), 587 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL, 588 0), 589 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0, 590 NULL, 0), 591 592 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 593 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0, 594 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 595 596 SND_SOC_DAPM_OUTPUT("SPO"), 597 }; 598 599 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = { 600 { "DAC", NULL, "AIFRX" }, 601 { "DAC", NULL, "LDO2" }, 602 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll}, 603 { "DAC", NULL, "INT RC CLK" }, 604 { "DAC", NULL, "ISENSE" }, 605 { "DAC", NULL, "VSENSE" }, 606 { "DAC", NULL, "BG1 BG2" }, 607 { "DAC", NULL, "MBIAS BG" }, 608 { "DAC", NULL, "VBAT" }, 609 { "DAC", NULL, "MBIAS" }, 610 { "DAC", NULL, "ADCV" }, 611 { "DAC", NULL, "MIXERV" }, 612 { "DAC", NULL, "SUMV" }, 613 { "DAC", NULL, "VREFLV" }, 614 { "SPO", NULL, "DAC" }, 615 }; 616 617 static int rt1015_hw_params(struct snd_pcm_substream *substream, 618 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 619 { 620 struct snd_soc_component *component = dai->component; 621 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 622 int pre_div, bclk_ms, frame_size; 623 unsigned int val_len = 0; 624 625 rt1015->lrck = params_rate(params); 626 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck); 627 if (pre_div < 0) { 628 dev_err(component->dev, "Unsupported clock rate\n"); 629 return -EINVAL; 630 } 631 632 frame_size = snd_soc_params_to_frame_size(params); 633 if (frame_size < 0) { 634 dev_err(component->dev, "Unsupported frame size: %d\n", 635 frame_size); 636 return -EINVAL; 637 } 638 639 bclk_ms = frame_size > 32; 640 rt1015->bclk = rt1015->lrck * (32 << bclk_ms); 641 642 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 643 bclk_ms, pre_div, dai->id); 644 645 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 646 rt1015->lrck, pre_div, dai->id); 647 648 switch (params_width(params)) { 649 case 16: 650 break; 651 case 20: 652 val_len = RT1015_I2S_DL_20; 653 break; 654 case 24: 655 val_len = RT1015_I2S_DL_24; 656 break; 657 case 8: 658 val_len = RT1015_I2S_DL_8; 659 break; 660 default: 661 return -EINVAL; 662 } 663 664 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 665 RT1015_I2S_DL_MASK, val_len); 666 snd_soc_component_update_bits(component, RT1015_CLK2, 667 RT1015_FS_PD_MASK, pre_div); 668 669 return 0; 670 } 671 672 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 673 { 674 struct snd_soc_component *component = dai->component; 675 unsigned int reg_val = 0, reg_val2 = 0; 676 677 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 678 case SND_SOC_DAIFMT_CBM_CFM: 679 reg_val |= RT1015_TCON_TDM_MS_M; 680 break; 681 case SND_SOC_DAIFMT_CBS_CFS: 682 reg_val |= RT1015_TCON_TDM_MS_S; 683 break; 684 default: 685 return -EINVAL; 686 } 687 688 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 689 case SND_SOC_DAIFMT_NB_NF: 690 break; 691 case SND_SOC_DAIFMT_IB_NF: 692 reg_val2 |= RT1015_TDM_INV_BCLK; 693 break; 694 default: 695 return -EINVAL; 696 } 697 698 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 699 case SND_SOC_DAIFMT_I2S: 700 break; 701 702 case SND_SOC_DAIFMT_LEFT_J: 703 reg_val |= RT1015_I2S_M_DF_LEFT; 704 break; 705 706 case SND_SOC_DAIFMT_DSP_A: 707 reg_val |= RT1015_I2S_M_DF_PCM_A; 708 break; 709 710 case SND_SOC_DAIFMT_DSP_B: 711 reg_val |= RT1015_I2S_M_DF_PCM_B; 712 break; 713 714 default: 715 return -EINVAL; 716 } 717 718 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 719 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK, 720 reg_val); 721 snd_soc_component_update_bits(component, RT1015_TDM1_1, 722 RT1015_TDM_INV_BCLK_MASK, reg_val2); 723 724 return 0; 725 } 726 727 static int rt1015_set_component_sysclk(struct snd_soc_component *component, 728 int clk_id, int source, unsigned int freq, int dir) 729 { 730 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 731 unsigned int reg_val = 0; 732 733 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src) 734 return 0; 735 736 switch (clk_id) { 737 case RT1015_SCLK_S_MCLK: 738 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK; 739 break; 740 741 case RT1015_SCLK_S_PLL: 742 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL; 743 break; 744 745 default: 746 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 747 return -EINVAL; 748 } 749 750 rt1015->sysclk = freq; 751 rt1015->sysclk_src = clk_id; 752 753 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 754 freq, clk_id); 755 756 snd_soc_component_update_bits(component, RT1015_CLK2, 757 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val); 758 759 return 0; 760 } 761 762 static int rt1015_set_component_pll(struct snd_soc_component *component, 763 int pll_id, int source, unsigned int freq_in, 764 unsigned int freq_out) 765 { 766 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 767 struct rl6231_pll_code pll_code; 768 int ret; 769 770 if (!freq_in || !freq_out) { 771 dev_dbg(component->dev, "PLL disabled\n"); 772 773 rt1015->pll_in = 0; 774 rt1015->pll_out = 0; 775 776 return 0; 777 } 778 779 if (source == rt1015->pll_src && freq_in == rt1015->pll_in && 780 freq_out == rt1015->pll_out) 781 return 0; 782 783 switch (source) { 784 case RT1015_PLL_S_MCLK: 785 snd_soc_component_update_bits(component, RT1015_CLK2, 786 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2); 787 break; 788 789 case RT1015_PLL_S_BCLK: 790 snd_soc_component_update_bits(component, RT1015_CLK2, 791 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK); 792 break; 793 794 default: 795 dev_err(component->dev, "Unknown PLL Source %d\n", source); 796 return -EINVAL; 797 } 798 799 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 800 if (ret < 0) { 801 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 802 return ret; 803 } 804 805 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 806 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 807 pll_code.n_code, pll_code.k_code); 808 809 snd_soc_component_write(component, RT1015_PLL1, 810 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT | 811 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code); 812 snd_soc_component_write(component, RT1015_PLL2, 813 pll_code.k_code); 814 815 rt1015->pll_in = freq_in; 816 rt1015->pll_out = freq_out; 817 rt1015->pll_src = source; 818 819 return 0; 820 } 821 822 static int rt1015_probe(struct snd_soc_component *component) 823 { 824 struct rt1015_priv *rt1015 = 825 snd_soc_component_get_drvdata(component); 826 827 rt1015->component = component; 828 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c); 829 830 return 0; 831 } 832 833 static void rt1015_remove(struct snd_soc_component *component) 834 { 835 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 836 837 regmap_write(rt1015->regmap, RT1015_RESET, 0); 838 } 839 840 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000 841 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 842 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 843 844 struct snd_soc_dai_ops rt1015_aif_dai_ops = { 845 .hw_params = rt1015_hw_params, 846 .set_fmt = rt1015_set_dai_fmt, 847 }; 848 849 struct snd_soc_dai_driver rt1015_dai[] = { 850 { 851 .name = "rt1015-aif", 852 .id = 0, 853 .playback = { 854 .stream_name = "AIF Playback", 855 .channels_min = 1, 856 .channels_max = 4, 857 .rates = RT1015_STEREO_RATES, 858 .formats = RT1015_FORMATS, 859 }, 860 } 861 }; 862 863 #ifdef CONFIG_PM 864 static int rt1015_suspend(struct snd_soc_component *component) 865 { 866 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 867 868 regcache_cache_only(rt1015->regmap, true); 869 regcache_mark_dirty(rt1015->regmap); 870 871 return 0; 872 } 873 874 static int rt1015_resume(struct snd_soc_component *component) 875 { 876 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 877 878 regcache_cache_only(rt1015->regmap, false); 879 regcache_sync(rt1015->regmap); 880 return 0; 881 } 882 #else 883 #define rt1015_suspend NULL 884 #define rt1015_resume NULL 885 #endif 886 887 static const struct snd_soc_component_driver soc_component_dev_rt1015 = { 888 .probe = rt1015_probe, 889 .remove = rt1015_remove, 890 .suspend = rt1015_suspend, 891 .resume = rt1015_resume, 892 .controls = rt1015_snd_controls, 893 .num_controls = ARRAY_SIZE(rt1015_snd_controls), 894 .dapm_widgets = rt1015_dapm_widgets, 895 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets), 896 .dapm_routes = rt1015_dapm_routes, 897 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes), 898 .set_sysclk = rt1015_set_component_sysclk, 899 .set_pll = rt1015_set_component_pll, 900 .use_pmdown_time = 1, 901 .endianness = 1, 902 .non_legacy_dai_naming = 1, 903 }; 904 905 static const struct regmap_config rt1015_regmap = { 906 .reg_bits = 16, 907 .val_bits = 16, 908 .max_register = RT1015_S_BST_TIMING_INTER36, 909 .volatile_reg = rt1015_volatile_register, 910 .readable_reg = rt1015_readable_register, 911 .cache_type = REGCACHE_RBTREE, 912 .reg_defaults = rt1015_reg, 913 .num_reg_defaults = ARRAY_SIZE(rt1015_reg), 914 }; 915 916 static const struct i2c_device_id rt1015_i2c_id[] = { 917 { "rt1015", 0 }, 918 { } 919 }; 920 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id); 921 922 #if defined(CONFIG_OF) 923 static const struct of_device_id rt1015_of_match[] = { 924 { .compatible = "realtek,rt1015", }, 925 {}, 926 }; 927 MODULE_DEVICE_TABLE(of, rt1015_of_match); 928 #endif 929 930 #ifdef CONFIG_ACPI 931 static struct acpi_device_id rt1015_acpi_match[] = { 932 {"10EC1015", 0,}, 933 {}, 934 }; 935 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match); 936 #endif 937 938 static int rt1015_i2c_probe(struct i2c_client *i2c, 939 const struct i2c_device_id *id) 940 { 941 struct rt1015_priv *rt1015; 942 int ret; 943 unsigned int val; 944 945 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv), 946 GFP_KERNEL); 947 if (rt1015 == NULL) 948 return -ENOMEM; 949 950 i2c_set_clientdata(i2c, rt1015); 951 952 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap); 953 if (IS_ERR(rt1015->regmap)) { 954 ret = PTR_ERR(rt1015->regmap); 955 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 956 ret); 957 return ret; 958 } 959 960 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val); 961 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) { 962 dev_err(&i2c->dev, 963 "Device with ID register %x is not rt1015\n", val); 964 return -ENODEV; 965 } 966 967 return devm_snd_soc_register_component(&i2c->dev, 968 &soc_component_dev_rt1015, 969 rt1015_dai, ARRAY_SIZE(rt1015_dai)); 970 } 971 972 static void rt1015_i2c_shutdown(struct i2c_client *client) 973 { 974 struct rt1015_priv *rt1015 = i2c_get_clientdata(client); 975 976 regmap_write(rt1015->regmap, RT1015_RESET, 0); 977 } 978 979 static struct i2c_driver rt1015_i2c_driver = { 980 .driver = { 981 .name = "rt1015", 982 .of_match_table = of_match_ptr(rt1015_of_match), 983 .acpi_match_table = ACPI_PTR(rt1015_acpi_match), 984 }, 985 .probe = rt1015_i2c_probe, 986 .shutdown = rt1015_i2c_shutdown, 987 .id_table = rt1015_i2c_id, 988 }; 989 module_i2c_driver(rt1015_i2c_driver); 990 991 MODULE_DESCRIPTION("ASoC RT1015 driver"); 992 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 993 MODULE_LICENSE("GPL v2"); 994