xref: /openbmc/linux/sound/soc/codecs/rt1011.c (revision 4eb5928d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * rt1011.c -- rt1011 ALSA SoC amplifier component driver
4  *
5  * Copyright(c) 2019 Realtek Semiconductor Corp.
6  *
7  * Author: Shuming Fan <shumingf@realtek.com>
8  *
9  */
10 
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/gpio.h>
17 #include <linux/i2c.h>
18 #include <linux/acpi.h>
19 #include <linux/regmap.h>
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
22 #include <linux/firmware.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 
31 #include "rl6231.h"
32 #include "rt1011.h"
33 
34 static int rt1011_calibrate(struct rt1011_priv *rt1011,
35 	unsigned char cali_flag);
36 
37 static const struct reg_sequence init_list[] = {
38 
39 	{ RT1011_POWER_9, 0xa840 },
40 
41 	{ RT1011_ADC_SET_5, 0x0a20 },
42 	{ RT1011_DAC_SET_2, 0xa032 },
43 
44 	{ RT1011_SPK_PRO_DC_DET_1, 0xb00c },
45 	{ RT1011_SPK_PRO_DC_DET_2, 0xcccc },
46 
47 	{ RT1011_A_TIMING_1, 0x6054 },
48 
49 	{ RT1011_POWER_7, 0x3e55 },
50 	{ RT1011_POWER_8, 0x0520 },
51 	{ RT1011_BOOST_CON_1, 0xe188 },
52 	{ RT1011_POWER_4, 0x16f2 },
53 
54 	{ RT1011_CROSS_BQ_SET_1, 0x0004 },
55 	{ RT1011_SIL_DET, 0xc313 },
56 	{ RT1011_SINE_GEN_REG_1, 0x0707 },
57 
58 	{ RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
59 
60 	{ RT1011_DAC_SET_1, 0xe702 },
61 	{ RT1011_DAC_SET_3, 0x2004 },
62 };
63 
64 static const struct reg_default rt1011_reg[] = {
65 	{0x0000, 0x0000},
66 	{0x0002, 0x0000},
67 	{0x0004, 0xa000},
68 	{0x0006, 0x0000},
69 	{0x0008, 0x0003},
70 	{0x000a, 0x087e},
71 	{0x000c, 0x0020},
72 	{0x000e, 0x9002},
73 	{0x0010, 0x0000},
74 	{0x0012, 0x0000},
75 	{0x0020, 0x0c40},
76 	{0x0022, 0x4313},
77 	{0x0076, 0x0000},
78 	{0x0078, 0x0000},
79 	{0x007a, 0x0000},
80 	{0x007c, 0x10ec},
81 	{0x007d, 0x1011},
82 	{0x00f0, 0x5000},
83 	{0x00f2, 0x0374},
84 	{0x00f3, 0x0000},
85 	{0x00f4, 0x0000},
86 	{0x0100, 0x0038},
87 	{0x0102, 0xff02},
88 	{0x0104, 0x0232},
89 	{0x0106, 0x200c},
90 	{0x0107, 0x0000},
91 	{0x0108, 0x2f2f},
92 	{0x010a, 0x2f2f},
93 	{0x010c, 0x002f},
94 	{0x010e, 0xe000},
95 	{0x0110, 0x0820},
96 	{0x0111, 0x4010},
97 	{0x0112, 0x0000},
98 	{0x0114, 0x0000},
99 	{0x0116, 0x0000},
100 	{0x0118, 0x0000},
101 	{0x011a, 0x0101},
102 	{0x011c, 0x4567},
103 	{0x011e, 0x0000},
104 	{0x0120, 0x0000},
105 	{0x0122, 0x0000},
106 	{0x0124, 0x0123},
107 	{0x0126, 0x4567},
108 	{0x0200, 0x0000},
109 	{0x0300, 0xffdd},
110 	{0x0302, 0x001e},
111 	{0x0311, 0x0000},
112 	{0x0313, 0x5254},
113 	{0x0314, 0x0062},
114 	{0x0316, 0x7f40},
115 	{0x0319, 0x000f},
116 	{0x031a, 0xffff},
117 	{0x031b, 0x0000},
118 	{0x031c, 0x009f},
119 	{0x031d, 0xffff},
120 	{0x031e, 0x0000},
121 	{0x031f, 0x0000},
122 	{0x0320, 0xe31c},
123 	{0x0321, 0x0000},
124 	{0x0322, 0x0000},
125 	{0x0324, 0x0000},
126 	{0x0326, 0x0002},
127 	{0x0328, 0x20b2},
128 	{0x0329, 0x0175},
129 	{0x032a, 0x32ad},
130 	{0x032b, 0x3455},
131 	{0x032c, 0x0528},
132 	{0x032d, 0xa800},
133 	{0x032e, 0x030e},
134 	{0x0330, 0x2080},
135 	{0x0332, 0x0034},
136 	{0x0334, 0x0000},
137 	{0x0508, 0x0010},
138 	{0x050a, 0x0018},
139 	{0x050c, 0x0000},
140 	{0x050d, 0xffff},
141 	{0x050e, 0x1f1f},
142 	{0x050f, 0x04ff},
143 	{0x0510, 0x4020},
144 	{0x0511, 0x01f0},
145 	{0x0512, 0x0702},
146 	{0x0516, 0xbb80},
147 	{0x0517, 0xffff},
148 	{0x0518, 0xffff},
149 	{0x0519, 0x307f},
150 	{0x051a, 0xffff},
151 	{0x051b, 0x0000},
152 	{0x051c, 0x0000},
153 	{0x051d, 0x2000},
154 	{0x051e, 0x0000},
155 	{0x051f, 0x0000},
156 	{0x0520, 0x0000},
157 	{0x0521, 0x1001},
158 	{0x0522, 0x7fff},
159 	{0x0524, 0x7fff},
160 	{0x0526, 0x0000},
161 	{0x0528, 0x0000},
162 	{0x052a, 0x0000},
163 	{0x0530, 0x0401},
164 	{0x0532, 0x3000},
165 	{0x0534, 0x0000},
166 	{0x0535, 0xffff},
167 	{0x0536, 0x101c},
168 	{0x0538, 0x1814},
169 	{0x053a, 0x100c},
170 	{0x053c, 0x0804},
171 	{0x053d, 0x0000},
172 	{0x053e, 0x0000},
173 	{0x053f, 0x0000},
174 	{0x0540, 0x0000},
175 	{0x0541, 0x0000},
176 	{0x0542, 0x0000},
177 	{0x0543, 0x0000},
178 	{0x0544, 0x001c},
179 	{0x0545, 0x1814},
180 	{0x0546, 0x100c},
181 	{0x0547, 0x0804},
182 	{0x0548, 0x0000},
183 	{0x0549, 0x0000},
184 	{0x054a, 0x0000},
185 	{0x054b, 0x0000},
186 	{0x054c, 0x0000},
187 	{0x054d, 0x0000},
188 	{0x054e, 0x0000},
189 	{0x054f, 0x0000},
190 	{0x0566, 0x0000},
191 	{0x0568, 0x20f1},
192 	{0x056a, 0x0007},
193 	{0x0600, 0x9d00},
194 	{0x0611, 0x2000},
195 	{0x0612, 0x505f},
196 	{0x0613, 0x0444},
197 	{0x0614, 0x4000},
198 	{0x0615, 0x4004},
199 	{0x0616, 0x0606},
200 	{0x0617, 0x8904},
201 	{0x0618, 0xe021},
202 	{0x0621, 0x2000},
203 	{0x0622, 0x505f},
204 	{0x0623, 0x0444},
205 	{0x0624, 0x4000},
206 	{0x0625, 0x4004},
207 	{0x0626, 0x0606},
208 	{0x0627, 0x8704},
209 	{0x0628, 0xe021},
210 	{0x0631, 0x2000},
211 	{0x0632, 0x517f},
212 	{0x0633, 0x0440},
213 	{0x0634, 0x4000},
214 	{0x0635, 0x4104},
215 	{0x0636, 0x0306},
216 	{0x0637, 0x8904},
217 	{0x0638, 0xe021},
218 	{0x0702, 0x0014},
219 	{0x0704, 0x0000},
220 	{0x0706, 0x0014},
221 	{0x0708, 0x0000},
222 	{0x070a, 0x0000},
223 	{0x0710, 0x0200},
224 	{0x0711, 0x0000},
225 	{0x0712, 0x0200},
226 	{0x0713, 0x0000},
227 	{0x0720, 0x0200},
228 	{0x0721, 0x0000},
229 	{0x0722, 0x0000},
230 	{0x0723, 0x0000},
231 	{0x0724, 0x0000},
232 	{0x0725, 0x0000},
233 	{0x0726, 0x0000},
234 	{0x0727, 0x0000},
235 	{0x0728, 0x0000},
236 	{0x0729, 0x0000},
237 	{0x0730, 0x0200},
238 	{0x0731, 0x0000},
239 	{0x0732, 0x0000},
240 	{0x0733, 0x0000},
241 	{0x0734, 0x0000},
242 	{0x0735, 0x0000},
243 	{0x0736, 0x0000},
244 	{0x0737, 0x0000},
245 	{0x0738, 0x0000},
246 	{0x0739, 0x0000},
247 	{0x0740, 0x0200},
248 	{0x0741, 0x0000},
249 	{0x0742, 0x0000},
250 	{0x0743, 0x0000},
251 	{0x0744, 0x0000},
252 	{0x0745, 0x0000},
253 	{0x0746, 0x0000},
254 	{0x0747, 0x0000},
255 	{0x0748, 0x0000},
256 	{0x0749, 0x0000},
257 	{0x0750, 0x0200},
258 	{0x0751, 0x0000},
259 	{0x0752, 0x0000},
260 	{0x0753, 0x0000},
261 	{0x0754, 0x0000},
262 	{0x0755, 0x0000},
263 	{0x0756, 0x0000},
264 	{0x0757, 0x0000},
265 	{0x0758, 0x0000},
266 	{0x0759, 0x0000},
267 	{0x0760, 0x0200},
268 	{0x0761, 0x0000},
269 	{0x0762, 0x0000},
270 	{0x0763, 0x0000},
271 	{0x0764, 0x0000},
272 	{0x0765, 0x0000},
273 	{0x0766, 0x0000},
274 	{0x0767, 0x0000},
275 	{0x0768, 0x0000},
276 	{0x0769, 0x0000},
277 	{0x0770, 0x0200},
278 	{0x0771, 0x0000},
279 	{0x0772, 0x0000},
280 	{0x0773, 0x0000},
281 	{0x0774, 0x0000},
282 	{0x0775, 0x0000},
283 	{0x0776, 0x0000},
284 	{0x0777, 0x0000},
285 	{0x0778, 0x0000},
286 	{0x0779, 0x0000},
287 	{0x0780, 0x0200},
288 	{0x0781, 0x0000},
289 	{0x0782, 0x0000},
290 	{0x0783, 0x0000},
291 	{0x0784, 0x0000},
292 	{0x0785, 0x0000},
293 	{0x0786, 0x0000},
294 	{0x0787, 0x0000},
295 	{0x0788, 0x0000},
296 	{0x0789, 0x0000},
297 	{0x0790, 0x0200},
298 	{0x0791, 0x0000},
299 	{0x0792, 0x0000},
300 	{0x0793, 0x0000},
301 	{0x0794, 0x0000},
302 	{0x0795, 0x0000},
303 	{0x0796, 0x0000},
304 	{0x0797, 0x0000},
305 	{0x0798, 0x0000},
306 	{0x0799, 0x0000},
307 	{0x07a0, 0x0200},
308 	{0x07a1, 0x0000},
309 	{0x07a2, 0x0000},
310 	{0x07a3, 0x0000},
311 	{0x07a4, 0x0000},
312 	{0x07a5, 0x0000},
313 	{0x07a6, 0x0000},
314 	{0x07a7, 0x0000},
315 	{0x07a8, 0x0000},
316 	{0x07a9, 0x0000},
317 	{0x07b0, 0x0200},
318 	{0x07b1, 0x0000},
319 	{0x07b2, 0x0000},
320 	{0x07b3, 0x0000},
321 	{0x07b4, 0x0000},
322 	{0x07b5, 0x0000},
323 	{0x07b6, 0x0000},
324 	{0x07b7, 0x0000},
325 	{0x07b8, 0x0000},
326 	{0x07b9, 0x0000},
327 	{0x07c0, 0x0200},
328 	{0x07c1, 0x0000},
329 	{0x07c2, 0x0000},
330 	{0x07c3, 0x0000},
331 	{0x07c4, 0x0000},
332 	{0x07c5, 0x0000},
333 	{0x07c6, 0x0000},
334 	{0x07c7, 0x0000},
335 	{0x07c8, 0x0000},
336 	{0x07c9, 0x0000},
337 	{0x1000, 0x4040},
338 	{0x1002, 0x6505},
339 	{0x1004, 0x5405},
340 	{0x1006, 0x5555},
341 	{0x1007, 0x003f},
342 	{0x1008, 0x7fd7},
343 	{0x1009, 0x770f},
344 	{0x100a, 0xfffe},
345 	{0x100b, 0xe000},
346 	{0x100c, 0x0000},
347 	{0x100d, 0x0007},
348 	{0x1010, 0xa433},
349 	{0x1020, 0x0000},
350 	{0x1022, 0x0000},
351 	{0x1024, 0x0000},
352 	{0x1200, 0x5a01},
353 	{0x1202, 0x6324},
354 	{0x1204, 0x0b00},
355 	{0x1206, 0x0000},
356 	{0x1208, 0x0000},
357 	{0x120a, 0x0024},
358 	{0x120c, 0x0000},
359 	{0x120e, 0x000e},
360 	{0x1210, 0x0000},
361 	{0x1212, 0x0000},
362 	{0x1300, 0x0701},
363 	{0x1302, 0x12f9},
364 	{0x1304, 0x3405},
365 	{0x1305, 0x0844},
366 	{0x1306, 0x5611},
367 	{0x1308, 0x555e},
368 	{0x130a, 0xa605},
369 	{0x130c, 0x2000},
370 	{0x130e, 0x0000},
371 	{0x130f, 0x0001},
372 	{0x1310, 0xaa48},
373 	{0x1312, 0x0285},
374 	{0x1314, 0xaaaa},
375 	{0x1316, 0xaaa0},
376 	{0x1318, 0x2aaa},
377 	{0x131a, 0xaa07},
378 	{0x1322, 0x0029},
379 	{0x1323, 0x4a52},
380 	{0x1324, 0x002c},
381 	{0x1325, 0x0b02},
382 	{0x1326, 0x002d},
383 	{0x1327, 0x6b5a},
384 	{0x1328, 0x002e},
385 	{0x1329, 0xcbb2},
386 	{0x132a, 0x0030},
387 	{0x132b, 0x2c0b},
388 	{0x1330, 0x0031},
389 	{0x1331, 0x8c63},
390 	{0x1332, 0x0032},
391 	{0x1333, 0xecbb},
392 	{0x1334, 0x0034},
393 	{0x1335, 0x4d13},
394 	{0x1336, 0x0037},
395 	{0x1337, 0x0dc3},
396 	{0x1338, 0x003d},
397 	{0x1339, 0xef7b},
398 	{0x133a, 0x0044},
399 	{0x133b, 0xd134},
400 	{0x133c, 0x0047},
401 	{0x133d, 0x91e4},
402 	{0x133e, 0x004d},
403 	{0x133f, 0xc370},
404 	{0x1340, 0x0053},
405 	{0x1341, 0xf4fd},
406 	{0x1342, 0x0060},
407 	{0x1343, 0x5816},
408 	{0x1344, 0x006c},
409 	{0x1345, 0xbb2e},
410 	{0x1346, 0x0072},
411 	{0x1347, 0xecbb},
412 	{0x1348, 0x0076},
413 	{0x1349, 0x5d97},
414 	{0x1500, 0x0702},
415 	{0x1502, 0x002f},
416 	{0x1504, 0x0000},
417 	{0x1510, 0x0064},
418 	{0x1512, 0x0000},
419 	{0x1514, 0xdf47},
420 	{0x1516, 0x079c},
421 	{0x1518, 0xfbf5},
422 	{0x151a, 0x00bc},
423 	{0x151c, 0x3b85},
424 	{0x151e, 0x02b3},
425 	{0x1520, 0x3333},
426 	{0x1522, 0x0000},
427 	{0x1524, 0x4000},
428 	{0x1528, 0x0064},
429 	{0x152a, 0x0000},
430 	{0x152c, 0x0000},
431 	{0x152e, 0x0000},
432 	{0x1530, 0x0000},
433 	{0x1532, 0x0000},
434 	{0x1534, 0x0000},
435 	{0x1536, 0x0000},
436 	{0x1538, 0x0040},
437 	{0x1539, 0x0000},
438 	{0x153a, 0x0040},
439 	{0x153b, 0x0000},
440 	{0x153c, 0x0064},
441 	{0x153e, 0x0bf9},
442 	{0x1540, 0xb2a9},
443 	{0x1544, 0x0200},
444 	{0x1546, 0x0000},
445 	{0x1548, 0x00ca},
446 	{0x1552, 0x03ff},
447 	{0x1554, 0x017f},
448 	{0x1556, 0x017f},
449 	{0x155a, 0x0000},
450 	{0x155c, 0x0000},
451 	{0x1560, 0x0040},
452 	{0x1562, 0x0000},
453 	{0x1570, 0x03ff},
454 	{0x1571, 0xdcff},
455 	{0x1572, 0x1e00},
456 	{0x1573, 0x224f},
457 	{0x1574, 0x0000},
458 	{0x1575, 0x0000},
459 	{0x1576, 0x1e00},
460 	{0x1577, 0x0000},
461 	{0x1578, 0x0000},
462 	{0x1579, 0x1128},
463 	{0x157a, 0x03ff},
464 	{0x157b, 0xdcff},
465 	{0x157c, 0x1e00},
466 	{0x157d, 0x224f},
467 	{0x157e, 0x0000},
468 	{0x157f, 0x0000},
469 	{0x1580, 0x1e00},
470 	{0x1581, 0x0000},
471 	{0x1582, 0x0000},
472 	{0x1583, 0x1128},
473 	{0x1590, 0x03ff},
474 	{0x1591, 0xdcff},
475 	{0x1592, 0x1e00},
476 	{0x1593, 0x224f},
477 	{0x1594, 0x0000},
478 	{0x1595, 0x0000},
479 	{0x1596, 0x1e00},
480 	{0x1597, 0x0000},
481 	{0x1598, 0x0000},
482 	{0x1599, 0x1128},
483 	{0x159a, 0x03ff},
484 	{0x159b, 0xdcff},
485 	{0x159c, 0x1e00},
486 	{0x159d, 0x224f},
487 	{0x159e, 0x0000},
488 	{0x159f, 0x0000},
489 	{0x15a0, 0x1e00},
490 	{0x15a1, 0x0000},
491 	{0x15a2, 0x0000},
492 	{0x15a3, 0x1128},
493 	{0x15b0, 0x007f},
494 	{0x15b1, 0xffff},
495 	{0x15b2, 0x007f},
496 	{0x15b3, 0xffff},
497 	{0x15b4, 0x007f},
498 	{0x15b5, 0xffff},
499 	{0x15b8, 0x007f},
500 	{0x15b9, 0xffff},
501 	{0x15bc, 0x0000},
502 	{0x15bd, 0x0000},
503 	{0x15be, 0xff00},
504 	{0x15bf, 0x0000},
505 	{0x15c0, 0xff00},
506 	{0x15c1, 0x0000},
507 	{0x15c3, 0xfc00},
508 	{0x15c4, 0xbb80},
509 	{0x15d0, 0x0000},
510 	{0x15d1, 0x0000},
511 	{0x15d2, 0x0000},
512 	{0x15d3, 0x0000},
513 	{0x15d4, 0x0000},
514 	{0x15d5, 0x0000},
515 	{0x15d6, 0x0000},
516 	{0x15d7, 0x0000},
517 	{0x15d8, 0x0200},
518 	{0x15d9, 0x0000},
519 	{0x15da, 0x0000},
520 	{0x15db, 0x0000},
521 	{0x15dc, 0x0000},
522 	{0x15dd, 0x0000},
523 	{0x15de, 0x0000},
524 	{0x15df, 0x0000},
525 	{0x15e0, 0x0000},
526 	{0x15e1, 0x0000},
527 	{0x15e2, 0x0200},
528 	{0x15e3, 0x0000},
529 	{0x15e4, 0x0000},
530 	{0x15e5, 0x0000},
531 	{0x15e6, 0x0000},
532 	{0x15e7, 0x0000},
533 	{0x15e8, 0x0000},
534 	{0x15e9, 0x0000},
535 	{0x15ea, 0x0000},
536 	{0x15eb, 0x0000},
537 	{0x15ec, 0x0200},
538 	{0x15ed, 0x0000},
539 	{0x15ee, 0x0000},
540 	{0x15ef, 0x0000},
541 	{0x15f0, 0x0000},
542 	{0x15f1, 0x0000},
543 	{0x15f2, 0x0000},
544 	{0x15f3, 0x0000},
545 	{0x15f4, 0x0000},
546 	{0x15f5, 0x0000},
547 	{0x15f6, 0x0200},
548 	{0x15f7, 0x0200},
549 	{0x15f8, 0x8200},
550 	{0x15f9, 0x0000},
551 	{0x1600, 0x007d},
552 	{0x1601, 0xa178},
553 	{0x1602, 0x00c2},
554 	{0x1603, 0x5383},
555 	{0x1604, 0x0000},
556 	{0x1605, 0x02c1},
557 	{0x1606, 0x007d},
558 	{0x1607, 0xa178},
559 	{0x1608, 0x00c2},
560 	{0x1609, 0x5383},
561 	{0x160a, 0x003e},
562 	{0x160b, 0xd37d},
563 	{0x1611, 0x3210},
564 	{0x1612, 0x7418},
565 	{0x1613, 0xc0ff},
566 	{0x1614, 0x0000},
567 	{0x1615, 0x00ff},
568 	{0x1616, 0x0000},
569 	{0x1617, 0x0000},
570 	{0x1621, 0x6210},
571 	{0x1622, 0x7418},
572 	{0x1623, 0xc0ff},
573 	{0x1624, 0x0000},
574 	{0x1625, 0x00ff},
575 	{0x1626, 0x0000},
576 	{0x1627, 0x0000},
577 	{0x1631, 0x3a14},
578 	{0x1632, 0x7418},
579 	{0x1633, 0xc3ff},
580 	{0x1634, 0x0000},
581 	{0x1635, 0x00ff},
582 	{0x1636, 0x0000},
583 	{0x1637, 0x0000},
584 	{0x1638, 0x0000},
585 	{0x163a, 0x0000},
586 	{0x163c, 0x0000},
587 	{0x163e, 0x0000},
588 	{0x1640, 0x0000},
589 	{0x1642, 0x0000},
590 	{0x1644, 0x0000},
591 	{0x1646, 0x0000},
592 	{0x1648, 0x0000},
593 	{0x1650, 0x0000},
594 	{0x1652, 0x0000},
595 	{0x1654, 0x0000},
596 	{0x1656, 0x0000},
597 	{0x1658, 0x0000},
598 	{0x1660, 0x0000},
599 	{0x1662, 0x0000},
600 	{0x1664, 0x0000},
601 	{0x1666, 0x0000},
602 	{0x1668, 0x0000},
603 	{0x1670, 0x0000},
604 	{0x1672, 0x0000},
605 	{0x1674, 0x0000},
606 	{0x1676, 0x0000},
607 	{0x1678, 0x0000},
608 	{0x1680, 0x0000},
609 	{0x1682, 0x0000},
610 	{0x1684, 0x0000},
611 	{0x1686, 0x0000},
612 	{0x1688, 0x0000},
613 	{0x1690, 0x0000},
614 	{0x1692, 0x0000},
615 	{0x1694, 0x0000},
616 	{0x1696, 0x0000},
617 	{0x1698, 0x0000},
618 	{0x1700, 0x0000},
619 	{0x1702, 0x0000},
620 	{0x1704, 0x0000},
621 	{0x1706, 0x0000},
622 	{0x1708, 0x0000},
623 	{0x1710, 0x0000},
624 	{0x1712, 0x0000},
625 	{0x1714, 0x0000},
626 	{0x1716, 0x0000},
627 	{0x1718, 0x0000},
628 	{0x1720, 0x0000},
629 	{0x1722, 0x0000},
630 	{0x1724, 0x0000},
631 	{0x1726, 0x0000},
632 	{0x1728, 0x0000},
633 	{0x1730, 0x0000},
634 	{0x1732, 0x0000},
635 	{0x1734, 0x0000},
636 	{0x1736, 0x0000},
637 	{0x1738, 0x0000},
638 	{0x173a, 0x0000},
639 	{0x173c, 0x0000},
640 	{0x173e, 0x0000},
641 	{0x17bb, 0x0500},
642 	{0x17bd, 0x0004},
643 	{0x17bf, 0x0004},
644 	{0x17c1, 0x0004},
645 	{0x17c2, 0x7fff},
646 	{0x17c3, 0x0000},
647 	{0x17c5, 0x0000},
648 	{0x17c7, 0x0000},
649 	{0x17c9, 0x0000},
650 	{0x17cb, 0x2010},
651 	{0x17cd, 0x0000},
652 	{0x17cf, 0x0000},
653 	{0x17d1, 0x0000},
654 	{0x17d3, 0x0000},
655 	{0x17d5, 0x0000},
656 	{0x17d7, 0x0000},
657 	{0x17d9, 0x0000},
658 	{0x17db, 0x0000},
659 	{0x17dd, 0x0000},
660 	{0x17df, 0x0000},
661 	{0x17e1, 0x0000},
662 	{0x17e3, 0x0000},
663 	{0x17e5, 0x0000},
664 	{0x17e7, 0x0000},
665 	{0x17e9, 0x0000},
666 	{0x17eb, 0x0000},
667 	{0x17ed, 0x0000},
668 	{0x17ef, 0x0000},
669 	{0x17f1, 0x0000},
670 	{0x17f3, 0x0000},
671 	{0x17f5, 0x0000},
672 	{0x17f7, 0x0000},
673 	{0x17f9, 0x0000},
674 	{0x17fb, 0x0000},
675 	{0x17fd, 0x0000},
676 	{0x17ff, 0x0000},
677 	{0x1801, 0x0000},
678 	{0x1803, 0x0000},
679 };
680 
681 static int rt1011_reg_init(struct snd_soc_component *component)
682 {
683 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
684 
685 	regmap_multi_reg_write(rt1011->regmap,
686 		init_list, ARRAY_SIZE(init_list));
687 	return 0;
688 }
689 
690 static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
691 {
692 	switch (reg) {
693 	case RT1011_RESET:
694 	case RT1011_SRC_2:
695 	case RT1011_CLK_DET:
696 	case RT1011_SIL_DET:
697 	case RT1011_VERSION_ID:
698 	case RT1011_VENDOR_ID:
699 	case RT1011_DEVICE_ID:
700 	case RT1011_DUM_RO:
701 	case RT1011_DAC_SET_3:
702 	case RT1011_PWM_CAL:
703 	case RT1011_SPK_VOL_TEST_OUT:
704 	case RT1011_VBAT_VOL_DET_1:
705 	case RT1011_VBAT_TEST_OUT_1:
706 	case RT1011_VBAT_TEST_OUT_2:
707 	case RT1011_VBAT_PROTECTION:
708 	case RT1011_VBAT_DET:
709 	case RT1011_BOOST_CON_1:
710 	case RT1011_SHORT_CIRCUIT_DET_1:
711 	case RT1011_SPK_TEMP_PROTECT_3:
712 	case RT1011_SPK_TEMP_PROTECT_6:
713 	case RT1011_SPK_PRO_DC_DET_3:
714 	case RT1011_SPK_PRO_DC_DET_7:
715 	case RT1011_SPK_PRO_DC_DET_8:
716 	case RT1011_SPL_1:
717 	case RT1011_SPL_4:
718 	case RT1011_EXCUR_PROTECT_1:
719 	case RT1011_CROSS_BQ_SET_1:
720 	case RT1011_CROSS_BQ_SET_2:
721 	case RT1011_BQ_SET_0:
722 	case RT1011_BQ_SET_1:
723 	case RT1011_BQ_SET_2:
724 	case RT1011_TEST_PAD_STATUS:
725 	case RT1011_DC_CALIB_CLASSD_1:
726 	case RT1011_DC_CALIB_CLASSD_5:
727 	case RT1011_DC_CALIB_CLASSD_6:
728 	case RT1011_DC_CALIB_CLASSD_7:
729 	case RT1011_DC_CALIB_CLASSD_8:
730 	case RT1011_SINE_GEN_REG_2:
731 	case RT1011_STP_CALIB_RS_TEMP:
732 	case RT1011_SPK_RESISTANCE_1:
733 	case RT1011_SPK_RESISTANCE_2:
734 	case RT1011_SPK_THERMAL:
735 	case RT1011_ALC_BK_GAIN_O:
736 	case RT1011_ALC_BK_GAIN_O_PRE:
737 	case RT1011_SPK_DC_O_23_16:
738 	case RT1011_SPK_DC_O_15_0:
739 	case RT1011_INIT_RECIPROCAL_SYN_24_16:
740 	case RT1011_INIT_RECIPROCAL_SYN_15_0:
741 	case RT1011_SPK_EXCURSION_23_16:
742 	case RT1011_SPK_EXCURSION_15_0:
743 	case RT1011_SEP_MAIN_OUT_23_16:
744 	case RT1011_SEP_MAIN_OUT_15_0:
745 	case RT1011_ALC_DRC_HB_INTERNAL_5:
746 	case RT1011_ALC_DRC_HB_INTERNAL_6:
747 	case RT1011_ALC_DRC_HB_INTERNAL_7:
748 	case RT1011_ALC_DRC_BB_INTERNAL_5:
749 	case RT1011_ALC_DRC_BB_INTERNAL_6:
750 	case RT1011_ALC_DRC_BB_INTERNAL_7:
751 	case RT1011_ALC_DRC_POS_INTERNAL_5:
752 	case RT1011_ALC_DRC_POS_INTERNAL_6:
753 	case RT1011_ALC_DRC_POS_INTERNAL_7:
754 	case RT1011_ALC_DRC_POS_INTERNAL_8:
755 	case RT1011_ALC_DRC_POS_INTERNAL_9:
756 	case RT1011_ALC_DRC_POS_INTERNAL_10:
757 	case RT1011_ALC_DRC_POS_INTERNAL_11:
758 	case RT1011_IRQ_1:
759 	case RT1011_EFUSE_CONTROL_1:
760 	case RT1011_EFUSE_CONTROL_2:
761 	case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
762 		return true;
763 
764 	default:
765 		return false;
766 	}
767 }
768 
769 static bool rt1011_readable_register(struct device *dev, unsigned int reg)
770 {
771 	switch (reg) {
772 	case RT1011_RESET:
773 	case RT1011_CLK_1:
774 	case RT1011_CLK_2:
775 	case RT1011_CLK_3:
776 	case RT1011_CLK_4:
777 	case RT1011_PLL_1:
778 	case RT1011_PLL_2:
779 	case RT1011_SRC_1:
780 	case RT1011_SRC_2:
781 	case RT1011_SRC_3:
782 	case RT1011_CLK_DET:
783 	case RT1011_SIL_DET:
784 	case RT1011_PRIV_INDEX:
785 	case RT1011_PRIV_DATA:
786 	case RT1011_CUSTOMER_ID:
787 	case RT1011_FM_VER:
788 	case RT1011_VERSION_ID:
789 	case RT1011_VENDOR_ID:
790 	case RT1011_DEVICE_ID:
791 	case RT1011_DUM_RW_0:
792 	case RT1011_DUM_YUN:
793 	case RT1011_DUM_RW_1:
794 	case RT1011_DUM_RO:
795 	case RT1011_MAN_I2C_DEV:
796 	case RT1011_DAC_SET_1:
797 	case RT1011_DAC_SET_2:
798 	case RT1011_DAC_SET_3:
799 	case RT1011_ADC_SET:
800 	case RT1011_ADC_SET_1:
801 	case RT1011_ADC_SET_2:
802 	case RT1011_ADC_SET_3:
803 	case RT1011_ADC_SET_4:
804 	case RT1011_ADC_SET_5:
805 	case RT1011_TDM_TOTAL_SET:
806 	case RT1011_TDM1_SET_TCON:
807 	case RT1011_TDM1_SET_1:
808 	case RT1011_TDM1_SET_2:
809 	case RT1011_TDM1_SET_3:
810 	case RT1011_TDM1_SET_4:
811 	case RT1011_TDM1_SET_5:
812 	case RT1011_TDM2_SET_1:
813 	case RT1011_TDM2_SET_2:
814 	case RT1011_TDM2_SET_3:
815 	case RT1011_TDM2_SET_4:
816 	case RT1011_TDM2_SET_5:
817 	case RT1011_PWM_CAL:
818 	case RT1011_MIXER_1:
819 	case RT1011_MIXER_2:
820 	case RT1011_ADRC_LIMIT:
821 	case RT1011_A_PRO:
822 	case RT1011_A_TIMING_1:
823 	case RT1011_A_TIMING_2:
824 	case RT1011_A_TEMP_SEN:
825 	case RT1011_SPK_VOL_DET_1:
826 	case RT1011_SPK_VOL_DET_2:
827 	case RT1011_SPK_VOL_TEST_OUT:
828 	case RT1011_VBAT_VOL_DET_1:
829 	case RT1011_VBAT_VOL_DET_2:
830 	case RT1011_VBAT_TEST_OUT_1:
831 	case RT1011_VBAT_TEST_OUT_2:
832 	case RT1011_VBAT_PROTECTION:
833 	case RT1011_VBAT_DET:
834 	case RT1011_POWER_1:
835 	case RT1011_POWER_2:
836 	case RT1011_POWER_3:
837 	case RT1011_POWER_4:
838 	case RT1011_POWER_5:
839 	case RT1011_POWER_6:
840 	case RT1011_POWER_7:
841 	case RT1011_POWER_8:
842 	case RT1011_POWER_9:
843 	case RT1011_CLASS_D_POS:
844 	case RT1011_BOOST_CON_1:
845 	case RT1011_BOOST_CON_2:
846 	case RT1011_ANALOG_CTRL:
847 	case RT1011_POWER_SEQ:
848 	case RT1011_SHORT_CIRCUIT_DET_1:
849 	case RT1011_SHORT_CIRCUIT_DET_2:
850 	case RT1011_SPK_TEMP_PROTECT_0:
851 	case RT1011_SPK_TEMP_PROTECT_1:
852 	case RT1011_SPK_TEMP_PROTECT_2:
853 	case RT1011_SPK_TEMP_PROTECT_3:
854 	case RT1011_SPK_TEMP_PROTECT_4:
855 	case RT1011_SPK_TEMP_PROTECT_5:
856 	case RT1011_SPK_TEMP_PROTECT_6:
857 	case RT1011_SPK_TEMP_PROTECT_7:
858 	case RT1011_SPK_TEMP_PROTECT_8:
859 	case RT1011_SPK_TEMP_PROTECT_9:
860 	case RT1011_SPK_PRO_DC_DET_1:
861 	case RT1011_SPK_PRO_DC_DET_2:
862 	case RT1011_SPK_PRO_DC_DET_3:
863 	case RT1011_SPK_PRO_DC_DET_4:
864 	case RT1011_SPK_PRO_DC_DET_5:
865 	case RT1011_SPK_PRO_DC_DET_6:
866 	case RT1011_SPK_PRO_DC_DET_7:
867 	case RT1011_SPK_PRO_DC_DET_8:
868 	case RT1011_SPL_1:
869 	case RT1011_SPL_2:
870 	case RT1011_SPL_3:
871 	case RT1011_SPL_4:
872 	case RT1011_THER_FOLD_BACK_1:
873 	case RT1011_THER_FOLD_BACK_2:
874 	case RT1011_EXCUR_PROTECT_1:
875 	case RT1011_EXCUR_PROTECT_2:
876 	case RT1011_EXCUR_PROTECT_3:
877 	case RT1011_EXCUR_PROTECT_4:
878 	case RT1011_BAT_GAIN_1:
879 	case RT1011_BAT_GAIN_2:
880 	case RT1011_BAT_GAIN_3:
881 	case RT1011_BAT_GAIN_4:
882 	case RT1011_BAT_GAIN_5:
883 	case RT1011_BAT_GAIN_6:
884 	case RT1011_BAT_GAIN_7:
885 	case RT1011_BAT_GAIN_8:
886 	case RT1011_BAT_GAIN_9:
887 	case RT1011_BAT_GAIN_10:
888 	case RT1011_BAT_GAIN_11:
889 	case RT1011_BAT_RT_THMAX_1:
890 	case RT1011_BAT_RT_THMAX_2:
891 	case RT1011_BAT_RT_THMAX_3:
892 	case RT1011_BAT_RT_THMAX_4:
893 	case RT1011_BAT_RT_THMAX_5:
894 	case RT1011_BAT_RT_THMAX_6:
895 	case RT1011_BAT_RT_THMAX_7:
896 	case RT1011_BAT_RT_THMAX_8:
897 	case RT1011_BAT_RT_THMAX_9:
898 	case RT1011_BAT_RT_THMAX_10:
899 	case RT1011_BAT_RT_THMAX_11:
900 	case RT1011_BAT_RT_THMAX_12:
901 	case RT1011_SPREAD_SPECTURM:
902 	case RT1011_PRO_GAIN_MODE:
903 	case RT1011_RT_DRC_CROSS:
904 	case RT1011_RT_DRC_HB_1:
905 	case RT1011_RT_DRC_HB_2:
906 	case RT1011_RT_DRC_HB_3:
907 	case RT1011_RT_DRC_HB_4:
908 	case RT1011_RT_DRC_HB_5:
909 	case RT1011_RT_DRC_HB_6:
910 	case RT1011_RT_DRC_HB_7:
911 	case RT1011_RT_DRC_HB_8:
912 	case RT1011_RT_DRC_BB_1:
913 	case RT1011_RT_DRC_BB_2:
914 	case RT1011_RT_DRC_BB_3:
915 	case RT1011_RT_DRC_BB_4:
916 	case RT1011_RT_DRC_BB_5:
917 	case RT1011_RT_DRC_BB_6:
918 	case RT1011_RT_DRC_BB_7:
919 	case RT1011_RT_DRC_BB_8:
920 	case RT1011_RT_DRC_POS_1:
921 	case RT1011_RT_DRC_POS_2:
922 	case RT1011_RT_DRC_POS_3:
923 	case RT1011_RT_DRC_POS_4:
924 	case RT1011_RT_DRC_POS_5:
925 	case RT1011_RT_DRC_POS_6:
926 	case RT1011_RT_DRC_POS_7:
927 	case RT1011_RT_DRC_POS_8:
928 	case RT1011_CROSS_BQ_SET_1:
929 	case RT1011_CROSS_BQ_SET_2:
930 	case RT1011_BQ_SET_0:
931 	case RT1011_BQ_SET_1:
932 	case RT1011_BQ_SET_2:
933 	case RT1011_BQ_PRE_GAIN_28_16:
934 	case RT1011_BQ_PRE_GAIN_15_0:
935 	case RT1011_BQ_POST_GAIN_28_16:
936 	case RT1011_BQ_POST_GAIN_15_0:
937 	case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
938 	case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
939 	case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
940 	case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
941 	case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
942 	case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
943 	case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
944 	case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
945 	case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
946 	case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
947 	case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
948 	case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
949 	case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
950 	case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
951 	case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
952 	case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
953 	case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
954 	case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
955 	case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
956 	case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
957 	case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
958 	case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
959 	case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
960 	case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
961 	case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
962 	case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
963 	case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
964 	case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
965 	case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
966 	case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
967 	case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
968 	case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
969 	case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
970 	case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
971 	case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
972 	case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
973 	case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
974 		return true;
975 	default:
976 		return false;
977 	}
978 }
979 
980 static const char * const rt1011_din_source_select[] = {
981 	"Left",
982 	"Right",
983 	"Left + Right average",
984 };
985 
986 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
987 	rt1011_din_source_select);
988 
989 static const char * const rt1011_tdm_data_out_select[] = {
990 	"TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
991 	"ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
992 	"SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
993 };
994 
995 static const char * const rt1011_tdm_l_ch_data_select[] = {
996 	"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
997 };
998 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
999 	rt1011_tdm_l_ch_data_select);
1000 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
1001 	rt1011_tdm_l_ch_data_select);
1002 
1003 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1004 	RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1005 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1006 	rt1011_tdm_l_ch_data_select);
1007 
1008 static const char * const rt1011_adc_data_mode_select[] = {
1009 	"Stereo", "Mono"
1010 };
1011 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1012 	rt1011_adc_data_mode_select);
1013 
1014 static const char * const rt1011_tdm_adc_data_len_control[] = {
1015 	"1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1016 };
1017 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1018 	rt1011_tdm_adc_data_len_control);
1019 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1020 	rt1011_tdm_adc_data_len_control);
1021 
1022 static const char * const rt1011_tdm_adc_swap_select[] = {
1023 	"L/R", "R/L", "L/L", "R/R"
1024 };
1025 
1026 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1027 	rt1011_tdm_adc_swap_select);
1028 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
1029 	rt1011_tdm_adc_swap_select);
1030 
1031 static void rt1011_reset(struct regmap *regmap)
1032 {
1033 	regmap_write(regmap, RT1011_RESET, 0);
1034 }
1035 
1036 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1037 		struct snd_ctl_elem_value *ucontrol)
1038 {
1039 	struct snd_soc_component *component =
1040 		snd_soc_kcontrol_component(kcontrol);
1041 	struct rt1011_priv *rt1011 =
1042 		snd_soc_component_get_drvdata(component);
1043 
1044 	ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1045 
1046 	return 0;
1047 }
1048 
1049 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1050 		struct snd_ctl_elem_value *ucontrol)
1051 {
1052 	struct snd_soc_component *component =
1053 		snd_soc_kcontrol_component(kcontrol);
1054 	struct rt1011_priv *rt1011 =
1055 		snd_soc_component_get_drvdata(component);
1056 
1057 	if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1058 		return 0;
1059 
1060 	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1061 		rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1062 
1063 		if (rt1011->recv_spk_mode) {
1064 
1065 			/* 1: recevier mode on */
1066 			snd_soc_component_update_bits(component,
1067 				RT1011_CLASSD_INTERNAL_SET_3,
1068 				RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1069 				RT1011_REG_GAIN_CLASSD_RI_410K);
1070 			snd_soc_component_update_bits(component,
1071 				RT1011_CLASSD_INTERNAL_SET_1,
1072 				RT1011_RECV_MODE_SPK_MASK,
1073 				RT1011_RECV_MODE);
1074 		} else {
1075 			/* 0: speaker mode on */
1076 			snd_soc_component_update_bits(component,
1077 				RT1011_CLASSD_INTERNAL_SET_3,
1078 				RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1079 				RT1011_REG_GAIN_CLASSD_RI_72P5K);
1080 			snd_soc_component_update_bits(component,
1081 				RT1011_CLASSD_INTERNAL_SET_1,
1082 				RT1011_RECV_MODE_SPK_MASK,
1083 				RT1011_SPK_MODE);
1084 		}
1085 	}
1086 
1087 	return 0;
1088 }
1089 
1090 static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1091 {
1092 	if ((reg == RT1011_DAC_SET_1) |
1093 		(reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) |
1094 		(reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) |
1095 		(reg == RT1011_MIXER_1) |
1096 		(reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 &&
1097 		reg <= RT1011_POWER_8) |
1098 		(reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) |
1099 		(reg >= RT1011_SPK_TEMP_PROTECT_0 &&
1100 		reg <= RT1011_SPK_TEMP_PROTECT_6) |
1101 		(reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) |
1102 		(reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) |
1103 		(reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) |
1104 		(reg >= RT1011_SMART_BOOST_TIMING_1 &&
1105 		reg <= RT1011_SMART_BOOST_TIMING_36) |
1106 		(reg == RT1011_SINE_GEN_REG_1) |
1107 		(reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB &&
1108 		reg <= RT1011_BQ_6_PARAMS_CHECK_5) |
1109 		(reg >= RT1011_BQ_7_PARAMS_CHECK_1 &&
1110 		reg <= RT1011_BQ_10_PARAMS_CHECK_5))
1111 		return true;
1112 
1113 	return false;
1114 }
1115 
1116 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1117 					struct snd_ctl_elem_value *ucontrol)
1118 {
1119 	struct snd_soc_component *component =
1120 		snd_soc_kcontrol_component(kcontrol);
1121 	struct rt1011_priv *rt1011 =
1122 		snd_soc_component_get_drvdata(component);
1123 	struct rt1011_bq_drc_params *bq_drc_info;
1124 	struct rt1011_bq_drc_params *params =
1125 		(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1126 	unsigned int i, mode_idx = 0;
1127 
1128 	if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1129 		mode_idx = RT1011_ADVMODE_INITIAL_SET;
1130 	else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1131 		mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1132 	else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1133 		mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1134 	else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1135 		mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1136 	else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1137 		mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1138 	else
1139 		return -EINVAL;
1140 
1141 	pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1142 		ucontrol->id.name, mode_idx);
1143 	bq_drc_info = rt1011->bq_drc_params[mode_idx];
1144 
1145 	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1146 		params[i].reg = bq_drc_info[i].reg;
1147 		params[i].val = bq_drc_info[i].val;
1148 	}
1149 
1150 	return 0;
1151 }
1152 
1153 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1154 					struct snd_ctl_elem_value *ucontrol)
1155 {
1156 	struct snd_soc_component *component =
1157 		snd_soc_kcontrol_component(kcontrol);
1158 	struct rt1011_priv *rt1011 =
1159 		snd_soc_component_get_drvdata(component);
1160 	struct rt1011_bq_drc_params *bq_drc_info;
1161 	struct rt1011_bq_drc_params *params =
1162 		(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1163 	unsigned int i, mode_idx = 0;
1164 
1165 	if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1166 		mode_idx = RT1011_ADVMODE_INITIAL_SET;
1167 	else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1168 		mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1169 	else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1170 		mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1171 	else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1172 		mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1173 	else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1174 		mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1175 	else
1176 		return -EINVAL;
1177 
1178 	bq_drc_info = rt1011->bq_drc_params[mode_idx];
1179 	memset(bq_drc_info, 0,
1180 		sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1181 
1182 	pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1183 		ucontrol->id.name, mode_idx);
1184 	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1185 		bq_drc_info[i].reg = params[i].reg;
1186 		bq_drc_info[i].val = params[i].val;
1187 	}
1188 
1189 	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1190 		if (bq_drc_info[i].reg == 0)
1191 			break;
1192 		else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1193 			snd_soc_component_write(component, bq_drc_info[i].reg,
1194 					bq_drc_info[i].val);
1195 		}
1196 	}
1197 
1198 	return 0;
1199 }
1200 
1201 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1202 			 struct snd_ctl_elem_info *uinfo)
1203 {
1204 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1205 	uinfo->count = 128;
1206 	uinfo->value.integer.max = 0x17ffffff;
1207 
1208 	return 0;
1209 }
1210 
1211 #define RT1011_BQ_DRC(xname) \
1212 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1213 	.info = rt1011_bq_drc_info, \
1214 	.get = rt1011_bq_drc_coeff_get, \
1215 	.put = rt1011_bq_drc_coeff_put \
1216 }
1217 
1218 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1219 		struct snd_ctl_elem_value *ucontrol)
1220 {
1221 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1222 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1223 
1224 	ucontrol->value.integer.value[0] = rt1011->cali_done;
1225 
1226 	return 0;
1227 }
1228 
1229 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1230 		struct snd_ctl_elem_value *ucontrol)
1231 {
1232 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1233 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1234 
1235 	rt1011->cali_done = 0;
1236 	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1237 		ucontrol->value.integer.value[0])
1238 		rt1011_calibrate(rt1011, 1);
1239 
1240 	return 0;
1241 }
1242 
1243 static int rt1011_r0_load(struct rt1011_priv *rt1011)
1244 {
1245 	if (!rt1011->r0_reg)
1246 		return -EINVAL;
1247 
1248 	/* write R0 to register */
1249 	regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1250 		((rt1011->r0_reg>>16) & 0x1ff));
1251 	regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1252 		(rt1011->r0_reg & 0xffff));
1253 	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1254 
1255 	return 0;
1256 }
1257 
1258 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1259 		struct snd_ctl_elem_value *ucontrol)
1260 {
1261 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1262 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1263 
1264 	ucontrol->value.integer.value[0] = rt1011->r0_reg;
1265 
1266 	return 0;
1267 }
1268 
1269 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1270 		struct snd_ctl_elem_value *ucontrol)
1271 {
1272 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1273 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1274 	struct device *dev;
1275 	unsigned int r0_integer, r0_factor, format;
1276 
1277 	if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1278 		return 0;
1279 
1280 	if (ucontrol->value.integer.value[0] == 0)
1281 		return -EINVAL;
1282 
1283 	dev = regmap_get_device(rt1011->regmap);
1284 	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1285 		rt1011->r0_reg = ucontrol->value.integer.value[0];
1286 
1287 		format = 2147483648U; /* 2^24 * 128 */
1288 		r0_integer = format / rt1011->r0_reg / 128;
1289 		r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1290 						- (r0_integer * 100);
1291 		dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1292 			r0_integer, r0_factor, rt1011->r0_reg);
1293 
1294 		if (rt1011->r0_reg)
1295 			rt1011_r0_load(rt1011);
1296 	}
1297 
1298 	return 0;
1299 }
1300 
1301 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1302 			 struct snd_ctl_elem_info *uinfo)
1303 {
1304 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1305 	uinfo->count = 1;
1306 	uinfo->value.integer.max = 0x1ffffff;
1307 
1308 	return 0;
1309 }
1310 
1311 #define RT1011_R0_LOAD(xname) \
1312 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1313 	.info = rt1011_r0_load_info, \
1314 	.get = rt1011_r0_load_mode_get, \
1315 	.put = rt1011_r0_load_mode_put \
1316 }
1317 
1318 static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1319 	/* I2S Data In Selection */
1320 	SOC_ENUM("DIN Source", rt1011_din_source_enum),
1321 
1322 	/* TDM Data In Selection */
1323 	SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1324 	SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1325 
1326 	/* TDM1 Data Out Selection */
1327 	SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1328 	SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1329 	SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
1330 	SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
1331 
1332 	/* Data Out Mode */
1333 	SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1334 	SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1335 	SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1336 
1337 	/* Speaker/Receiver Mode */
1338 	SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1339 		rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1340 
1341 	/* BiQuad/DRC/SmartBoost Settings */
1342 	RT1011_BQ_DRC("AdvanceMode Initial Set"),
1343 	RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1344 	RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1345 	RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1346 	RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1347 
1348 	/* R0 */
1349 	SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1350 		rt1011_r0_cali_get, rt1011_r0_cali_put),
1351 	RT1011_R0_LOAD("R0 Load Mode"),
1352 
1353 	/* R0 temperature */
1354 	SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
1355 		2, 255, 0),
1356 };
1357 
1358 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1359 			 struct snd_soc_dapm_widget *sink)
1360 {
1361 	struct snd_soc_component *component =
1362 		snd_soc_dapm_to_component(source->dapm);
1363 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1364 
1365 	if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1366 		return 1;
1367 	else
1368 		return 0;
1369 }
1370 
1371 static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1372 	struct snd_kcontrol *kcontrol, int event)
1373 {
1374 	struct snd_soc_component *component =
1375 		snd_soc_dapm_to_component(w->dapm);
1376 
1377 	switch (event) {
1378 	case SND_SOC_DAPM_POST_PMU:
1379 		snd_soc_component_update_bits(component,
1380 			RT1011_SPK_TEMP_PROTECT_0,
1381 			RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1382 			RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1383 		snd_soc_component_update_bits(component, RT1011_POWER_9,
1384 			RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1385 		msleep(50);
1386 		snd_soc_component_update_bits(component,
1387 			RT1011_CLASSD_INTERNAL_SET_1,
1388 			RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1389 		break;
1390 	case SND_SOC_DAPM_PRE_PMD:
1391 		snd_soc_component_update_bits(component, RT1011_POWER_9,
1392 			RT1011_POW_MNL_SDB_MASK, 0);
1393 		snd_soc_component_update_bits(component,
1394 			RT1011_SPK_TEMP_PROTECT_0,
1395 			RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1396 		msleep(200);
1397 		snd_soc_component_update_bits(component,
1398 			RT1011_CLASSD_INTERNAL_SET_1,
1399 			RT1011_DRIVER_READY_SPK, 0);
1400 		break;
1401 
1402 	default:
1403 		return 0;
1404 	}
1405 
1406 	return 0;
1407 }
1408 
1409 
1410 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1411 	SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1412 		RT1011_POW_LDO2_BIT, 0, NULL, 0),
1413 	SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1414 		RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1415 	SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1416 		RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1417 
1418 	SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1419 		RT1011_PLLEN_BIT, 0, NULL, 0),
1420 	SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1421 		RT1011_POW_BG_BIT, 0, NULL, 0),
1422 	SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1423 		RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1424 
1425 	SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1426 		RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1427 	SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1428 		RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1429 	SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1430 		RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1431 	SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1432 		RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1433 	SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1434 		RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1435 	SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1436 		RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1437 	SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1438 		RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1439 	SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1440 		RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1441 	SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1442 		RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1443 	SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1444 		RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1445 	SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1446 		RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1447 	SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1448 		RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1449 
1450 	SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1451 		RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1452 	SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1453 		RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1454 	SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1455 		RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1456 
1457 	SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1458 		RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1459 
1460 	/* Audio Interface */
1461 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1462 	/* Digital Interface */
1463 	SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1464 		RT1011_POW_DAC_BIT, 0, NULL, 0),
1465 	SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1466 		RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1467 	SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1468 		RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1469 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1470 
1471 	/* Output Lines */
1472 	SND_SOC_DAPM_OUTPUT("SPO"),
1473 };
1474 
1475 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1476 
1477 	{ "DAC", NULL, "AIF1RX" },
1478 	{ "DAC", NULL, "DAC Power" },
1479 	{ "DAC", NULL, "LDO2" },
1480 	{ "DAC", NULL, "ISENSE SPK" },
1481 	{ "DAC", NULL, "VSENSE SPK" },
1482 	{ "DAC", NULL, "CLK12M" },
1483 
1484 	{ "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1485 	{ "DAC", NULL, "BG" },
1486 	{ "DAC", NULL, "BG MBIAS" },
1487 
1488 	{ "DAC", NULL, "BOOST SWR" },
1489 	{ "DAC", NULL, "BGOK SWR" },
1490 	{ "DAC", NULL, "VPOK SWR" },
1491 
1492 	{ "DAC", NULL, "DET VBAT" },
1493 	{ "DAC", NULL, "MBIAS" },
1494 	{ "DAC", NULL, "VREF" },
1495 	{ "DAC", NULL, "ADC I" },
1496 	{ "DAC", NULL, "ADC V" },
1497 	{ "DAC", NULL, "ADC T" },
1498 	{ "DAC", NULL, "DITHER ADC T" },
1499 	{ "DAC", NULL, "MIX I" },
1500 	{ "DAC", NULL, "MIX V" },
1501 	{ "DAC", NULL, "SUM I" },
1502 	{ "DAC", NULL, "SUM V" },
1503 	{ "DAC", NULL, "MIX T" },
1504 
1505 	{ "DAC", NULL, "TEMP REG" },
1506 
1507 	{ "SPO", NULL, "DAC" },
1508 };
1509 
1510 static int rt1011_get_clk_info(int sclk, int rate)
1511 {
1512 	int i;
1513 	static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1514 
1515 	if (sclk <= 0 || rate <= 0)
1516 		return -EINVAL;
1517 
1518 	rate = rate << 8;
1519 	for (i = 0; i < ARRAY_SIZE(pd); i++)
1520 		if (sclk == rate * pd[i])
1521 			return i;
1522 
1523 	return -EINVAL;
1524 }
1525 
1526 static int rt1011_hw_params(struct snd_pcm_substream *substream,
1527 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1528 {
1529 	struct snd_soc_component *component = dai->component;
1530 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1531 	unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1532 	int pre_div, bclk_ms, frame_size;
1533 
1534 	rt1011->lrck = params_rate(params);
1535 	pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1536 	if (pre_div < 0) {
1537 		dev_warn(component->dev, "Force using PLL ");
1538 		snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1539 			rt1011->lrck * 64, rt1011->lrck * 256);
1540 		snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1541 			rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1542 		pre_div = 0;
1543 	}
1544 	frame_size = snd_soc_params_to_frame_size(params);
1545 	if (frame_size < 0) {
1546 		dev_err(component->dev, "Unsupported frame size: %d\n",
1547 			frame_size);
1548 		return -EINVAL;
1549 	}
1550 
1551 	bclk_ms = frame_size > 32;
1552 	rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1553 
1554 	dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1555 				bclk_ms, pre_div, dai->id);
1556 
1557 	dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1558 				rt1011->lrck, pre_div, dai->id);
1559 
1560 	switch (params_width(params)) {
1561 	case 16:
1562 		val_len |= RT1011_I2S_TX_DL_16B;
1563 		val_len |= RT1011_I2S_RX_DL_16B;
1564 		ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1565 		ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1566 		break;
1567 	case 20:
1568 		val_len |= RT1011_I2S_TX_DL_20B;
1569 		val_len |= RT1011_I2S_RX_DL_20B;
1570 		ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1571 		ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1572 		break;
1573 	case 24:
1574 		val_len |= RT1011_I2S_TX_DL_24B;
1575 		val_len |= RT1011_I2S_RX_DL_24B;
1576 		ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1577 		ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1578 		break;
1579 	case 32:
1580 		val_len |= RT1011_I2S_TX_DL_32B;
1581 		val_len |= RT1011_I2S_RX_DL_32B;
1582 		ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1583 		ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1584 		break;
1585 	case 8:
1586 		val_len |= RT1011_I2S_TX_DL_8B;
1587 		val_len |= RT1011_I2S_RX_DL_8B;
1588 		ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1589 		ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1590 		break;
1591 	default:
1592 		return -EINVAL;
1593 	}
1594 
1595 	switch (dai->id) {
1596 	case RT1011_AIF1:
1597 		mask_clk = RT1011_FS_SYS_DIV_MASK;
1598 		val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1599 		snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1600 			RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1601 			val_len);
1602 		snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1603 			RT1011_I2S_CH_TX_LEN_MASK |
1604 			RT1011_I2S_CH_RX_LEN_MASK,
1605 			ch_len);
1606 		break;
1607 	default:
1608 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1609 		return -EINVAL;
1610 	}
1611 
1612 	snd_soc_component_update_bits(component,
1613 		RT1011_CLK_2, mask_clk, val_clk);
1614 
1615 	return 0;
1616 }
1617 
1618 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1619 {
1620 	struct snd_soc_component *component = dai->component;
1621 	struct snd_soc_dapm_context *dapm =
1622 		snd_soc_component_get_dapm(component);
1623 	unsigned int reg_val = 0, reg_bclk_inv = 0;
1624 	int ret = 0;
1625 
1626 	snd_soc_dapm_mutex_lock(dapm);
1627 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1628 	case SND_SOC_DAIFMT_CBS_CFS:
1629 		reg_val |= RT1011_I2S_TDM_MS_S;
1630 		break;
1631 	default:
1632 		ret = -EINVAL;
1633 		goto _set_fmt_err_;
1634 	}
1635 
1636 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1637 	case SND_SOC_DAIFMT_NB_NF:
1638 		break;
1639 	case SND_SOC_DAIFMT_IB_NF:
1640 		reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1641 		break;
1642 	default:
1643 		ret = -EINVAL;
1644 		goto _set_fmt_err_;
1645 	}
1646 
1647 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1648 	case SND_SOC_DAIFMT_I2S:
1649 		break;
1650 	case SND_SOC_DAIFMT_LEFT_J:
1651 		reg_val |= RT1011_I2S_TDM_DF_LEFT;
1652 		break;
1653 	case SND_SOC_DAIFMT_DSP_A:
1654 		reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1655 		break;
1656 	case SND_SOC_DAIFMT_DSP_B:
1657 		reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1658 		break;
1659 	default:
1660 		ret = -EINVAL;
1661 		goto _set_fmt_err_;
1662 	}
1663 
1664 	switch (dai->id) {
1665 	case RT1011_AIF1:
1666 		snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1667 			RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1668 			reg_val);
1669 		snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1670 			RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1671 		snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1672 			RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1673 		break;
1674 	default:
1675 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1676 		ret = -EINVAL;
1677 	}
1678 
1679 _set_fmt_err_:
1680 	snd_soc_dapm_mutex_unlock(dapm);
1681 	return ret;
1682 }
1683 
1684 static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1685 		int clk_id, int source, unsigned int freq, int dir)
1686 {
1687 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1688 	unsigned int reg_val = 0;
1689 
1690 	if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1691 		return 0;
1692 
1693 	/* disable MCLK detect in default */
1694 	snd_soc_component_update_bits(component, RT1011_CLK_DET,
1695 			RT1011_EN_MCLK_DET_MASK, 0);
1696 
1697 	switch (clk_id) {
1698 	case RT1011_FS_SYS_PRE_S_MCLK:
1699 		reg_val |= RT1011_FS_SYS_PRE_MCLK;
1700 		snd_soc_component_update_bits(component, RT1011_CLK_DET,
1701 			RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1702 		break;
1703 	case RT1011_FS_SYS_PRE_S_BCLK:
1704 		reg_val |= RT1011_FS_SYS_PRE_BCLK;
1705 		break;
1706 	case RT1011_FS_SYS_PRE_S_PLL1:
1707 		reg_val |= RT1011_FS_SYS_PRE_PLL1;
1708 		break;
1709 	case RT1011_FS_SYS_PRE_S_RCCLK:
1710 		reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1711 		break;
1712 	default:
1713 		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1714 		return -EINVAL;
1715 	}
1716 	snd_soc_component_update_bits(component, RT1011_CLK_2,
1717 		RT1011_FS_SYS_PRE_MASK, reg_val);
1718 	rt1011->sysclk = freq;
1719 	rt1011->sysclk_src = clk_id;
1720 
1721 	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1722 		freq, clk_id);
1723 
1724 	return 0;
1725 }
1726 
1727 static int rt1011_set_component_pll(struct snd_soc_component *component,
1728 		int pll_id, int source, unsigned int freq_in,
1729 		unsigned int freq_out)
1730 {
1731 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1732 	struct rl6231_pll_code pll_code;
1733 	int ret;
1734 
1735 	if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1736 	    freq_out == rt1011->pll_out)
1737 		return 0;
1738 
1739 	if (!freq_in || !freq_out) {
1740 		dev_dbg(component->dev, "PLL disabled\n");
1741 
1742 		rt1011->pll_in = 0;
1743 		rt1011->pll_out = 0;
1744 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1745 			RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1746 		return 0;
1747 	}
1748 
1749 	switch (source) {
1750 	case RT1011_PLL2_S_MCLK:
1751 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1752 			RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1753 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1754 			RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1755 		snd_soc_component_update_bits(component, RT1011_CLK_DET,
1756 			RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1757 		break;
1758 	case RT1011_PLL1_S_BCLK:
1759 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1760 				RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1761 		break;
1762 	case RT1011_PLL2_S_RCCLK:
1763 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1764 			RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1765 		snd_soc_component_update_bits(component, RT1011_CLK_2,
1766 			RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1767 		break;
1768 	default:
1769 		dev_err(component->dev, "Unknown PLL Source %d\n", source);
1770 		return -EINVAL;
1771 	}
1772 
1773 	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1774 	if (ret < 0) {
1775 		dev_err(component->dev, "Unsupported input clock %d\n",
1776 			freq_in);
1777 		return ret;
1778 	}
1779 
1780 	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1781 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1782 		pll_code.n_code, pll_code.k_code);
1783 
1784 	snd_soc_component_write(component, RT1011_PLL_1,
1785 		(pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT |
1786 		pll_code.m_bp << RT1011_PLL1_BPM_SFT | pll_code.n_code);
1787 	snd_soc_component_write(component, RT1011_PLL_2,
1788 		pll_code.k_code);
1789 
1790 	rt1011->pll_in = freq_in;
1791 	rt1011->pll_out = freq_out;
1792 	rt1011->pll_src = source;
1793 
1794 	return 0;
1795 }
1796 
1797 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1798 	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1799 {
1800 	struct snd_soc_component *component = dai->component;
1801 	struct snd_soc_dapm_context *dapm =
1802 		snd_soc_component_get_dapm(component);
1803 	unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
1804 	int ret = 0, first_bit, last_bit;
1805 
1806 	snd_soc_dapm_mutex_lock(dapm);
1807 	if (rx_mask || tx_mask)
1808 		tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1809 
1810 	switch (slots) {
1811 	case 4:
1812 		val |= RT1011_I2S_TX_4CH;
1813 		val |= RT1011_I2S_RX_4CH;
1814 		break;
1815 	case 6:
1816 		val |= RT1011_I2S_TX_6CH;
1817 		val |= RT1011_I2S_RX_6CH;
1818 		break;
1819 	case 8:
1820 		val |= RT1011_I2S_TX_8CH;
1821 		val |= RT1011_I2S_RX_8CH;
1822 		break;
1823 	case 2:
1824 		break;
1825 	default:
1826 		ret = -EINVAL;
1827 		goto _set_tdm_err_;
1828 	}
1829 
1830 	switch (slot_width) {
1831 	case 20:
1832 		val |= RT1011_I2S_CH_TX_LEN_20B;
1833 		val |= RT1011_I2S_CH_RX_LEN_20B;
1834 		break;
1835 	case 24:
1836 		val |= RT1011_I2S_CH_TX_LEN_24B;
1837 		val |= RT1011_I2S_CH_RX_LEN_24B;
1838 		break;
1839 	case 32:
1840 		val |= RT1011_I2S_CH_TX_LEN_32B;
1841 		val |= RT1011_I2S_CH_RX_LEN_32B;
1842 		break;
1843 	case 16:
1844 		break;
1845 	default:
1846 		ret = -EINVAL;
1847 		goto _set_tdm_err_;
1848 	}
1849 
1850 	/* Rx slot configuration */
1851 	rx_slotnum = hweight_long(rx_mask);
1852 	if (rx_slotnum > 1 || !rx_slotnum) {
1853 		ret = -EINVAL;
1854 		dev_err(component->dev, "too many rx slots or zero slot\n");
1855 		goto _set_tdm_err_;
1856 	}
1857 
1858 	first_bit = __ffs(rx_mask);
1859 	switch (first_bit) {
1860 	case 0:
1861 	case 2:
1862 	case 4:
1863 	case 6:
1864 		snd_soc_component_update_bits(component,
1865 			RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1866 			RT1011_MONO_L_CHANNEL);
1867 		snd_soc_component_update_bits(component,
1868 			RT1011_TDM1_SET_4,
1869 			RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1870 			RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1871 			(first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1872 			((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1873 		break;
1874 	case 1:
1875 	case 3:
1876 	case 5:
1877 	case 7:
1878 		snd_soc_component_update_bits(component,
1879 			RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1880 			RT1011_MONO_R_CHANNEL);
1881 		snd_soc_component_update_bits(component,
1882 			RT1011_TDM1_SET_4,
1883 			RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1884 			RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1885 			((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1886 			(first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1887 		break;
1888 	default:
1889 		ret = -EINVAL;
1890 		goto _set_tdm_err_;
1891 	}
1892 
1893 	/* Tx slot configuration */
1894 	tx_slotnum = hweight_long(tx_mask);
1895 	if (tx_slotnum > 2 || !tx_slotnum) {
1896 		ret = -EINVAL;
1897 		dev_err(component->dev, "too many tx slots or zero slot\n");
1898 		goto _set_tdm_err_;
1899 	}
1900 
1901 	first_bit = __ffs(tx_mask);
1902 	last_bit = __fls(tx_mask);
1903 	if (last_bit - first_bit > 1) {
1904 		ret = -EINVAL;
1905 		dev_err(component->dev, "tx slot location error\n");
1906 		goto _set_tdm_err_;
1907 	}
1908 
1909 	if (tx_slotnum == 1) {
1910 		snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1911 			RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1912 			RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
1913 		switch (first_bit) {
1914 		case 1:
1915 			snd_soc_component_update_bits(component,
1916 				RT1011_TDM1_SET_3,
1917 				RT1011_TDM_I2S_RX_ADC1_1_MASK,
1918 				RT1011_TDM_I2S_RX_ADC1_1_LL);
1919 			break;
1920 		case 3:
1921 			snd_soc_component_update_bits(component,
1922 				RT1011_TDM1_SET_3,
1923 				RT1011_TDM_I2S_RX_ADC2_1_MASK,
1924 				RT1011_TDM_I2S_RX_ADC2_1_LL);
1925 			break;
1926 		case 5:
1927 			snd_soc_component_update_bits(component,
1928 				RT1011_TDM1_SET_3,
1929 				RT1011_TDM_I2S_RX_ADC3_1_MASK,
1930 				RT1011_TDM_I2S_RX_ADC3_1_LL);
1931 			break;
1932 		case 7:
1933 			snd_soc_component_update_bits(component,
1934 				RT1011_TDM1_SET_3,
1935 				RT1011_TDM_I2S_RX_ADC4_1_MASK,
1936 				RT1011_TDM_I2S_RX_ADC4_1_LL);
1937 			break;
1938 		case 0:
1939 			snd_soc_component_update_bits(component,
1940 				RT1011_TDM1_SET_3,
1941 				RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
1942 			break;
1943 		case 2:
1944 			snd_soc_component_update_bits(component,
1945 				RT1011_TDM1_SET_3,
1946 				RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
1947 			break;
1948 		case 4:
1949 			snd_soc_component_update_bits(component,
1950 				RT1011_TDM1_SET_3,
1951 				RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
1952 			break;
1953 		case 6:
1954 			snd_soc_component_update_bits(component,
1955 				RT1011_TDM1_SET_3,
1956 				RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
1957 			break;
1958 		default:
1959 			ret = -EINVAL;
1960 			dev_dbg(component->dev,
1961 				"tx slot location error\n");
1962 			goto _set_tdm_err_;
1963 		}
1964 	} else if (tx_slotnum == 2) {
1965 		switch (first_bit) {
1966 		case 0:
1967 		case 2:
1968 		case 4:
1969 		case 6:
1970 			snd_soc_component_update_bits(component,
1971 				RT1011_TDM1_SET_2,
1972 				RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1973 				RT1011_TDM_ADCDAT1_DATA_LOCATION,
1974 				RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
1975 			break;
1976 		default:
1977 			ret = -EINVAL;
1978 			dev_dbg(component->dev,
1979 				"tx slot location should be paired and start from slot0/2/4/6\n");
1980 			goto _set_tdm_err_;
1981 		}
1982 	}
1983 
1984 	snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1985 		RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1986 		RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1987 	snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1988 		RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1989 		RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1990 	snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1991 		RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
1992 	snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
1993 		RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
1994 	if (tx_slotnum)
1995 		snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1996 			RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
1997 			RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
1998 
1999 _set_tdm_err_:
2000 	snd_soc_dapm_mutex_unlock(dapm);
2001 	return ret;
2002 }
2003 
2004 static int rt1011_probe(struct snd_soc_component *component)
2005 {
2006 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2007 	int i;
2008 
2009 	rt1011->component = component;
2010 
2011 	schedule_work(&rt1011->cali_work);
2012 
2013 	rt1011->bq_drc_params = devm_kcalloc(component->dev,
2014 		RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
2015 		GFP_KERNEL);
2016 	if (!rt1011->bq_drc_params)
2017 		return -ENOMEM;
2018 
2019 	for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
2020 		rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
2021 			RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
2022 			GFP_KERNEL);
2023 		if (!rt1011->bq_drc_params[i])
2024 			return -ENOMEM;
2025 	}
2026 
2027 	return 0;
2028 }
2029 
2030 static void rt1011_remove(struct snd_soc_component *component)
2031 {
2032 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2033 
2034 	cancel_work_sync(&rt1011->cali_work);
2035 	rt1011_reset(rt1011->regmap);
2036 }
2037 
2038 #ifdef CONFIG_PM
2039 static int rt1011_suspend(struct snd_soc_component *component)
2040 {
2041 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2042 
2043 	regcache_cache_only(rt1011->regmap, true);
2044 	regcache_mark_dirty(rt1011->regmap);
2045 
2046 	return 0;
2047 }
2048 
2049 static int rt1011_resume(struct snd_soc_component *component)
2050 {
2051 	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2052 
2053 	regcache_cache_only(rt1011->regmap, false);
2054 	regcache_sync(rt1011->regmap);
2055 
2056 	return 0;
2057 }
2058 #else
2059 #define rt1011_suspend NULL
2060 #define rt1011_resume NULL
2061 #endif
2062 
2063 static int rt1011_set_bias_level(struct snd_soc_component *component,
2064 				 enum snd_soc_bias_level level)
2065 {
2066 	switch (level) {
2067 	case SND_SOC_BIAS_OFF:
2068 		snd_soc_component_write(component,
2069 			RT1011_SYSTEM_RESET_1, 0x0000);
2070 		snd_soc_component_write(component,
2071 			RT1011_SYSTEM_RESET_2, 0x0000);
2072 		snd_soc_component_write(component,
2073 			RT1011_SYSTEM_RESET_3, 0x0001);
2074 		snd_soc_component_write(component,
2075 			RT1011_SYSTEM_RESET_1, 0x003f);
2076 		snd_soc_component_write(component,
2077 			RT1011_SYSTEM_RESET_2, 0x7fd7);
2078 		snd_soc_component_write(component,
2079 			RT1011_SYSTEM_RESET_3, 0x770f);
2080 		break;
2081 	default:
2082 		break;
2083 	}
2084 
2085 	return 0;
2086 }
2087 
2088 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2089 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
2090 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
2091 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2092 
2093 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
2094 	.hw_params = rt1011_hw_params,
2095 	.set_fmt = rt1011_set_dai_fmt,
2096 	.set_tdm_slot = rt1011_set_tdm_slot,
2097 };
2098 
2099 static struct snd_soc_dai_driver rt1011_dai[] = {
2100 	{
2101 		.name = "rt1011-aif",
2102 		.playback = {
2103 			.stream_name = "AIF1 Playback",
2104 			.channels_min = 1,
2105 			.channels_max = 2,
2106 			.rates = RT1011_STEREO_RATES,
2107 			.formats = RT1011_FORMATS,
2108 		},
2109 		.ops = &rt1011_aif_dai_ops,
2110 	},
2111 };
2112 
2113 static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
2114 	.probe = rt1011_probe,
2115 	.remove = rt1011_remove,
2116 	.suspend = rt1011_suspend,
2117 	.resume = rt1011_resume,
2118 	.set_bias_level = rt1011_set_bias_level,
2119 	.controls = rt1011_snd_controls,
2120 	.num_controls = ARRAY_SIZE(rt1011_snd_controls),
2121 	.dapm_widgets = rt1011_dapm_widgets,
2122 	.num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
2123 	.dapm_routes = rt1011_dapm_routes,
2124 	.num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
2125 	.set_sysclk = rt1011_set_component_sysclk,
2126 	.set_pll = rt1011_set_component_pll,
2127 	.use_pmdown_time = 1,
2128 	.endianness = 1,
2129 	.non_legacy_dai_naming = 1,
2130 };
2131 
2132 static const struct regmap_config rt1011_regmap = {
2133 	.reg_bits = 16,
2134 	.val_bits = 16,
2135 	.max_register = RT1011_MAX_REG + 1,
2136 	.volatile_reg = rt1011_volatile_register,
2137 	.readable_reg = rt1011_readable_register,
2138 	.cache_type = REGCACHE_RBTREE,
2139 	.reg_defaults = rt1011_reg,
2140 	.num_reg_defaults = ARRAY_SIZE(rt1011_reg),
2141 	.use_single_read = true,
2142 	.use_single_write = true,
2143 };
2144 
2145 #if defined(CONFIG_OF)
2146 static const struct of_device_id rt1011_of_match[] = {
2147 	{ .compatible = "realtek,rt1011", },
2148 	{},
2149 };
2150 MODULE_DEVICE_TABLE(of, rt1011_of_match);
2151 #endif
2152 
2153 #ifdef CONFIG_ACPI
2154 static struct acpi_device_id rt1011_acpi_match[] = {
2155 	{"10EC1011", 0,},
2156 	{},
2157 };
2158 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2159 #endif
2160 
2161 static const struct i2c_device_id rt1011_i2c_id[] = {
2162 	{ "rt1011", 0 },
2163 	{ }
2164 };
2165 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2166 
2167 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2168 {
2169 	unsigned int value, count = 0, r0[3];
2170 	unsigned int chk_cnt = 50; /* DONT change this */
2171 	unsigned int dc_offset;
2172 	unsigned int r0_integer, r0_factor, format;
2173 	struct device *dev = regmap_get_device(rt1011->regmap);
2174 	struct snd_soc_dapm_context *dapm =
2175 		snd_soc_component_get_dapm(rt1011->component);
2176 	int ret = 0;
2177 
2178 	snd_soc_dapm_mutex_lock(dapm);
2179 	regcache_cache_bypass(rt1011->regmap, true);
2180 
2181 	regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2182 	regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2183 	regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2184 
2185 	/* RC clock */
2186 	regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2187 	regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2188 	regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2189 	regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2190 
2191 	/* ADC/DAC setting */
2192 	regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2193 	regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
2194 	regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2195 
2196 	/* DC detection */
2197 	regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2198 	regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2199 
2200 	/* Power */
2201 	regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2202 	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2203 	regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2204 	regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2205 
2206 	/* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2207 	regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2208 	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2209 	regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2210 	regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2211 	regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2212 
2213 	/* DC offset from EFUSE */
2214 	regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2215 	regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2216 	regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2217 	regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2218 
2219 	/* mixer */
2220 	regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2221 
2222 	/* EFUSE read */
2223 	regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2224 	msleep(30);
2225 
2226 	regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2227 	dc_offset = value << 16;
2228 	regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2229 	dc_offset |= (value & 0xffff);
2230 	dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2231 	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2232 	dc_offset = value << 16;
2233 	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2234 	dc_offset |= (value & 0xffff);
2235 	dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2236 	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2237 	dc_offset = value << 16;
2238 	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2239 	dc_offset |= (value & 0xffff);
2240 	dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2241 
2242 	/* check the package info. */
2243 	regmap_read(rt1011->regmap, RT1011_EFUSE_MATCH_DONE, &value);
2244 	if (value & 0x4)
2245 		rt1011->pack_id = 1;
2246 
2247 	if (cali_flag) {
2248 
2249 		if (rt1011->pack_id)
2250 			regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x292c);
2251 		else
2252 			regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2253 
2254 		/* Class D on */
2255 		regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2256 		regmap_write(rt1011->regmap,
2257 			RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2258 
2259 		/* STP enable */
2260 		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2261 		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2262 		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2263 		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2264 		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2265 
2266 		r0[0] = r0[1] = r0[2] = count = 0;
2267 		while (count < chk_cnt) {
2268 			msleep(100);
2269 			regmap_read(rt1011->regmap,
2270 				RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2271 			r0[count%3] = value << 16;
2272 			regmap_read(rt1011->regmap,
2273 				RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2274 			r0[count%3] |= value;
2275 
2276 			if (r0[count%3] == 0)
2277 				continue;
2278 
2279 			count++;
2280 
2281 			if (r0[0] == r0[1] && r0[1] == r0[2])
2282 				break;
2283 		}
2284 		if (count > chk_cnt) {
2285 			dev_err(dev, "Calibrate R0 Failure\n");
2286 			ret = -EAGAIN;
2287 		} else {
2288 			format = 2147483648U; /* 2^24 * 128 */
2289 			r0_integer = format / r0[0] / 128;
2290 			r0_factor = ((format / r0[0] * 100) / 128)
2291 							- (r0_integer * 100);
2292 			rt1011->r0_reg = r0[0];
2293 			rt1011->cali_done = 1;
2294 			dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2295 				r0_integer, r0_factor, r0[0]);
2296 		}
2297 	}
2298 
2299 	/* depop */
2300 	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2301 	msleep(400);
2302 	regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2303 	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2304 	regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2305 	regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2306 	regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2307 	regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2308 	regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2309 	regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2310 	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2311 	regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2312 
2313 	regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2314 
2315 	if (cali_flag) {
2316 		if (count <= chk_cnt) {
2317 			regmap_write(rt1011->regmap,
2318 				RT1011_INIT_RECIPROCAL_REG_24_16,
2319 				((r0[0]>>16) & 0x1ff));
2320 			regmap_write(rt1011->regmap,
2321 				RT1011_INIT_RECIPROCAL_REG_15_0,
2322 				(r0[0] & 0xffff));
2323 			regmap_write(rt1011->regmap,
2324 				RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2325 		}
2326 	}
2327 
2328 	regcache_cache_bypass(rt1011->regmap, false);
2329 	regcache_mark_dirty(rt1011->regmap);
2330 	regcache_sync(rt1011->regmap);
2331 	snd_soc_dapm_mutex_unlock(dapm);
2332 
2333 	return ret;
2334 }
2335 
2336 static void rt1011_calibration_work(struct work_struct *work)
2337 {
2338 	struct rt1011_priv *rt1011 =
2339 		container_of(work, struct rt1011_priv, cali_work);
2340 	struct snd_soc_component *component = rt1011->component;
2341 	unsigned int r0_integer, r0_factor, format;
2342 
2343 	if (rt1011->r0_calib)
2344 		rt1011_calibrate(rt1011, 0);
2345 	else
2346 		rt1011_calibrate(rt1011, 1);
2347 
2348 	/*
2349 	 * This flag should reset after booting.
2350 	 * The factory test will do calibration again and use this flag to check
2351 	 * whether the calibration completed
2352 	 */
2353 	rt1011->cali_done = 0;
2354 
2355 	/* initial */
2356 	rt1011_reg_init(component);
2357 
2358 	/* Apply temperature and calibration data from device property */
2359 	if (rt1011->temperature_calib <= 0xff &&
2360 		rt1011->temperature_calib > 0) {
2361 		snd_soc_component_update_bits(component,
2362 			RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
2363 			(rt1011->temperature_calib << 2));
2364 	}
2365 
2366 	if (rt1011->r0_calib) {
2367 		rt1011->r0_reg = rt1011->r0_calib;
2368 
2369 		format = 2147483648U; /* 2^24 * 128 */
2370 		r0_integer = format / rt1011->r0_reg / 128;
2371 		r0_factor = ((format / rt1011->r0_reg * 100) / 128)
2372 						- (r0_integer * 100);
2373 		dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
2374 			r0_integer, r0_factor, rt1011->r0_reg);
2375 
2376 		rt1011_r0_load(rt1011);
2377 	}
2378 
2379 	if (rt1011->pack_id)
2380 		snd_soc_component_write(component, RT1011_ADC_SET_1, 0x292c);
2381 	else
2382 		snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
2383 }
2384 
2385 static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
2386 {
2387 	device_property_read_u32(dev, "realtek,temperature_calib",
2388 		&rt1011->temperature_calib);
2389 	device_property_read_u32(dev, "realtek,r0_calib",
2390 		&rt1011->r0_calib);
2391 
2392 	dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
2393 		__func__, rt1011->r0_calib, rt1011->temperature_calib);
2394 
2395 	return 0;
2396 }
2397 
2398 static int rt1011_i2c_probe(struct i2c_client *i2c,
2399 		    const struct i2c_device_id *id)
2400 {
2401 	struct rt1011_priv *rt1011;
2402 	int ret;
2403 	unsigned int val;
2404 
2405 	rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2406 				GFP_KERNEL);
2407 	if (!rt1011)
2408 		return -ENOMEM;
2409 
2410 	i2c_set_clientdata(i2c, rt1011);
2411 
2412 	rt1011_parse_dp(rt1011, &i2c->dev);
2413 
2414 	rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2415 	if (IS_ERR(rt1011->regmap)) {
2416 		ret = PTR_ERR(rt1011->regmap);
2417 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2418 			ret);
2419 		return ret;
2420 	}
2421 
2422 	regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2423 	if (val != RT1011_DEVICE_ID_NUM) {
2424 		dev_err(&i2c->dev,
2425 			"Device with ID register %x is not rt1011\n", val);
2426 		return -ENODEV;
2427 	}
2428 
2429 	INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2430 
2431 	return devm_snd_soc_register_component(&i2c->dev,
2432 		&soc_component_dev_rt1011,
2433 		rt1011_dai, ARRAY_SIZE(rt1011_dai));
2434 
2435 }
2436 
2437 static void rt1011_i2c_shutdown(struct i2c_client *client)
2438 {
2439 	struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2440 
2441 	rt1011_reset(rt1011->regmap);
2442 }
2443 
2444 static struct i2c_driver rt1011_i2c_driver = {
2445 	.driver = {
2446 		.name = "rt1011",
2447 		.of_match_table = of_match_ptr(rt1011_of_match),
2448 		.acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2449 	},
2450 	.probe = rt1011_i2c_probe,
2451 	.shutdown = rt1011_i2c_shutdown,
2452 	.id_table = rt1011_i2c_id,
2453 };
2454 module_i2c_driver(rt1011_i2c_driver);
2455 
2456 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2457 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2458 MODULE_LICENSE("GPL");
2459