1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver 4 * 5 * Copyright(c) 2019 Realtek Semiconductor Corp. 6 * 7 * Author: Shuming Fan <shumingf@realtek.com> 8 * 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/gpio.h> 17 #include <linux/i2c.h> 18 #include <linux/acpi.h> 19 #include <linux/regmap.h> 20 #include <linux/of_gpio.h> 21 #include <linux/platform_device.h> 22 #include <linux/firmware.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 31 #include "rl6231.h" 32 #include "rt1011.h" 33 34 static int rt1011_calibrate(struct rt1011_priv *rt1011, 35 unsigned char cali_flag); 36 37 static const struct reg_sequence init_list[] = { 38 39 { RT1011_POWER_9, 0xa840 }, 40 41 { RT1011_ADC_SET_5, 0x0a20 }, 42 { RT1011_DAC_SET_2, 0xa032 }, 43 { RT1011_ADC_SET_1, 0x2925 }, 44 45 { RT1011_SPK_PRO_DC_DET_1, 0xb00c }, 46 { RT1011_SPK_PRO_DC_DET_2, 0xcccc }, 47 48 { RT1011_A_TIMING_1, 0x6054 }, 49 50 { RT1011_POWER_7, 0x3e55 }, 51 { RT1011_POWER_8, 0x0520 }, 52 { RT1011_BOOST_CON_1, 0xe188 }, 53 { RT1011_POWER_4, 0x16f2 }, 54 55 { RT1011_CROSS_BQ_SET_1, 0x0004 }, 56 { RT1011_SIL_DET, 0xc313 }, 57 { RT1011_SINE_GEN_REG_1, 0x0707 }, 58 59 { RT1011_DC_CALIB_CLASSD_3, 0xcb00 }, 60 61 { RT1011_DAC_SET_1, 0xe702 }, 62 { RT1011_DAC_SET_3, 0x2004 }, 63 }; 64 65 static const struct reg_default rt1011_reg[] = { 66 {0x0000, 0x0000}, 67 {0x0002, 0x0000}, 68 {0x0004, 0xa000}, 69 {0x0006, 0x0000}, 70 {0x0008, 0x0003}, 71 {0x000a, 0x087e}, 72 {0x000c, 0x0020}, 73 {0x000e, 0x9002}, 74 {0x0010, 0x0000}, 75 {0x0012, 0x0000}, 76 {0x0020, 0x0c40}, 77 {0x0022, 0x4313}, 78 {0x0076, 0x0000}, 79 {0x0078, 0x0000}, 80 {0x007a, 0x0000}, 81 {0x007c, 0x10ec}, 82 {0x007d, 0x1011}, 83 {0x00f0, 0x5000}, 84 {0x00f2, 0x0374}, 85 {0x00f3, 0x0000}, 86 {0x00f4, 0x0000}, 87 {0x0100, 0x0038}, 88 {0x0102, 0xff02}, 89 {0x0104, 0x0232}, 90 {0x0106, 0x200c}, 91 {0x0107, 0x0000}, 92 {0x0108, 0x2f2f}, 93 {0x010a, 0x2f2f}, 94 {0x010c, 0x002f}, 95 {0x010e, 0xe000}, 96 {0x0110, 0x0820}, 97 {0x0111, 0x4010}, 98 {0x0112, 0x0000}, 99 {0x0114, 0x0000}, 100 {0x0116, 0x0000}, 101 {0x0118, 0x0000}, 102 {0x011a, 0x0101}, 103 {0x011c, 0x4567}, 104 {0x011e, 0x0000}, 105 {0x0120, 0x0000}, 106 {0x0122, 0x0000}, 107 {0x0124, 0x0123}, 108 {0x0126, 0x4567}, 109 {0x0200, 0x0000}, 110 {0x0300, 0xffdd}, 111 {0x0302, 0x001e}, 112 {0x0311, 0x0000}, 113 {0x0313, 0x5254}, 114 {0x0314, 0x0062}, 115 {0x0316, 0x7f40}, 116 {0x0319, 0x000f}, 117 {0x031a, 0xffff}, 118 {0x031b, 0x0000}, 119 {0x031c, 0x009f}, 120 {0x031d, 0xffff}, 121 {0x031e, 0x0000}, 122 {0x031f, 0x0000}, 123 {0x0320, 0xe31c}, 124 {0x0321, 0x0000}, 125 {0x0322, 0x0000}, 126 {0x0324, 0x0000}, 127 {0x0326, 0x0002}, 128 {0x0328, 0x20b2}, 129 {0x0329, 0x0175}, 130 {0x032a, 0x32ad}, 131 {0x032b, 0x3455}, 132 {0x032c, 0x0528}, 133 {0x032d, 0xa800}, 134 {0x032e, 0x030e}, 135 {0x0330, 0x2080}, 136 {0x0332, 0x0034}, 137 {0x0334, 0x0000}, 138 {0x0508, 0x0010}, 139 {0x050a, 0x0018}, 140 {0x050c, 0x0000}, 141 {0x050d, 0xffff}, 142 {0x050e, 0x1f1f}, 143 {0x050f, 0x04ff}, 144 {0x0510, 0x4020}, 145 {0x0511, 0x01f0}, 146 {0x0512, 0x0702}, 147 {0x0516, 0xbb80}, 148 {0x0517, 0xffff}, 149 {0x0518, 0xffff}, 150 {0x0519, 0x307f}, 151 {0x051a, 0xffff}, 152 {0x051b, 0x0000}, 153 {0x051c, 0x0000}, 154 {0x051d, 0x2000}, 155 {0x051e, 0x0000}, 156 {0x051f, 0x0000}, 157 {0x0520, 0x0000}, 158 {0x0521, 0x1001}, 159 {0x0522, 0x7fff}, 160 {0x0524, 0x7fff}, 161 {0x0526, 0x0000}, 162 {0x0528, 0x0000}, 163 {0x052a, 0x0000}, 164 {0x0530, 0x0401}, 165 {0x0532, 0x3000}, 166 {0x0534, 0x0000}, 167 {0x0535, 0xffff}, 168 {0x0536, 0x101c}, 169 {0x0538, 0x1814}, 170 {0x053a, 0x100c}, 171 {0x053c, 0x0804}, 172 {0x053d, 0x0000}, 173 {0x053e, 0x0000}, 174 {0x053f, 0x0000}, 175 {0x0540, 0x0000}, 176 {0x0541, 0x0000}, 177 {0x0542, 0x0000}, 178 {0x0543, 0x0000}, 179 {0x0544, 0x001c}, 180 {0x0545, 0x1814}, 181 {0x0546, 0x100c}, 182 {0x0547, 0x0804}, 183 {0x0548, 0x0000}, 184 {0x0549, 0x0000}, 185 {0x054a, 0x0000}, 186 {0x054b, 0x0000}, 187 {0x054c, 0x0000}, 188 {0x054d, 0x0000}, 189 {0x054e, 0x0000}, 190 {0x054f, 0x0000}, 191 {0x0566, 0x0000}, 192 {0x0568, 0x20f1}, 193 {0x056a, 0x0007}, 194 {0x0600, 0x9d00}, 195 {0x0611, 0x2000}, 196 {0x0612, 0x505f}, 197 {0x0613, 0x0444}, 198 {0x0614, 0x4000}, 199 {0x0615, 0x4004}, 200 {0x0616, 0x0606}, 201 {0x0617, 0x8904}, 202 {0x0618, 0xe021}, 203 {0x0621, 0x2000}, 204 {0x0622, 0x505f}, 205 {0x0623, 0x0444}, 206 {0x0624, 0x4000}, 207 {0x0625, 0x4004}, 208 {0x0626, 0x0606}, 209 {0x0627, 0x8704}, 210 {0x0628, 0xe021}, 211 {0x0631, 0x2000}, 212 {0x0632, 0x517f}, 213 {0x0633, 0x0440}, 214 {0x0634, 0x4000}, 215 {0x0635, 0x4104}, 216 {0x0636, 0x0306}, 217 {0x0637, 0x8904}, 218 {0x0638, 0xe021}, 219 {0x0702, 0x0014}, 220 {0x0704, 0x0000}, 221 {0x0706, 0x0014}, 222 {0x0708, 0x0000}, 223 {0x070a, 0x0000}, 224 {0x0710, 0x0200}, 225 {0x0711, 0x0000}, 226 {0x0712, 0x0200}, 227 {0x0713, 0x0000}, 228 {0x0720, 0x0200}, 229 {0x0721, 0x0000}, 230 {0x0722, 0x0000}, 231 {0x0723, 0x0000}, 232 {0x0724, 0x0000}, 233 {0x0725, 0x0000}, 234 {0x0726, 0x0000}, 235 {0x0727, 0x0000}, 236 {0x0728, 0x0000}, 237 {0x0729, 0x0000}, 238 {0x0730, 0x0200}, 239 {0x0731, 0x0000}, 240 {0x0732, 0x0000}, 241 {0x0733, 0x0000}, 242 {0x0734, 0x0000}, 243 {0x0735, 0x0000}, 244 {0x0736, 0x0000}, 245 {0x0737, 0x0000}, 246 {0x0738, 0x0000}, 247 {0x0739, 0x0000}, 248 {0x0740, 0x0200}, 249 {0x0741, 0x0000}, 250 {0x0742, 0x0000}, 251 {0x0743, 0x0000}, 252 {0x0744, 0x0000}, 253 {0x0745, 0x0000}, 254 {0x0746, 0x0000}, 255 {0x0747, 0x0000}, 256 {0x0748, 0x0000}, 257 {0x0749, 0x0000}, 258 {0x0750, 0x0200}, 259 {0x0751, 0x0000}, 260 {0x0752, 0x0000}, 261 {0x0753, 0x0000}, 262 {0x0754, 0x0000}, 263 {0x0755, 0x0000}, 264 {0x0756, 0x0000}, 265 {0x0757, 0x0000}, 266 {0x0758, 0x0000}, 267 {0x0759, 0x0000}, 268 {0x0760, 0x0200}, 269 {0x0761, 0x0000}, 270 {0x0762, 0x0000}, 271 {0x0763, 0x0000}, 272 {0x0764, 0x0000}, 273 {0x0765, 0x0000}, 274 {0x0766, 0x0000}, 275 {0x0767, 0x0000}, 276 {0x0768, 0x0000}, 277 {0x0769, 0x0000}, 278 {0x0770, 0x0200}, 279 {0x0771, 0x0000}, 280 {0x0772, 0x0000}, 281 {0x0773, 0x0000}, 282 {0x0774, 0x0000}, 283 {0x0775, 0x0000}, 284 {0x0776, 0x0000}, 285 {0x0777, 0x0000}, 286 {0x0778, 0x0000}, 287 {0x0779, 0x0000}, 288 {0x0780, 0x0200}, 289 {0x0781, 0x0000}, 290 {0x0782, 0x0000}, 291 {0x0783, 0x0000}, 292 {0x0784, 0x0000}, 293 {0x0785, 0x0000}, 294 {0x0786, 0x0000}, 295 {0x0787, 0x0000}, 296 {0x0788, 0x0000}, 297 {0x0789, 0x0000}, 298 {0x0790, 0x0200}, 299 {0x0791, 0x0000}, 300 {0x0792, 0x0000}, 301 {0x0793, 0x0000}, 302 {0x0794, 0x0000}, 303 {0x0795, 0x0000}, 304 {0x0796, 0x0000}, 305 {0x0797, 0x0000}, 306 {0x0798, 0x0000}, 307 {0x0799, 0x0000}, 308 {0x07a0, 0x0200}, 309 {0x07a1, 0x0000}, 310 {0x07a2, 0x0000}, 311 {0x07a3, 0x0000}, 312 {0x07a4, 0x0000}, 313 {0x07a5, 0x0000}, 314 {0x07a6, 0x0000}, 315 {0x07a7, 0x0000}, 316 {0x07a8, 0x0000}, 317 {0x07a9, 0x0000}, 318 {0x07b0, 0x0200}, 319 {0x07b1, 0x0000}, 320 {0x07b2, 0x0000}, 321 {0x07b3, 0x0000}, 322 {0x07b4, 0x0000}, 323 {0x07b5, 0x0000}, 324 {0x07b6, 0x0000}, 325 {0x07b7, 0x0000}, 326 {0x07b8, 0x0000}, 327 {0x07b9, 0x0000}, 328 {0x07c0, 0x0200}, 329 {0x07c1, 0x0000}, 330 {0x07c2, 0x0000}, 331 {0x07c3, 0x0000}, 332 {0x07c4, 0x0000}, 333 {0x07c5, 0x0000}, 334 {0x07c6, 0x0000}, 335 {0x07c7, 0x0000}, 336 {0x07c8, 0x0000}, 337 {0x07c9, 0x0000}, 338 {0x1000, 0x4040}, 339 {0x1002, 0x6505}, 340 {0x1004, 0x5405}, 341 {0x1006, 0x5555}, 342 {0x1007, 0x003f}, 343 {0x1008, 0x7fd7}, 344 {0x1009, 0x770f}, 345 {0x100a, 0xfffe}, 346 {0x100b, 0xe000}, 347 {0x100c, 0x0000}, 348 {0x100d, 0x0007}, 349 {0x1010, 0xa433}, 350 {0x1020, 0x0000}, 351 {0x1022, 0x0000}, 352 {0x1024, 0x0000}, 353 {0x1200, 0x5a01}, 354 {0x1202, 0x6324}, 355 {0x1204, 0x0b00}, 356 {0x1206, 0x0000}, 357 {0x1208, 0x0000}, 358 {0x120a, 0x0024}, 359 {0x120c, 0x0000}, 360 {0x120e, 0x000e}, 361 {0x1210, 0x0000}, 362 {0x1212, 0x0000}, 363 {0x1300, 0x0701}, 364 {0x1302, 0x12f9}, 365 {0x1304, 0x3405}, 366 {0x1305, 0x0844}, 367 {0x1306, 0x5611}, 368 {0x1308, 0x555e}, 369 {0x130a, 0xa605}, 370 {0x130c, 0x2000}, 371 {0x130e, 0x0000}, 372 {0x130f, 0x0001}, 373 {0x1310, 0xaa48}, 374 {0x1312, 0x0285}, 375 {0x1314, 0xaaaa}, 376 {0x1316, 0xaaa0}, 377 {0x1318, 0x2aaa}, 378 {0x131a, 0xaa07}, 379 {0x1322, 0x0029}, 380 {0x1323, 0x4a52}, 381 {0x1324, 0x002c}, 382 {0x1325, 0x0b02}, 383 {0x1326, 0x002d}, 384 {0x1327, 0x6b5a}, 385 {0x1328, 0x002e}, 386 {0x1329, 0xcbb2}, 387 {0x132a, 0x0030}, 388 {0x132b, 0x2c0b}, 389 {0x1330, 0x0031}, 390 {0x1331, 0x8c63}, 391 {0x1332, 0x0032}, 392 {0x1333, 0xecbb}, 393 {0x1334, 0x0034}, 394 {0x1335, 0x4d13}, 395 {0x1336, 0x0037}, 396 {0x1337, 0x0dc3}, 397 {0x1338, 0x003d}, 398 {0x1339, 0xef7b}, 399 {0x133a, 0x0044}, 400 {0x133b, 0xd134}, 401 {0x133c, 0x0047}, 402 {0x133d, 0x91e4}, 403 {0x133e, 0x004d}, 404 {0x133f, 0xc370}, 405 {0x1340, 0x0053}, 406 {0x1341, 0xf4fd}, 407 {0x1342, 0x0060}, 408 {0x1343, 0x5816}, 409 {0x1344, 0x006c}, 410 {0x1345, 0xbb2e}, 411 {0x1346, 0x0072}, 412 {0x1347, 0xecbb}, 413 {0x1348, 0x0076}, 414 {0x1349, 0x5d97}, 415 {0x1500, 0x0702}, 416 {0x1502, 0x002f}, 417 {0x1504, 0x0000}, 418 {0x1510, 0x0064}, 419 {0x1512, 0x0000}, 420 {0x1514, 0xdf47}, 421 {0x1516, 0x079c}, 422 {0x1518, 0xfbf5}, 423 {0x151a, 0x00bc}, 424 {0x151c, 0x3b85}, 425 {0x151e, 0x02b3}, 426 {0x1520, 0x3333}, 427 {0x1522, 0x0000}, 428 {0x1524, 0x4000}, 429 {0x1528, 0x0064}, 430 {0x152a, 0x0000}, 431 {0x152c, 0x0000}, 432 {0x152e, 0x0000}, 433 {0x1530, 0x0000}, 434 {0x1532, 0x0000}, 435 {0x1534, 0x0000}, 436 {0x1536, 0x0000}, 437 {0x1538, 0x0040}, 438 {0x1539, 0x0000}, 439 {0x153a, 0x0040}, 440 {0x153b, 0x0000}, 441 {0x153c, 0x0064}, 442 {0x153e, 0x0bf9}, 443 {0x1540, 0xb2a9}, 444 {0x1544, 0x0200}, 445 {0x1546, 0x0000}, 446 {0x1548, 0x00ca}, 447 {0x1552, 0x03ff}, 448 {0x1554, 0x017f}, 449 {0x1556, 0x017f}, 450 {0x155a, 0x0000}, 451 {0x155c, 0x0000}, 452 {0x1560, 0x0040}, 453 {0x1562, 0x0000}, 454 {0x1570, 0x03ff}, 455 {0x1571, 0xdcff}, 456 {0x1572, 0x1e00}, 457 {0x1573, 0x224f}, 458 {0x1574, 0x0000}, 459 {0x1575, 0x0000}, 460 {0x1576, 0x1e00}, 461 {0x1577, 0x0000}, 462 {0x1578, 0x0000}, 463 {0x1579, 0x1128}, 464 {0x157a, 0x03ff}, 465 {0x157b, 0xdcff}, 466 {0x157c, 0x1e00}, 467 {0x157d, 0x224f}, 468 {0x157e, 0x0000}, 469 {0x157f, 0x0000}, 470 {0x1580, 0x1e00}, 471 {0x1581, 0x0000}, 472 {0x1582, 0x0000}, 473 {0x1583, 0x1128}, 474 {0x1590, 0x03ff}, 475 {0x1591, 0xdcff}, 476 {0x1592, 0x1e00}, 477 {0x1593, 0x224f}, 478 {0x1594, 0x0000}, 479 {0x1595, 0x0000}, 480 {0x1596, 0x1e00}, 481 {0x1597, 0x0000}, 482 {0x1598, 0x0000}, 483 {0x1599, 0x1128}, 484 {0x159a, 0x03ff}, 485 {0x159b, 0xdcff}, 486 {0x159c, 0x1e00}, 487 {0x159d, 0x224f}, 488 {0x159e, 0x0000}, 489 {0x159f, 0x0000}, 490 {0x15a0, 0x1e00}, 491 {0x15a1, 0x0000}, 492 {0x15a2, 0x0000}, 493 {0x15a3, 0x1128}, 494 {0x15b0, 0x007f}, 495 {0x15b1, 0xffff}, 496 {0x15b2, 0x007f}, 497 {0x15b3, 0xffff}, 498 {0x15b4, 0x007f}, 499 {0x15b5, 0xffff}, 500 {0x15b8, 0x007f}, 501 {0x15b9, 0xffff}, 502 {0x15bc, 0x0000}, 503 {0x15bd, 0x0000}, 504 {0x15be, 0xff00}, 505 {0x15bf, 0x0000}, 506 {0x15c0, 0xff00}, 507 {0x15c1, 0x0000}, 508 {0x15c3, 0xfc00}, 509 {0x15c4, 0xbb80}, 510 {0x15d0, 0x0000}, 511 {0x15d1, 0x0000}, 512 {0x15d2, 0x0000}, 513 {0x15d3, 0x0000}, 514 {0x15d4, 0x0000}, 515 {0x15d5, 0x0000}, 516 {0x15d6, 0x0000}, 517 {0x15d7, 0x0000}, 518 {0x15d8, 0x0200}, 519 {0x15d9, 0x0000}, 520 {0x15da, 0x0000}, 521 {0x15db, 0x0000}, 522 {0x15dc, 0x0000}, 523 {0x15dd, 0x0000}, 524 {0x15de, 0x0000}, 525 {0x15df, 0x0000}, 526 {0x15e0, 0x0000}, 527 {0x15e1, 0x0000}, 528 {0x15e2, 0x0200}, 529 {0x15e3, 0x0000}, 530 {0x15e4, 0x0000}, 531 {0x15e5, 0x0000}, 532 {0x15e6, 0x0000}, 533 {0x15e7, 0x0000}, 534 {0x15e8, 0x0000}, 535 {0x15e9, 0x0000}, 536 {0x15ea, 0x0000}, 537 {0x15eb, 0x0000}, 538 {0x15ec, 0x0200}, 539 {0x15ed, 0x0000}, 540 {0x15ee, 0x0000}, 541 {0x15ef, 0x0000}, 542 {0x15f0, 0x0000}, 543 {0x15f1, 0x0000}, 544 {0x15f2, 0x0000}, 545 {0x15f3, 0x0000}, 546 {0x15f4, 0x0000}, 547 {0x15f5, 0x0000}, 548 {0x15f6, 0x0200}, 549 {0x15f7, 0x0200}, 550 {0x15f8, 0x8200}, 551 {0x15f9, 0x0000}, 552 {0x1600, 0x007d}, 553 {0x1601, 0xa178}, 554 {0x1602, 0x00c2}, 555 {0x1603, 0x5383}, 556 {0x1604, 0x0000}, 557 {0x1605, 0x02c1}, 558 {0x1606, 0x007d}, 559 {0x1607, 0xa178}, 560 {0x1608, 0x00c2}, 561 {0x1609, 0x5383}, 562 {0x160a, 0x003e}, 563 {0x160b, 0xd37d}, 564 {0x1611, 0x3210}, 565 {0x1612, 0x7418}, 566 {0x1613, 0xc0ff}, 567 {0x1614, 0x0000}, 568 {0x1615, 0x00ff}, 569 {0x1616, 0x0000}, 570 {0x1617, 0x0000}, 571 {0x1621, 0x6210}, 572 {0x1622, 0x7418}, 573 {0x1623, 0xc0ff}, 574 {0x1624, 0x0000}, 575 {0x1625, 0x00ff}, 576 {0x1626, 0x0000}, 577 {0x1627, 0x0000}, 578 {0x1631, 0x3a14}, 579 {0x1632, 0x7418}, 580 {0x1633, 0xc3ff}, 581 {0x1634, 0x0000}, 582 {0x1635, 0x00ff}, 583 {0x1636, 0x0000}, 584 {0x1637, 0x0000}, 585 {0x1638, 0x0000}, 586 {0x163a, 0x0000}, 587 {0x163c, 0x0000}, 588 {0x163e, 0x0000}, 589 {0x1640, 0x0000}, 590 {0x1642, 0x0000}, 591 {0x1644, 0x0000}, 592 {0x1646, 0x0000}, 593 {0x1648, 0x0000}, 594 {0x1650, 0x0000}, 595 {0x1652, 0x0000}, 596 {0x1654, 0x0000}, 597 {0x1656, 0x0000}, 598 {0x1658, 0x0000}, 599 {0x1660, 0x0000}, 600 {0x1662, 0x0000}, 601 {0x1664, 0x0000}, 602 {0x1666, 0x0000}, 603 {0x1668, 0x0000}, 604 {0x1670, 0x0000}, 605 {0x1672, 0x0000}, 606 {0x1674, 0x0000}, 607 {0x1676, 0x0000}, 608 {0x1678, 0x0000}, 609 {0x1680, 0x0000}, 610 {0x1682, 0x0000}, 611 {0x1684, 0x0000}, 612 {0x1686, 0x0000}, 613 {0x1688, 0x0000}, 614 {0x1690, 0x0000}, 615 {0x1692, 0x0000}, 616 {0x1694, 0x0000}, 617 {0x1696, 0x0000}, 618 {0x1698, 0x0000}, 619 {0x1700, 0x0000}, 620 {0x1702, 0x0000}, 621 {0x1704, 0x0000}, 622 {0x1706, 0x0000}, 623 {0x1708, 0x0000}, 624 {0x1710, 0x0000}, 625 {0x1712, 0x0000}, 626 {0x1714, 0x0000}, 627 {0x1716, 0x0000}, 628 {0x1718, 0x0000}, 629 {0x1720, 0x0000}, 630 {0x1722, 0x0000}, 631 {0x1724, 0x0000}, 632 {0x1726, 0x0000}, 633 {0x1728, 0x0000}, 634 {0x1730, 0x0000}, 635 {0x1732, 0x0000}, 636 {0x1734, 0x0000}, 637 {0x1736, 0x0000}, 638 {0x1738, 0x0000}, 639 {0x173a, 0x0000}, 640 {0x173c, 0x0000}, 641 {0x173e, 0x0000}, 642 {0x17bb, 0x0500}, 643 {0x17bd, 0x0004}, 644 {0x17bf, 0x0004}, 645 {0x17c1, 0x0004}, 646 {0x17c2, 0x7fff}, 647 {0x17c3, 0x0000}, 648 {0x17c5, 0x0000}, 649 {0x17c7, 0x0000}, 650 {0x17c9, 0x0000}, 651 {0x17cb, 0x2010}, 652 {0x17cd, 0x0000}, 653 {0x17cf, 0x0000}, 654 {0x17d1, 0x0000}, 655 {0x17d3, 0x0000}, 656 {0x17d5, 0x0000}, 657 {0x17d7, 0x0000}, 658 {0x17d9, 0x0000}, 659 {0x17db, 0x0000}, 660 {0x17dd, 0x0000}, 661 {0x17df, 0x0000}, 662 {0x17e1, 0x0000}, 663 {0x17e3, 0x0000}, 664 {0x17e5, 0x0000}, 665 {0x17e7, 0x0000}, 666 {0x17e9, 0x0000}, 667 {0x17eb, 0x0000}, 668 {0x17ed, 0x0000}, 669 {0x17ef, 0x0000}, 670 {0x17f1, 0x0000}, 671 {0x17f3, 0x0000}, 672 {0x17f5, 0x0000}, 673 {0x17f7, 0x0000}, 674 {0x17f9, 0x0000}, 675 {0x17fb, 0x0000}, 676 {0x17fd, 0x0000}, 677 {0x17ff, 0x0000}, 678 {0x1801, 0x0000}, 679 {0x1803, 0x0000}, 680 }; 681 682 static int rt1011_reg_init(struct snd_soc_component *component) 683 { 684 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 685 686 regmap_multi_reg_write(rt1011->regmap, 687 init_list, ARRAY_SIZE(init_list)); 688 return 0; 689 } 690 691 static bool rt1011_volatile_register(struct device *dev, unsigned int reg) 692 { 693 switch (reg) { 694 case RT1011_RESET: 695 case RT1011_SRC_2: 696 case RT1011_CLK_DET: 697 case RT1011_SIL_DET: 698 case RT1011_VERSION_ID: 699 case RT1011_VENDOR_ID: 700 case RT1011_DEVICE_ID: 701 case RT1011_DUM_RO: 702 case RT1011_DAC_SET_3: 703 case RT1011_PWM_CAL: 704 case RT1011_SPK_VOL_TEST_OUT: 705 case RT1011_VBAT_VOL_DET_1: 706 case RT1011_VBAT_TEST_OUT_1: 707 case RT1011_VBAT_TEST_OUT_2: 708 case RT1011_VBAT_PROTECTION: 709 case RT1011_VBAT_DET: 710 case RT1011_BOOST_CON_1: 711 case RT1011_SHORT_CIRCUIT_DET_1: 712 case RT1011_SPK_TEMP_PROTECT_3: 713 case RT1011_SPK_TEMP_PROTECT_6: 714 case RT1011_SPK_PRO_DC_DET_3: 715 case RT1011_SPK_PRO_DC_DET_7: 716 case RT1011_SPK_PRO_DC_DET_8: 717 case RT1011_SPL_1: 718 case RT1011_SPL_4: 719 case RT1011_EXCUR_PROTECT_1: 720 case RT1011_CROSS_BQ_SET_1: 721 case RT1011_CROSS_BQ_SET_2: 722 case RT1011_BQ_SET_0: 723 case RT1011_BQ_SET_1: 724 case RT1011_BQ_SET_2: 725 case RT1011_TEST_PAD_STATUS: 726 case RT1011_DC_CALIB_CLASSD_1: 727 case RT1011_DC_CALIB_CLASSD_5: 728 case RT1011_DC_CALIB_CLASSD_6: 729 case RT1011_DC_CALIB_CLASSD_7: 730 case RT1011_DC_CALIB_CLASSD_8: 731 case RT1011_SINE_GEN_REG_2: 732 case RT1011_STP_CALIB_RS_TEMP: 733 case RT1011_SPK_RESISTANCE_1: 734 case RT1011_SPK_RESISTANCE_2: 735 case RT1011_SPK_THERMAL: 736 case RT1011_ALC_BK_GAIN_O: 737 case RT1011_ALC_BK_GAIN_O_PRE: 738 case RT1011_SPK_DC_O_23_16: 739 case RT1011_SPK_DC_O_15_0: 740 case RT1011_INIT_RECIPROCAL_SYN_24_16: 741 case RT1011_INIT_RECIPROCAL_SYN_15_0: 742 case RT1011_SPK_EXCURSION_23_16: 743 case RT1011_SPK_EXCURSION_15_0: 744 case RT1011_SEP_MAIN_OUT_23_16: 745 case RT1011_SEP_MAIN_OUT_15_0: 746 case RT1011_ALC_DRC_HB_INTERNAL_5: 747 case RT1011_ALC_DRC_HB_INTERNAL_6: 748 case RT1011_ALC_DRC_HB_INTERNAL_7: 749 case RT1011_ALC_DRC_BB_INTERNAL_5: 750 case RT1011_ALC_DRC_BB_INTERNAL_6: 751 case RT1011_ALC_DRC_BB_INTERNAL_7: 752 case RT1011_ALC_DRC_POS_INTERNAL_5: 753 case RT1011_ALC_DRC_POS_INTERNAL_6: 754 case RT1011_ALC_DRC_POS_INTERNAL_7: 755 case RT1011_ALC_DRC_POS_INTERNAL_8: 756 case RT1011_ALC_DRC_POS_INTERNAL_9: 757 case RT1011_ALC_DRC_POS_INTERNAL_10: 758 case RT1011_ALC_DRC_POS_INTERNAL_11: 759 case RT1011_IRQ_1: 760 case RT1011_EFUSE_CONTROL_1: 761 case RT1011_EFUSE_CONTROL_2: 762 case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0: 763 return true; 764 765 default: 766 return false; 767 } 768 } 769 770 static bool rt1011_readable_register(struct device *dev, unsigned int reg) 771 { 772 switch (reg) { 773 case RT1011_RESET: 774 case RT1011_CLK_1: 775 case RT1011_CLK_2: 776 case RT1011_CLK_3: 777 case RT1011_CLK_4: 778 case RT1011_PLL_1: 779 case RT1011_PLL_2: 780 case RT1011_SRC_1: 781 case RT1011_SRC_2: 782 case RT1011_SRC_3: 783 case RT1011_CLK_DET: 784 case RT1011_SIL_DET: 785 case RT1011_PRIV_INDEX: 786 case RT1011_PRIV_DATA: 787 case RT1011_CUSTOMER_ID: 788 case RT1011_FM_VER: 789 case RT1011_VERSION_ID: 790 case RT1011_VENDOR_ID: 791 case RT1011_DEVICE_ID: 792 case RT1011_DUM_RW_0: 793 case RT1011_DUM_YUN: 794 case RT1011_DUM_RW_1: 795 case RT1011_DUM_RO: 796 case RT1011_MAN_I2C_DEV: 797 case RT1011_DAC_SET_1: 798 case RT1011_DAC_SET_2: 799 case RT1011_DAC_SET_3: 800 case RT1011_ADC_SET: 801 case RT1011_ADC_SET_1: 802 case RT1011_ADC_SET_2: 803 case RT1011_ADC_SET_3: 804 case RT1011_ADC_SET_4: 805 case RT1011_ADC_SET_5: 806 case RT1011_TDM_TOTAL_SET: 807 case RT1011_TDM1_SET_TCON: 808 case RT1011_TDM1_SET_1: 809 case RT1011_TDM1_SET_2: 810 case RT1011_TDM1_SET_3: 811 case RT1011_TDM1_SET_4: 812 case RT1011_TDM1_SET_5: 813 case RT1011_TDM2_SET_1: 814 case RT1011_TDM2_SET_2: 815 case RT1011_TDM2_SET_3: 816 case RT1011_TDM2_SET_4: 817 case RT1011_TDM2_SET_5: 818 case RT1011_PWM_CAL: 819 case RT1011_MIXER_1: 820 case RT1011_MIXER_2: 821 case RT1011_ADRC_LIMIT: 822 case RT1011_A_PRO: 823 case RT1011_A_TIMING_1: 824 case RT1011_A_TIMING_2: 825 case RT1011_A_TEMP_SEN: 826 case RT1011_SPK_VOL_DET_1: 827 case RT1011_SPK_VOL_DET_2: 828 case RT1011_SPK_VOL_TEST_OUT: 829 case RT1011_VBAT_VOL_DET_1: 830 case RT1011_VBAT_VOL_DET_2: 831 case RT1011_VBAT_TEST_OUT_1: 832 case RT1011_VBAT_TEST_OUT_2: 833 case RT1011_VBAT_PROTECTION: 834 case RT1011_VBAT_DET: 835 case RT1011_POWER_1: 836 case RT1011_POWER_2: 837 case RT1011_POWER_3: 838 case RT1011_POWER_4: 839 case RT1011_POWER_5: 840 case RT1011_POWER_6: 841 case RT1011_POWER_7: 842 case RT1011_POWER_8: 843 case RT1011_POWER_9: 844 case RT1011_CLASS_D_POS: 845 case RT1011_BOOST_CON_1: 846 case RT1011_BOOST_CON_2: 847 case RT1011_ANALOG_CTRL: 848 case RT1011_POWER_SEQ: 849 case RT1011_SHORT_CIRCUIT_DET_1: 850 case RT1011_SHORT_CIRCUIT_DET_2: 851 case RT1011_SPK_TEMP_PROTECT_0: 852 case RT1011_SPK_TEMP_PROTECT_1: 853 case RT1011_SPK_TEMP_PROTECT_2: 854 case RT1011_SPK_TEMP_PROTECT_3: 855 case RT1011_SPK_TEMP_PROTECT_4: 856 case RT1011_SPK_TEMP_PROTECT_5: 857 case RT1011_SPK_TEMP_PROTECT_6: 858 case RT1011_SPK_TEMP_PROTECT_7: 859 case RT1011_SPK_TEMP_PROTECT_8: 860 case RT1011_SPK_TEMP_PROTECT_9: 861 case RT1011_SPK_PRO_DC_DET_1: 862 case RT1011_SPK_PRO_DC_DET_2: 863 case RT1011_SPK_PRO_DC_DET_3: 864 case RT1011_SPK_PRO_DC_DET_4: 865 case RT1011_SPK_PRO_DC_DET_5: 866 case RT1011_SPK_PRO_DC_DET_6: 867 case RT1011_SPK_PRO_DC_DET_7: 868 case RT1011_SPK_PRO_DC_DET_8: 869 case RT1011_SPL_1: 870 case RT1011_SPL_2: 871 case RT1011_SPL_3: 872 case RT1011_SPL_4: 873 case RT1011_THER_FOLD_BACK_1: 874 case RT1011_THER_FOLD_BACK_2: 875 case RT1011_EXCUR_PROTECT_1: 876 case RT1011_EXCUR_PROTECT_2: 877 case RT1011_EXCUR_PROTECT_3: 878 case RT1011_EXCUR_PROTECT_4: 879 case RT1011_BAT_GAIN_1: 880 case RT1011_BAT_GAIN_2: 881 case RT1011_BAT_GAIN_3: 882 case RT1011_BAT_GAIN_4: 883 case RT1011_BAT_GAIN_5: 884 case RT1011_BAT_GAIN_6: 885 case RT1011_BAT_GAIN_7: 886 case RT1011_BAT_GAIN_8: 887 case RT1011_BAT_GAIN_9: 888 case RT1011_BAT_GAIN_10: 889 case RT1011_BAT_GAIN_11: 890 case RT1011_BAT_RT_THMAX_1: 891 case RT1011_BAT_RT_THMAX_2: 892 case RT1011_BAT_RT_THMAX_3: 893 case RT1011_BAT_RT_THMAX_4: 894 case RT1011_BAT_RT_THMAX_5: 895 case RT1011_BAT_RT_THMAX_6: 896 case RT1011_BAT_RT_THMAX_7: 897 case RT1011_BAT_RT_THMAX_8: 898 case RT1011_BAT_RT_THMAX_9: 899 case RT1011_BAT_RT_THMAX_10: 900 case RT1011_BAT_RT_THMAX_11: 901 case RT1011_BAT_RT_THMAX_12: 902 case RT1011_SPREAD_SPECTURM: 903 case RT1011_PRO_GAIN_MODE: 904 case RT1011_RT_DRC_CROSS: 905 case RT1011_RT_DRC_HB_1: 906 case RT1011_RT_DRC_HB_2: 907 case RT1011_RT_DRC_HB_3: 908 case RT1011_RT_DRC_HB_4: 909 case RT1011_RT_DRC_HB_5: 910 case RT1011_RT_DRC_HB_6: 911 case RT1011_RT_DRC_HB_7: 912 case RT1011_RT_DRC_HB_8: 913 case RT1011_RT_DRC_BB_1: 914 case RT1011_RT_DRC_BB_2: 915 case RT1011_RT_DRC_BB_3: 916 case RT1011_RT_DRC_BB_4: 917 case RT1011_RT_DRC_BB_5: 918 case RT1011_RT_DRC_BB_6: 919 case RT1011_RT_DRC_BB_7: 920 case RT1011_RT_DRC_BB_8: 921 case RT1011_RT_DRC_POS_1: 922 case RT1011_RT_DRC_POS_2: 923 case RT1011_RT_DRC_POS_3: 924 case RT1011_RT_DRC_POS_4: 925 case RT1011_RT_DRC_POS_5: 926 case RT1011_RT_DRC_POS_6: 927 case RT1011_RT_DRC_POS_7: 928 case RT1011_RT_DRC_POS_8: 929 case RT1011_CROSS_BQ_SET_1: 930 case RT1011_CROSS_BQ_SET_2: 931 case RT1011_BQ_SET_0: 932 case RT1011_BQ_SET_1: 933 case RT1011_BQ_SET_2: 934 case RT1011_BQ_PRE_GAIN_28_16: 935 case RT1011_BQ_PRE_GAIN_15_0: 936 case RT1011_BQ_POST_GAIN_28_16: 937 case RT1011_BQ_POST_GAIN_15_0: 938 case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0: 939 case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0: 940 case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0: 941 case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0: 942 case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0: 943 case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0: 944 case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0: 945 case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0: 946 case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0: 947 case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0: 948 case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0: 949 case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET: 950 case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3: 951 case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10: 952 case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1: 953 case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36: 954 case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3: 955 case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL: 956 case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0: 957 case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0: 958 case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0: 959 case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12: 960 case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7: 961 case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7: 962 case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8: 963 case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5: 964 case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5: 965 case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5: 966 case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5: 967 case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5: 968 case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5: 969 case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5: 970 case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5: 971 case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5: 972 case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5: 973 case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE: 974 case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0: 975 return true; 976 default: 977 return false; 978 } 979 } 980 981 static const char * const rt1011_din_source_select[] = { 982 "Left", 983 "Right", 984 "Left + Right average", 985 }; 986 987 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5, 988 rt1011_din_source_select); 989 990 static const char * const rt1011_tdm_data_out_select[] = { 991 "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR", 992 "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS", 993 "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST" 994 }; 995 996 static const char * const rt1011_tdm_l_ch_data_select[] = { 997 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 998 }; 999 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12, 1000 rt1011_tdm_l_ch_data_select); 1001 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12, 1002 rt1011_tdm_l_ch_data_select); 1003 1004 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum, 1005 RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select); 1006 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0, 1007 rt1011_tdm_l_ch_data_select); 1008 1009 static const char * const rt1011_adc_data_mode_select[] = { 1010 "Stereo", "Mono" 1011 }; 1012 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12, 1013 rt1011_adc_data_mode_select); 1014 1015 static const char * const rt1011_tdm_adc_data_len_control[] = { 1016 "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH" 1017 }; 1018 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13, 1019 rt1011_tdm_adc_data_len_control); 1020 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13, 1021 rt1011_tdm_adc_data_len_control); 1022 1023 static const char * const rt1011_tdm_adc_swap_select[] = { 1024 "L/R", "R/L", "L/L", "R/R" 1025 }; 1026 1027 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6, 1028 rt1011_tdm_adc_swap_select); 1029 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4, 1030 rt1011_tdm_adc_swap_select); 1031 1032 static void rt1011_reset(struct regmap *regmap) 1033 { 1034 regmap_write(regmap, RT1011_RESET, 0); 1035 } 1036 1037 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol, 1038 struct snd_ctl_elem_value *ucontrol) 1039 { 1040 struct snd_soc_component *component = 1041 snd_soc_kcontrol_component(kcontrol); 1042 struct rt1011_priv *rt1011 = 1043 snd_soc_component_get_drvdata(component); 1044 1045 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode; 1046 1047 return 0; 1048 } 1049 1050 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol, 1051 struct snd_ctl_elem_value *ucontrol) 1052 { 1053 struct snd_soc_component *component = 1054 snd_soc_kcontrol_component(kcontrol); 1055 struct rt1011_priv *rt1011 = 1056 snd_soc_component_get_drvdata(component); 1057 1058 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode) 1059 return 0; 1060 1061 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1062 rt1011->recv_spk_mode = ucontrol->value.integer.value[0]; 1063 1064 if (rt1011->recv_spk_mode) { 1065 1066 /* 1: recevier mode on */ 1067 snd_soc_component_update_bits(component, 1068 RT1011_CLASSD_INTERNAL_SET_3, 1069 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, 1070 RT1011_REG_GAIN_CLASSD_RI_410K); 1071 snd_soc_component_update_bits(component, 1072 RT1011_CLASSD_INTERNAL_SET_1, 1073 RT1011_RECV_MODE_SPK_MASK, 1074 RT1011_RECV_MODE); 1075 } else { 1076 /* 0: speaker mode on */ 1077 snd_soc_component_update_bits(component, 1078 RT1011_CLASSD_INTERNAL_SET_3, 1079 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, 1080 RT1011_REG_GAIN_CLASSD_RI_72P5K); 1081 snd_soc_component_update_bits(component, 1082 RT1011_CLASSD_INTERNAL_SET_1, 1083 RT1011_RECV_MODE_SPK_MASK, 1084 RT1011_SPK_MODE); 1085 } 1086 } 1087 1088 return 0; 1089 } 1090 1091 static bool rt1011_validate_bq_drc_coeff(unsigned short reg) 1092 { 1093 if ((reg == RT1011_DAC_SET_1) | 1094 (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) | 1095 (reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) | 1096 (reg == RT1011_MIXER_1) | 1097 (reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 && 1098 reg <= RT1011_POWER_8) | 1099 (reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) | 1100 (reg >= RT1011_SPK_TEMP_PROTECT_0 && 1101 reg <= RT1011_SPK_TEMP_PROTECT_6) | 1102 (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) | 1103 (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) | 1104 (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) | 1105 (reg >= RT1011_SMART_BOOST_TIMING_1 && 1106 reg <= RT1011_SMART_BOOST_TIMING_36) | 1107 (reg == RT1011_SINE_GEN_REG_1) | 1108 (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && 1109 reg <= RT1011_BQ_6_PARAMS_CHECK_5) | 1110 (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && 1111 reg <= RT1011_BQ_10_PARAMS_CHECK_5)) 1112 return true; 1113 1114 return false; 1115 } 1116 1117 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol, 1118 struct snd_ctl_elem_value *ucontrol) 1119 { 1120 struct snd_soc_component *component = 1121 snd_soc_kcontrol_component(kcontrol); 1122 struct rt1011_priv *rt1011 = 1123 snd_soc_component_get_drvdata(component); 1124 struct rt1011_bq_drc_params *bq_drc_info; 1125 struct rt1011_bq_drc_params *params = 1126 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; 1127 unsigned int i, mode_idx = 0; 1128 1129 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) 1130 mode_idx = RT1011_ADVMODE_INITIAL_SET; 1131 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) 1132 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; 1133 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) 1134 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; 1135 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) 1136 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; 1137 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) 1138 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; 1139 else 1140 return -EINVAL; 1141 1142 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, 1143 ucontrol->id.name, mode_idx); 1144 bq_drc_info = rt1011->bq_drc_params[mode_idx]; 1145 1146 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1147 params[i].reg = bq_drc_info[i].reg; 1148 params[i].val = bq_drc_info[i].val; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol, 1155 struct snd_ctl_elem_value *ucontrol) 1156 { 1157 struct snd_soc_component *component = 1158 snd_soc_kcontrol_component(kcontrol); 1159 struct rt1011_priv *rt1011 = 1160 snd_soc_component_get_drvdata(component); 1161 struct rt1011_bq_drc_params *bq_drc_info; 1162 struct rt1011_bq_drc_params *params = 1163 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; 1164 unsigned int i, mode_idx = 0; 1165 1166 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) 1167 mode_idx = RT1011_ADVMODE_INITIAL_SET; 1168 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) 1169 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; 1170 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) 1171 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; 1172 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) 1173 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; 1174 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) 1175 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; 1176 else 1177 return -EINVAL; 1178 1179 bq_drc_info = rt1011->bq_drc_params[mode_idx]; 1180 memset(bq_drc_info, 0, 1181 sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM); 1182 1183 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, 1184 ucontrol->id.name, mode_idx); 1185 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1186 bq_drc_info[i].reg = params[i].reg; 1187 bq_drc_info[i].val = params[i].val; 1188 } 1189 1190 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1191 if (bq_drc_info[i].reg == 0) 1192 break; 1193 else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) { 1194 snd_soc_component_write(component, bq_drc_info[i].reg, 1195 bq_drc_info[i].val); 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol, 1203 struct snd_ctl_elem_info *uinfo) 1204 { 1205 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1206 uinfo->count = 128; 1207 uinfo->value.integer.max = 0x17ffffff; 1208 1209 return 0; 1210 } 1211 1212 #define RT1011_BQ_DRC(xname) \ 1213 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1214 .info = rt1011_bq_drc_info, \ 1215 .get = rt1011_bq_drc_coeff_get, \ 1216 .put = rt1011_bq_drc_coeff_put \ 1217 } 1218 1219 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol, 1220 struct snd_ctl_elem_value *ucontrol) 1221 { 1222 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1223 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1224 1225 ucontrol->value.integer.value[0] = rt1011->cali_done; 1226 1227 return 0; 1228 } 1229 1230 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol, 1231 struct snd_ctl_elem_value *ucontrol) 1232 { 1233 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1234 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1235 1236 rt1011->cali_done = 0; 1237 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && 1238 ucontrol->value.integer.value[0]) 1239 rt1011_calibrate(rt1011, 1); 1240 1241 return 0; 1242 } 1243 1244 static int rt1011_r0_load(struct rt1011_priv *rt1011) 1245 { 1246 if (!rt1011->r0_reg) 1247 return -EINVAL; 1248 1249 /* write R0 to register */ 1250 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16, 1251 ((rt1011->r0_reg>>16) & 0x1ff)); 1252 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0, 1253 (rt1011->r0_reg & 0xffff)); 1254 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080); 1255 1256 return 0; 1257 } 1258 1259 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol, 1260 struct snd_ctl_elem_value *ucontrol) 1261 { 1262 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1263 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1264 1265 ucontrol->value.integer.value[0] = rt1011->r0_reg; 1266 1267 return 0; 1268 } 1269 1270 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol, 1271 struct snd_ctl_elem_value *ucontrol) 1272 { 1273 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1274 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1275 struct device *dev; 1276 unsigned int r0_integer, r0_factor, format; 1277 1278 if (ucontrol->value.integer.value[0] == rt1011->r0_reg) 1279 return 0; 1280 1281 if (ucontrol->value.integer.value[0] == 0) 1282 return -EINVAL; 1283 1284 dev = regmap_get_device(rt1011->regmap); 1285 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1286 rt1011->r0_reg = ucontrol->value.integer.value[0]; 1287 1288 format = 2147483648U; /* 2^24 * 128 */ 1289 r0_integer = format / rt1011->r0_reg / 128; 1290 r0_factor = ((format / rt1011->r0_reg * 100) / 128) 1291 - (r0_integer * 100); 1292 dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n", 1293 r0_integer, r0_factor, rt1011->r0_reg); 1294 1295 if (rt1011->r0_reg) 1296 rt1011_r0_load(rt1011); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol, 1303 struct snd_ctl_elem_info *uinfo) 1304 { 1305 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1306 uinfo->count = 1; 1307 uinfo->value.integer.max = 0x1ffffff; 1308 1309 return 0; 1310 } 1311 1312 #define RT1011_R0_LOAD(xname) \ 1313 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1314 .info = rt1011_r0_load_info, \ 1315 .get = rt1011_r0_load_mode_get, \ 1316 .put = rt1011_r0_load_mode_put \ 1317 } 1318 1319 static const struct snd_kcontrol_new rt1011_snd_controls[] = { 1320 /* I2S Data In Selection */ 1321 SOC_ENUM("DIN Source", rt1011_din_source_enum), 1322 1323 /* TDM Data In Selection */ 1324 SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum), 1325 SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum), 1326 1327 /* TDM1 Data Out Selection */ 1328 SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum), 1329 SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum), 1330 SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum), 1331 SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum), 1332 1333 /* Data Out Mode */ 1334 SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum), 1335 SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum), 1336 SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum), 1337 1338 /* Speaker/Receiver Mode */ 1339 SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0, 1340 rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put), 1341 1342 /* BiQuad/DRC/SmartBoost Settings */ 1343 RT1011_BQ_DRC("AdvanceMode Initial Set"), 1344 RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"), 1345 RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"), 1346 RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"), 1347 RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"), 1348 1349 /* R0 */ 1350 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, 1351 rt1011_r0_cali_get, rt1011_r0_cali_put), 1352 RT1011_R0_LOAD("R0 Load Mode"), 1353 1354 /* R0 temperature */ 1355 SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP, 1356 2, 255, 0), 1357 }; 1358 1359 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1360 struct snd_soc_dapm_widget *sink) 1361 { 1362 struct snd_soc_component *component = 1363 snd_soc_dapm_to_component(source->dapm); 1364 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1365 1366 if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1) 1367 return 1; 1368 else 1369 return 0; 1370 } 1371 1372 static int rt1011_dac_event(struct snd_soc_dapm_widget *w, 1373 struct snd_kcontrol *kcontrol, int event) 1374 { 1375 struct snd_soc_component *component = 1376 snd_soc_dapm_to_component(w->dapm); 1377 1378 switch (event) { 1379 case SND_SOC_DAPM_POST_PMU: 1380 snd_soc_component_update_bits(component, 1381 RT1011_SPK_TEMP_PROTECT_0, 1382 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 1383 RT1011_STP_EN | RT1011_STP_RS_CLB_EN); 1384 snd_soc_component_update_bits(component, RT1011_POWER_9, 1385 RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB); 1386 msleep(50); 1387 snd_soc_component_update_bits(component, 1388 RT1011_CLASSD_INTERNAL_SET_1, 1389 RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK); 1390 break; 1391 case SND_SOC_DAPM_PRE_PMD: 1392 snd_soc_component_update_bits(component, RT1011_POWER_9, 1393 RT1011_POW_MNL_SDB_MASK, 0); 1394 snd_soc_component_update_bits(component, 1395 RT1011_SPK_TEMP_PROTECT_0, 1396 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0); 1397 msleep(200); 1398 snd_soc_component_update_bits(component, 1399 RT1011_CLASSD_INTERNAL_SET_1, 1400 RT1011_DRIVER_READY_SPK, 0); 1401 break; 1402 1403 default: 1404 return 0; 1405 } 1406 1407 return 0; 1408 } 1409 1410 1411 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = { 1412 SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1, 1413 RT1011_POW_LDO2_BIT, 0, NULL, 0), 1414 SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1, 1415 RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0), 1416 SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1, 1417 RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0), 1418 1419 SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2, 1420 RT1011_PLLEN_BIT, 0, NULL, 0), 1421 SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2, 1422 RT1011_POW_BG_BIT, 0, NULL, 0), 1423 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2, 1424 RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0), 1425 1426 SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3, 1427 RT1011_POW_DET_VBAT_BIT, 0, NULL, 0), 1428 SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3, 1429 RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0), 1430 SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3, 1431 RT1011_POW_ADC_I_BIT, 0, NULL, 0), 1432 SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3, 1433 RT1011_POW_ADC_V_BIT, 0, NULL, 0), 1434 SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3, 1435 RT1011_POW_ADC_T_BIT, 0, NULL, 0), 1436 SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3, 1437 RT1011_POWD_ADC_T_BIT, 0, NULL, 0), 1438 SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3, 1439 RT1011_POW_MIX_I_BIT, 0, NULL, 0), 1440 SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3, 1441 RT1011_POW_MIX_V_BIT, 0, NULL, 0), 1442 SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3, 1443 RT1011_POW_SUM_I_BIT, 0, NULL, 0), 1444 SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3, 1445 RT1011_POW_SUM_V_BIT, 0, NULL, 0), 1446 SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3, 1447 RT1011_POW_MIX_T_BIT, 0, NULL, 0), 1448 SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3, 1449 RT1011_POW_VREF_LV_BIT, 0, NULL, 0), 1450 1451 SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4, 1452 RT1011_POW_EN_SWR_BIT, 0, NULL, 0), 1453 SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4, 1454 RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0), 1455 SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4, 1456 RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0), 1457 1458 SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN, 1459 RT1011_POW_TEMP_REG_BIT, 0, NULL, 0), 1460 1461 /* Audio Interface */ 1462 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1463 /* Digital Interface */ 1464 SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1, 1465 RT1011_POW_DAC_BIT, 0, NULL, 0), 1466 SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1, 1467 RT1011_POW_CLK12M_BIT, 0, NULL, 0), 1468 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3, 1469 RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event, 1470 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1471 1472 /* Output Lines */ 1473 SND_SOC_DAPM_OUTPUT("SPO"), 1474 }; 1475 1476 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = { 1477 1478 { "DAC", NULL, "AIF1RX" }, 1479 { "DAC", NULL, "DAC Power" }, 1480 { "DAC", NULL, "LDO2" }, 1481 { "DAC", NULL, "ISENSE SPK" }, 1482 { "DAC", NULL, "VSENSE SPK" }, 1483 { "DAC", NULL, "CLK12M" }, 1484 1485 { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll }, 1486 { "DAC", NULL, "BG" }, 1487 { "DAC", NULL, "BG MBIAS" }, 1488 1489 { "DAC", NULL, "BOOST SWR" }, 1490 { "DAC", NULL, "BGOK SWR" }, 1491 { "DAC", NULL, "VPOK SWR" }, 1492 1493 { "DAC", NULL, "DET VBAT" }, 1494 { "DAC", NULL, "MBIAS" }, 1495 { "DAC", NULL, "VREF" }, 1496 { "DAC", NULL, "ADC I" }, 1497 { "DAC", NULL, "ADC V" }, 1498 { "DAC", NULL, "ADC T" }, 1499 { "DAC", NULL, "DITHER ADC T" }, 1500 { "DAC", NULL, "MIX I" }, 1501 { "DAC", NULL, "MIX V" }, 1502 { "DAC", NULL, "SUM I" }, 1503 { "DAC", NULL, "SUM V" }, 1504 { "DAC", NULL, "MIX T" }, 1505 1506 { "DAC", NULL, "TEMP REG" }, 1507 1508 { "SPO", NULL, "DAC" }, 1509 }; 1510 1511 static int rt1011_get_clk_info(int sclk, int rate) 1512 { 1513 int i; 1514 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; 1515 1516 if (sclk <= 0 || rate <= 0) 1517 return -EINVAL; 1518 1519 rate = rate << 8; 1520 for (i = 0; i < ARRAY_SIZE(pd); i++) 1521 if (sclk == rate * pd[i]) 1522 return i; 1523 1524 return -EINVAL; 1525 } 1526 1527 static int rt1011_hw_params(struct snd_pcm_substream *substream, 1528 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1529 { 1530 struct snd_soc_component *component = dai->component; 1531 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1532 unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk; 1533 int pre_div, bclk_ms, frame_size; 1534 1535 rt1011->lrck = params_rate(params); 1536 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck); 1537 if (pre_div < 0) { 1538 dev_warn(component->dev, "Force using PLL "); 1539 snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK, 1540 rt1011->lrck * 64, rt1011->lrck * 256); 1541 snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1, 1542 rt1011->lrck * 256, SND_SOC_CLOCK_IN); 1543 pre_div = 0; 1544 } 1545 frame_size = snd_soc_params_to_frame_size(params); 1546 if (frame_size < 0) { 1547 dev_err(component->dev, "Unsupported frame size: %d\n", 1548 frame_size); 1549 return -EINVAL; 1550 } 1551 1552 bclk_ms = frame_size > 32; 1553 rt1011->bclk = rt1011->lrck * (32 << bclk_ms); 1554 1555 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 1556 bclk_ms, pre_div, dai->id); 1557 1558 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1559 rt1011->lrck, pre_div, dai->id); 1560 1561 switch (params_width(params)) { 1562 case 16: 1563 val_len |= RT1011_I2S_TX_DL_16B; 1564 val_len |= RT1011_I2S_RX_DL_16B; 1565 ch_len |= RT1011_I2S_CH_TX_LEN_16B; 1566 ch_len |= RT1011_I2S_CH_RX_LEN_16B; 1567 break; 1568 case 20: 1569 val_len |= RT1011_I2S_TX_DL_20B; 1570 val_len |= RT1011_I2S_RX_DL_20B; 1571 ch_len |= RT1011_I2S_CH_TX_LEN_20B; 1572 ch_len |= RT1011_I2S_CH_RX_LEN_20B; 1573 break; 1574 case 24: 1575 val_len |= RT1011_I2S_TX_DL_24B; 1576 val_len |= RT1011_I2S_RX_DL_24B; 1577 ch_len |= RT1011_I2S_CH_TX_LEN_24B; 1578 ch_len |= RT1011_I2S_CH_RX_LEN_24B; 1579 break; 1580 case 32: 1581 val_len |= RT1011_I2S_TX_DL_32B; 1582 val_len |= RT1011_I2S_RX_DL_32B; 1583 ch_len |= RT1011_I2S_CH_TX_LEN_32B; 1584 ch_len |= RT1011_I2S_CH_RX_LEN_32B; 1585 break; 1586 case 8: 1587 val_len |= RT1011_I2S_TX_DL_8B; 1588 val_len |= RT1011_I2S_RX_DL_8B; 1589 ch_len |= RT1011_I2S_CH_TX_LEN_8B; 1590 ch_len |= RT1011_I2S_CH_RX_LEN_8B; 1591 break; 1592 default: 1593 return -EINVAL; 1594 } 1595 1596 switch (dai->id) { 1597 case RT1011_AIF1: 1598 mask_clk = RT1011_FS_SYS_DIV_MASK; 1599 val_clk = pre_div << RT1011_FS_SYS_DIV_SFT; 1600 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1601 RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK, 1602 val_len); 1603 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1604 RT1011_I2S_CH_TX_LEN_MASK | 1605 RT1011_I2S_CH_RX_LEN_MASK, 1606 ch_len); 1607 break; 1608 default: 1609 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1610 return -EINVAL; 1611 } 1612 1613 snd_soc_component_update_bits(component, 1614 RT1011_CLK_2, mask_clk, val_clk); 1615 1616 return 0; 1617 } 1618 1619 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1620 { 1621 struct snd_soc_component *component = dai->component; 1622 struct snd_soc_dapm_context *dapm = 1623 snd_soc_component_get_dapm(component); 1624 unsigned int reg_val = 0, reg_bclk_inv = 0; 1625 int ret = 0; 1626 1627 snd_soc_dapm_mutex_lock(dapm); 1628 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1629 case SND_SOC_DAIFMT_CBS_CFS: 1630 reg_val |= RT1011_I2S_TDM_MS_S; 1631 break; 1632 default: 1633 ret = -EINVAL; 1634 goto _set_fmt_err_; 1635 } 1636 1637 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1638 case SND_SOC_DAIFMT_NB_NF: 1639 break; 1640 case SND_SOC_DAIFMT_IB_NF: 1641 reg_bclk_inv |= RT1011_TDM_INV_BCLK; 1642 break; 1643 default: 1644 ret = -EINVAL; 1645 goto _set_fmt_err_; 1646 } 1647 1648 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1649 case SND_SOC_DAIFMT_I2S: 1650 break; 1651 case SND_SOC_DAIFMT_LEFT_J: 1652 reg_val |= RT1011_I2S_TDM_DF_LEFT; 1653 break; 1654 case SND_SOC_DAIFMT_DSP_A: 1655 reg_val |= RT1011_I2S_TDM_DF_PCM_A; 1656 break; 1657 case SND_SOC_DAIFMT_DSP_B: 1658 reg_val |= RT1011_I2S_TDM_DF_PCM_B; 1659 break; 1660 default: 1661 ret = -EINVAL; 1662 goto _set_fmt_err_; 1663 } 1664 1665 switch (dai->id) { 1666 case RT1011_AIF1: 1667 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1668 RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK, 1669 reg_val); 1670 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1671 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); 1672 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, 1673 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); 1674 break; 1675 default: 1676 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1677 ret = -EINVAL; 1678 } 1679 1680 _set_fmt_err_: 1681 snd_soc_dapm_mutex_unlock(dapm); 1682 return ret; 1683 } 1684 1685 static int rt1011_set_component_sysclk(struct snd_soc_component *component, 1686 int clk_id, int source, unsigned int freq, int dir) 1687 { 1688 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1689 unsigned int reg_val = 0; 1690 1691 if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src) 1692 return 0; 1693 1694 /* disable MCLK detect in default */ 1695 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1696 RT1011_EN_MCLK_DET_MASK, 0); 1697 1698 switch (clk_id) { 1699 case RT1011_FS_SYS_PRE_S_MCLK: 1700 reg_val |= RT1011_FS_SYS_PRE_MCLK; 1701 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1702 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); 1703 break; 1704 case RT1011_FS_SYS_PRE_S_BCLK: 1705 reg_val |= RT1011_FS_SYS_PRE_BCLK; 1706 break; 1707 case RT1011_FS_SYS_PRE_S_PLL1: 1708 reg_val |= RT1011_FS_SYS_PRE_PLL1; 1709 break; 1710 case RT1011_FS_SYS_PRE_S_RCCLK: 1711 reg_val |= RT1011_FS_SYS_PRE_RCCLK; 1712 break; 1713 default: 1714 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 1715 return -EINVAL; 1716 } 1717 snd_soc_component_update_bits(component, RT1011_CLK_2, 1718 RT1011_FS_SYS_PRE_MASK, reg_val); 1719 rt1011->sysclk = freq; 1720 rt1011->sysclk_src = clk_id; 1721 1722 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 1723 freq, clk_id); 1724 1725 return 0; 1726 } 1727 1728 static int rt1011_set_component_pll(struct snd_soc_component *component, 1729 int pll_id, int source, unsigned int freq_in, 1730 unsigned int freq_out) 1731 { 1732 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1733 struct rl6231_pll_code pll_code; 1734 int ret; 1735 1736 if (source == rt1011->pll_src && freq_in == rt1011->pll_in && 1737 freq_out == rt1011->pll_out) 1738 return 0; 1739 1740 if (!freq_in || !freq_out) { 1741 dev_dbg(component->dev, "PLL disabled\n"); 1742 1743 rt1011->pll_in = 0; 1744 rt1011->pll_out = 0; 1745 snd_soc_component_update_bits(component, RT1011_CLK_2, 1746 RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK); 1747 return 0; 1748 } 1749 1750 switch (source) { 1751 case RT1011_PLL2_S_MCLK: 1752 snd_soc_component_update_bits(component, RT1011_CLK_2, 1753 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK); 1754 snd_soc_component_update_bits(component, RT1011_CLK_2, 1755 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); 1756 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1757 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); 1758 break; 1759 case RT1011_PLL1_S_BCLK: 1760 snd_soc_component_update_bits(component, RT1011_CLK_2, 1761 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK); 1762 break; 1763 case RT1011_PLL2_S_RCCLK: 1764 snd_soc_component_update_bits(component, RT1011_CLK_2, 1765 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK); 1766 snd_soc_component_update_bits(component, RT1011_CLK_2, 1767 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); 1768 break; 1769 default: 1770 dev_err(component->dev, "Unknown PLL Source %d\n", source); 1771 return -EINVAL; 1772 } 1773 1774 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 1775 if (ret < 0) { 1776 dev_err(component->dev, "Unsupported input clock %d\n", 1777 freq_in); 1778 return ret; 1779 } 1780 1781 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 1782 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 1783 pll_code.n_code, pll_code.k_code); 1784 1785 snd_soc_component_write(component, RT1011_PLL_1, 1786 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT | 1787 pll_code.m_bp << RT1011_PLL1_BPM_SFT | pll_code.n_code); 1788 snd_soc_component_write(component, RT1011_PLL_2, 1789 pll_code.k_code); 1790 1791 rt1011->pll_in = freq_in; 1792 rt1011->pll_out = freq_out; 1793 rt1011->pll_src = source; 1794 1795 return 0; 1796 } 1797 1798 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai, 1799 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1800 { 1801 struct snd_soc_component *component = dai->component; 1802 struct snd_soc_dapm_context *dapm = 1803 snd_soc_component_get_dapm(component); 1804 unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum; 1805 int ret = 0, first_bit, last_bit; 1806 1807 snd_soc_dapm_mutex_lock(dapm); 1808 if (rx_mask || tx_mask) 1809 tdm_en = RT1011_TDM_I2S_DOCK_EN_1; 1810 1811 switch (slots) { 1812 case 4: 1813 val |= RT1011_I2S_TX_4CH; 1814 val |= RT1011_I2S_RX_4CH; 1815 break; 1816 case 6: 1817 val |= RT1011_I2S_TX_6CH; 1818 val |= RT1011_I2S_RX_6CH; 1819 break; 1820 case 8: 1821 val |= RT1011_I2S_TX_8CH; 1822 val |= RT1011_I2S_RX_8CH; 1823 break; 1824 case 2: 1825 break; 1826 default: 1827 ret = -EINVAL; 1828 goto _set_tdm_err_; 1829 } 1830 1831 switch (slot_width) { 1832 case 20: 1833 val |= RT1011_I2S_CH_TX_LEN_20B; 1834 val |= RT1011_I2S_CH_RX_LEN_20B; 1835 break; 1836 case 24: 1837 val |= RT1011_I2S_CH_TX_LEN_24B; 1838 val |= RT1011_I2S_CH_RX_LEN_24B; 1839 break; 1840 case 32: 1841 val |= RT1011_I2S_CH_TX_LEN_32B; 1842 val |= RT1011_I2S_CH_RX_LEN_32B; 1843 break; 1844 case 16: 1845 break; 1846 default: 1847 ret = -EINVAL; 1848 goto _set_tdm_err_; 1849 } 1850 1851 /* Rx slot configuration */ 1852 rx_slotnum = hweight_long(rx_mask); 1853 first_bit = find_next_bit((unsigned long *)&rx_mask, 32, 0); 1854 if (rx_slotnum > 1 || rx_slotnum == 0) { 1855 ret = -EINVAL; 1856 dev_dbg(component->dev, "too many rx slots or zero slot\n"); 1857 goto _set_tdm_err_; 1858 } 1859 1860 switch (first_bit) { 1861 case 0: 1862 case 2: 1863 case 4: 1864 case 6: 1865 snd_soc_component_update_bits(component, 1866 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK, 1867 RT1011_MONO_L_CHANNEL); 1868 snd_soc_component_update_bits(component, 1869 RT1011_TDM1_SET_4, 1870 RT1011_TDM_I2S_TX_L_DAC1_1_MASK | 1871 RT1011_TDM_I2S_TX_R_DAC1_1_MASK, 1872 (first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) | 1873 ((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT)); 1874 break; 1875 case 1: 1876 case 3: 1877 case 5: 1878 case 7: 1879 snd_soc_component_update_bits(component, 1880 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK, 1881 RT1011_MONO_R_CHANNEL); 1882 snd_soc_component_update_bits(component, 1883 RT1011_TDM1_SET_4, 1884 RT1011_TDM_I2S_TX_L_DAC1_1_MASK | 1885 RT1011_TDM_I2S_TX_R_DAC1_1_MASK, 1886 ((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) | 1887 (first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT)); 1888 break; 1889 default: 1890 ret = -EINVAL; 1891 goto _set_tdm_err_; 1892 } 1893 1894 /* Tx slot configuration */ 1895 tx_slotnum = hweight_long(tx_mask); 1896 first_bit = find_next_bit((unsigned long *)&tx_mask, 32, 0); 1897 last_bit = find_last_bit((unsigned long *)&tx_mask, 32); 1898 if (tx_slotnum > 2 || (last_bit-first_bit) > 1) { 1899 ret = -EINVAL; 1900 dev_dbg(component->dev, "too many tx slots or tx slot location error\n"); 1901 goto _set_tdm_err_; 1902 } 1903 1904 if (tx_slotnum == 1) { 1905 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2, 1906 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK | 1907 RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit); 1908 switch (first_bit) { 1909 case 1: 1910 snd_soc_component_update_bits(component, 1911 RT1011_TDM1_SET_3, 1912 RT1011_TDM_I2S_RX_ADC1_1_MASK, 1913 RT1011_TDM_I2S_RX_ADC1_1_LL); 1914 break; 1915 case 3: 1916 snd_soc_component_update_bits(component, 1917 RT1011_TDM1_SET_3, 1918 RT1011_TDM_I2S_RX_ADC2_1_MASK, 1919 RT1011_TDM_I2S_RX_ADC2_1_LL); 1920 break; 1921 case 5: 1922 snd_soc_component_update_bits(component, 1923 RT1011_TDM1_SET_3, 1924 RT1011_TDM_I2S_RX_ADC3_1_MASK, 1925 RT1011_TDM_I2S_RX_ADC3_1_LL); 1926 break; 1927 case 7: 1928 snd_soc_component_update_bits(component, 1929 RT1011_TDM1_SET_3, 1930 RT1011_TDM_I2S_RX_ADC4_1_MASK, 1931 RT1011_TDM_I2S_RX_ADC4_1_LL); 1932 break; 1933 case 0: 1934 snd_soc_component_update_bits(component, 1935 RT1011_TDM1_SET_3, 1936 RT1011_TDM_I2S_RX_ADC1_1_MASK, 0); 1937 break; 1938 case 2: 1939 snd_soc_component_update_bits(component, 1940 RT1011_TDM1_SET_3, 1941 RT1011_TDM_I2S_RX_ADC2_1_MASK, 0); 1942 break; 1943 case 4: 1944 snd_soc_component_update_bits(component, 1945 RT1011_TDM1_SET_3, 1946 RT1011_TDM_I2S_RX_ADC3_1_MASK, 0); 1947 break; 1948 case 6: 1949 snd_soc_component_update_bits(component, 1950 RT1011_TDM1_SET_3, 1951 RT1011_TDM_I2S_RX_ADC4_1_MASK, 0); 1952 break; 1953 default: 1954 ret = -EINVAL; 1955 dev_dbg(component->dev, 1956 "tx slot location error\n"); 1957 goto _set_tdm_err_; 1958 } 1959 } else if (tx_slotnum == 2) { 1960 switch (first_bit) { 1961 case 0: 1962 case 2: 1963 case 4: 1964 case 6: 1965 snd_soc_component_update_bits(component, 1966 RT1011_TDM1_SET_2, 1967 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK | 1968 RT1011_TDM_ADCDAT1_DATA_LOCATION, 1969 RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit); 1970 break; 1971 default: 1972 ret = -EINVAL; 1973 dev_dbg(component->dev, 1974 "tx slot location should be paired and start from slot0/2/4/6\n"); 1975 goto _set_tdm_err_; 1976 } 1977 } 1978 1979 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1980 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | 1981 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); 1982 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, 1983 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | 1984 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); 1985 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2, 1986 RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en); 1987 snd_soc_component_update_bits(component, RT1011_TDM2_SET_2, 1988 RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en); 1989 if (tx_slotnum) 1990 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1991 RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG, 1992 RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT); 1993 1994 _set_tdm_err_: 1995 snd_soc_dapm_mutex_unlock(dapm); 1996 return ret; 1997 } 1998 1999 static int rt1011_probe(struct snd_soc_component *component) 2000 { 2001 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 2002 int i; 2003 2004 rt1011->component = component; 2005 2006 schedule_work(&rt1011->cali_work); 2007 2008 rt1011->bq_drc_params = devm_kcalloc(component->dev, 2009 RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *), 2010 GFP_KERNEL); 2011 if (!rt1011->bq_drc_params) 2012 return -ENOMEM; 2013 2014 for (i = 0; i < RT1011_ADVMODE_NUM; i++) { 2015 rt1011->bq_drc_params[i] = devm_kcalloc(component->dev, 2016 RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params), 2017 GFP_KERNEL); 2018 if (!rt1011->bq_drc_params[i]) 2019 return -ENOMEM; 2020 } 2021 2022 return 0; 2023 } 2024 2025 static void rt1011_remove(struct snd_soc_component *component) 2026 { 2027 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 2028 2029 cancel_work_sync(&rt1011->cali_work); 2030 rt1011_reset(rt1011->regmap); 2031 } 2032 2033 #ifdef CONFIG_PM 2034 static int rt1011_suspend(struct snd_soc_component *component) 2035 { 2036 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 2037 2038 regcache_cache_only(rt1011->regmap, true); 2039 regcache_mark_dirty(rt1011->regmap); 2040 2041 return 0; 2042 } 2043 2044 static int rt1011_resume(struct snd_soc_component *component) 2045 { 2046 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 2047 2048 regcache_cache_only(rt1011->regmap, false); 2049 regcache_sync(rt1011->regmap); 2050 2051 return 0; 2052 } 2053 #else 2054 #define rt1011_suspend NULL 2055 #define rt1011_resume NULL 2056 #endif 2057 2058 static int rt1011_set_bias_level(struct snd_soc_component *component, 2059 enum snd_soc_bias_level level) 2060 { 2061 switch (level) { 2062 case SND_SOC_BIAS_OFF: 2063 snd_soc_component_write(component, 2064 RT1011_SYSTEM_RESET_1, 0x0000); 2065 snd_soc_component_write(component, 2066 RT1011_SYSTEM_RESET_2, 0x0000); 2067 snd_soc_component_write(component, 2068 RT1011_SYSTEM_RESET_3, 0x0001); 2069 snd_soc_component_write(component, 2070 RT1011_SYSTEM_RESET_1, 0x003f); 2071 snd_soc_component_write(component, 2072 RT1011_SYSTEM_RESET_2, 0x7fd7); 2073 snd_soc_component_write(component, 2074 RT1011_SYSTEM_RESET_3, 0x770f); 2075 break; 2076 default: 2077 break; 2078 } 2079 2080 return 0; 2081 } 2082 2083 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2084 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 2085 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 2086 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2087 2088 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = { 2089 .hw_params = rt1011_hw_params, 2090 .set_fmt = rt1011_set_dai_fmt, 2091 .set_tdm_slot = rt1011_set_tdm_slot, 2092 }; 2093 2094 static struct snd_soc_dai_driver rt1011_dai[] = { 2095 { 2096 .name = "rt1011-aif", 2097 .playback = { 2098 .stream_name = "AIF1 Playback", 2099 .channels_min = 1, 2100 .channels_max = 2, 2101 .rates = RT1011_STEREO_RATES, 2102 .formats = RT1011_FORMATS, 2103 }, 2104 .ops = &rt1011_aif_dai_ops, 2105 }, 2106 }; 2107 2108 static const struct snd_soc_component_driver soc_component_dev_rt1011 = { 2109 .probe = rt1011_probe, 2110 .remove = rt1011_remove, 2111 .suspend = rt1011_suspend, 2112 .resume = rt1011_resume, 2113 .set_bias_level = rt1011_set_bias_level, 2114 .controls = rt1011_snd_controls, 2115 .num_controls = ARRAY_SIZE(rt1011_snd_controls), 2116 .dapm_widgets = rt1011_dapm_widgets, 2117 .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets), 2118 .dapm_routes = rt1011_dapm_routes, 2119 .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes), 2120 .set_sysclk = rt1011_set_component_sysclk, 2121 .set_pll = rt1011_set_component_pll, 2122 .use_pmdown_time = 1, 2123 .endianness = 1, 2124 .non_legacy_dai_naming = 1, 2125 }; 2126 2127 static const struct regmap_config rt1011_regmap = { 2128 .reg_bits = 16, 2129 .val_bits = 16, 2130 .max_register = RT1011_MAX_REG + 1, 2131 .volatile_reg = rt1011_volatile_register, 2132 .readable_reg = rt1011_readable_register, 2133 .cache_type = REGCACHE_RBTREE, 2134 .reg_defaults = rt1011_reg, 2135 .num_reg_defaults = ARRAY_SIZE(rt1011_reg), 2136 .use_single_read = true, 2137 .use_single_write = true, 2138 }; 2139 2140 #if defined(CONFIG_OF) 2141 static const struct of_device_id rt1011_of_match[] = { 2142 { .compatible = "realtek,rt1011", }, 2143 {}, 2144 }; 2145 MODULE_DEVICE_TABLE(of, rt1011_of_match); 2146 #endif 2147 2148 #ifdef CONFIG_ACPI 2149 static struct acpi_device_id rt1011_acpi_match[] = { 2150 {"10EC1011", 0,}, 2151 {}, 2152 }; 2153 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match); 2154 #endif 2155 2156 static const struct i2c_device_id rt1011_i2c_id[] = { 2157 { "rt1011", 0 }, 2158 { } 2159 }; 2160 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id); 2161 2162 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag) 2163 { 2164 unsigned int value, count = 0, r0[3]; 2165 unsigned int chk_cnt = 50; /* DONT change this */ 2166 unsigned int dc_offset; 2167 unsigned int r0_integer, r0_factor, format; 2168 struct device *dev = regmap_get_device(rt1011->regmap); 2169 struct snd_soc_dapm_context *dapm = 2170 snd_soc_component_get_dapm(rt1011->component); 2171 int ret = 0; 2172 2173 snd_soc_dapm_mutex_lock(dapm); 2174 regcache_cache_bypass(rt1011->regmap, true); 2175 2176 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); 2177 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f); 2178 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f); 2179 2180 /* RC clock */ 2181 regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400); 2182 regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800); 2183 regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020); 2184 regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800); 2185 2186 /* ADC/DAC setting */ 2187 regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20); 2188 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232); 2189 regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925); 2190 regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000); 2191 2192 /* DC detection */ 2193 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c); 2194 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc); 2195 2196 /* Power */ 2197 regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0); 2198 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003); 2199 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860); 2200 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032); 2201 2202 /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */ 2203 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007); 2204 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7); 2205 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44); 2206 regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054); 2207 regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c); 2208 2209 /* DC offset from EFUSE */ 2210 regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00); 2211 regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080); 2212 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2); 2213 regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad); 2214 2215 /* mixer */ 2216 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d); 2217 2218 /* EFUSE read */ 2219 regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a); 2220 msleep(30); 2221 2222 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value); 2223 dc_offset = value << 16; 2224 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value); 2225 dc_offset |= (value & 0xffff); 2226 dev_info(dev, "ADC offset=0x%x\n", dc_offset); 2227 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value); 2228 dc_offset = value << 16; 2229 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value); 2230 dc_offset |= (value & 0xffff); 2231 dev_info(dev, "Gain0 offset=0x%x\n", dc_offset); 2232 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value); 2233 dc_offset = value << 16; 2234 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value); 2235 dc_offset |= (value & 0xffff); 2236 dev_info(dev, "Gain1 offset=0x%x\n", dc_offset); 2237 2238 2239 if (cali_flag) { 2240 /* Class D on */ 2241 regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e); 2242 regmap_write(rt1011->regmap, 2243 RT1011_CLASSD_INTERNAL_SET_1, 0x1701); 2244 2245 /* STP enable */ 2246 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000); 2247 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000); 2248 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040); 2249 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000); 2250 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2); 2251 2252 r0[0] = r0[1] = r0[2] = count = 0; 2253 while (count < chk_cnt) { 2254 msleep(100); 2255 regmap_read(rt1011->regmap, 2256 RT1011_INIT_RECIPROCAL_SYN_24_16, &value); 2257 r0[count%3] = value << 16; 2258 regmap_read(rt1011->regmap, 2259 RT1011_INIT_RECIPROCAL_SYN_15_0, &value); 2260 r0[count%3] |= value; 2261 2262 if (r0[count%3] == 0) 2263 continue; 2264 2265 count++; 2266 2267 if (r0[0] == r0[1] && r0[1] == r0[2]) 2268 break; 2269 } 2270 if (count > chk_cnt) { 2271 dev_err(dev, "Calibrate R0 Failure\n"); 2272 ret = -EAGAIN; 2273 } else { 2274 format = 2147483648U; /* 2^24 * 128 */ 2275 r0_integer = format / r0[0] / 128; 2276 r0_factor = ((format / r0[0] * 100) / 128) 2277 - (r0_integer * 100); 2278 rt1011->r0_reg = r0[0]; 2279 rt1011->cali_done = 1; 2280 dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n", 2281 r0_integer, r0_factor, r0[0]); 2282 } 2283 } 2284 2285 /* depop */ 2286 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000); 2287 msleep(400); 2288 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840); 2289 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702); 2290 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd); 2291 regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701); 2292 regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004); 2293 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40); 2294 regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000); 2295 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000); 2296 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002); 2297 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2); 2298 2299 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); 2300 2301 if (cali_flag) { 2302 if (count <= chk_cnt) { 2303 regmap_write(rt1011->regmap, 2304 RT1011_INIT_RECIPROCAL_REG_24_16, 2305 ((r0[0]>>16) & 0x1ff)); 2306 regmap_write(rt1011->regmap, 2307 RT1011_INIT_RECIPROCAL_REG_15_0, 2308 (r0[0] & 0xffff)); 2309 regmap_write(rt1011->regmap, 2310 RT1011_SPK_TEMP_PROTECT_4, 0x4080); 2311 } 2312 } 2313 2314 regcache_cache_bypass(rt1011->regmap, false); 2315 regcache_mark_dirty(rt1011->regmap); 2316 regcache_sync(rt1011->regmap); 2317 snd_soc_dapm_mutex_unlock(dapm); 2318 2319 return ret; 2320 } 2321 2322 static void rt1011_calibration_work(struct work_struct *work) 2323 { 2324 struct rt1011_priv *rt1011 = 2325 container_of(work, struct rt1011_priv, cali_work); 2326 struct snd_soc_component *component = rt1011->component; 2327 unsigned int r0_integer, r0_factor, format; 2328 2329 if (rt1011->r0_calib) 2330 rt1011_calibrate(rt1011, 0); 2331 else 2332 rt1011_calibrate(rt1011, 1); 2333 2334 /* 2335 * This flag should reset after booting. 2336 * The factory test will do calibration again and use this flag to check 2337 * whether the calibration completed 2338 */ 2339 rt1011->cali_done = 0; 2340 2341 /* initial */ 2342 rt1011_reg_init(component); 2343 2344 /* Apply temperature and calibration data from device property */ 2345 if (rt1011->temperature_calib <= 0xff && 2346 rt1011->temperature_calib > 0) { 2347 snd_soc_component_update_bits(component, 2348 RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff, 2349 (rt1011->temperature_calib << 2)); 2350 } 2351 2352 if (rt1011->r0_calib) { 2353 rt1011->r0_reg = rt1011->r0_calib; 2354 2355 format = 2147483648U; /* 2^24 * 128 */ 2356 r0_integer = format / rt1011->r0_reg / 128; 2357 r0_factor = ((format / rt1011->r0_reg * 100) / 128) 2358 - (r0_integer * 100); 2359 dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n", 2360 r0_integer, r0_factor, rt1011->r0_reg); 2361 2362 rt1011_r0_load(rt1011); 2363 } 2364 } 2365 2366 static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev) 2367 { 2368 device_property_read_u32(dev, "realtek,temperature_calib", 2369 &rt1011->temperature_calib); 2370 device_property_read_u32(dev, "realtek,r0_calib", 2371 &rt1011->r0_calib); 2372 2373 dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x", 2374 __func__, rt1011->r0_calib, rt1011->temperature_calib); 2375 2376 return 0; 2377 } 2378 2379 static int rt1011_i2c_probe(struct i2c_client *i2c, 2380 const struct i2c_device_id *id) 2381 { 2382 struct rt1011_priv *rt1011; 2383 int ret; 2384 unsigned int val; 2385 2386 rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv), 2387 GFP_KERNEL); 2388 if (!rt1011) 2389 return -ENOMEM; 2390 2391 i2c_set_clientdata(i2c, rt1011); 2392 2393 rt1011_parse_dp(rt1011, &i2c->dev); 2394 2395 rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap); 2396 if (IS_ERR(rt1011->regmap)) { 2397 ret = PTR_ERR(rt1011->regmap); 2398 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2399 ret); 2400 return ret; 2401 } 2402 2403 regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val); 2404 if (val != RT1011_DEVICE_ID_NUM) { 2405 dev_err(&i2c->dev, 2406 "Device with ID register %x is not rt1011\n", val); 2407 return -ENODEV; 2408 } 2409 2410 INIT_WORK(&rt1011->cali_work, rt1011_calibration_work); 2411 2412 return devm_snd_soc_register_component(&i2c->dev, 2413 &soc_component_dev_rt1011, 2414 rt1011_dai, ARRAY_SIZE(rt1011_dai)); 2415 2416 } 2417 2418 static void rt1011_i2c_shutdown(struct i2c_client *client) 2419 { 2420 struct rt1011_priv *rt1011 = i2c_get_clientdata(client); 2421 2422 rt1011_reset(rt1011->regmap); 2423 } 2424 2425 static struct i2c_driver rt1011_i2c_driver = { 2426 .driver = { 2427 .name = "rt1011", 2428 .of_match_table = of_match_ptr(rt1011_of_match), 2429 .acpi_match_table = ACPI_PTR(rt1011_acpi_match) 2430 }, 2431 .probe = rt1011_i2c_probe, 2432 .shutdown = rt1011_i2c_shutdown, 2433 .id_table = rt1011_i2c_id, 2434 }; 2435 module_i2c_driver(rt1011_i2c_driver); 2436 2437 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver"); 2438 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 2439 MODULE_LICENSE("GPL"); 2440