1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver 4 * 5 * Copyright(c) 2019 Realtek Semiconductor Corp. 6 * 7 * Author: Shuming Fan <shumingf@realtek.com> 8 * 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/gpio.h> 17 #include <linux/i2c.h> 18 #include <linux/acpi.h> 19 #include <linux/regmap.h> 20 #include <linux/of_gpio.h> 21 #include <linux/platform_device.h> 22 #include <linux/firmware.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 31 #include "rl6231.h" 32 #include "rt1011.h" 33 34 static int rt1011_calibrate(struct rt1011_priv *rt1011, 35 unsigned char cali_flag); 36 37 static const struct reg_sequence init_list[] = { 38 39 { RT1011_POWER_9, 0xa840 }, 40 41 { RT1011_ADC_SET_5, 0x0a20 }, 42 { RT1011_DAC_SET_2, 0xa032 }, 43 { RT1011_ADC_SET_1, 0x2925 }, 44 45 { RT1011_SPK_PRO_DC_DET_1, 0xb00c }, 46 { RT1011_SPK_PRO_DC_DET_2, 0xcccc }, 47 48 { RT1011_A_TIMING_1, 0x6054 }, 49 50 { RT1011_POWER_7, 0x3e55 }, 51 { RT1011_POWER_8, 0x0520 }, 52 { RT1011_BOOST_CON_1, 0xe188 }, 53 { RT1011_POWER_4, 0x16f2 }, 54 55 { RT1011_CROSS_BQ_SET_1, 0x0004 }, 56 { RT1011_SIL_DET, 0xc313 }, 57 { RT1011_SINE_GEN_REG_1, 0x0707 }, 58 59 { RT1011_DC_CALIB_CLASSD_3, 0xcb00 }, 60 61 { RT1011_DAC_SET_1, 0xe702 }, 62 { RT1011_DAC_SET_3, 0x2004 }, 63 }; 64 #define RT1011_INIT_REG_LEN ARRAY_SIZE(init_list) 65 66 static const struct reg_default rt1011_reg[] = { 67 {0x0000, 0x0000}, 68 {0x0002, 0x0000}, 69 {0x0004, 0xa000}, 70 {0x0006, 0x0000}, 71 {0x0008, 0x0003}, 72 {0x000a, 0x087e}, 73 {0x000c, 0x0020}, 74 {0x000e, 0x9002}, 75 {0x0010, 0x0000}, 76 {0x0012, 0x0000}, 77 {0x0020, 0x0c40}, 78 {0x0022, 0x4313}, 79 {0x0076, 0x0000}, 80 {0x0078, 0x0000}, 81 {0x007a, 0x0000}, 82 {0x007c, 0x10ec}, 83 {0x007d, 0x1011}, 84 {0x00f0, 0x5000}, 85 {0x00f2, 0x0374}, 86 {0x00f3, 0x0000}, 87 {0x00f4, 0x0000}, 88 {0x0100, 0x0038}, 89 {0x0102, 0xff02}, 90 {0x0104, 0x0232}, 91 {0x0106, 0x200c}, 92 {0x0107, 0x0000}, 93 {0x0108, 0x2f2f}, 94 {0x010a, 0x2f2f}, 95 {0x010c, 0x002f}, 96 {0x010e, 0xe000}, 97 {0x0110, 0x0820}, 98 {0x0111, 0x4010}, 99 {0x0112, 0x0000}, 100 {0x0114, 0x0000}, 101 {0x0116, 0x0000}, 102 {0x0118, 0x0000}, 103 {0x011a, 0x0101}, 104 {0x011c, 0x4567}, 105 {0x011e, 0x0000}, 106 {0x0120, 0x0000}, 107 {0x0122, 0x0000}, 108 {0x0124, 0x0123}, 109 {0x0126, 0x4567}, 110 {0x0200, 0x0000}, 111 {0x0300, 0xffdd}, 112 {0x0302, 0x001e}, 113 {0x0311, 0x0000}, 114 {0x0313, 0x5254}, 115 {0x0314, 0x0062}, 116 {0x0316, 0x7f40}, 117 {0x0319, 0x000f}, 118 {0x031a, 0xffff}, 119 {0x031b, 0x0000}, 120 {0x031c, 0x009f}, 121 {0x031d, 0xffff}, 122 {0x031e, 0x0000}, 123 {0x031f, 0x0000}, 124 {0x0320, 0xe31c}, 125 {0x0321, 0x0000}, 126 {0x0322, 0x0000}, 127 {0x0324, 0x0000}, 128 {0x0326, 0x0002}, 129 {0x0328, 0x20b2}, 130 {0x0329, 0x0175}, 131 {0x032a, 0x32ad}, 132 {0x032b, 0x3455}, 133 {0x032c, 0x0528}, 134 {0x032d, 0xa800}, 135 {0x032e, 0x030e}, 136 {0x0330, 0x2080}, 137 {0x0332, 0x0034}, 138 {0x0334, 0x0000}, 139 {0x0508, 0x0010}, 140 {0x050a, 0x0018}, 141 {0x050c, 0x0000}, 142 {0x050d, 0xffff}, 143 {0x050e, 0x1f1f}, 144 {0x050f, 0x04ff}, 145 {0x0510, 0x4020}, 146 {0x0511, 0x01f0}, 147 {0x0512, 0x0702}, 148 {0x0516, 0xbb80}, 149 {0x0517, 0xffff}, 150 {0x0518, 0xffff}, 151 {0x0519, 0x307f}, 152 {0x051a, 0xffff}, 153 {0x051b, 0x0000}, 154 {0x051c, 0x0000}, 155 {0x051d, 0x2000}, 156 {0x051e, 0x0000}, 157 {0x051f, 0x0000}, 158 {0x0520, 0x0000}, 159 {0x0521, 0x1001}, 160 {0x0522, 0x7fff}, 161 {0x0524, 0x7fff}, 162 {0x0526, 0x0000}, 163 {0x0528, 0x0000}, 164 {0x052a, 0x0000}, 165 {0x0530, 0x0401}, 166 {0x0532, 0x3000}, 167 {0x0534, 0x0000}, 168 {0x0535, 0xffff}, 169 {0x0536, 0x101c}, 170 {0x0538, 0x1814}, 171 {0x053a, 0x100c}, 172 {0x053c, 0x0804}, 173 {0x053d, 0x0000}, 174 {0x053e, 0x0000}, 175 {0x053f, 0x0000}, 176 {0x0540, 0x0000}, 177 {0x0541, 0x0000}, 178 {0x0542, 0x0000}, 179 {0x0543, 0x0000}, 180 {0x0544, 0x001c}, 181 {0x0545, 0x1814}, 182 {0x0546, 0x100c}, 183 {0x0547, 0x0804}, 184 {0x0548, 0x0000}, 185 {0x0549, 0x0000}, 186 {0x054a, 0x0000}, 187 {0x054b, 0x0000}, 188 {0x054c, 0x0000}, 189 {0x054d, 0x0000}, 190 {0x054e, 0x0000}, 191 {0x054f, 0x0000}, 192 {0x0566, 0x0000}, 193 {0x0568, 0x20f1}, 194 {0x056a, 0x0007}, 195 {0x0600, 0x9d00}, 196 {0x0611, 0x2000}, 197 {0x0612, 0x505f}, 198 {0x0613, 0x0444}, 199 {0x0614, 0x4000}, 200 {0x0615, 0x4004}, 201 {0x0616, 0x0606}, 202 {0x0617, 0x8904}, 203 {0x0618, 0xe021}, 204 {0x0621, 0x2000}, 205 {0x0622, 0x505f}, 206 {0x0623, 0x0444}, 207 {0x0624, 0x4000}, 208 {0x0625, 0x4004}, 209 {0x0626, 0x0606}, 210 {0x0627, 0x8704}, 211 {0x0628, 0xe021}, 212 {0x0631, 0x2000}, 213 {0x0632, 0x517f}, 214 {0x0633, 0x0440}, 215 {0x0634, 0x4000}, 216 {0x0635, 0x4104}, 217 {0x0636, 0x0306}, 218 {0x0637, 0x8904}, 219 {0x0638, 0xe021}, 220 {0x0702, 0x0014}, 221 {0x0704, 0x0000}, 222 {0x0706, 0x0014}, 223 {0x0708, 0x0000}, 224 {0x070a, 0x0000}, 225 {0x0710, 0x0200}, 226 {0x0711, 0x0000}, 227 {0x0712, 0x0200}, 228 {0x0713, 0x0000}, 229 {0x0720, 0x0200}, 230 {0x0721, 0x0000}, 231 {0x0722, 0x0000}, 232 {0x0723, 0x0000}, 233 {0x0724, 0x0000}, 234 {0x0725, 0x0000}, 235 {0x0726, 0x0000}, 236 {0x0727, 0x0000}, 237 {0x0728, 0x0000}, 238 {0x0729, 0x0000}, 239 {0x0730, 0x0200}, 240 {0x0731, 0x0000}, 241 {0x0732, 0x0000}, 242 {0x0733, 0x0000}, 243 {0x0734, 0x0000}, 244 {0x0735, 0x0000}, 245 {0x0736, 0x0000}, 246 {0x0737, 0x0000}, 247 {0x0738, 0x0000}, 248 {0x0739, 0x0000}, 249 {0x0740, 0x0200}, 250 {0x0741, 0x0000}, 251 {0x0742, 0x0000}, 252 {0x0743, 0x0000}, 253 {0x0744, 0x0000}, 254 {0x0745, 0x0000}, 255 {0x0746, 0x0000}, 256 {0x0747, 0x0000}, 257 {0x0748, 0x0000}, 258 {0x0749, 0x0000}, 259 {0x0750, 0x0200}, 260 {0x0751, 0x0000}, 261 {0x0752, 0x0000}, 262 {0x0753, 0x0000}, 263 {0x0754, 0x0000}, 264 {0x0755, 0x0000}, 265 {0x0756, 0x0000}, 266 {0x0757, 0x0000}, 267 {0x0758, 0x0000}, 268 {0x0759, 0x0000}, 269 {0x0760, 0x0200}, 270 {0x0761, 0x0000}, 271 {0x0762, 0x0000}, 272 {0x0763, 0x0000}, 273 {0x0764, 0x0000}, 274 {0x0765, 0x0000}, 275 {0x0766, 0x0000}, 276 {0x0767, 0x0000}, 277 {0x0768, 0x0000}, 278 {0x0769, 0x0000}, 279 {0x0770, 0x0200}, 280 {0x0771, 0x0000}, 281 {0x0772, 0x0000}, 282 {0x0773, 0x0000}, 283 {0x0774, 0x0000}, 284 {0x0775, 0x0000}, 285 {0x0776, 0x0000}, 286 {0x0777, 0x0000}, 287 {0x0778, 0x0000}, 288 {0x0779, 0x0000}, 289 {0x0780, 0x0200}, 290 {0x0781, 0x0000}, 291 {0x0782, 0x0000}, 292 {0x0783, 0x0000}, 293 {0x0784, 0x0000}, 294 {0x0785, 0x0000}, 295 {0x0786, 0x0000}, 296 {0x0787, 0x0000}, 297 {0x0788, 0x0000}, 298 {0x0789, 0x0000}, 299 {0x0790, 0x0200}, 300 {0x0791, 0x0000}, 301 {0x0792, 0x0000}, 302 {0x0793, 0x0000}, 303 {0x0794, 0x0000}, 304 {0x0795, 0x0000}, 305 {0x0796, 0x0000}, 306 {0x0797, 0x0000}, 307 {0x0798, 0x0000}, 308 {0x0799, 0x0000}, 309 {0x07a0, 0x0200}, 310 {0x07a1, 0x0000}, 311 {0x07a2, 0x0000}, 312 {0x07a3, 0x0000}, 313 {0x07a4, 0x0000}, 314 {0x07a5, 0x0000}, 315 {0x07a6, 0x0000}, 316 {0x07a7, 0x0000}, 317 {0x07a8, 0x0000}, 318 {0x07a9, 0x0000}, 319 {0x07b0, 0x0200}, 320 {0x07b1, 0x0000}, 321 {0x07b2, 0x0000}, 322 {0x07b3, 0x0000}, 323 {0x07b4, 0x0000}, 324 {0x07b5, 0x0000}, 325 {0x07b6, 0x0000}, 326 {0x07b7, 0x0000}, 327 {0x07b8, 0x0000}, 328 {0x07b9, 0x0000}, 329 {0x07c0, 0x0200}, 330 {0x07c1, 0x0000}, 331 {0x07c2, 0x0000}, 332 {0x07c3, 0x0000}, 333 {0x07c4, 0x0000}, 334 {0x07c5, 0x0000}, 335 {0x07c6, 0x0000}, 336 {0x07c7, 0x0000}, 337 {0x07c8, 0x0000}, 338 {0x07c9, 0x0000}, 339 {0x1000, 0x4040}, 340 {0x1002, 0x6505}, 341 {0x1004, 0x5405}, 342 {0x1006, 0x5555}, 343 {0x1007, 0x003f}, 344 {0x1008, 0x7fd7}, 345 {0x1009, 0x770f}, 346 {0x100a, 0xfffe}, 347 {0x100b, 0xe000}, 348 {0x100c, 0x0000}, 349 {0x100d, 0x0007}, 350 {0x1010, 0xa433}, 351 {0x1020, 0x0000}, 352 {0x1022, 0x0000}, 353 {0x1024, 0x0000}, 354 {0x1200, 0x5a01}, 355 {0x1202, 0x6324}, 356 {0x1204, 0x0b00}, 357 {0x1206, 0x0000}, 358 {0x1208, 0x0000}, 359 {0x120a, 0x0024}, 360 {0x120c, 0x0000}, 361 {0x120e, 0x000e}, 362 {0x1210, 0x0000}, 363 {0x1212, 0x0000}, 364 {0x1300, 0x0701}, 365 {0x1302, 0x12f9}, 366 {0x1304, 0x3405}, 367 {0x1305, 0x0844}, 368 {0x1306, 0x5611}, 369 {0x1308, 0x555e}, 370 {0x130a, 0xa605}, 371 {0x130c, 0x2000}, 372 {0x130e, 0x0000}, 373 {0x130f, 0x0001}, 374 {0x1310, 0xaa48}, 375 {0x1312, 0x0285}, 376 {0x1314, 0xaaaa}, 377 {0x1316, 0xaaa0}, 378 {0x1318, 0x2aaa}, 379 {0x131a, 0xaa07}, 380 {0x1322, 0x0029}, 381 {0x1323, 0x4a52}, 382 {0x1324, 0x002c}, 383 {0x1325, 0x0b02}, 384 {0x1326, 0x002d}, 385 {0x1327, 0x6b5a}, 386 {0x1328, 0x002e}, 387 {0x1329, 0xcbb2}, 388 {0x132a, 0x0030}, 389 {0x132b, 0x2c0b}, 390 {0x1330, 0x0031}, 391 {0x1331, 0x8c63}, 392 {0x1332, 0x0032}, 393 {0x1333, 0xecbb}, 394 {0x1334, 0x0034}, 395 {0x1335, 0x4d13}, 396 {0x1336, 0x0037}, 397 {0x1337, 0x0dc3}, 398 {0x1338, 0x003d}, 399 {0x1339, 0xef7b}, 400 {0x133a, 0x0044}, 401 {0x133b, 0xd134}, 402 {0x133c, 0x0047}, 403 {0x133d, 0x91e4}, 404 {0x133e, 0x004d}, 405 {0x133f, 0xc370}, 406 {0x1340, 0x0053}, 407 {0x1341, 0xf4fd}, 408 {0x1342, 0x0060}, 409 {0x1343, 0x5816}, 410 {0x1344, 0x006c}, 411 {0x1345, 0xbb2e}, 412 {0x1346, 0x0072}, 413 {0x1347, 0xecbb}, 414 {0x1348, 0x0076}, 415 {0x1349, 0x5d97}, 416 {0x1500, 0x0702}, 417 {0x1502, 0x002f}, 418 {0x1504, 0x0000}, 419 {0x1510, 0x0064}, 420 {0x1512, 0x0000}, 421 {0x1514, 0xdf47}, 422 {0x1516, 0x079c}, 423 {0x1518, 0xfbf5}, 424 {0x151a, 0x00bc}, 425 {0x151c, 0x3b85}, 426 {0x151e, 0x02b3}, 427 {0x1520, 0x3333}, 428 {0x1522, 0x0000}, 429 {0x1524, 0x4000}, 430 {0x1528, 0x0064}, 431 {0x152a, 0x0000}, 432 {0x152c, 0x0000}, 433 {0x152e, 0x0000}, 434 {0x1530, 0x0000}, 435 {0x1532, 0x0000}, 436 {0x1534, 0x0000}, 437 {0x1536, 0x0000}, 438 {0x1538, 0x0040}, 439 {0x1539, 0x0000}, 440 {0x153a, 0x0040}, 441 {0x153b, 0x0000}, 442 {0x153c, 0x0064}, 443 {0x153e, 0x0bf9}, 444 {0x1540, 0xb2a9}, 445 {0x1544, 0x0200}, 446 {0x1546, 0x0000}, 447 {0x1548, 0x00ca}, 448 {0x1552, 0x03ff}, 449 {0x1554, 0x017f}, 450 {0x1556, 0x017f}, 451 {0x155a, 0x0000}, 452 {0x155c, 0x0000}, 453 {0x1560, 0x0040}, 454 {0x1562, 0x0000}, 455 {0x1570, 0x03ff}, 456 {0x1571, 0xdcff}, 457 {0x1572, 0x1e00}, 458 {0x1573, 0x224f}, 459 {0x1574, 0x0000}, 460 {0x1575, 0x0000}, 461 {0x1576, 0x1e00}, 462 {0x1577, 0x0000}, 463 {0x1578, 0x0000}, 464 {0x1579, 0x1128}, 465 {0x157a, 0x03ff}, 466 {0x157b, 0xdcff}, 467 {0x157c, 0x1e00}, 468 {0x157d, 0x224f}, 469 {0x157e, 0x0000}, 470 {0x157f, 0x0000}, 471 {0x1580, 0x1e00}, 472 {0x1581, 0x0000}, 473 {0x1582, 0x0000}, 474 {0x1583, 0x1128}, 475 {0x1590, 0x03ff}, 476 {0x1591, 0xdcff}, 477 {0x1592, 0x1e00}, 478 {0x1593, 0x224f}, 479 {0x1594, 0x0000}, 480 {0x1595, 0x0000}, 481 {0x1596, 0x1e00}, 482 {0x1597, 0x0000}, 483 {0x1598, 0x0000}, 484 {0x1599, 0x1128}, 485 {0x159a, 0x03ff}, 486 {0x159b, 0xdcff}, 487 {0x159c, 0x1e00}, 488 {0x159d, 0x224f}, 489 {0x159e, 0x0000}, 490 {0x159f, 0x0000}, 491 {0x15a0, 0x1e00}, 492 {0x15a1, 0x0000}, 493 {0x15a2, 0x0000}, 494 {0x15a3, 0x1128}, 495 {0x15b0, 0x007f}, 496 {0x15b1, 0xffff}, 497 {0x15b2, 0x007f}, 498 {0x15b3, 0xffff}, 499 {0x15b4, 0x007f}, 500 {0x15b5, 0xffff}, 501 {0x15b8, 0x007f}, 502 {0x15b9, 0xffff}, 503 {0x15bc, 0x0000}, 504 {0x15bd, 0x0000}, 505 {0x15be, 0xff00}, 506 {0x15bf, 0x0000}, 507 {0x15c0, 0xff00}, 508 {0x15c1, 0x0000}, 509 {0x15c3, 0xfc00}, 510 {0x15c4, 0xbb80}, 511 {0x15d0, 0x0000}, 512 {0x15d1, 0x0000}, 513 {0x15d2, 0x0000}, 514 {0x15d3, 0x0000}, 515 {0x15d4, 0x0000}, 516 {0x15d5, 0x0000}, 517 {0x15d6, 0x0000}, 518 {0x15d7, 0x0000}, 519 {0x15d8, 0x0200}, 520 {0x15d9, 0x0000}, 521 {0x15da, 0x0000}, 522 {0x15db, 0x0000}, 523 {0x15dc, 0x0000}, 524 {0x15dd, 0x0000}, 525 {0x15de, 0x0000}, 526 {0x15df, 0x0000}, 527 {0x15e0, 0x0000}, 528 {0x15e1, 0x0000}, 529 {0x15e2, 0x0200}, 530 {0x15e3, 0x0000}, 531 {0x15e4, 0x0000}, 532 {0x15e5, 0x0000}, 533 {0x15e6, 0x0000}, 534 {0x15e7, 0x0000}, 535 {0x15e8, 0x0000}, 536 {0x15e9, 0x0000}, 537 {0x15ea, 0x0000}, 538 {0x15eb, 0x0000}, 539 {0x15ec, 0x0200}, 540 {0x15ed, 0x0000}, 541 {0x15ee, 0x0000}, 542 {0x15ef, 0x0000}, 543 {0x15f0, 0x0000}, 544 {0x15f1, 0x0000}, 545 {0x15f2, 0x0000}, 546 {0x15f3, 0x0000}, 547 {0x15f4, 0x0000}, 548 {0x15f5, 0x0000}, 549 {0x15f6, 0x0200}, 550 {0x15f7, 0x0200}, 551 {0x15f8, 0x8200}, 552 {0x15f9, 0x0000}, 553 {0x1600, 0x007d}, 554 {0x1601, 0xa178}, 555 {0x1602, 0x00c2}, 556 {0x1603, 0x5383}, 557 {0x1604, 0x0000}, 558 {0x1605, 0x02c1}, 559 {0x1606, 0x007d}, 560 {0x1607, 0xa178}, 561 {0x1608, 0x00c2}, 562 {0x1609, 0x5383}, 563 {0x160a, 0x003e}, 564 {0x160b, 0xd37d}, 565 {0x1611, 0x3210}, 566 {0x1612, 0x7418}, 567 {0x1613, 0xc0ff}, 568 {0x1614, 0x0000}, 569 {0x1615, 0x00ff}, 570 {0x1616, 0x0000}, 571 {0x1617, 0x0000}, 572 {0x1621, 0x6210}, 573 {0x1622, 0x7418}, 574 {0x1623, 0xc0ff}, 575 {0x1624, 0x0000}, 576 {0x1625, 0x00ff}, 577 {0x1626, 0x0000}, 578 {0x1627, 0x0000}, 579 {0x1631, 0x3a14}, 580 {0x1632, 0x7418}, 581 {0x1633, 0xc3ff}, 582 {0x1634, 0x0000}, 583 {0x1635, 0x00ff}, 584 {0x1636, 0x0000}, 585 {0x1637, 0x0000}, 586 {0x1638, 0x0000}, 587 {0x163a, 0x0000}, 588 {0x163c, 0x0000}, 589 {0x163e, 0x0000}, 590 {0x1640, 0x0000}, 591 {0x1642, 0x0000}, 592 {0x1644, 0x0000}, 593 {0x1646, 0x0000}, 594 {0x1648, 0x0000}, 595 {0x1650, 0x0000}, 596 {0x1652, 0x0000}, 597 {0x1654, 0x0000}, 598 {0x1656, 0x0000}, 599 {0x1658, 0x0000}, 600 {0x1660, 0x0000}, 601 {0x1662, 0x0000}, 602 {0x1664, 0x0000}, 603 {0x1666, 0x0000}, 604 {0x1668, 0x0000}, 605 {0x1670, 0x0000}, 606 {0x1672, 0x0000}, 607 {0x1674, 0x0000}, 608 {0x1676, 0x0000}, 609 {0x1678, 0x0000}, 610 {0x1680, 0x0000}, 611 {0x1682, 0x0000}, 612 {0x1684, 0x0000}, 613 {0x1686, 0x0000}, 614 {0x1688, 0x0000}, 615 {0x1690, 0x0000}, 616 {0x1692, 0x0000}, 617 {0x1694, 0x0000}, 618 {0x1696, 0x0000}, 619 {0x1698, 0x0000}, 620 {0x1700, 0x0000}, 621 {0x1702, 0x0000}, 622 {0x1704, 0x0000}, 623 {0x1706, 0x0000}, 624 {0x1708, 0x0000}, 625 {0x1710, 0x0000}, 626 {0x1712, 0x0000}, 627 {0x1714, 0x0000}, 628 {0x1716, 0x0000}, 629 {0x1718, 0x0000}, 630 {0x1720, 0x0000}, 631 {0x1722, 0x0000}, 632 {0x1724, 0x0000}, 633 {0x1726, 0x0000}, 634 {0x1728, 0x0000}, 635 {0x1730, 0x0000}, 636 {0x1732, 0x0000}, 637 {0x1734, 0x0000}, 638 {0x1736, 0x0000}, 639 {0x1738, 0x0000}, 640 {0x173a, 0x0000}, 641 {0x173c, 0x0000}, 642 {0x173e, 0x0000}, 643 {0x17bb, 0x0500}, 644 {0x17bd, 0x0004}, 645 {0x17bf, 0x0004}, 646 {0x17c1, 0x0004}, 647 {0x17c2, 0x7fff}, 648 {0x17c3, 0x0000}, 649 {0x17c5, 0x0000}, 650 {0x17c7, 0x0000}, 651 {0x17c9, 0x0000}, 652 {0x17cb, 0x2010}, 653 {0x17cd, 0x0000}, 654 {0x17cf, 0x0000}, 655 {0x17d1, 0x0000}, 656 {0x17d3, 0x0000}, 657 {0x17d5, 0x0000}, 658 {0x17d7, 0x0000}, 659 {0x17d9, 0x0000}, 660 {0x17db, 0x0000}, 661 {0x17dd, 0x0000}, 662 {0x17df, 0x0000}, 663 {0x17e1, 0x0000}, 664 {0x17e3, 0x0000}, 665 {0x17e5, 0x0000}, 666 {0x17e7, 0x0000}, 667 {0x17e9, 0x0000}, 668 {0x17eb, 0x0000}, 669 {0x17ed, 0x0000}, 670 {0x17ef, 0x0000}, 671 {0x17f1, 0x0000}, 672 {0x17f3, 0x0000}, 673 {0x17f5, 0x0000}, 674 {0x17f7, 0x0000}, 675 {0x17f9, 0x0000}, 676 {0x17fb, 0x0000}, 677 {0x17fd, 0x0000}, 678 {0x17ff, 0x0000}, 679 {0x1801, 0x0000}, 680 {0x1803, 0x0000}, 681 }; 682 683 static int rt1011_reg_init(struct snd_soc_component *component) 684 { 685 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 686 687 regmap_multi_reg_write(rt1011->regmap, init_list, RT1011_INIT_REG_LEN); 688 return 0; 689 } 690 691 static bool rt1011_volatile_register(struct device *dev, unsigned int reg) 692 { 693 switch (reg) { 694 case RT1011_RESET: 695 case RT1011_SRC_2: 696 case RT1011_CLK_DET: 697 case RT1011_SIL_DET: 698 case RT1011_VERSION_ID: 699 case RT1011_VENDOR_ID: 700 case RT1011_DEVICE_ID: 701 case RT1011_DUM_RO: 702 case RT1011_DAC_SET_3: 703 case RT1011_PWM_CAL: 704 case RT1011_SPK_VOL_TEST_OUT: 705 case RT1011_VBAT_VOL_DET_1: 706 case RT1011_VBAT_TEST_OUT_1: 707 case RT1011_VBAT_TEST_OUT_2: 708 case RT1011_VBAT_PROTECTION: 709 case RT1011_VBAT_DET: 710 case RT1011_BOOST_CON_1: 711 case RT1011_SHORT_CIRCUIT_DET_1: 712 case RT1011_SPK_TEMP_PROTECT_3: 713 case RT1011_SPK_TEMP_PROTECT_6: 714 case RT1011_SPK_PRO_DC_DET_3: 715 case RT1011_SPK_PRO_DC_DET_7: 716 case RT1011_SPK_PRO_DC_DET_8: 717 case RT1011_SPL_1: 718 case RT1011_SPL_4: 719 case RT1011_EXCUR_PROTECT_1: 720 case RT1011_CROSS_BQ_SET_1: 721 case RT1011_CROSS_BQ_SET_2: 722 case RT1011_BQ_SET_0: 723 case RT1011_BQ_SET_1: 724 case RT1011_BQ_SET_2: 725 case RT1011_TEST_PAD_STATUS: 726 case RT1011_DC_CALIB_CLASSD_1: 727 case RT1011_DC_CALIB_CLASSD_5: 728 case RT1011_DC_CALIB_CLASSD_6: 729 case RT1011_DC_CALIB_CLASSD_7: 730 case RT1011_DC_CALIB_CLASSD_8: 731 case RT1011_SINE_GEN_REG_2: 732 case RT1011_STP_CALIB_RS_TEMP: 733 case RT1011_SPK_RESISTANCE_1: 734 case RT1011_SPK_RESISTANCE_2: 735 case RT1011_SPK_THERMAL: 736 case RT1011_ALC_BK_GAIN_O: 737 case RT1011_ALC_BK_GAIN_O_PRE: 738 case RT1011_SPK_DC_O_23_16: 739 case RT1011_SPK_DC_O_15_0: 740 case RT1011_INIT_RECIPROCAL_SYN_24_16: 741 case RT1011_INIT_RECIPROCAL_SYN_15_0: 742 case RT1011_SPK_EXCURSION_23_16: 743 case RT1011_SPK_EXCURSION_15_0: 744 case RT1011_SEP_MAIN_OUT_23_16: 745 case RT1011_SEP_MAIN_OUT_15_0: 746 case RT1011_ALC_DRC_HB_INTERNAL_5: 747 case RT1011_ALC_DRC_HB_INTERNAL_6: 748 case RT1011_ALC_DRC_HB_INTERNAL_7: 749 case RT1011_ALC_DRC_BB_INTERNAL_5: 750 case RT1011_ALC_DRC_BB_INTERNAL_6: 751 case RT1011_ALC_DRC_BB_INTERNAL_7: 752 case RT1011_ALC_DRC_POS_INTERNAL_5: 753 case RT1011_ALC_DRC_POS_INTERNAL_6: 754 case RT1011_ALC_DRC_POS_INTERNAL_7: 755 case RT1011_ALC_DRC_POS_INTERNAL_8: 756 case RT1011_ALC_DRC_POS_INTERNAL_9: 757 case RT1011_ALC_DRC_POS_INTERNAL_10: 758 case RT1011_ALC_DRC_POS_INTERNAL_11: 759 case RT1011_IRQ_1: 760 case RT1011_EFUSE_CONTROL_1: 761 case RT1011_EFUSE_CONTROL_2: 762 case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0: 763 return true; 764 765 default: 766 return false; 767 } 768 } 769 770 static bool rt1011_readable_register(struct device *dev, unsigned int reg) 771 { 772 switch (reg) { 773 case RT1011_RESET: 774 case RT1011_CLK_1: 775 case RT1011_CLK_2: 776 case RT1011_CLK_3: 777 case RT1011_CLK_4: 778 case RT1011_PLL_1: 779 case RT1011_PLL_2: 780 case RT1011_SRC_1: 781 case RT1011_SRC_2: 782 case RT1011_SRC_3: 783 case RT1011_CLK_DET: 784 case RT1011_SIL_DET: 785 case RT1011_PRIV_INDEX: 786 case RT1011_PRIV_DATA: 787 case RT1011_CUSTOMER_ID: 788 case RT1011_FM_VER: 789 case RT1011_VERSION_ID: 790 case RT1011_VENDOR_ID: 791 case RT1011_DEVICE_ID: 792 case RT1011_DUM_RW_0: 793 case RT1011_DUM_YUN: 794 case RT1011_DUM_RW_1: 795 case RT1011_DUM_RO: 796 case RT1011_MAN_I2C_DEV: 797 case RT1011_DAC_SET_1: 798 case RT1011_DAC_SET_2: 799 case RT1011_DAC_SET_3: 800 case RT1011_ADC_SET: 801 case RT1011_ADC_SET_1: 802 case RT1011_ADC_SET_2: 803 case RT1011_ADC_SET_3: 804 case RT1011_ADC_SET_4: 805 case RT1011_ADC_SET_5: 806 case RT1011_TDM_TOTAL_SET: 807 case RT1011_TDM1_SET_TCON: 808 case RT1011_TDM1_SET_1: 809 case RT1011_TDM1_SET_2: 810 case RT1011_TDM1_SET_3: 811 case RT1011_TDM1_SET_4: 812 case RT1011_TDM1_SET_5: 813 case RT1011_TDM2_SET_1: 814 case RT1011_TDM2_SET_2: 815 case RT1011_TDM2_SET_3: 816 case RT1011_TDM2_SET_4: 817 case RT1011_TDM2_SET_5: 818 case RT1011_PWM_CAL: 819 case RT1011_MIXER_1: 820 case RT1011_MIXER_2: 821 case RT1011_ADRC_LIMIT: 822 case RT1011_A_PRO: 823 case RT1011_A_TIMING_1: 824 case RT1011_A_TIMING_2: 825 case RT1011_A_TEMP_SEN: 826 case RT1011_SPK_VOL_DET_1: 827 case RT1011_SPK_VOL_DET_2: 828 case RT1011_SPK_VOL_TEST_OUT: 829 case RT1011_VBAT_VOL_DET_1: 830 case RT1011_VBAT_VOL_DET_2: 831 case RT1011_VBAT_TEST_OUT_1: 832 case RT1011_VBAT_TEST_OUT_2: 833 case RT1011_VBAT_PROTECTION: 834 case RT1011_VBAT_DET: 835 case RT1011_POWER_1: 836 case RT1011_POWER_2: 837 case RT1011_POWER_3: 838 case RT1011_POWER_4: 839 case RT1011_POWER_5: 840 case RT1011_POWER_6: 841 case RT1011_POWER_7: 842 case RT1011_POWER_8: 843 case RT1011_POWER_9: 844 case RT1011_CLASS_D_POS: 845 case RT1011_BOOST_CON_1: 846 case RT1011_BOOST_CON_2: 847 case RT1011_ANALOG_CTRL: 848 case RT1011_POWER_SEQ: 849 case RT1011_SHORT_CIRCUIT_DET_1: 850 case RT1011_SHORT_CIRCUIT_DET_2: 851 case RT1011_SPK_TEMP_PROTECT_0: 852 case RT1011_SPK_TEMP_PROTECT_1: 853 case RT1011_SPK_TEMP_PROTECT_2: 854 case RT1011_SPK_TEMP_PROTECT_3: 855 case RT1011_SPK_TEMP_PROTECT_4: 856 case RT1011_SPK_TEMP_PROTECT_5: 857 case RT1011_SPK_TEMP_PROTECT_6: 858 case RT1011_SPK_TEMP_PROTECT_7: 859 case RT1011_SPK_TEMP_PROTECT_8: 860 case RT1011_SPK_TEMP_PROTECT_9: 861 case RT1011_SPK_PRO_DC_DET_1: 862 case RT1011_SPK_PRO_DC_DET_2: 863 case RT1011_SPK_PRO_DC_DET_3: 864 case RT1011_SPK_PRO_DC_DET_4: 865 case RT1011_SPK_PRO_DC_DET_5: 866 case RT1011_SPK_PRO_DC_DET_6: 867 case RT1011_SPK_PRO_DC_DET_7: 868 case RT1011_SPK_PRO_DC_DET_8: 869 case RT1011_SPL_1: 870 case RT1011_SPL_2: 871 case RT1011_SPL_3: 872 case RT1011_SPL_4: 873 case RT1011_THER_FOLD_BACK_1: 874 case RT1011_THER_FOLD_BACK_2: 875 case RT1011_EXCUR_PROTECT_1: 876 case RT1011_EXCUR_PROTECT_2: 877 case RT1011_EXCUR_PROTECT_3: 878 case RT1011_EXCUR_PROTECT_4: 879 case RT1011_BAT_GAIN_1: 880 case RT1011_BAT_GAIN_2: 881 case RT1011_BAT_GAIN_3: 882 case RT1011_BAT_GAIN_4: 883 case RT1011_BAT_GAIN_5: 884 case RT1011_BAT_GAIN_6: 885 case RT1011_BAT_GAIN_7: 886 case RT1011_BAT_GAIN_8: 887 case RT1011_BAT_GAIN_9: 888 case RT1011_BAT_GAIN_10: 889 case RT1011_BAT_GAIN_11: 890 case RT1011_BAT_RT_THMAX_1: 891 case RT1011_BAT_RT_THMAX_2: 892 case RT1011_BAT_RT_THMAX_3: 893 case RT1011_BAT_RT_THMAX_4: 894 case RT1011_BAT_RT_THMAX_5: 895 case RT1011_BAT_RT_THMAX_6: 896 case RT1011_BAT_RT_THMAX_7: 897 case RT1011_BAT_RT_THMAX_8: 898 case RT1011_BAT_RT_THMAX_9: 899 case RT1011_BAT_RT_THMAX_10: 900 case RT1011_BAT_RT_THMAX_11: 901 case RT1011_BAT_RT_THMAX_12: 902 case RT1011_SPREAD_SPECTURM: 903 case RT1011_PRO_GAIN_MODE: 904 case RT1011_RT_DRC_CROSS: 905 case RT1011_RT_DRC_HB_1: 906 case RT1011_RT_DRC_HB_2: 907 case RT1011_RT_DRC_HB_3: 908 case RT1011_RT_DRC_HB_4: 909 case RT1011_RT_DRC_HB_5: 910 case RT1011_RT_DRC_HB_6: 911 case RT1011_RT_DRC_HB_7: 912 case RT1011_RT_DRC_HB_8: 913 case RT1011_RT_DRC_BB_1: 914 case RT1011_RT_DRC_BB_2: 915 case RT1011_RT_DRC_BB_3: 916 case RT1011_RT_DRC_BB_4: 917 case RT1011_RT_DRC_BB_5: 918 case RT1011_RT_DRC_BB_6: 919 case RT1011_RT_DRC_BB_7: 920 case RT1011_RT_DRC_BB_8: 921 case RT1011_RT_DRC_POS_1: 922 case RT1011_RT_DRC_POS_2: 923 case RT1011_RT_DRC_POS_3: 924 case RT1011_RT_DRC_POS_4: 925 case RT1011_RT_DRC_POS_5: 926 case RT1011_RT_DRC_POS_6: 927 case RT1011_RT_DRC_POS_7: 928 case RT1011_RT_DRC_POS_8: 929 case RT1011_CROSS_BQ_SET_1: 930 case RT1011_CROSS_BQ_SET_2: 931 case RT1011_BQ_SET_0: 932 case RT1011_BQ_SET_1: 933 case RT1011_BQ_SET_2: 934 case RT1011_BQ_PRE_GAIN_28_16: 935 case RT1011_BQ_PRE_GAIN_15_0: 936 case RT1011_BQ_POST_GAIN_28_16: 937 case RT1011_BQ_POST_GAIN_15_0: 938 case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0: 939 case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0: 940 case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0: 941 case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0: 942 case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0: 943 case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0: 944 case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0: 945 case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0: 946 case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0: 947 case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0: 948 case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0: 949 case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET: 950 case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3: 951 case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10: 952 case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1: 953 case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36: 954 case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3: 955 case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL: 956 case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0: 957 case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0: 958 case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0: 959 case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12: 960 case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7: 961 case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7: 962 case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8: 963 case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5: 964 case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5: 965 case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5: 966 case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5: 967 case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5: 968 case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5: 969 case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5: 970 case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5: 971 case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5: 972 case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5: 973 case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE: 974 case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0: 975 return true; 976 default: 977 return false; 978 } 979 } 980 981 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0); 982 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1739, 37, 0); 983 984 static const char * const rt1011_din_source_select[] = { 985 "Left", 986 "Right", 987 "Left + Right average", 988 }; 989 990 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5, 991 rt1011_din_source_select); 992 993 static const char * const rt1011_tdm_data_out_select[] = { 994 "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR", 995 "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS", 996 "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST" 997 }; 998 999 static const char * const rt1011_tdm_l_ch_data_select[] = { 1000 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 1001 }; 1002 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12, 1003 rt1011_tdm_l_ch_data_select); 1004 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12, 1005 rt1011_tdm_l_ch_data_select); 1006 1007 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum, 1008 RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select); 1009 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0, 1010 rt1011_tdm_l_ch_data_select); 1011 1012 static const char * const rt1011_adc_data_mode_select[] = { 1013 "Stereo", "Mono" 1014 }; 1015 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12, 1016 rt1011_adc_data_mode_select); 1017 1018 static const char * const rt1011_tdm_adc_data_len_control[] = { 1019 "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH" 1020 }; 1021 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13, 1022 rt1011_tdm_adc_data_len_control); 1023 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13, 1024 rt1011_tdm_adc_data_len_control); 1025 1026 static const char * const rt1011_tdm_adc_swap_select[] = { 1027 "L/R", "R/L", "L/L", "R/R" 1028 }; 1029 1030 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6, 1031 rt1011_tdm_adc_swap_select); 1032 1033 static void rt1011_reset(struct regmap *regmap) 1034 { 1035 regmap_write(regmap, RT1011_RESET, 0); 1036 } 1037 1038 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol, 1039 struct snd_ctl_elem_value *ucontrol) 1040 { 1041 struct snd_soc_component *component = 1042 snd_soc_kcontrol_component(kcontrol); 1043 struct rt1011_priv *rt1011 = 1044 snd_soc_component_get_drvdata(component); 1045 1046 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode; 1047 1048 return 0; 1049 } 1050 1051 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol, 1052 struct snd_ctl_elem_value *ucontrol) 1053 { 1054 struct snd_soc_component *component = 1055 snd_soc_kcontrol_component(kcontrol); 1056 struct rt1011_priv *rt1011 = 1057 snd_soc_component_get_drvdata(component); 1058 1059 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode) 1060 return 0; 1061 1062 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1063 rt1011->recv_spk_mode = ucontrol->value.integer.value[0]; 1064 1065 if (rt1011->recv_spk_mode) { 1066 1067 /* 1: recevier mode on */ 1068 snd_soc_component_update_bits(component, 1069 RT1011_CLASSD_INTERNAL_SET_3, 1070 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, 1071 RT1011_REG_GAIN_CLASSD_RI_410K); 1072 snd_soc_component_update_bits(component, 1073 RT1011_CLASSD_INTERNAL_SET_1, 1074 RT1011_RECV_MODE_SPK_MASK, 1075 RT1011_RECV_MODE); 1076 } else { 1077 /* 0: speaker mode on */ 1078 snd_soc_component_update_bits(component, 1079 RT1011_CLASSD_INTERNAL_SET_3, 1080 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, 1081 RT1011_REG_GAIN_CLASSD_RI_72P5K); 1082 snd_soc_component_update_bits(component, 1083 RT1011_CLASSD_INTERNAL_SET_1, 1084 RT1011_RECV_MODE_SPK_MASK, 1085 RT1011_SPK_MODE); 1086 } 1087 } 1088 1089 return 0; 1090 } 1091 1092 static bool rt1011_validate_bq_drc_coeff(unsigned short reg) 1093 { 1094 if ((reg == RT1011_DAC_SET_1) | 1095 (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) | 1096 (reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) | 1097 (reg == RT1011_MIXER_1) | 1098 (reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 && 1099 reg <= RT1011_POWER_8) | 1100 (reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) | 1101 (reg >= RT1011_SPK_TEMP_PROTECT_0 && 1102 reg <= RT1011_SPK_TEMP_PROTECT_6) | 1103 (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) | 1104 (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) | 1105 (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) | 1106 (reg >= RT1011_SMART_BOOST_TIMING_1 && 1107 reg <= RT1011_SMART_BOOST_TIMING_36) | 1108 (reg == RT1011_SINE_GEN_REG_1) | 1109 (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && 1110 reg <= RT1011_BQ_6_PARAMS_CHECK_5) | 1111 (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && 1112 reg <= RT1011_BQ_10_PARAMS_CHECK_5)) 1113 return true; 1114 1115 return false; 1116 } 1117 1118 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol, 1119 struct snd_ctl_elem_value *ucontrol) 1120 { 1121 struct snd_soc_component *component = 1122 snd_soc_kcontrol_component(kcontrol); 1123 struct rt1011_priv *rt1011 = 1124 snd_soc_component_get_drvdata(component); 1125 struct rt1011_bq_drc_params *bq_drc_info; 1126 struct rt1011_bq_drc_params *params = 1127 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; 1128 unsigned int i, mode_idx = 0; 1129 1130 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) 1131 mode_idx = RT1011_ADVMODE_INITIAL_SET; 1132 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) 1133 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; 1134 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) 1135 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; 1136 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) 1137 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; 1138 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) 1139 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; 1140 else 1141 return -EINVAL; 1142 1143 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, 1144 ucontrol->id.name, mode_idx); 1145 bq_drc_info = rt1011->bq_drc_params[mode_idx]; 1146 1147 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1148 params[i].reg = bq_drc_info[i].reg; 1149 params[i].val = bq_drc_info[i].val; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol, 1156 struct snd_ctl_elem_value *ucontrol) 1157 { 1158 struct snd_soc_component *component = 1159 snd_soc_kcontrol_component(kcontrol); 1160 struct rt1011_priv *rt1011 = 1161 snd_soc_component_get_drvdata(component); 1162 struct rt1011_bq_drc_params *bq_drc_info; 1163 struct rt1011_bq_drc_params *params = 1164 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; 1165 unsigned int i, mode_idx = 0; 1166 1167 if (!component->card->instantiated) 1168 return 0; 1169 1170 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) 1171 mode_idx = RT1011_ADVMODE_INITIAL_SET; 1172 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) 1173 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; 1174 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) 1175 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; 1176 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) 1177 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; 1178 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) 1179 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; 1180 else 1181 return -EINVAL; 1182 1183 bq_drc_info = rt1011->bq_drc_params[mode_idx]; 1184 memset(bq_drc_info, 0, 1185 sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM); 1186 1187 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, 1188 ucontrol->id.name, mode_idx); 1189 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1190 bq_drc_info[i].reg = params[i].reg; 1191 bq_drc_info[i].val = params[i].val; 1192 } 1193 1194 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { 1195 if (bq_drc_info[i].reg == 0) 1196 break; 1197 else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) { 1198 snd_soc_component_write(component, bq_drc_info[i].reg, 1199 bq_drc_info[i].val); 1200 } 1201 } 1202 1203 return 0; 1204 } 1205 1206 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol, 1207 struct snd_ctl_elem_info *uinfo) 1208 { 1209 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1210 uinfo->count = 128; 1211 uinfo->value.integer.max = 0x17ffffff; 1212 1213 return 0; 1214 } 1215 1216 #define RT1011_BQ_DRC(xname) \ 1217 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1218 .info = rt1011_bq_drc_info, \ 1219 .get = rt1011_bq_drc_coeff_get, \ 1220 .put = rt1011_bq_drc_coeff_put \ 1221 } 1222 1223 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol, 1224 struct snd_ctl_elem_value *ucontrol) 1225 { 1226 ucontrol->value.integer.value[0] = 0; 1227 1228 return 0; 1229 } 1230 1231 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol, 1232 struct snd_ctl_elem_value *ucontrol) 1233 { 1234 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1235 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1236 1237 if (!component->card->instantiated) 1238 return 0; 1239 1240 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && 1241 ucontrol->value.integer.value[0]) 1242 rt1011_calibrate(rt1011, 1); 1243 1244 return 0; 1245 } 1246 1247 static int rt1011_r0_load(struct rt1011_priv *rt1011) 1248 { 1249 if (!rt1011->r0_reg) 1250 return -EINVAL; 1251 1252 /* write R0 to register */ 1253 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16, 1254 ((rt1011->r0_reg>>16) & 0x1ff)); 1255 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0, 1256 (rt1011->r0_reg & 0xffff)); 1257 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080); 1258 1259 return 0; 1260 } 1261 1262 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol, 1263 struct snd_ctl_elem_value *ucontrol) 1264 { 1265 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1266 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1267 1268 ucontrol->value.integer.value[0] = rt1011->r0_reg; 1269 1270 return 0; 1271 } 1272 1273 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol, 1274 struct snd_ctl_elem_value *ucontrol) 1275 { 1276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1277 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1278 struct device *dev; 1279 unsigned int r0_integer, r0_factor, format; 1280 1281 if (ucontrol->value.integer.value[0] == rt1011->r0_reg) 1282 return 0; 1283 1284 if (!component->card->instantiated) 1285 return 0; 1286 1287 if (ucontrol->value.integer.value[0] == 0) 1288 return -EINVAL; 1289 1290 dev = regmap_get_device(rt1011->regmap); 1291 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1292 rt1011->r0_reg = ucontrol->value.integer.value[0]; 1293 1294 format = 2147483648U; /* 2^24 * 128 */ 1295 r0_integer = format / rt1011->r0_reg / 128; 1296 r0_factor = ((format / rt1011->r0_reg * 100) / 128) 1297 - (r0_integer * 100); 1298 dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n", 1299 r0_integer, r0_factor, rt1011->r0_reg); 1300 1301 if (rt1011->r0_reg) 1302 rt1011_r0_load(rt1011); 1303 } 1304 1305 return 0; 1306 } 1307 1308 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol, 1309 struct snd_ctl_elem_info *uinfo) 1310 { 1311 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1312 uinfo->count = 1; 1313 uinfo->value.integer.max = 0x1ffffff; 1314 1315 return 0; 1316 } 1317 1318 #define RT1011_R0_LOAD(xname) \ 1319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1320 .info = rt1011_r0_load_info, \ 1321 .get = rt1011_r0_load_mode_get, \ 1322 .put = rt1011_r0_load_mode_put \ 1323 } 1324 1325 static const struct snd_kcontrol_new rt1011_snd_controls[] = { 1326 /* I2S Data In Selection */ 1327 SOC_ENUM("DIN Source", rt1011_din_source_enum), 1328 1329 /* TDM Data In Selection */ 1330 SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum), 1331 SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum), 1332 1333 /* TDM1 Data Out Selection */ 1334 SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum), 1335 SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum), 1336 SOC_ENUM("TDM1 ADCDAT Swap Select", rt1011_tdm_adc1_1_enum), 1337 1338 /* Data Out Mode */ 1339 SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum), 1340 SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum), 1341 SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum), 1342 1343 /* Speaker/Receiver Mode */ 1344 SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0, 1345 rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put), 1346 1347 /* BiQuad/DRC/SmartBoost Settings */ 1348 RT1011_BQ_DRC("AdvanceMode Initial Set"), 1349 RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"), 1350 RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"), 1351 RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"), 1352 RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"), 1353 1354 /* R0 */ 1355 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, 1356 rt1011_r0_cali_get, rt1011_r0_cali_put), 1357 RT1011_R0_LOAD("R0 Load Mode"), 1358 }; 1359 1360 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1361 struct snd_soc_dapm_widget *sink) 1362 { 1363 struct snd_soc_component *component = 1364 snd_soc_dapm_to_component(source->dapm); 1365 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1366 1367 if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1) 1368 return 1; 1369 else 1370 return 0; 1371 } 1372 1373 static int rt1011_dac_event(struct snd_soc_dapm_widget *w, 1374 struct snd_kcontrol *kcontrol, int event) 1375 { 1376 struct snd_soc_component *component = 1377 snd_soc_dapm_to_component(w->dapm); 1378 1379 switch (event) { 1380 case SND_SOC_DAPM_POST_PMU: 1381 snd_soc_component_update_bits(component, 1382 RT1011_SPK_TEMP_PROTECT_0, 1383 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 1384 RT1011_STP_EN | RT1011_STP_RS_CLB_EN); 1385 snd_soc_component_update_bits(component, RT1011_POWER_9, 1386 RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB); 1387 msleep(50); 1388 snd_soc_component_update_bits(component, 1389 RT1011_CLASSD_INTERNAL_SET_1, 1390 RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK); 1391 break; 1392 case SND_SOC_DAPM_PRE_PMD: 1393 snd_soc_component_update_bits(component, RT1011_POWER_9, 1394 RT1011_POW_MNL_SDB_MASK, 0); 1395 snd_soc_component_update_bits(component, 1396 RT1011_SPK_TEMP_PROTECT_0, 1397 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0); 1398 msleep(200); 1399 snd_soc_component_update_bits(component, 1400 RT1011_CLASSD_INTERNAL_SET_1, 1401 RT1011_DRIVER_READY_SPK, 0); 1402 break; 1403 1404 default: 1405 return 0; 1406 } 1407 1408 return 0; 1409 } 1410 1411 1412 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = { 1413 SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1, 1414 RT1011_POW_LDO2_BIT, 0, NULL, 0), 1415 SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1, 1416 RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0), 1417 SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1, 1418 RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0), 1419 1420 SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2, 1421 RT1011_PLLEN_BIT, 0, NULL, 0), 1422 SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2, 1423 RT1011_POW_BG_BIT, 0, NULL, 0), 1424 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2, 1425 RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0), 1426 1427 SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3, 1428 RT1011_POW_DET_VBAT_BIT, 0, NULL, 0), 1429 SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3, 1430 RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0), 1431 SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3, 1432 RT1011_POW_ADC_I_BIT, 0, NULL, 0), 1433 SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3, 1434 RT1011_POW_ADC_V_BIT, 0, NULL, 0), 1435 SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3, 1436 RT1011_POW_ADC_T_BIT, 0, NULL, 0), 1437 SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3, 1438 RT1011_POWD_ADC_T_BIT, 0, NULL, 0), 1439 SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3, 1440 RT1011_POW_MIX_I_BIT, 0, NULL, 0), 1441 SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3, 1442 RT1011_POW_MIX_V_BIT, 0, NULL, 0), 1443 SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3, 1444 RT1011_POW_SUM_I_BIT, 0, NULL, 0), 1445 SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3, 1446 RT1011_POW_SUM_V_BIT, 0, NULL, 0), 1447 SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3, 1448 RT1011_POW_MIX_T_BIT, 0, NULL, 0), 1449 SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3, 1450 RT1011_POW_VREF_LV_BIT, 0, NULL, 0), 1451 1452 SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4, 1453 RT1011_POW_EN_SWR_BIT, 0, NULL, 0), 1454 SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4, 1455 RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0), 1456 SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4, 1457 RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0), 1458 1459 SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN, 1460 RT1011_POW_TEMP_REG_BIT, 0, NULL, 0), 1461 1462 /* Audio Interface */ 1463 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1464 /* Digital Interface */ 1465 SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1, 1466 RT1011_POW_DAC_BIT, 0, NULL, 0), 1467 SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1, 1468 RT1011_POW_CLK12M_BIT, 0, NULL, 0), 1469 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3, 1470 RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event, 1471 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1472 1473 /* Output Lines */ 1474 SND_SOC_DAPM_OUTPUT("SPO"), 1475 }; 1476 1477 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = { 1478 1479 { "DAC", NULL, "AIF1RX" }, 1480 { "DAC", NULL, "DAC Power" }, 1481 { "DAC", NULL, "LDO2" }, 1482 { "DAC", NULL, "ISENSE SPK" }, 1483 { "DAC", NULL, "VSENSE SPK" }, 1484 { "DAC", NULL, "CLK12M" }, 1485 1486 { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll }, 1487 { "DAC", NULL, "BG" }, 1488 { "DAC", NULL, "BG MBIAS" }, 1489 1490 { "DAC", NULL, "BOOST SWR" }, 1491 { "DAC", NULL, "BGOK SWR" }, 1492 { "DAC", NULL, "VPOK SWR" }, 1493 1494 { "DAC", NULL, "DET VBAT" }, 1495 { "DAC", NULL, "MBIAS" }, 1496 { "DAC", NULL, "VREF" }, 1497 { "DAC", NULL, "ADC I" }, 1498 { "DAC", NULL, "ADC V" }, 1499 { "DAC", NULL, "ADC T" }, 1500 { "DAC", NULL, "DITHER ADC T" }, 1501 { "DAC", NULL, "MIX I" }, 1502 { "DAC", NULL, "MIX V" }, 1503 { "DAC", NULL, "SUM I" }, 1504 { "DAC", NULL, "SUM V" }, 1505 { "DAC", NULL, "MIX T" }, 1506 1507 { "DAC", NULL, "TEMP REG" }, 1508 1509 { "SPO", NULL, "DAC" }, 1510 }; 1511 1512 static int rt1011_get_clk_info(int sclk, int rate) 1513 { 1514 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; 1515 1516 if (sclk <= 0 || rate <= 0) 1517 return -EINVAL; 1518 1519 rate = rate << 8; 1520 for (i = 0; i < ARRAY_SIZE(pd); i++) 1521 if (sclk == rate * pd[i]) 1522 return i; 1523 1524 return -EINVAL; 1525 } 1526 1527 static int rt1011_hw_params(struct snd_pcm_substream *substream, 1528 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1529 { 1530 struct snd_soc_component *component = dai->component; 1531 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1532 unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk; 1533 int pre_div, bclk_ms, frame_size; 1534 1535 rt1011->lrck = params_rate(params); 1536 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck); 1537 if (pre_div < 0) { 1538 dev_warn(component->dev, "Force using PLL "); 1539 snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK, 1540 rt1011->lrck * 64, rt1011->lrck * 256); 1541 snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1, 1542 rt1011->lrck * 256, SND_SOC_CLOCK_IN); 1543 pre_div = 0; 1544 } 1545 frame_size = snd_soc_params_to_frame_size(params); 1546 if (frame_size < 0) { 1547 dev_err(component->dev, "Unsupported frame size: %d\n", 1548 frame_size); 1549 return -EINVAL; 1550 } 1551 1552 bclk_ms = frame_size > 32; 1553 rt1011->bclk = rt1011->lrck * (32 << bclk_ms); 1554 1555 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 1556 bclk_ms, pre_div, dai->id); 1557 1558 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1559 rt1011->lrck, pre_div, dai->id); 1560 1561 switch (params_width(params)) { 1562 case 16: 1563 val_len |= RT1011_I2S_TX_DL_16B; 1564 val_len |= RT1011_I2S_RX_DL_16B; 1565 ch_len |= RT1011_I2S_CH_TX_LEN_16B; 1566 ch_len |= RT1011_I2S_CH_RX_LEN_16B; 1567 break; 1568 case 20: 1569 val_len |= RT1011_I2S_TX_DL_20B; 1570 val_len |= RT1011_I2S_RX_DL_20B; 1571 ch_len |= RT1011_I2S_CH_TX_LEN_20B; 1572 ch_len |= RT1011_I2S_CH_RX_LEN_20B; 1573 break; 1574 case 24: 1575 val_len |= RT1011_I2S_TX_DL_24B; 1576 val_len |= RT1011_I2S_RX_DL_24B; 1577 ch_len |= RT1011_I2S_CH_TX_LEN_24B; 1578 ch_len |= RT1011_I2S_CH_RX_LEN_24B; 1579 break; 1580 case 32: 1581 val_len |= RT1011_I2S_TX_DL_32B; 1582 val_len |= RT1011_I2S_RX_DL_32B; 1583 ch_len |= RT1011_I2S_CH_TX_LEN_32B; 1584 ch_len |= RT1011_I2S_CH_RX_LEN_32B; 1585 break; 1586 case 8: 1587 val_len |= RT1011_I2S_TX_DL_8B; 1588 val_len |= RT1011_I2S_RX_DL_8B; 1589 ch_len |= RT1011_I2S_CH_TX_LEN_8B; 1590 ch_len |= RT1011_I2S_CH_RX_LEN_8B; 1591 break; 1592 default: 1593 return -EINVAL; 1594 } 1595 1596 switch (dai->id) { 1597 case RT1011_AIF1: 1598 mask_clk = RT1011_FS_SYS_DIV_MASK; 1599 val_clk = pre_div << RT1011_FS_SYS_DIV_SFT; 1600 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1601 RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK, 1602 val_len); 1603 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1604 RT1011_I2S_CH_TX_LEN_MASK | 1605 RT1011_I2S_CH_RX_LEN_MASK, 1606 ch_len); 1607 break; 1608 default: 1609 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1610 return -EINVAL; 1611 } 1612 1613 snd_soc_component_update_bits(component, 1614 RT1011_CLK_2, mask_clk, val_clk); 1615 1616 return 0; 1617 } 1618 1619 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1620 { 1621 struct snd_soc_component *component = dai->component; 1622 unsigned int reg_val = 0, reg_bclk_inv = 0; 1623 1624 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1625 case SND_SOC_DAIFMT_CBS_CFS: 1626 reg_val |= RT1011_I2S_TDM_MS_S; 1627 break; 1628 default: 1629 return -EINVAL; 1630 } 1631 1632 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1633 case SND_SOC_DAIFMT_NB_NF: 1634 break; 1635 case SND_SOC_DAIFMT_IB_NF: 1636 reg_bclk_inv |= RT1011_TDM_INV_BCLK; 1637 break; 1638 default: 1639 return -EINVAL; 1640 } 1641 1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1643 case SND_SOC_DAIFMT_I2S: 1644 break; 1645 case SND_SOC_DAIFMT_LEFT_J: 1646 reg_val |= RT1011_I2S_TDM_DF_LEFT; 1647 break; 1648 case SND_SOC_DAIFMT_DSP_A: 1649 reg_val |= RT1011_I2S_TDM_DF_PCM_A; 1650 break; 1651 case SND_SOC_DAIFMT_DSP_B: 1652 reg_val |= RT1011_I2S_TDM_DF_PCM_B; 1653 break; 1654 default: 1655 return -EINVAL; 1656 } 1657 1658 switch (dai->id) { 1659 case RT1011_AIF1: 1660 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1661 RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK, 1662 reg_val); 1663 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1664 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); 1665 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, 1666 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); 1667 break; 1668 default: 1669 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1670 return -EINVAL; 1671 } 1672 return 0; 1673 } 1674 1675 static int rt1011_set_component_sysclk(struct snd_soc_component *component, 1676 int clk_id, int source, unsigned int freq, int dir) 1677 { 1678 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1679 unsigned int reg_val = 0; 1680 1681 if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src) 1682 return 0; 1683 1684 /* disable MCLK detect in default */ 1685 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1686 RT1011_EN_MCLK_DET_MASK, 0); 1687 1688 switch (clk_id) { 1689 case RT1011_FS_SYS_PRE_S_MCLK: 1690 reg_val |= RT1011_FS_SYS_PRE_MCLK; 1691 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1692 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); 1693 break; 1694 case RT1011_FS_SYS_PRE_S_BCLK: 1695 reg_val |= RT1011_FS_SYS_PRE_BCLK; 1696 break; 1697 case RT1011_FS_SYS_PRE_S_PLL1: 1698 reg_val |= RT1011_FS_SYS_PRE_PLL1; 1699 break; 1700 case RT1011_FS_SYS_PRE_S_RCCLK: 1701 reg_val |= RT1011_FS_SYS_PRE_RCCLK; 1702 break; 1703 default: 1704 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 1705 return -EINVAL; 1706 } 1707 snd_soc_component_update_bits(component, RT1011_CLK_2, 1708 RT1011_FS_SYS_PRE_MASK, reg_val); 1709 rt1011->sysclk = freq; 1710 rt1011->sysclk_src = clk_id; 1711 1712 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 1713 freq, clk_id); 1714 1715 return 0; 1716 } 1717 1718 static int rt1011_set_component_pll(struct snd_soc_component *component, 1719 int pll_id, int source, unsigned int freq_in, 1720 unsigned int freq_out) 1721 { 1722 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1723 struct rl6231_pll_code pll_code; 1724 int ret; 1725 1726 if (source == rt1011->pll_src && freq_in == rt1011->pll_in && 1727 freq_out == rt1011->pll_out) 1728 return 0; 1729 1730 if (!freq_in || !freq_out) { 1731 dev_dbg(component->dev, "PLL disabled\n"); 1732 1733 rt1011->pll_in = 0; 1734 rt1011->pll_out = 0; 1735 snd_soc_component_update_bits(component, RT1011_CLK_2, 1736 RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK); 1737 return 0; 1738 } 1739 1740 switch (source) { 1741 case RT1011_PLL2_S_MCLK: 1742 snd_soc_component_update_bits(component, RT1011_CLK_2, 1743 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK); 1744 snd_soc_component_update_bits(component, RT1011_CLK_2, 1745 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); 1746 snd_soc_component_update_bits(component, RT1011_CLK_DET, 1747 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); 1748 break; 1749 case RT1011_PLL1_S_BCLK: 1750 snd_soc_component_update_bits(component, RT1011_CLK_2, 1751 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK); 1752 break; 1753 case RT1011_PLL2_S_RCCLK: 1754 snd_soc_component_update_bits(component, RT1011_CLK_2, 1755 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK); 1756 snd_soc_component_update_bits(component, RT1011_CLK_2, 1757 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); 1758 break; 1759 default: 1760 dev_err(component->dev, "Unknown PLL Source %d\n", source); 1761 return -EINVAL; 1762 } 1763 1764 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 1765 if (ret < 0) { 1766 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 1767 return ret; 1768 } 1769 1770 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 1771 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 1772 pll_code.n_code, pll_code.k_code); 1773 1774 snd_soc_component_write(component, RT1011_PLL_1, 1775 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT | 1776 pll_code.m_bp << RT1011_PLL1_BPM_SFT | pll_code.n_code); 1777 snd_soc_component_write(component, RT1011_PLL_2, 1778 pll_code.k_code); 1779 1780 rt1011->pll_in = freq_in; 1781 rt1011->pll_out = freq_out; 1782 rt1011->pll_src = source; 1783 1784 return 0; 1785 } 1786 1787 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai, 1788 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1789 { 1790 struct snd_soc_component *component = dai->component; 1791 unsigned int val = 0, tdm_en = 0; 1792 1793 if (rx_mask || tx_mask) 1794 tdm_en = RT1011_TDM_I2S_DOCK_EN_1; 1795 1796 switch (slots) { 1797 case 4: 1798 val |= RT1011_I2S_TX_4CH; 1799 val |= RT1011_I2S_RX_4CH; 1800 break; 1801 case 6: 1802 val |= RT1011_I2S_TX_6CH; 1803 val |= RT1011_I2S_RX_6CH; 1804 break; 1805 case 8: 1806 val |= RT1011_I2S_TX_8CH; 1807 val |= RT1011_I2S_RX_8CH; 1808 break; 1809 case 2: 1810 break; 1811 default: 1812 return -EINVAL; 1813 } 1814 1815 switch (slot_width) { 1816 case 20: 1817 val |= RT1011_I2S_CH_TX_LEN_20B; 1818 val |= RT1011_I2S_CH_RX_LEN_20B; 1819 break; 1820 case 24: 1821 val |= RT1011_I2S_CH_TX_LEN_24B; 1822 val |= RT1011_I2S_CH_RX_LEN_24B; 1823 break; 1824 case 32: 1825 val |= RT1011_I2S_CH_TX_LEN_32B; 1826 val |= RT1011_I2S_CH_RX_LEN_32B; 1827 break; 1828 case 16: 1829 break; 1830 default: 1831 return -EINVAL; 1832 } 1833 1834 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, 1835 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | 1836 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); 1837 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, 1838 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | 1839 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); 1840 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2, 1841 RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en); 1842 snd_soc_component_update_bits(component, RT1011_TDM2_SET_2, 1843 RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en); 1844 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, 1845 RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG, 1846 RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT); 1847 1848 return 0; 1849 } 1850 1851 static int rt1011_probe(struct snd_soc_component *component) 1852 { 1853 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1854 int i; 1855 1856 rt1011->component = component; 1857 1858 schedule_work(&rt1011->cali_work); 1859 1860 rt1011->bq_drc_params = devm_kcalloc(component->dev, 1861 RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *), 1862 GFP_KERNEL); 1863 if (!rt1011->bq_drc_params) 1864 return -ENOMEM; 1865 1866 for (i = 0; i < RT1011_ADVMODE_NUM; i++) { 1867 rt1011->bq_drc_params[i] = devm_kcalloc(component->dev, 1868 RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params), 1869 GFP_KERNEL); 1870 if (!rt1011->bq_drc_params[i]) 1871 return -ENOMEM; 1872 } 1873 1874 return 0; 1875 } 1876 1877 static void rt1011_remove(struct snd_soc_component *component) 1878 { 1879 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1880 1881 cancel_work_sync(&rt1011->cali_work); 1882 rt1011_reset(rt1011->regmap); 1883 } 1884 1885 #ifdef CONFIG_PM 1886 static int rt1011_suspend(struct snd_soc_component *component) 1887 { 1888 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1889 1890 regcache_cache_only(rt1011->regmap, true); 1891 regcache_mark_dirty(rt1011->regmap); 1892 1893 return 0; 1894 } 1895 1896 static int rt1011_resume(struct snd_soc_component *component) 1897 { 1898 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); 1899 1900 regcache_cache_only(rt1011->regmap, false); 1901 regcache_sync(rt1011->regmap); 1902 1903 return 0; 1904 } 1905 #else 1906 #define rt1011_suspend NULL 1907 #define rt1011_resume NULL 1908 #endif 1909 1910 static int rt1011_set_bias_level(struct snd_soc_component *component, 1911 enum snd_soc_bias_level level) 1912 { 1913 switch (level) { 1914 case SND_SOC_BIAS_OFF: 1915 snd_soc_component_write(component, 1916 RT1011_SYSTEM_RESET_1, 0x0000); 1917 snd_soc_component_write(component, 1918 RT1011_SYSTEM_RESET_2, 0x0000); 1919 snd_soc_component_write(component, 1920 RT1011_SYSTEM_RESET_3, 0x0001); 1921 snd_soc_component_write(component, 1922 RT1011_SYSTEM_RESET_1, 0x003f); 1923 snd_soc_component_write(component, 1924 RT1011_SYSTEM_RESET_2, 0x7fd7); 1925 snd_soc_component_write(component, 1926 RT1011_SYSTEM_RESET_3, 0x770f); 1927 break; 1928 default: 1929 break; 1930 } 1931 1932 return 0; 1933 } 1934 1935 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1936 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 1937 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 1938 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1939 1940 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = { 1941 .hw_params = rt1011_hw_params, 1942 .set_fmt = rt1011_set_dai_fmt, 1943 .set_tdm_slot = rt1011_set_tdm_slot, 1944 }; 1945 1946 static struct snd_soc_dai_driver rt1011_dai[] = { 1947 { 1948 .name = "rt1011-aif", 1949 .playback = { 1950 .stream_name = "AIF1 Playback", 1951 .channels_min = 1, 1952 .channels_max = 2, 1953 .rates = RT1011_STEREO_RATES, 1954 .formats = RT1011_FORMATS, 1955 }, 1956 .ops = &rt1011_aif_dai_ops, 1957 }, 1958 }; 1959 1960 static const struct snd_soc_component_driver soc_component_dev_rt1011 = { 1961 .probe = rt1011_probe, 1962 .remove = rt1011_remove, 1963 .suspend = rt1011_suspend, 1964 .resume = rt1011_resume, 1965 .set_bias_level = rt1011_set_bias_level, 1966 .controls = rt1011_snd_controls, 1967 .num_controls = ARRAY_SIZE(rt1011_snd_controls), 1968 .dapm_widgets = rt1011_dapm_widgets, 1969 .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets), 1970 .dapm_routes = rt1011_dapm_routes, 1971 .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes), 1972 .set_sysclk = rt1011_set_component_sysclk, 1973 .set_pll = rt1011_set_component_pll, 1974 .use_pmdown_time = 1, 1975 .endianness = 1, 1976 .non_legacy_dai_naming = 1, 1977 }; 1978 1979 static const struct regmap_config rt1011_regmap = { 1980 .reg_bits = 16, 1981 .val_bits = 16, 1982 .max_register = RT1011_MAX_REG + 1, 1983 .volatile_reg = rt1011_volatile_register, 1984 .readable_reg = rt1011_readable_register, 1985 .cache_type = REGCACHE_RBTREE, 1986 .reg_defaults = rt1011_reg, 1987 .num_reg_defaults = ARRAY_SIZE(rt1011_reg), 1988 .use_single_read = true, 1989 .use_single_write = true, 1990 }; 1991 1992 #if defined(CONFIG_OF) 1993 static const struct of_device_id rt1011_of_match[] = { 1994 { .compatible = "realtek,rt1011", }, 1995 {}, 1996 }; 1997 MODULE_DEVICE_TABLE(of, rt1011_of_match); 1998 #endif 1999 2000 #ifdef CONFIG_ACPI 2001 static struct acpi_device_id rt1011_acpi_match[] = { 2002 {"10EC1011", 0,}, 2003 {}, 2004 }; 2005 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match); 2006 #endif 2007 2008 static const struct i2c_device_id rt1011_i2c_id[] = { 2009 { "rt1011", 0 }, 2010 { } 2011 }; 2012 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id); 2013 2014 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag) 2015 { 2016 unsigned int value, count = 0, r0[3]; 2017 unsigned int chk_cnt = 50; /* DONT change this */ 2018 unsigned int dc_offset; 2019 unsigned int r0_integer, r0_factor, format; 2020 struct device *dev = regmap_get_device(rt1011->regmap); 2021 struct snd_soc_dapm_context *dapm = 2022 snd_soc_component_get_dapm(rt1011->component); 2023 int ret = 0; 2024 2025 snd_soc_dapm_mutex_lock(dapm); 2026 regcache_cache_bypass(rt1011->regmap, true); 2027 2028 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); 2029 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f); 2030 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f); 2031 2032 /* RC clock */ 2033 regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400); 2034 regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800); 2035 regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020); 2036 regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800); 2037 2038 /* ADC/DAC setting */ 2039 regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20); 2040 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232); 2041 regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925); 2042 regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000); 2043 2044 /* DC detection */ 2045 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c); 2046 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc); 2047 2048 /* Power */ 2049 regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0); 2050 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003); 2051 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860); 2052 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032); 2053 2054 /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */ 2055 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007); 2056 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7); 2057 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44); 2058 regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054); 2059 regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c); 2060 2061 /* DC offset from EFUSE */ 2062 regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00); 2063 regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080); 2064 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2); 2065 regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad); 2066 2067 /* mixer */ 2068 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d); 2069 2070 /* EFUSE read */ 2071 regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a); 2072 msleep(30); 2073 2074 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value); 2075 dc_offset = value << 16; 2076 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value); 2077 dc_offset |= (value & 0xffff); 2078 dev_info(dev, "ADC offset=0x%x\n", dc_offset); 2079 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value); 2080 dc_offset = value << 16; 2081 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value); 2082 dc_offset |= (value & 0xffff); 2083 dev_info(dev, "Gain0 offset=0x%x\n", dc_offset); 2084 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value); 2085 dc_offset = value << 16; 2086 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value); 2087 dc_offset |= (value & 0xffff); 2088 dev_info(dev, "Gain1 offset=0x%x\n", dc_offset); 2089 2090 2091 if (cali_flag) { 2092 /* Class D on */ 2093 regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e); 2094 regmap_write(rt1011->regmap, 2095 RT1011_CLASSD_INTERNAL_SET_1, 0x1701); 2096 2097 /* STP enable */ 2098 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000); 2099 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000); 2100 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040); 2101 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000); 2102 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2); 2103 2104 r0[0] = r0[1] = r0[2] = count = 0; 2105 while (count < chk_cnt) { 2106 msleep(100); 2107 regmap_read(rt1011->regmap, 2108 RT1011_INIT_RECIPROCAL_SYN_24_16, &value); 2109 r0[count%3] = value << 16; 2110 regmap_read(rt1011->regmap, 2111 RT1011_INIT_RECIPROCAL_SYN_15_0, &value); 2112 r0[count%3] |= value; 2113 2114 if (r0[count%3] == 0) 2115 continue; 2116 2117 count++; 2118 2119 if (r0[0] == r0[1] && r0[1] == r0[2]) 2120 break; 2121 } 2122 if (count > chk_cnt) { 2123 dev_err(dev, "Calibrate R0 Failure\n"); 2124 ret = -EAGAIN; 2125 } else { 2126 format = 2147483648U; /* 2^24 * 128 */ 2127 r0_integer = format / r0[0] / 128; 2128 r0_factor = ((format / r0[0] * 100) / 128) 2129 - (r0_integer * 100); 2130 rt1011->r0_reg = r0[0]; 2131 dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n", 2132 r0_integer, r0_factor, r0[0]); 2133 } 2134 } 2135 2136 /* depop */ 2137 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000); 2138 msleep(400); 2139 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840); 2140 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702); 2141 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd); 2142 regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701); 2143 regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004); 2144 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40); 2145 regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000); 2146 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000); 2147 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002); 2148 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2); 2149 2150 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); 2151 2152 if (cali_flag) { 2153 if (count <= chk_cnt) { 2154 regmap_write(rt1011->regmap, 2155 RT1011_INIT_RECIPROCAL_REG_24_16, 2156 ((r0[0]>>16) & 0x1ff)); 2157 regmap_write(rt1011->regmap, 2158 RT1011_INIT_RECIPROCAL_REG_15_0, 2159 (r0[0] & 0xffff)); 2160 regmap_write(rt1011->regmap, 2161 RT1011_SPK_TEMP_PROTECT_4, 0x4080); 2162 } 2163 } 2164 2165 regcache_cache_bypass(rt1011->regmap, false); 2166 regcache_mark_dirty(rt1011->regmap); 2167 regcache_sync(rt1011->regmap); 2168 snd_soc_dapm_mutex_unlock(dapm); 2169 2170 return ret; 2171 } 2172 2173 static void rt1011_calibration_work(struct work_struct *work) 2174 { 2175 struct rt1011_priv *rt1011 = 2176 container_of(work, struct rt1011_priv, cali_work); 2177 struct snd_soc_component *component = rt1011->component; 2178 2179 rt1011_calibrate(rt1011, 1); 2180 2181 /* initial */ 2182 rt1011_reg_init(component); 2183 } 2184 2185 static int rt1011_i2c_probe(struct i2c_client *i2c, 2186 const struct i2c_device_id *id) 2187 { 2188 struct rt1011_priv *rt1011; 2189 int ret; 2190 unsigned int val; 2191 2192 rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv), 2193 GFP_KERNEL); 2194 if (rt1011 == NULL) 2195 return -ENOMEM; 2196 2197 i2c_set_clientdata(i2c, rt1011); 2198 2199 rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap); 2200 if (IS_ERR(rt1011->regmap)) { 2201 ret = PTR_ERR(rt1011->regmap); 2202 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2203 ret); 2204 return ret; 2205 } 2206 2207 regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val); 2208 if (val != RT1011_DEVICE_ID_NUM) { 2209 dev_err(&i2c->dev, 2210 "Device with ID register %x is not rt1011\n", val); 2211 return -ENODEV; 2212 } 2213 2214 INIT_WORK(&rt1011->cali_work, rt1011_calibration_work); 2215 2216 return devm_snd_soc_register_component(&i2c->dev, 2217 &soc_component_dev_rt1011, 2218 rt1011_dai, ARRAY_SIZE(rt1011_dai)); 2219 2220 } 2221 2222 static void rt1011_i2c_shutdown(struct i2c_client *client) 2223 { 2224 struct rt1011_priv *rt1011 = i2c_get_clientdata(client); 2225 2226 rt1011_reset(rt1011->regmap); 2227 } 2228 2229 2230 static struct i2c_driver rt1011_i2c_driver = { 2231 .driver = { 2232 .name = "rt1011", 2233 .of_match_table = of_match_ptr(rt1011_of_match), 2234 .acpi_match_table = ACPI_PTR(rt1011_acpi_match) 2235 }, 2236 .probe = rt1011_i2c_probe, 2237 .shutdown = rt1011_i2c_shutdown, 2238 .id_table = rt1011_i2c_id, 2239 }; 2240 module_i2c_driver(rt1011_i2c_driver); 2241 2242 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver"); 2243 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 2244 MODULE_LICENSE("GPL"); 2245