1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rl6231.c - RL6231 class device shared support 4 * 5 * Copyright 2014 Realtek Semiconductor Corp. 6 * 7 * Author: Oder Chiou <oder_chiou@realtek.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/regmap.h> 12 13 #include <linux/gcd.h> 14 #include "rl6231.h" 15 16 /** 17 * rl6231_get_pre_div - Return the value of pre divider. 18 * 19 * @map: map for setting. 20 * @reg: register. 21 * @sft: shift. 22 * 23 * Return the value of pre divider from given register value. 24 * Return negative error code for unexpected register value. 25 */ 26 int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft) 27 { 28 int pd, val; 29 30 regmap_read(map, reg, &val); 31 32 val = (val >> sft) & 0x7; 33 34 switch (val) { 35 case 0: 36 case 1: 37 case 2: 38 case 3: 39 pd = val + 1; 40 break; 41 case 4: 42 pd = 6; 43 break; 44 case 5: 45 pd = 8; 46 break; 47 case 6: 48 pd = 12; 49 break; 50 case 7: 51 pd = 16; 52 break; 53 default: 54 pd = -EINVAL; 55 break; 56 } 57 58 return pd; 59 } 60 EXPORT_SYMBOL_GPL(rl6231_get_pre_div); 61 62 /** 63 * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic. 64 * 65 * @rate: base clock rate. 66 * 67 * Choose divider parameter that gives the highest possible DMIC frequency in 68 * 1MHz - 3MHz range. 69 */ 70 int rl6231_calc_dmic_clk(int rate) 71 { 72 static const int div[] = {2, 3, 4, 6, 8, 12}; 73 int i; 74 75 if (rate < 1000000 * div[0]) { 76 pr_warn("Base clock rate %d is too low\n", rate); 77 return -EINVAL; 78 } 79 80 for (i = 0; i < ARRAY_SIZE(div); i++) { 81 if ((div[i] % 3) == 0) 82 continue; 83 /* find divider that gives DMIC frequency below 3.072MHz */ 84 if (3072000 * div[i] >= rate) 85 return i; 86 } 87 88 pr_warn("Base clock rate %d is too high\n", rate); 89 return -EINVAL; 90 } 91 EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk); 92 93 struct pll_calc_map { 94 unsigned int pll_in; 95 unsigned int pll_out; 96 int k; 97 int n; 98 int m; 99 bool m_bp; 100 }; 101 102 static const struct pll_calc_map pll_preset_table[] = { 103 {19200000, 4096000, 23, 14, 1, false}, 104 {19200000, 24576000, 3, 30, 3, false}, 105 }; 106 107 static unsigned int find_best_div(unsigned int in, 108 unsigned int max, unsigned int div) 109 { 110 unsigned int d; 111 112 if (in <= max) 113 return 1; 114 115 d = in / max; 116 if (in % max) 117 d++; 118 119 while (div % d != 0) 120 d++; 121 122 123 return d; 124 } 125 126 /** 127 * rl6231_pll_calc - Calcualte PLL M/N/K code. 128 * @freq_in: external clock provided to codec. 129 * @freq_out: target clock which codec works on. 130 * @pll_code: Pointer to structure with M, N, K and bypass flag. 131 * 132 * Calcualte M/N/K code to configure PLL for codec. 133 * 134 * Returns 0 for success or negative error code. 135 */ 136 int rl6231_pll_calc(const unsigned int freq_in, 137 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 138 { 139 int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX; 140 int i, k, n_t; 141 int k_t, min_k, max_k, n = 0, m = 0, m_t = 0; 142 unsigned int red, pll_out, in_t, out_t, div, div_t; 143 unsigned int red_t = abs(freq_out - freq_in); 144 unsigned int f_in, f_out, f_max; 145 bool bypass = false; 146 147 if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in) 148 return -EINVAL; 149 150 for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) { 151 if (freq_in == pll_preset_table[i].pll_in && 152 freq_out == pll_preset_table[i].pll_out) { 153 k = pll_preset_table[i].k; 154 m = pll_preset_table[i].m; 155 n = pll_preset_table[i].n; 156 bypass = pll_preset_table[i].m_bp; 157 pr_debug("Use preset PLL parameter table\n"); 158 goto code_find; 159 } 160 } 161 162 min_k = 80000000 / freq_out - 2; 163 max_k = 150000000 / freq_out - 2; 164 if (max_k > RL6231_PLL_K_MAX) 165 max_k = RL6231_PLL_K_MAX; 166 if (min_k > RL6231_PLL_K_MAX) 167 min_k = max_k = RL6231_PLL_K_MAX; 168 div_t = gcd(freq_in, freq_out); 169 f_max = 0xffffffff / RL6231_PLL_N_MAX; 170 div = find_best_div(freq_in, f_max, div_t); 171 f_in = freq_in / div; 172 f_out = freq_out / div; 173 k = min_k; 174 for (k_t = min_k; k_t <= max_k; k_t++) { 175 for (n_t = 0; n_t <= max_n; n_t++) { 176 in_t = f_in * (n_t + 2); 177 pll_out = f_out * (k_t + 2); 178 if (in_t == pll_out) { 179 bypass = true; 180 n = n_t; 181 k = k_t; 182 goto code_find; 183 } 184 out_t = in_t / (k_t + 2); 185 red = abs(f_out - out_t); 186 if (red < red_t) { 187 bypass = true; 188 n = n_t; 189 m = 0; 190 k = k_t; 191 if (red == 0) 192 goto code_find; 193 red_t = red; 194 } 195 for (m_t = 0; m_t <= max_m; m_t++) { 196 out_t = in_t / ((m_t + 2) * (k_t + 2)); 197 red = abs(f_out - out_t); 198 if (red < red_t) { 199 bypass = false; 200 n = n_t; 201 m = m_t; 202 k = k_t; 203 if (red == 0) 204 goto code_find; 205 red_t = red; 206 } 207 } 208 } 209 } 210 pr_debug("Only get approximation about PLL\n"); 211 212 code_find: 213 214 pll_code->m_bp = bypass; 215 pll_code->m_code = m; 216 pll_code->n_code = n; 217 pll_code->k_code = k; 218 return 0; 219 } 220 EXPORT_SYMBOL_GPL(rl6231_pll_calc); 221 222 int rl6231_get_clk_info(int sclk, int rate) 223 { 224 int i; 225 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; 226 227 if (sclk <= 0 || rate <= 0) 228 return -EINVAL; 229 230 rate = rate << 8; 231 for (i = 0; i < ARRAY_SIZE(pd); i++) 232 if (sclk == rate * pd[i]) 233 return i; 234 235 return -EINVAL; 236 } 237 EXPORT_SYMBOL_GPL(rl6231_get_clk_info); 238 239 MODULE_DESCRIPTION("RL6231 class device shared support"); 240 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 241 MODULE_LICENSE("GPL v2"); 242