1 /* 2 * Driver for the PCM512x CODECs 3 * 4 * Author: Mark Brown <broonie@kernel.org> 5 * Copyright 2014 Linaro Ltd 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/clk.h> 21 #include <linux/kernel.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/gcd.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/tlv.h> 30 31 #include "pcm512x.h" 32 33 #define PCM512x_NUM_SUPPLIES 3 34 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 35 "AVDD", 36 "DVDD", 37 "CPVDD", 38 }; 39 40 struct pcm512x_priv { 41 struct regmap *regmap; 42 struct clk *sclk; 43 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 44 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 45 int fmt; 46 int pll_in; 47 int pll_out; 48 int pll_r; 49 int pll_j; 50 int pll_d; 51 int pll_p; 52 unsigned long real_pll; 53 unsigned long overclock_pll; 54 unsigned long overclock_dac; 55 unsigned long overclock_dsp; 56 int mute; 57 struct mutex mutex; 58 unsigned int bclk_ratio; 59 }; 60 61 /* 62 * We can't use the same notifier block for more than one supply and 63 * there's no way I can see to get from a callback to the caller 64 * except container_of(). 65 */ 66 #define PCM512x_REGULATOR_EVENT(n) \ 67 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 68 unsigned long event, void *data) \ 69 { \ 70 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 71 supply_nb[n]); \ 72 if (event & REGULATOR_EVENT_DISABLE) { \ 73 regcache_mark_dirty(pcm512x->regmap); \ 74 regcache_cache_only(pcm512x->regmap, true); \ 75 } \ 76 return 0; \ 77 } 78 79 PCM512x_REGULATOR_EVENT(0) 80 PCM512x_REGULATOR_EVENT(1) 81 PCM512x_REGULATOR_EVENT(2) 82 83 static const struct reg_default pcm512x_reg_defaults[] = { 84 { PCM512x_RESET, 0x00 }, 85 { PCM512x_POWER, 0x00 }, 86 { PCM512x_MUTE, 0x00 }, 87 { PCM512x_DSP, 0x00 }, 88 { PCM512x_PLL_REF, 0x00 }, 89 { PCM512x_DAC_REF, 0x00 }, 90 { PCM512x_DAC_ROUTING, 0x11 }, 91 { PCM512x_DSP_PROGRAM, 0x01 }, 92 { PCM512x_CLKDET, 0x00 }, 93 { PCM512x_AUTO_MUTE, 0x00 }, 94 { PCM512x_ERROR_DETECT, 0x00 }, 95 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 96 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 97 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 98 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 99 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 100 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 101 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 102 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 103 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 104 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 105 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 106 { PCM512x_VCOM_CTRL_1, 0x00 }, 107 { PCM512x_VCOM_CTRL_2, 0x01 }, 108 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 109 { PCM512x_MASTER_MODE, 0x7c }, 110 { PCM512x_GPIO_DACIN, 0x00 }, 111 { PCM512x_GPIO_PLLIN, 0x00 }, 112 { PCM512x_SYNCHRONIZE, 0x10 }, 113 { PCM512x_PLL_COEFF_0, 0x00 }, 114 { PCM512x_PLL_COEFF_1, 0x00 }, 115 { PCM512x_PLL_COEFF_2, 0x00 }, 116 { PCM512x_PLL_COEFF_3, 0x00 }, 117 { PCM512x_PLL_COEFF_4, 0x00 }, 118 { PCM512x_DSP_CLKDIV, 0x00 }, 119 { PCM512x_DAC_CLKDIV, 0x00 }, 120 { PCM512x_NCP_CLKDIV, 0x00 }, 121 { PCM512x_OSR_CLKDIV, 0x00 }, 122 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 123 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 124 { PCM512x_FS_SPEED_MODE, 0x00 }, 125 { PCM512x_IDAC_1, 0x01 }, 126 { PCM512x_IDAC_2, 0x00 }, 127 }; 128 129 static bool pcm512x_readable(struct device *dev, unsigned int reg) 130 { 131 switch (reg) { 132 case PCM512x_RESET: 133 case PCM512x_POWER: 134 case PCM512x_MUTE: 135 case PCM512x_PLL_EN: 136 case PCM512x_SPI_MISO_FUNCTION: 137 case PCM512x_DSP: 138 case PCM512x_GPIO_EN: 139 case PCM512x_BCLK_LRCLK_CFG: 140 case PCM512x_DSP_GPIO_INPUT: 141 case PCM512x_MASTER_MODE: 142 case PCM512x_PLL_REF: 143 case PCM512x_DAC_REF: 144 case PCM512x_GPIO_DACIN: 145 case PCM512x_GPIO_PLLIN: 146 case PCM512x_SYNCHRONIZE: 147 case PCM512x_PLL_COEFF_0: 148 case PCM512x_PLL_COEFF_1: 149 case PCM512x_PLL_COEFF_2: 150 case PCM512x_PLL_COEFF_3: 151 case PCM512x_PLL_COEFF_4: 152 case PCM512x_DSP_CLKDIV: 153 case PCM512x_DAC_CLKDIV: 154 case PCM512x_NCP_CLKDIV: 155 case PCM512x_OSR_CLKDIV: 156 case PCM512x_MASTER_CLKDIV_1: 157 case PCM512x_MASTER_CLKDIV_2: 158 case PCM512x_FS_SPEED_MODE: 159 case PCM512x_IDAC_1: 160 case PCM512x_IDAC_2: 161 case PCM512x_ERROR_DETECT: 162 case PCM512x_I2S_1: 163 case PCM512x_I2S_2: 164 case PCM512x_DAC_ROUTING: 165 case PCM512x_DSP_PROGRAM: 166 case PCM512x_CLKDET: 167 case PCM512x_AUTO_MUTE: 168 case PCM512x_DIGITAL_VOLUME_1: 169 case PCM512x_DIGITAL_VOLUME_2: 170 case PCM512x_DIGITAL_VOLUME_3: 171 case PCM512x_DIGITAL_MUTE_1: 172 case PCM512x_DIGITAL_MUTE_2: 173 case PCM512x_DIGITAL_MUTE_3: 174 case PCM512x_GPIO_OUTPUT_1: 175 case PCM512x_GPIO_OUTPUT_2: 176 case PCM512x_GPIO_OUTPUT_3: 177 case PCM512x_GPIO_OUTPUT_4: 178 case PCM512x_GPIO_OUTPUT_5: 179 case PCM512x_GPIO_OUTPUT_6: 180 case PCM512x_GPIO_CONTROL_1: 181 case PCM512x_GPIO_CONTROL_2: 182 case PCM512x_OVERFLOW: 183 case PCM512x_RATE_DET_1: 184 case PCM512x_RATE_DET_2: 185 case PCM512x_RATE_DET_3: 186 case PCM512x_RATE_DET_4: 187 case PCM512x_CLOCK_STATUS: 188 case PCM512x_ANALOG_MUTE_DET: 189 case PCM512x_GPIN: 190 case PCM512x_DIGITAL_MUTE_DET: 191 case PCM512x_OUTPUT_AMPLITUDE: 192 case PCM512x_ANALOG_GAIN_CTRL: 193 case PCM512x_UNDERVOLTAGE_PROT: 194 case PCM512x_ANALOG_MUTE_CTRL: 195 case PCM512x_ANALOG_GAIN_BOOST: 196 case PCM512x_VCOM_CTRL_1: 197 case PCM512x_VCOM_CTRL_2: 198 case PCM512x_CRAM_CTRL: 199 case PCM512x_FLEX_A: 200 case PCM512x_FLEX_B: 201 return true; 202 default: 203 /* There are 256 raw register addresses */ 204 return reg < 0xff; 205 } 206 } 207 208 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 209 { 210 switch (reg) { 211 case PCM512x_PLL_EN: 212 case PCM512x_OVERFLOW: 213 case PCM512x_RATE_DET_1: 214 case PCM512x_RATE_DET_2: 215 case PCM512x_RATE_DET_3: 216 case PCM512x_RATE_DET_4: 217 case PCM512x_CLOCK_STATUS: 218 case PCM512x_ANALOG_MUTE_DET: 219 case PCM512x_GPIN: 220 case PCM512x_DIGITAL_MUTE_DET: 221 case PCM512x_CRAM_CTRL: 222 return true; 223 default: 224 /* There are 256 raw register addresses */ 225 return reg < 0xff; 226 } 227 } 228 229 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 230 struct snd_ctl_elem_value *ucontrol) 231 { 232 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 233 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 234 235 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 236 return 0; 237 } 238 239 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 240 struct snd_ctl_elem_value *ucontrol) 241 { 242 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 243 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 244 245 switch (snd_soc_component_get_bias_level(component)) { 246 case SND_SOC_BIAS_OFF: 247 case SND_SOC_BIAS_STANDBY: 248 break; 249 default: 250 return -EBUSY; 251 } 252 253 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 254 return 0; 255 } 256 257 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 258 struct snd_ctl_elem_value *ucontrol) 259 { 260 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 261 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 262 263 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 264 return 0; 265 } 266 267 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 268 struct snd_ctl_elem_value *ucontrol) 269 { 270 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 271 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 272 273 switch (snd_soc_component_get_bias_level(component)) { 274 case SND_SOC_BIAS_OFF: 275 case SND_SOC_BIAS_STANDBY: 276 break; 277 default: 278 return -EBUSY; 279 } 280 281 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 282 return 0; 283 } 284 285 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 286 struct snd_ctl_elem_value *ucontrol) 287 { 288 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 289 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 290 291 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 292 return 0; 293 } 294 295 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 296 struct snd_ctl_elem_value *ucontrol) 297 { 298 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 299 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 300 301 switch (snd_soc_component_get_bias_level(component)) { 302 case SND_SOC_BIAS_OFF: 303 case SND_SOC_BIAS_STANDBY: 304 break; 305 default: 306 return -EBUSY; 307 } 308 309 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 310 return 0; 311 } 312 313 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 314 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 315 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 316 317 static const char * const pcm512x_dsp_program_texts[] = { 318 "FIR interpolation with de-emphasis", 319 "Low latency IIR with de-emphasis", 320 "High attenuation with de-emphasis", 321 "Fixed process flow", 322 "Ringing-less low latency FIR", 323 }; 324 325 static const unsigned int pcm512x_dsp_program_values[] = { 326 1, 327 2, 328 3, 329 5, 330 7, 331 }; 332 333 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 334 PCM512x_DSP_PROGRAM, 0, 0x1f, 335 pcm512x_dsp_program_texts, 336 pcm512x_dsp_program_values); 337 338 static const char * const pcm512x_clk_missing_text[] = { 339 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 340 }; 341 342 static const struct soc_enum pcm512x_clk_missing = 343 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 344 345 static const char * const pcm512x_autom_text[] = { 346 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 347 }; 348 349 static const struct soc_enum pcm512x_autom_l = 350 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 351 pcm512x_autom_text); 352 353 static const struct soc_enum pcm512x_autom_r = 354 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 355 pcm512x_autom_text); 356 357 static const char * const pcm512x_ramp_rate_text[] = { 358 "1 sample/update", "2 samples/update", "4 samples/update", 359 "Immediate" 360 }; 361 362 static const struct soc_enum pcm512x_vndf = 363 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 364 pcm512x_ramp_rate_text); 365 366 static const struct soc_enum pcm512x_vnuf = 367 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 368 pcm512x_ramp_rate_text); 369 370 static const struct soc_enum pcm512x_vedf = 371 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 372 pcm512x_ramp_rate_text); 373 374 static const char * const pcm512x_ramp_step_text[] = { 375 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 376 }; 377 378 static const struct soc_enum pcm512x_vnds = 379 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 380 pcm512x_ramp_step_text); 381 382 static const struct soc_enum pcm512x_vnus = 383 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 384 pcm512x_ramp_step_text); 385 386 static const struct soc_enum pcm512x_veds = 387 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 388 pcm512x_ramp_step_text); 389 390 static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) 391 { 392 return regmap_update_bits( 393 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, 394 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) 395 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); 396 } 397 398 static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, 399 struct snd_ctl_elem_value *ucontrol) 400 { 401 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 402 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 403 404 mutex_lock(&pcm512x->mutex); 405 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); 406 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); 407 mutex_unlock(&pcm512x->mutex); 408 409 return 0; 410 } 411 412 static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, 413 struct snd_ctl_elem_value *ucontrol) 414 { 415 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 416 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 417 int ret, changed = 0; 418 419 mutex_lock(&pcm512x->mutex); 420 421 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { 422 pcm512x->mute ^= 0x4; 423 changed = 1; 424 } 425 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { 426 pcm512x->mute ^= 0x2; 427 changed = 1; 428 } 429 430 if (changed) { 431 ret = pcm512x_update_mute(pcm512x); 432 if (ret != 0) { 433 dev_err(component->dev, 434 "Failed to update digital mute: %d\n", ret); 435 mutex_unlock(&pcm512x->mutex); 436 return ret; 437 } 438 } 439 440 mutex_unlock(&pcm512x->mutex); 441 442 return changed; 443 } 444 445 static const struct snd_kcontrol_new pcm512x_controls[] = { 446 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 447 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 448 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 449 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 450 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 451 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 452 { 453 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 454 .name = "Digital Playback Switch", 455 .index = 0, 456 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 457 .info = snd_ctl_boolean_stereo_info, 458 .get = pcm512x_digital_playback_switch_get, 459 .put = pcm512x_digital_playback_switch_put 460 }, 461 462 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 463 SOC_ENUM("DSP Program", pcm512x_dsp_program), 464 465 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 466 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 467 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 468 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 469 PCM512x_ACTL_SHIFT, 1, 0), 470 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 471 PCM512x_AMRE_SHIFT, 1, 0), 472 473 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 474 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 475 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 476 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 477 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 478 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 479 480 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 481 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 482 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 483 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 484 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 485 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 486 }; 487 488 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 489 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 490 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 491 492 SND_SOC_DAPM_OUTPUT("OUTL"), 493 SND_SOC_DAPM_OUTPUT("OUTR"), 494 }; 495 496 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 497 { "DACL", NULL, "Playback" }, 498 { "DACR", NULL, "Playback" }, 499 500 { "OUTL", NULL, "DACL" }, 501 { "OUTR", NULL, "DACR" }, 502 }; 503 504 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 505 { 506 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 507 } 508 509 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 510 { 511 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 512 } 513 514 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 515 unsigned long rate) 516 { 517 return rate + rate * pcm512x->overclock_dac / 100; 518 } 519 520 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 521 { 522 if (!pcm512x->pll_out) 523 return 25000000; 524 return pcm512x_pll_max(pcm512x); 525 } 526 527 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 528 unsigned long dac_rate) 529 { 530 /* 531 * If the DAC is not actually overclocked, use the good old 532 * NCP target rate... 533 */ 534 if (dac_rate <= 6144000) 535 return 1536000; 536 /* 537 * ...but if the DAC is in fact overclocked, bump the NCP target 538 * rate to get the recommended dividers even when overclocking. 539 */ 540 return pcm512x_dac_max(pcm512x, 1536000); 541 } 542 543 static const u32 pcm512x_dai_rates[] = { 544 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 545 88200, 96000, 176400, 192000, 384000, 546 }; 547 548 static const struct snd_pcm_hw_constraint_list constraints_slave = { 549 .count = ARRAY_SIZE(pcm512x_dai_rates), 550 .list = pcm512x_dai_rates, 551 }; 552 553 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 554 struct snd_pcm_hw_rule *rule) 555 { 556 struct pcm512x_priv *pcm512x = rule->private; 557 struct snd_interval ranges[2]; 558 int frame_size; 559 560 frame_size = snd_soc_params_to_frame_size(params); 561 if (frame_size < 0) 562 return frame_size; 563 564 switch (frame_size) { 565 case 32: 566 /* No hole when the frame size is 32. */ 567 return 0; 568 case 48: 569 case 64: 570 /* There is only one hole in the range of supported 571 * rates, but it moves with the frame size. 572 */ 573 memset(ranges, 0, sizeof(ranges)); 574 ranges[0].min = 8000; 575 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 576 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 577 ranges[1].max = 384000; 578 break; 579 default: 580 return -EINVAL; 581 } 582 583 return snd_interval_ranges(hw_param_interval(params, rule->var), 584 ARRAY_SIZE(ranges), ranges, 0); 585 } 586 587 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 588 struct snd_soc_dai *dai) 589 { 590 struct snd_soc_component *component = dai->component; 591 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 592 struct device *dev = dai->dev; 593 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 594 struct snd_ratnum *rats_no_pll; 595 596 if (IS_ERR(pcm512x->sclk)) { 597 dev_err(dev, "Need SCLK for master mode: %ld\n", 598 PTR_ERR(pcm512x->sclk)); 599 return PTR_ERR(pcm512x->sclk); 600 } 601 602 if (pcm512x->pll_out) 603 return snd_pcm_hw_rule_add(substream->runtime, 0, 604 SNDRV_PCM_HW_PARAM_RATE, 605 pcm512x_hw_rule_rate, 606 pcm512x, 607 SNDRV_PCM_HW_PARAM_FRAME_BITS, 608 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 609 610 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 611 GFP_KERNEL); 612 if (!constraints_no_pll) 613 return -ENOMEM; 614 constraints_no_pll->nrats = 1; 615 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 616 if (!rats_no_pll) 617 return -ENOMEM; 618 constraints_no_pll->rats = rats_no_pll; 619 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 620 rats_no_pll->den_min = 1; 621 rats_no_pll->den_max = 128; 622 rats_no_pll->den_step = 1; 623 624 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 625 SNDRV_PCM_HW_PARAM_RATE, 626 constraints_no_pll); 627 } 628 629 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 630 struct snd_soc_dai *dai) 631 { 632 struct snd_soc_component *component = dai->component; 633 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 634 struct device *dev = dai->dev; 635 struct regmap *regmap = pcm512x->regmap; 636 637 if (IS_ERR(pcm512x->sclk)) { 638 dev_info(dev, "No SCLK, using BCLK: %ld\n", 639 PTR_ERR(pcm512x->sclk)); 640 641 /* Disable reporting of missing SCLK as an error */ 642 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 643 PCM512x_IDCH, PCM512x_IDCH); 644 645 /* Switch PLL input to BCLK */ 646 regmap_update_bits(regmap, PCM512x_PLL_REF, 647 PCM512x_SREF, PCM512x_SREF_BCK); 648 } 649 650 return snd_pcm_hw_constraint_list(substream->runtime, 0, 651 SNDRV_PCM_HW_PARAM_RATE, 652 &constraints_slave); 653 } 654 655 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 656 struct snd_soc_dai *dai) 657 { 658 struct snd_soc_component *component = dai->component; 659 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 660 661 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 662 case SND_SOC_DAIFMT_CBM_CFM: 663 case SND_SOC_DAIFMT_CBM_CFS: 664 return pcm512x_dai_startup_master(substream, dai); 665 666 case SND_SOC_DAIFMT_CBS_CFS: 667 return pcm512x_dai_startup_slave(substream, dai); 668 669 default: 670 return -EINVAL; 671 } 672 } 673 674 static int pcm512x_set_bias_level(struct snd_soc_component *component, 675 enum snd_soc_bias_level level) 676 { 677 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev); 678 int ret; 679 680 switch (level) { 681 case SND_SOC_BIAS_ON: 682 case SND_SOC_BIAS_PREPARE: 683 break; 684 685 case SND_SOC_BIAS_STANDBY: 686 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 687 PCM512x_RQST, 0); 688 if (ret != 0) { 689 dev_err(component->dev, "Failed to remove standby: %d\n", 690 ret); 691 return ret; 692 } 693 break; 694 695 case SND_SOC_BIAS_OFF: 696 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 697 PCM512x_RQST, PCM512x_RQST); 698 if (ret != 0) { 699 dev_err(component->dev, "Failed to request standby: %d\n", 700 ret); 701 return ret; 702 } 703 break; 704 } 705 706 return 0; 707 } 708 709 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 710 unsigned long bclk_rate) 711 { 712 struct device *dev = dai->dev; 713 struct snd_soc_component *component = dai->component; 714 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 715 unsigned long sck_rate; 716 int pow2; 717 718 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 719 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 720 721 /* select sck_rate as a multiple of bclk_rate but still with 722 * as many factors of 2 as possible, as that makes it easier 723 * to find a fast DAC rate 724 */ 725 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 726 for (; pow2; pow2 >>= 1) { 727 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 728 bclk_rate * pow2); 729 if (sck_rate >= 16000000) 730 break; 731 } 732 if (!pow2) { 733 dev_err(dev, "Impossible to generate a suitable SCK\n"); 734 return 0; 735 } 736 737 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 738 return sck_rate; 739 } 740 741 /* pll_rate = pllin_rate * R * J.D / P 742 * 1 <= R <= 16 743 * 1 <= J <= 63 744 * 0 <= D <= 9999 745 * 1 <= P <= 15 746 * 64 MHz <= pll_rate <= 100 MHz 747 * if D == 0 748 * 1 MHz <= pllin_rate / P <= 20 MHz 749 * else if D > 0 750 * 6.667 MHz <= pllin_rate / P <= 20 MHz 751 * 4 <= J <= 11 752 * R = 1 753 */ 754 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 755 unsigned long pllin_rate, 756 unsigned long pll_rate) 757 { 758 struct device *dev = dai->dev; 759 struct snd_soc_component *component = dai->component; 760 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 761 unsigned long common; 762 int R, J, D, P; 763 unsigned long K; /* 10000 * J.D */ 764 unsigned long num; 765 unsigned long den; 766 767 common = gcd(pll_rate, pllin_rate); 768 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 769 pll_rate, pllin_rate, common); 770 num = pll_rate / common; 771 den = pllin_rate / common; 772 773 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 774 if (pllin_rate / den > 20000000 && num < 8) { 775 num *= DIV_ROUND_UP(pllin_rate / den, 20000000); 776 den *= DIV_ROUND_UP(pllin_rate / den, 20000000); 777 } 778 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 779 780 P = den; 781 if (den <= 15 && num <= 16 * 63 782 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 783 /* Try the case with D = 0 */ 784 D = 0; 785 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 786 for (R = 16; R; R--) { 787 if (num % R) 788 continue; 789 J = num / R; 790 if (J == 0 || J > 63) 791 continue; 792 793 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 794 pcm512x->real_pll = pll_rate; 795 goto done; 796 } 797 /* no luck */ 798 } 799 800 R = 1; 801 802 if (num > 0xffffffffUL / 10000) 803 goto fallback; 804 805 /* Try to find an exact pll_rate using the D > 0 case */ 806 common = gcd(10000 * num, den); 807 num = 10000 * num / common; 808 den /= common; 809 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 810 811 for (P = den; P <= 15; P++) { 812 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 813 continue; 814 if (num * P % den) 815 continue; 816 K = num * P / den; 817 /* J == 12 is ok if D == 0 */ 818 if (K < 40000 || K > 120000) 819 continue; 820 821 J = K / 10000; 822 D = K % 10000; 823 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 824 pcm512x->real_pll = pll_rate; 825 goto done; 826 } 827 828 /* Fall back to an approximate pll_rate */ 829 830 fallback: 831 /* find smallest possible P */ 832 P = DIV_ROUND_UP(pllin_rate, 20000000); 833 if (!P) 834 P = 1; 835 else if (P > 15) { 836 dev_err(dev, "Need a slower clock as pll-input\n"); 837 return -EINVAL; 838 } 839 if (pllin_rate / P < 6667000) { 840 dev_err(dev, "Need a faster clock as pll-input\n"); 841 return -EINVAL; 842 } 843 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 844 if (K < 40000) 845 K = 40000; 846 /* J == 12 is ok if D == 0 */ 847 if (K > 120000) 848 K = 120000; 849 J = K / 10000; 850 D = K % 10000; 851 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 852 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 853 854 done: 855 pcm512x->pll_r = R; 856 pcm512x->pll_j = J; 857 pcm512x->pll_d = D; 858 pcm512x->pll_p = P; 859 return 0; 860 } 861 862 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 863 unsigned long osr_rate, 864 unsigned long pllin_rate) 865 { 866 struct snd_soc_component *component = dai->component; 867 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 868 unsigned long dac_rate; 869 870 if (!pcm512x->pll_out) 871 return 0; /* no PLL to bypass, force SCK as DAC input */ 872 873 if (pllin_rate % osr_rate) 874 return 0; /* futile, quit early */ 875 876 /* run DAC no faster than 6144000 Hz */ 877 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 878 dac_rate; 879 dac_rate -= osr_rate) { 880 881 if (pllin_rate / dac_rate > 128) 882 return 0; /* DAC divider would be too big */ 883 884 if (!(pllin_rate % dac_rate)) 885 return dac_rate; 886 887 dac_rate -= osr_rate; 888 } 889 890 return 0; 891 } 892 893 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 894 struct snd_pcm_hw_params *params) 895 { 896 struct device *dev = dai->dev; 897 struct snd_soc_component *component = dai->component; 898 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 899 unsigned long pllin_rate = 0; 900 unsigned long pll_rate; 901 unsigned long sck_rate; 902 unsigned long mck_rate; 903 unsigned long bclk_rate; 904 unsigned long sample_rate; 905 unsigned long osr_rate; 906 unsigned long dacsrc_rate; 907 int bclk_div; 908 int lrclk_div; 909 int dsp_div; 910 int dac_div; 911 unsigned long dac_rate; 912 int ncp_div; 913 int osr_div; 914 int ret; 915 int idac; 916 int fssp; 917 int gpio; 918 919 if (pcm512x->bclk_ratio > 0) { 920 lrclk_div = pcm512x->bclk_ratio; 921 } else { 922 lrclk_div = snd_soc_params_to_frame_size(params); 923 924 if (lrclk_div == 0) { 925 dev_err(dev, "No LRCLK?\n"); 926 return -EINVAL; 927 } 928 } 929 930 if (!pcm512x->pll_out) { 931 sck_rate = clk_get_rate(pcm512x->sclk); 932 bclk_rate = params_rate(params) * lrclk_div; 933 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 934 935 mck_rate = sck_rate; 936 } else { 937 ret = snd_soc_params_to_bclk(params); 938 if (ret < 0) { 939 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 940 return ret; 941 } 942 if (ret == 0) { 943 dev_err(dev, "No BCLK?\n"); 944 return -EINVAL; 945 } 946 bclk_rate = ret; 947 948 pllin_rate = clk_get_rate(pcm512x->sclk); 949 950 sck_rate = pcm512x_find_sck(dai, bclk_rate); 951 if (!sck_rate) 952 return -EINVAL; 953 pll_rate = 4 * sck_rate; 954 955 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 956 if (ret != 0) 957 return ret; 958 959 ret = regmap_write(pcm512x->regmap, 960 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 961 if (ret != 0) { 962 dev_err(dev, "Failed to write PLL P: %d\n", ret); 963 return ret; 964 } 965 966 ret = regmap_write(pcm512x->regmap, 967 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 968 if (ret != 0) { 969 dev_err(dev, "Failed to write PLL J: %d\n", ret); 970 return ret; 971 } 972 973 ret = regmap_write(pcm512x->regmap, 974 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 975 if (ret != 0) { 976 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 977 return ret; 978 } 979 980 ret = regmap_write(pcm512x->regmap, 981 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 982 if (ret != 0) { 983 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 984 return ret; 985 } 986 987 ret = regmap_write(pcm512x->regmap, 988 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 989 if (ret != 0) { 990 dev_err(dev, "Failed to write PLL R: %d\n", ret); 991 return ret; 992 } 993 994 mck_rate = pcm512x->real_pll; 995 996 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 997 } 998 999 if (bclk_div > 128) { 1000 dev_err(dev, "Failed to find BCLK divider\n"); 1001 return -EINVAL; 1002 } 1003 1004 /* the actual rate */ 1005 sample_rate = sck_rate / bclk_div / lrclk_div; 1006 osr_rate = 16 * sample_rate; 1007 1008 /* run DSP no faster than 50 MHz */ 1009 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 1010 1011 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 1012 if (dac_rate) { 1013 /* the desired clock rate is "compatible" with the pll input 1014 * clock, so use that clock as dac input instead of the pll 1015 * output clock since the pll will introduce jitter and thus 1016 * noise. 1017 */ 1018 dev_dbg(dev, "using pll input as dac input\n"); 1019 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1020 PCM512x_SDAC, PCM512x_SDAC_GPIO); 1021 if (ret != 0) { 1022 dev_err(component->dev, 1023 "Failed to set gpio as dacref: %d\n", ret); 1024 return ret; 1025 } 1026 1027 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1028 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 1029 PCM512x_GREF, gpio); 1030 if (ret != 0) { 1031 dev_err(component->dev, 1032 "Failed to set gpio %d as dacin: %d\n", 1033 pcm512x->pll_in, ret); 1034 return ret; 1035 } 1036 1037 dacsrc_rate = pllin_rate; 1038 } else { 1039 /* run DAC no faster than 6144000 Hz */ 1040 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 1041 / osr_rate; 1042 unsigned long sck_mul = sck_rate / osr_rate; 1043 1044 for (; dac_mul; dac_mul--) { 1045 if (!(sck_mul % dac_mul)) 1046 break; 1047 } 1048 if (!dac_mul) { 1049 dev_err(dev, "Failed to find DAC rate\n"); 1050 return -EINVAL; 1051 } 1052 1053 dac_rate = dac_mul * osr_rate; 1054 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 1055 dac_rate, sample_rate); 1056 1057 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1058 PCM512x_SDAC, PCM512x_SDAC_SCK); 1059 if (ret != 0) { 1060 dev_err(component->dev, 1061 "Failed to set sck as dacref: %d\n", ret); 1062 return ret; 1063 } 1064 1065 dacsrc_rate = sck_rate; 1066 } 1067 1068 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1069 if (osr_div > 128) { 1070 dev_err(dev, "Failed to find OSR divider\n"); 1071 return -EINVAL; 1072 } 1073 1074 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1075 if (dac_div > 128) { 1076 dev_err(dev, "Failed to find DAC divider\n"); 1077 return -EINVAL; 1078 } 1079 dac_rate = dacsrc_rate / dac_div; 1080 1081 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1082 pcm512x_ncp_target(pcm512x, dac_rate)); 1083 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1084 /* run NCP no faster than 2048000 Hz, but why? */ 1085 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1086 if (ncp_div > 128) { 1087 dev_err(dev, "Failed to find NCP divider\n"); 1088 return -EINVAL; 1089 } 1090 } 1091 1092 idac = mck_rate / (dsp_div * sample_rate); 1093 1094 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1095 if (ret != 0) { 1096 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1097 return ret; 1098 } 1099 1100 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1101 if (ret != 0) { 1102 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1103 return ret; 1104 } 1105 1106 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1107 if (ret != 0) { 1108 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1109 return ret; 1110 } 1111 1112 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1113 if (ret != 0) { 1114 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1115 return ret; 1116 } 1117 1118 ret = regmap_write(pcm512x->regmap, 1119 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1120 if (ret != 0) { 1121 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1122 return ret; 1123 } 1124 1125 ret = regmap_write(pcm512x->regmap, 1126 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1127 if (ret != 0) { 1128 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1129 return ret; 1130 } 1131 1132 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1133 if (ret != 0) { 1134 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1135 return ret; 1136 } 1137 1138 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1139 if (ret != 0) { 1140 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1141 return ret; 1142 } 1143 1144 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1145 fssp = PCM512x_FSSP_48KHZ; 1146 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1147 fssp = PCM512x_FSSP_96KHZ; 1148 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1149 fssp = PCM512x_FSSP_192KHZ; 1150 else 1151 fssp = PCM512x_FSSP_384KHZ; 1152 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1153 PCM512x_FSSP, fssp); 1154 if (ret != 0) { 1155 dev_err(component->dev, "Failed to set fs speed: %d\n", ret); 1156 return ret; 1157 } 1158 1159 dev_dbg(component->dev, "DSP divider %d\n", dsp_div); 1160 dev_dbg(component->dev, "DAC divider %d\n", dac_div); 1161 dev_dbg(component->dev, "NCP divider %d\n", ncp_div); 1162 dev_dbg(component->dev, "OSR divider %d\n", osr_div); 1163 dev_dbg(component->dev, "BCK divider %d\n", bclk_div); 1164 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div); 1165 dev_dbg(component->dev, "IDAC %d\n", idac); 1166 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp); 1167 1168 return 0; 1169 } 1170 1171 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1172 struct snd_pcm_hw_params *params, 1173 struct snd_soc_dai *dai) 1174 { 1175 struct snd_soc_component *component = dai->component; 1176 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1177 int alen; 1178 int gpio; 1179 int clock_output; 1180 int master_mode; 1181 int ret; 1182 1183 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n", 1184 params_rate(params), 1185 params_channels(params)); 1186 1187 switch (params_width(params)) { 1188 case 16: 1189 alen = PCM512x_ALEN_16; 1190 break; 1191 case 20: 1192 alen = PCM512x_ALEN_20; 1193 break; 1194 case 24: 1195 alen = PCM512x_ALEN_24; 1196 break; 1197 case 32: 1198 alen = PCM512x_ALEN_32; 1199 break; 1200 default: 1201 dev_err(component->dev, "Bad frame size: %d\n", 1202 params_width(params)); 1203 return -EINVAL; 1204 } 1205 1206 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1207 case SND_SOC_DAIFMT_CBS_CFS: 1208 ret = regmap_update_bits(pcm512x->regmap, 1209 PCM512x_BCLK_LRCLK_CFG, 1210 PCM512x_BCKP 1211 | PCM512x_BCKO | PCM512x_LRKO, 1212 0); 1213 if (ret != 0) { 1214 dev_err(component->dev, 1215 "Failed to enable slave mode: %d\n", ret); 1216 return ret; 1217 } 1218 1219 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1220 PCM512x_DCAS, 0); 1221 if (ret != 0) { 1222 dev_err(component->dev, 1223 "Failed to enable clock divider autoset: %d\n", 1224 ret); 1225 return ret; 1226 } 1227 return 0; 1228 case SND_SOC_DAIFMT_CBM_CFM: 1229 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1230 master_mode = PCM512x_RLRK | PCM512x_RBCK; 1231 break; 1232 case SND_SOC_DAIFMT_CBM_CFS: 1233 clock_output = PCM512x_BCKO; 1234 master_mode = PCM512x_RBCK; 1235 break; 1236 default: 1237 return -EINVAL; 1238 } 1239 1240 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1241 PCM512x_ALEN, alen); 1242 if (ret != 0) { 1243 dev_err(component->dev, "Failed to set frame size: %d\n", ret); 1244 return ret; 1245 } 1246 1247 if (pcm512x->pll_out) { 1248 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1249 if (ret != 0) { 1250 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret); 1251 return ret; 1252 } 1253 1254 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1255 if (ret != 0) { 1256 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret); 1257 return ret; 1258 } 1259 1260 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1261 PCM512x_IDFS | PCM512x_IDBK 1262 | PCM512x_IDSK | PCM512x_IDCH 1263 | PCM512x_IDCM | PCM512x_DCAS 1264 | PCM512x_IPLK, 1265 PCM512x_IDFS | PCM512x_IDBK 1266 | PCM512x_IDSK | PCM512x_IDCH 1267 | PCM512x_DCAS); 1268 if (ret != 0) { 1269 dev_err(component->dev, 1270 "Failed to ignore auto-clock failures: %d\n", 1271 ret); 1272 return ret; 1273 } 1274 } else { 1275 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1276 PCM512x_IDFS | PCM512x_IDBK 1277 | PCM512x_IDSK | PCM512x_IDCH 1278 | PCM512x_IDCM | PCM512x_DCAS 1279 | PCM512x_IPLK, 1280 PCM512x_IDFS | PCM512x_IDBK 1281 | PCM512x_IDSK | PCM512x_IDCH 1282 | PCM512x_DCAS | PCM512x_IPLK); 1283 if (ret != 0) { 1284 dev_err(component->dev, 1285 "Failed to ignore auto-clock failures: %d\n", 1286 ret); 1287 return ret; 1288 } 1289 1290 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1291 PCM512x_PLLE, 0); 1292 if (ret != 0) { 1293 dev_err(component->dev, "Failed to disable pll: %d\n", ret); 1294 return ret; 1295 } 1296 } 1297 1298 ret = pcm512x_set_dividers(dai, params); 1299 if (ret != 0) 1300 return ret; 1301 1302 if (pcm512x->pll_out) { 1303 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1304 PCM512x_SREF, PCM512x_SREF_GPIO); 1305 if (ret != 0) { 1306 dev_err(component->dev, 1307 "Failed to set gpio as pllref: %d\n", ret); 1308 return ret; 1309 } 1310 1311 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1312 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1313 PCM512x_GREF, gpio); 1314 if (ret != 0) { 1315 dev_err(component->dev, 1316 "Failed to set gpio %d as pllin: %d\n", 1317 pcm512x->pll_in, ret); 1318 return ret; 1319 } 1320 1321 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1322 PCM512x_PLLE, PCM512x_PLLE); 1323 if (ret != 0) { 1324 dev_err(component->dev, "Failed to enable pll: %d\n", ret); 1325 return ret; 1326 } 1327 } 1328 1329 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1330 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1331 clock_output); 1332 if (ret != 0) { 1333 dev_err(component->dev, "Failed to enable clock output: %d\n", ret); 1334 return ret; 1335 } 1336 1337 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1338 PCM512x_RLRK | PCM512x_RBCK, 1339 master_mode); 1340 if (ret != 0) { 1341 dev_err(component->dev, "Failed to enable master mode: %d\n", ret); 1342 return ret; 1343 } 1344 1345 if (pcm512x->pll_out) { 1346 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1347 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1348 gpio, gpio); 1349 if (ret != 0) { 1350 dev_err(component->dev, "Failed to enable gpio %d: %d\n", 1351 pcm512x->pll_out, ret); 1352 return ret; 1353 } 1354 1355 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1356 ret = regmap_update_bits(pcm512x->regmap, gpio, 1357 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1358 if (ret != 0) { 1359 dev_err(component->dev, "Failed to output pll on %d: %d\n", 1360 ret, pcm512x->pll_out); 1361 return ret; 1362 } 1363 } 1364 1365 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1366 PCM512x_RQSY, PCM512x_RQSY_HALT); 1367 if (ret != 0) { 1368 dev_err(component->dev, "Failed to halt clocks: %d\n", ret); 1369 return ret; 1370 } 1371 1372 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1373 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1374 if (ret != 0) { 1375 dev_err(component->dev, "Failed to resume clocks: %d\n", ret); 1376 return ret; 1377 } 1378 1379 return 0; 1380 } 1381 1382 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1383 { 1384 struct snd_soc_component *component = dai->component; 1385 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1386 1387 pcm512x->fmt = fmt; 1388 1389 return 0; 1390 } 1391 1392 static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 1393 { 1394 struct snd_soc_component *component = dai->component; 1395 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1396 1397 if (ratio > 256) 1398 return -EINVAL; 1399 1400 pcm512x->bclk_ratio = ratio; 1401 1402 return 0; 1403 } 1404 1405 static int pcm512x_digital_mute(struct snd_soc_dai *dai, int mute) 1406 { 1407 struct snd_soc_component *component = dai->component; 1408 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1409 int ret; 1410 unsigned int mute_det; 1411 1412 mutex_lock(&pcm512x->mutex); 1413 1414 if (mute) { 1415 pcm512x->mute |= 0x1; 1416 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE, 1417 PCM512x_RQML | PCM512x_RQMR, 1418 PCM512x_RQML | PCM512x_RQMR); 1419 if (ret != 0) { 1420 dev_err(component->dev, 1421 "Failed to set digital mute: %d\n", ret); 1422 goto unlock; 1423 } 1424 1425 regmap_read_poll_timeout(pcm512x->regmap, 1426 PCM512x_ANALOG_MUTE_DET, 1427 mute_det, (mute_det & 0x3) == 0, 1428 200, 10000); 1429 } else { 1430 pcm512x->mute &= ~0x1; 1431 ret = pcm512x_update_mute(pcm512x); 1432 if (ret != 0) { 1433 dev_err(component->dev, 1434 "Failed to update digital mute: %d\n", ret); 1435 goto unlock; 1436 } 1437 1438 regmap_read_poll_timeout(pcm512x->regmap, 1439 PCM512x_ANALOG_MUTE_DET, 1440 mute_det, 1441 (mute_det & 0x3) 1442 == ((~pcm512x->mute >> 1) & 0x3), 1443 200, 10000); 1444 } 1445 1446 unlock: 1447 mutex_unlock(&pcm512x->mutex); 1448 1449 return ret; 1450 } 1451 1452 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1453 .startup = pcm512x_dai_startup, 1454 .hw_params = pcm512x_hw_params, 1455 .set_fmt = pcm512x_set_fmt, 1456 .digital_mute = pcm512x_digital_mute, 1457 .set_bclk_ratio = pcm512x_set_bclk_ratio, 1458 }; 1459 1460 static struct snd_soc_dai_driver pcm512x_dai = { 1461 .name = "pcm512x-hifi", 1462 .playback = { 1463 .stream_name = "Playback", 1464 .channels_min = 2, 1465 .channels_max = 2, 1466 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1467 .rate_min = 8000, 1468 .rate_max = 384000, 1469 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1470 SNDRV_PCM_FMTBIT_S24_LE | 1471 SNDRV_PCM_FMTBIT_S32_LE 1472 }, 1473 .ops = &pcm512x_dai_ops, 1474 }; 1475 1476 static const struct snd_soc_component_driver pcm512x_component_driver = { 1477 .set_bias_level = pcm512x_set_bias_level, 1478 .controls = pcm512x_controls, 1479 .num_controls = ARRAY_SIZE(pcm512x_controls), 1480 .dapm_widgets = pcm512x_dapm_widgets, 1481 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1482 .dapm_routes = pcm512x_dapm_routes, 1483 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1484 .use_pmdown_time = 1, 1485 .endianness = 1, 1486 .non_legacy_dai_naming = 1, 1487 }; 1488 1489 static const struct regmap_range_cfg pcm512x_range = { 1490 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1491 .range_max = PCM512x_MAX_REGISTER, 1492 .selector_reg = PCM512x_PAGE, 1493 .selector_mask = 0xff, 1494 .window_start = 0, .window_len = 0x100, 1495 }; 1496 1497 const struct regmap_config pcm512x_regmap = { 1498 .reg_bits = 8, 1499 .val_bits = 8, 1500 1501 .readable_reg = pcm512x_readable, 1502 .volatile_reg = pcm512x_volatile, 1503 1504 .ranges = &pcm512x_range, 1505 .num_ranges = 1, 1506 1507 .max_register = PCM512x_MAX_REGISTER, 1508 .reg_defaults = pcm512x_reg_defaults, 1509 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1510 .cache_type = REGCACHE_RBTREE, 1511 }; 1512 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1513 1514 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1515 { 1516 struct pcm512x_priv *pcm512x; 1517 int i, ret; 1518 1519 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1520 if (!pcm512x) 1521 return -ENOMEM; 1522 1523 mutex_init(&pcm512x->mutex); 1524 1525 dev_set_drvdata(dev, pcm512x); 1526 pcm512x->regmap = regmap; 1527 1528 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1529 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1530 1531 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1532 pcm512x->supplies); 1533 if (ret != 0) { 1534 dev_err(dev, "Failed to get supplies: %d\n", ret); 1535 return ret; 1536 } 1537 1538 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1539 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1540 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1541 1542 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1543 ret = devm_regulator_register_notifier( 1544 pcm512x->supplies[i].consumer, 1545 &pcm512x->supply_nb[i]); 1546 if (ret != 0) { 1547 dev_err(dev, 1548 "Failed to register regulator notifier: %d\n", 1549 ret); 1550 } 1551 } 1552 1553 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1554 pcm512x->supplies); 1555 if (ret != 0) { 1556 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1557 return ret; 1558 } 1559 1560 /* Reset the device, verifying I/O in the process for I2C */ 1561 ret = regmap_write(regmap, PCM512x_RESET, 1562 PCM512x_RSTM | PCM512x_RSTR); 1563 if (ret != 0) { 1564 dev_err(dev, "Failed to reset device: %d\n", ret); 1565 goto err; 1566 } 1567 1568 ret = regmap_write(regmap, PCM512x_RESET, 0); 1569 if (ret != 0) { 1570 dev_err(dev, "Failed to reset device: %d\n", ret); 1571 goto err; 1572 } 1573 1574 pcm512x->sclk = devm_clk_get(dev, NULL); 1575 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) 1576 return -EPROBE_DEFER; 1577 if (!IS_ERR(pcm512x->sclk)) { 1578 ret = clk_prepare_enable(pcm512x->sclk); 1579 if (ret != 0) { 1580 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1581 return ret; 1582 } 1583 } 1584 1585 /* Default to standby mode */ 1586 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1587 PCM512x_RQST, PCM512x_RQST); 1588 if (ret != 0) { 1589 dev_err(dev, "Failed to request standby: %d\n", 1590 ret); 1591 goto err_clk; 1592 } 1593 1594 pm_runtime_set_active(dev); 1595 pm_runtime_enable(dev); 1596 pm_runtime_idle(dev); 1597 1598 #ifdef CONFIG_OF 1599 if (dev->of_node) { 1600 const struct device_node *np = dev->of_node; 1601 u32 val; 1602 1603 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1604 if (val > 6) { 1605 dev_err(dev, "Invalid pll-in\n"); 1606 ret = -EINVAL; 1607 goto err_clk; 1608 } 1609 pcm512x->pll_in = val; 1610 } 1611 1612 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1613 if (val > 6) { 1614 dev_err(dev, "Invalid pll-out\n"); 1615 ret = -EINVAL; 1616 goto err_clk; 1617 } 1618 pcm512x->pll_out = val; 1619 } 1620 1621 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1622 dev_err(dev, 1623 "Error: both pll-in and pll-out, or none\n"); 1624 ret = -EINVAL; 1625 goto err_clk; 1626 } 1627 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1628 dev_err(dev, "Error: pll-in == pll-out\n"); 1629 ret = -EINVAL; 1630 goto err_clk; 1631 } 1632 } 1633 #endif 1634 1635 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver, 1636 &pcm512x_dai, 1); 1637 if (ret != 0) { 1638 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1639 goto err_pm; 1640 } 1641 1642 return 0; 1643 1644 err_pm: 1645 pm_runtime_disable(dev); 1646 err_clk: 1647 if (!IS_ERR(pcm512x->sclk)) 1648 clk_disable_unprepare(pcm512x->sclk); 1649 err: 1650 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1651 pcm512x->supplies); 1652 return ret; 1653 } 1654 EXPORT_SYMBOL_GPL(pcm512x_probe); 1655 1656 void pcm512x_remove(struct device *dev) 1657 { 1658 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1659 1660 pm_runtime_disable(dev); 1661 if (!IS_ERR(pcm512x->sclk)) 1662 clk_disable_unprepare(pcm512x->sclk); 1663 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1664 pcm512x->supplies); 1665 } 1666 EXPORT_SYMBOL_GPL(pcm512x_remove); 1667 1668 #ifdef CONFIG_PM 1669 static int pcm512x_suspend(struct device *dev) 1670 { 1671 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1672 int ret; 1673 1674 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1675 PCM512x_RQPD, PCM512x_RQPD); 1676 if (ret != 0) { 1677 dev_err(dev, "Failed to request power down: %d\n", ret); 1678 return ret; 1679 } 1680 1681 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1682 pcm512x->supplies); 1683 if (ret != 0) { 1684 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1685 return ret; 1686 } 1687 1688 if (!IS_ERR(pcm512x->sclk)) 1689 clk_disable_unprepare(pcm512x->sclk); 1690 1691 return 0; 1692 } 1693 1694 static int pcm512x_resume(struct device *dev) 1695 { 1696 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1697 int ret; 1698 1699 if (!IS_ERR(pcm512x->sclk)) { 1700 ret = clk_prepare_enable(pcm512x->sclk); 1701 if (ret != 0) { 1702 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1703 return ret; 1704 } 1705 } 1706 1707 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1708 pcm512x->supplies); 1709 if (ret != 0) { 1710 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1711 return ret; 1712 } 1713 1714 regcache_cache_only(pcm512x->regmap, false); 1715 ret = regcache_sync(pcm512x->regmap); 1716 if (ret != 0) { 1717 dev_err(dev, "Failed to sync cache: %d\n", ret); 1718 return ret; 1719 } 1720 1721 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1722 PCM512x_RQPD, 0); 1723 if (ret != 0) { 1724 dev_err(dev, "Failed to remove power down: %d\n", ret); 1725 return ret; 1726 } 1727 1728 return 0; 1729 } 1730 #endif 1731 1732 const struct dev_pm_ops pcm512x_pm_ops = { 1733 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1734 }; 1735 EXPORT_SYMBOL_GPL(pcm512x_pm_ops); 1736 1737 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1738 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); 1739 MODULE_LICENSE("GPL v2"); 1740