1 /* 2 * Driver for the PCM512x CODECs 3 * 4 * Author: Mark Brown <broonie@linaro.org> 5 * Copyright 2014 Linaro Ltd 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/clk.h> 21 #include <linux/kernel.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/gcd.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/tlv.h> 30 31 #include "pcm512x.h" 32 33 #define DIV_ROUND_DOWN_ULL(ll, d) \ 34 ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) 35 36 #define PCM512x_NUM_SUPPLIES 3 37 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 38 "AVDD", 39 "DVDD", 40 "CPVDD", 41 }; 42 43 struct pcm512x_priv { 44 struct regmap *regmap; 45 struct clk *sclk; 46 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 47 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 48 int fmt; 49 int pll_in; 50 int pll_out; 51 int pll_r; 52 int pll_j; 53 int pll_d; 54 int pll_p; 55 unsigned long real_pll; 56 unsigned long overclock_pll; 57 unsigned long overclock_dac; 58 unsigned long overclock_dsp; 59 }; 60 61 /* 62 * We can't use the same notifier block for more than one supply and 63 * there's no way I can see to get from a callback to the caller 64 * except container_of(). 65 */ 66 #define PCM512x_REGULATOR_EVENT(n) \ 67 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 68 unsigned long event, void *data) \ 69 { \ 70 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 71 supply_nb[n]); \ 72 if (event & REGULATOR_EVENT_DISABLE) { \ 73 regcache_mark_dirty(pcm512x->regmap); \ 74 regcache_cache_only(pcm512x->regmap, true); \ 75 } \ 76 return 0; \ 77 } 78 79 PCM512x_REGULATOR_EVENT(0) 80 PCM512x_REGULATOR_EVENT(1) 81 PCM512x_REGULATOR_EVENT(2) 82 83 static const struct reg_default pcm512x_reg_defaults[] = { 84 { PCM512x_RESET, 0x00 }, 85 { PCM512x_POWER, 0x00 }, 86 { PCM512x_MUTE, 0x00 }, 87 { PCM512x_DSP, 0x00 }, 88 { PCM512x_PLL_REF, 0x00 }, 89 { PCM512x_DAC_REF, 0x00 }, 90 { PCM512x_DAC_ROUTING, 0x11 }, 91 { PCM512x_DSP_PROGRAM, 0x01 }, 92 { PCM512x_CLKDET, 0x00 }, 93 { PCM512x_AUTO_MUTE, 0x00 }, 94 { PCM512x_ERROR_DETECT, 0x00 }, 95 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 96 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 97 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 98 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 99 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 100 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 101 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 102 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 103 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 104 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 105 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 106 { PCM512x_VCOM_CTRL_1, 0x00 }, 107 { PCM512x_VCOM_CTRL_2, 0x01 }, 108 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 109 { PCM512x_MASTER_MODE, 0x7c }, 110 { PCM512x_GPIO_DACIN, 0x00 }, 111 { PCM512x_GPIO_PLLIN, 0x00 }, 112 { PCM512x_SYNCHRONIZE, 0x10 }, 113 { PCM512x_PLL_COEFF_0, 0x00 }, 114 { PCM512x_PLL_COEFF_1, 0x00 }, 115 { PCM512x_PLL_COEFF_2, 0x00 }, 116 { PCM512x_PLL_COEFF_3, 0x00 }, 117 { PCM512x_PLL_COEFF_4, 0x00 }, 118 { PCM512x_DSP_CLKDIV, 0x00 }, 119 { PCM512x_DAC_CLKDIV, 0x00 }, 120 { PCM512x_NCP_CLKDIV, 0x00 }, 121 { PCM512x_OSR_CLKDIV, 0x00 }, 122 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 123 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 124 { PCM512x_FS_SPEED_MODE, 0x00 }, 125 { PCM512x_IDAC_1, 0x01 }, 126 { PCM512x_IDAC_2, 0x00 }, 127 }; 128 129 static bool pcm512x_readable(struct device *dev, unsigned int reg) 130 { 131 switch (reg) { 132 case PCM512x_RESET: 133 case PCM512x_POWER: 134 case PCM512x_MUTE: 135 case PCM512x_PLL_EN: 136 case PCM512x_SPI_MISO_FUNCTION: 137 case PCM512x_DSP: 138 case PCM512x_GPIO_EN: 139 case PCM512x_BCLK_LRCLK_CFG: 140 case PCM512x_DSP_GPIO_INPUT: 141 case PCM512x_MASTER_MODE: 142 case PCM512x_PLL_REF: 143 case PCM512x_DAC_REF: 144 case PCM512x_GPIO_DACIN: 145 case PCM512x_GPIO_PLLIN: 146 case PCM512x_SYNCHRONIZE: 147 case PCM512x_PLL_COEFF_0: 148 case PCM512x_PLL_COEFF_1: 149 case PCM512x_PLL_COEFF_2: 150 case PCM512x_PLL_COEFF_3: 151 case PCM512x_PLL_COEFF_4: 152 case PCM512x_DSP_CLKDIV: 153 case PCM512x_DAC_CLKDIV: 154 case PCM512x_NCP_CLKDIV: 155 case PCM512x_OSR_CLKDIV: 156 case PCM512x_MASTER_CLKDIV_1: 157 case PCM512x_MASTER_CLKDIV_2: 158 case PCM512x_FS_SPEED_MODE: 159 case PCM512x_IDAC_1: 160 case PCM512x_IDAC_2: 161 case PCM512x_ERROR_DETECT: 162 case PCM512x_I2S_1: 163 case PCM512x_I2S_2: 164 case PCM512x_DAC_ROUTING: 165 case PCM512x_DSP_PROGRAM: 166 case PCM512x_CLKDET: 167 case PCM512x_AUTO_MUTE: 168 case PCM512x_DIGITAL_VOLUME_1: 169 case PCM512x_DIGITAL_VOLUME_2: 170 case PCM512x_DIGITAL_VOLUME_3: 171 case PCM512x_DIGITAL_MUTE_1: 172 case PCM512x_DIGITAL_MUTE_2: 173 case PCM512x_DIGITAL_MUTE_3: 174 case PCM512x_GPIO_OUTPUT_1: 175 case PCM512x_GPIO_OUTPUT_2: 176 case PCM512x_GPIO_OUTPUT_3: 177 case PCM512x_GPIO_OUTPUT_4: 178 case PCM512x_GPIO_OUTPUT_5: 179 case PCM512x_GPIO_OUTPUT_6: 180 case PCM512x_GPIO_CONTROL_1: 181 case PCM512x_GPIO_CONTROL_2: 182 case PCM512x_OVERFLOW: 183 case PCM512x_RATE_DET_1: 184 case PCM512x_RATE_DET_2: 185 case PCM512x_RATE_DET_3: 186 case PCM512x_RATE_DET_4: 187 case PCM512x_CLOCK_STATUS: 188 case PCM512x_ANALOG_MUTE_DET: 189 case PCM512x_GPIN: 190 case PCM512x_DIGITAL_MUTE_DET: 191 case PCM512x_OUTPUT_AMPLITUDE: 192 case PCM512x_ANALOG_GAIN_CTRL: 193 case PCM512x_UNDERVOLTAGE_PROT: 194 case PCM512x_ANALOG_MUTE_CTRL: 195 case PCM512x_ANALOG_GAIN_BOOST: 196 case PCM512x_VCOM_CTRL_1: 197 case PCM512x_VCOM_CTRL_2: 198 case PCM512x_CRAM_CTRL: 199 case PCM512x_FLEX_A: 200 case PCM512x_FLEX_B: 201 return true; 202 default: 203 /* There are 256 raw register addresses */ 204 return reg < 0xff; 205 } 206 } 207 208 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 209 { 210 switch (reg) { 211 case PCM512x_PLL_EN: 212 case PCM512x_OVERFLOW: 213 case PCM512x_RATE_DET_1: 214 case PCM512x_RATE_DET_2: 215 case PCM512x_RATE_DET_3: 216 case PCM512x_RATE_DET_4: 217 case PCM512x_CLOCK_STATUS: 218 case PCM512x_ANALOG_MUTE_DET: 219 case PCM512x_GPIN: 220 case PCM512x_DIGITAL_MUTE_DET: 221 case PCM512x_CRAM_CTRL: 222 return true; 223 default: 224 /* There are 256 raw register addresses */ 225 return reg < 0xff; 226 } 227 } 228 229 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 230 struct snd_ctl_elem_value *ucontrol) 231 { 232 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 233 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 234 235 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 236 return 0; 237 } 238 239 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 240 struct snd_ctl_elem_value *ucontrol) 241 { 242 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 243 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 244 245 switch (codec->dapm.bias_level) { 246 case SND_SOC_BIAS_OFF: 247 case SND_SOC_BIAS_STANDBY: 248 break; 249 default: 250 return -EBUSY; 251 } 252 253 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 254 return 0; 255 } 256 257 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 258 struct snd_ctl_elem_value *ucontrol) 259 { 260 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 261 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 262 263 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 264 return 0; 265 } 266 267 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 268 struct snd_ctl_elem_value *ucontrol) 269 { 270 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 271 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 272 273 switch (codec->dapm.bias_level) { 274 case SND_SOC_BIAS_OFF: 275 case SND_SOC_BIAS_STANDBY: 276 break; 277 default: 278 return -EBUSY; 279 } 280 281 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 282 return 0; 283 } 284 285 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 286 struct snd_ctl_elem_value *ucontrol) 287 { 288 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 289 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 290 291 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 292 return 0; 293 } 294 295 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 296 struct snd_ctl_elem_value *ucontrol) 297 { 298 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 299 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 300 301 switch (codec->dapm.bias_level) { 302 case SND_SOC_BIAS_OFF: 303 case SND_SOC_BIAS_STANDBY: 304 break; 305 default: 306 return -EBUSY; 307 } 308 309 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 310 return 0; 311 } 312 313 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 314 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 315 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 316 317 static const char * const pcm512x_dsp_program_texts[] = { 318 "FIR interpolation with de-emphasis", 319 "Low latency IIR with de-emphasis", 320 "High attenuation with de-emphasis", 321 "Fixed process flow", 322 "Ringing-less low latency FIR", 323 }; 324 325 static const unsigned int pcm512x_dsp_program_values[] = { 326 1, 327 2, 328 3, 329 5, 330 7, 331 }; 332 333 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 334 PCM512x_DSP_PROGRAM, 0, 0x1f, 335 pcm512x_dsp_program_texts, 336 pcm512x_dsp_program_values); 337 338 static const char * const pcm512x_clk_missing_text[] = { 339 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 340 }; 341 342 static const struct soc_enum pcm512x_clk_missing = 343 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 344 345 static const char * const pcm512x_autom_text[] = { 346 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 347 }; 348 349 static const struct soc_enum pcm512x_autom_l = 350 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 351 pcm512x_autom_text); 352 353 static const struct soc_enum pcm512x_autom_r = 354 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 355 pcm512x_autom_text); 356 357 static const char * const pcm512x_ramp_rate_text[] = { 358 "1 sample/update", "2 samples/update", "4 samples/update", 359 "Immediate" 360 }; 361 362 static const struct soc_enum pcm512x_vndf = 363 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 364 pcm512x_ramp_rate_text); 365 366 static const struct soc_enum pcm512x_vnuf = 367 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 368 pcm512x_ramp_rate_text); 369 370 static const struct soc_enum pcm512x_vedf = 371 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 372 pcm512x_ramp_rate_text); 373 374 static const char * const pcm512x_ramp_step_text[] = { 375 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 376 }; 377 378 static const struct soc_enum pcm512x_vnds = 379 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 380 pcm512x_ramp_step_text); 381 382 static const struct soc_enum pcm512x_vnus = 383 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 384 pcm512x_ramp_step_text); 385 386 static const struct soc_enum pcm512x_veds = 387 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 388 pcm512x_ramp_step_text); 389 390 static const struct snd_kcontrol_new pcm512x_controls[] = { 391 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 392 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 393 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 394 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 395 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 396 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 397 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT, 398 PCM512x_RQMR_SHIFT, 1, 1), 399 400 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 401 SOC_ENUM("DSP Program", pcm512x_dsp_program), 402 403 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 404 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 405 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 406 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 407 PCM512x_ACTL_SHIFT, 1, 0), 408 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 409 PCM512x_AMRE_SHIFT, 1, 0), 410 411 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 412 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 413 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 414 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 415 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 416 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 417 418 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 419 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 420 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 421 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 422 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 423 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 424 }; 425 426 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 427 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 428 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 429 430 SND_SOC_DAPM_OUTPUT("OUTL"), 431 SND_SOC_DAPM_OUTPUT("OUTR"), 432 }; 433 434 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 435 { "DACL", NULL, "Playback" }, 436 { "DACR", NULL, "Playback" }, 437 438 { "OUTL", NULL, "DACL" }, 439 { "OUTR", NULL, "DACR" }, 440 }; 441 442 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 443 { 444 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 445 } 446 447 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 448 { 449 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 450 } 451 452 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 453 unsigned long rate) 454 { 455 return rate + rate * pcm512x->overclock_dac / 100; 456 } 457 458 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 459 { 460 if (!pcm512x->pll_out) 461 return 25000000; 462 return pcm512x_pll_max(pcm512x); 463 } 464 465 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 466 unsigned long dac_rate) 467 { 468 /* 469 * If the DAC is not actually overclocked, use the good old 470 * NCP target rate... 471 */ 472 if (dac_rate <= 6144000) 473 return 1536000; 474 /* 475 * ...but if the DAC is in fact overclocked, bump the NCP target 476 * rate to get the recommended dividers even when overclocking. 477 */ 478 return pcm512x_dac_max(pcm512x, 1536000); 479 } 480 481 static const u32 pcm512x_dai_rates[] = { 482 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 483 88200, 96000, 176400, 192000, 384000, 484 }; 485 486 static const struct snd_pcm_hw_constraint_list constraints_slave = { 487 .count = ARRAY_SIZE(pcm512x_dai_rates), 488 .list = pcm512x_dai_rates, 489 }; 490 491 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 492 struct snd_pcm_hw_rule *rule) 493 { 494 struct pcm512x_priv *pcm512x = rule->private; 495 struct snd_interval ranges[2]; 496 int frame_size; 497 498 frame_size = snd_soc_params_to_frame_size(params); 499 if (frame_size < 0) 500 return frame_size; 501 502 switch (frame_size) { 503 case 32: 504 /* No hole when the frame size is 32. */ 505 return 0; 506 case 48: 507 case 64: 508 /* There is only one hole in the range of supported 509 * rates, but it moves with the frame size. 510 */ 511 memset(ranges, 0, sizeof(ranges)); 512 ranges[0].min = 8000; 513 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 514 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 515 ranges[1].max = 384000; 516 break; 517 default: 518 return -EINVAL; 519 } 520 521 return snd_interval_ranges(hw_param_interval(params, rule->var), 522 ARRAY_SIZE(ranges), ranges, 0); 523 } 524 525 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 526 struct snd_soc_dai *dai) 527 { 528 struct snd_soc_codec *codec = dai->codec; 529 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 530 struct device *dev = dai->dev; 531 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 532 struct snd_ratnum *rats_no_pll; 533 534 if (IS_ERR(pcm512x->sclk)) { 535 dev_err(dev, "Need SCLK for master mode: %ld\n", 536 PTR_ERR(pcm512x->sclk)); 537 return PTR_ERR(pcm512x->sclk); 538 } 539 540 if (pcm512x->pll_out) 541 return snd_pcm_hw_rule_add(substream->runtime, 0, 542 SNDRV_PCM_HW_PARAM_RATE, 543 pcm512x_hw_rule_rate, 544 pcm512x, 545 SNDRV_PCM_HW_PARAM_FRAME_BITS, 546 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 547 548 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 549 GFP_KERNEL); 550 if (!constraints_no_pll) 551 return -ENOMEM; 552 constraints_no_pll->nrats = 1; 553 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 554 if (!rats_no_pll) 555 return -ENOMEM; 556 constraints_no_pll->rats = rats_no_pll; 557 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 558 rats_no_pll->den_min = 1; 559 rats_no_pll->den_max = 128; 560 rats_no_pll->den_step = 1; 561 562 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 563 SNDRV_PCM_HW_PARAM_RATE, 564 constraints_no_pll); 565 } 566 567 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 568 struct snd_soc_dai *dai) 569 { 570 struct snd_soc_codec *codec = dai->codec; 571 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 572 struct device *dev = dai->dev; 573 struct regmap *regmap = pcm512x->regmap; 574 575 if (IS_ERR(pcm512x->sclk)) { 576 dev_info(dev, "No SCLK, using BCLK: %ld\n", 577 PTR_ERR(pcm512x->sclk)); 578 579 /* Disable reporting of missing SCLK as an error */ 580 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 581 PCM512x_IDCH, PCM512x_IDCH); 582 583 /* Switch PLL input to BCLK */ 584 regmap_update_bits(regmap, PCM512x_PLL_REF, 585 PCM512x_SREF, PCM512x_SREF_BCK); 586 } 587 588 return snd_pcm_hw_constraint_list(substream->runtime, 0, 589 SNDRV_PCM_HW_PARAM_RATE, 590 &constraints_slave); 591 } 592 593 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 594 struct snd_soc_dai *dai) 595 { 596 struct snd_soc_codec *codec = dai->codec; 597 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 598 599 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 600 case SND_SOC_DAIFMT_CBM_CFM: 601 case SND_SOC_DAIFMT_CBM_CFS: 602 return pcm512x_dai_startup_master(substream, dai); 603 604 case SND_SOC_DAIFMT_CBS_CFS: 605 return pcm512x_dai_startup_slave(substream, dai); 606 607 default: 608 return -EINVAL; 609 } 610 } 611 612 static int pcm512x_set_bias_level(struct snd_soc_codec *codec, 613 enum snd_soc_bias_level level) 614 { 615 struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev); 616 int ret; 617 618 switch (level) { 619 case SND_SOC_BIAS_ON: 620 case SND_SOC_BIAS_PREPARE: 621 break; 622 623 case SND_SOC_BIAS_STANDBY: 624 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 625 PCM512x_RQST, 0); 626 if (ret != 0) { 627 dev_err(codec->dev, "Failed to remove standby: %d\n", 628 ret); 629 return ret; 630 } 631 break; 632 633 case SND_SOC_BIAS_OFF: 634 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 635 PCM512x_RQST, PCM512x_RQST); 636 if (ret != 0) { 637 dev_err(codec->dev, "Failed to request standby: %d\n", 638 ret); 639 return ret; 640 } 641 break; 642 } 643 644 codec->dapm.bias_level = level; 645 646 return 0; 647 } 648 649 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 650 unsigned long bclk_rate) 651 { 652 struct device *dev = dai->dev; 653 struct snd_soc_codec *codec = dai->codec; 654 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 655 unsigned long sck_rate; 656 int pow2; 657 658 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 659 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 660 661 /* select sck_rate as a multiple of bclk_rate but still with 662 * as many factors of 2 as possible, as that makes it easier 663 * to find a fast DAC rate 664 */ 665 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 666 for (; pow2; pow2 >>= 1) { 667 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 668 bclk_rate * pow2); 669 if (sck_rate >= 16000000) 670 break; 671 } 672 if (!pow2) { 673 dev_err(dev, "Impossible to generate a suitable SCK\n"); 674 return 0; 675 } 676 677 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 678 return sck_rate; 679 } 680 681 /* pll_rate = pllin_rate * R * J.D / P 682 * 1 <= R <= 16 683 * 1 <= J <= 63 684 * 0 <= D <= 9999 685 * 1 <= P <= 15 686 * 64 MHz <= pll_rate <= 100 MHz 687 * if D == 0 688 * 1 MHz <= pllin_rate / P <= 20 MHz 689 * else if D > 0 690 * 6.667 MHz <= pllin_rate / P <= 20 MHz 691 * 4 <= J <= 11 692 * R = 1 693 */ 694 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 695 unsigned long pllin_rate, 696 unsigned long pll_rate) 697 { 698 struct device *dev = dai->dev; 699 struct snd_soc_codec *codec = dai->codec; 700 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 701 unsigned long common; 702 int R, J, D, P; 703 unsigned long K; /* 10000 * J.D */ 704 unsigned long num; 705 unsigned long den; 706 707 common = gcd(pll_rate, pllin_rate); 708 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 709 pll_rate, pllin_rate, common); 710 num = pll_rate / common; 711 den = pllin_rate / common; 712 713 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 714 if (pllin_rate / den > 20000000 && num < 8) { 715 num *= DIV_ROUND_UP(pllin_rate / den, 20000000); 716 den *= DIV_ROUND_UP(pllin_rate / den, 20000000); 717 } 718 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 719 720 P = den; 721 if (den <= 15 && num <= 16 * 63 722 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 723 /* Try the case with D = 0 */ 724 D = 0; 725 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 726 for (R = 16; R; R--) { 727 if (num % R) 728 continue; 729 J = num / R; 730 if (J == 0 || J > 63) 731 continue; 732 733 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 734 pcm512x->real_pll = pll_rate; 735 goto done; 736 } 737 /* no luck */ 738 } 739 740 R = 1; 741 742 if (num > 0xffffffffUL / 10000) 743 goto fallback; 744 745 /* Try to find an exact pll_rate using the D > 0 case */ 746 common = gcd(10000 * num, den); 747 num = 10000 * num / common; 748 den /= common; 749 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 750 751 for (P = den; P <= 15; P++) { 752 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 753 continue; 754 if (num * P % den) 755 continue; 756 K = num * P / den; 757 /* J == 12 is ok if D == 0 */ 758 if (K < 40000 || K > 120000) 759 continue; 760 761 J = K / 10000; 762 D = K % 10000; 763 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 764 pcm512x->real_pll = pll_rate; 765 goto done; 766 } 767 768 /* Fall back to an approximate pll_rate */ 769 770 fallback: 771 /* find smallest possible P */ 772 P = DIV_ROUND_UP(pllin_rate, 20000000); 773 if (!P) 774 P = 1; 775 else if (P > 15) { 776 dev_err(dev, "Need a slower clock as pll-input\n"); 777 return -EINVAL; 778 } 779 if (pllin_rate / P < 6667000) { 780 dev_err(dev, "Need a faster clock as pll-input\n"); 781 return -EINVAL; 782 } 783 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 784 if (K < 40000) 785 K = 40000; 786 /* J == 12 is ok if D == 0 */ 787 if (K > 120000) 788 K = 120000; 789 J = K / 10000; 790 D = K % 10000; 791 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 792 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 793 794 done: 795 pcm512x->pll_r = R; 796 pcm512x->pll_j = J; 797 pcm512x->pll_d = D; 798 pcm512x->pll_p = P; 799 return 0; 800 } 801 802 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 803 unsigned long osr_rate, 804 unsigned long pllin_rate) 805 { 806 struct snd_soc_codec *codec = dai->codec; 807 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 808 unsigned long dac_rate; 809 810 if (!pcm512x->pll_out) 811 return 0; /* no PLL to bypass, force SCK as DAC input */ 812 813 if (pllin_rate % osr_rate) 814 return 0; /* futile, quit early */ 815 816 /* run DAC no faster than 6144000 Hz */ 817 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 818 dac_rate; 819 dac_rate -= osr_rate) { 820 821 if (pllin_rate / dac_rate > 128) 822 return 0; /* DAC divider would be too big */ 823 824 if (!(pllin_rate % dac_rate)) 825 return dac_rate; 826 827 dac_rate -= osr_rate; 828 } 829 830 return 0; 831 } 832 833 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 834 struct snd_pcm_hw_params *params) 835 { 836 struct device *dev = dai->dev; 837 struct snd_soc_codec *codec = dai->codec; 838 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 839 unsigned long pllin_rate = 0; 840 unsigned long pll_rate; 841 unsigned long sck_rate; 842 unsigned long mck_rate; 843 unsigned long bclk_rate; 844 unsigned long sample_rate; 845 unsigned long osr_rate; 846 unsigned long dacsrc_rate; 847 int bclk_div; 848 int lrclk_div; 849 int dsp_div; 850 int dac_div; 851 unsigned long dac_rate; 852 int ncp_div; 853 int osr_div; 854 int ret; 855 int idac; 856 int fssp; 857 int gpio; 858 859 lrclk_div = snd_soc_params_to_frame_size(params); 860 if (lrclk_div == 0) { 861 dev_err(dev, "No LRCLK?\n"); 862 return -EINVAL; 863 } 864 865 if (!pcm512x->pll_out) { 866 sck_rate = clk_get_rate(pcm512x->sclk); 867 bclk_div = params->rate_den * 64 / lrclk_div; 868 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); 869 870 mck_rate = sck_rate; 871 } else { 872 ret = snd_soc_params_to_bclk(params); 873 if (ret < 0) { 874 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 875 return ret; 876 } 877 if (ret == 0) { 878 dev_err(dev, "No BCLK?\n"); 879 return -EINVAL; 880 } 881 bclk_rate = ret; 882 883 pllin_rate = clk_get_rate(pcm512x->sclk); 884 885 sck_rate = pcm512x_find_sck(dai, bclk_rate); 886 if (!sck_rate) 887 return -EINVAL; 888 pll_rate = 4 * sck_rate; 889 890 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 891 if (ret != 0) 892 return ret; 893 894 ret = regmap_write(pcm512x->regmap, 895 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 896 if (ret != 0) { 897 dev_err(dev, "Failed to write PLL P: %d\n", ret); 898 return ret; 899 } 900 901 ret = regmap_write(pcm512x->regmap, 902 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 903 if (ret != 0) { 904 dev_err(dev, "Failed to write PLL J: %d\n", ret); 905 return ret; 906 } 907 908 ret = regmap_write(pcm512x->regmap, 909 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 910 if (ret != 0) { 911 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 912 return ret; 913 } 914 915 ret = regmap_write(pcm512x->regmap, 916 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 917 if (ret != 0) { 918 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 919 return ret; 920 } 921 922 ret = regmap_write(pcm512x->regmap, 923 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 924 if (ret != 0) { 925 dev_err(dev, "Failed to write PLL R: %d\n", ret); 926 return ret; 927 } 928 929 mck_rate = pcm512x->real_pll; 930 931 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 932 } 933 934 if (bclk_div > 128) { 935 dev_err(dev, "Failed to find BCLK divider\n"); 936 return -EINVAL; 937 } 938 939 /* the actual rate */ 940 sample_rate = sck_rate / bclk_div / lrclk_div; 941 osr_rate = 16 * sample_rate; 942 943 /* run DSP no faster than 50 MHz */ 944 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 945 946 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 947 if (dac_rate) { 948 /* the desired clock rate is "compatible" with the pll input 949 * clock, so use that clock as dac input instead of the pll 950 * output clock since the pll will introduce jitter and thus 951 * noise. 952 */ 953 dev_dbg(dev, "using pll input as dac input\n"); 954 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 955 PCM512x_SDAC, PCM512x_SDAC_GPIO); 956 if (ret != 0) { 957 dev_err(codec->dev, 958 "Failed to set gpio as dacref: %d\n", ret); 959 return ret; 960 } 961 962 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 963 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 964 PCM512x_GREF, gpio); 965 if (ret != 0) { 966 dev_err(codec->dev, 967 "Failed to set gpio %d as dacin: %d\n", 968 pcm512x->pll_in, ret); 969 return ret; 970 } 971 972 dacsrc_rate = pllin_rate; 973 } else { 974 /* run DAC no faster than 6144000 Hz */ 975 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 976 / osr_rate; 977 unsigned long sck_mul = sck_rate / osr_rate; 978 979 for (; dac_mul; dac_mul--) { 980 if (!(sck_mul % dac_mul)) 981 break; 982 } 983 if (!dac_mul) { 984 dev_err(dev, "Failed to find DAC rate\n"); 985 return -EINVAL; 986 } 987 988 dac_rate = dac_mul * osr_rate; 989 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 990 dac_rate, sample_rate); 991 992 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 993 PCM512x_SDAC, PCM512x_SDAC_SCK); 994 if (ret != 0) { 995 dev_err(codec->dev, 996 "Failed to set sck as dacref: %d\n", ret); 997 return ret; 998 } 999 1000 dacsrc_rate = sck_rate; 1001 } 1002 1003 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1004 if (osr_div > 128) { 1005 dev_err(dev, "Failed to find OSR divider\n"); 1006 return -EINVAL; 1007 } 1008 1009 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1010 if (dac_div > 128) { 1011 dev_err(dev, "Failed to find DAC divider\n"); 1012 return -EINVAL; 1013 } 1014 dac_rate = dacsrc_rate / dac_div; 1015 1016 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1017 pcm512x_ncp_target(pcm512x, dac_rate)); 1018 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1019 /* run NCP no faster than 2048000 Hz, but why? */ 1020 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1021 if (ncp_div > 128) { 1022 dev_err(dev, "Failed to find NCP divider\n"); 1023 return -EINVAL; 1024 } 1025 } 1026 1027 idac = mck_rate / (dsp_div * sample_rate); 1028 1029 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1030 if (ret != 0) { 1031 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1032 return ret; 1033 } 1034 1035 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1036 if (ret != 0) { 1037 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1038 return ret; 1039 } 1040 1041 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1042 if (ret != 0) { 1043 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1044 return ret; 1045 } 1046 1047 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1048 if (ret != 0) { 1049 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1050 return ret; 1051 } 1052 1053 ret = regmap_write(pcm512x->regmap, 1054 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1055 if (ret != 0) { 1056 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1057 return ret; 1058 } 1059 1060 ret = regmap_write(pcm512x->regmap, 1061 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1062 if (ret != 0) { 1063 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1064 return ret; 1065 } 1066 1067 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1068 if (ret != 0) { 1069 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1070 return ret; 1071 } 1072 1073 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1074 if (ret != 0) { 1075 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1076 return ret; 1077 } 1078 1079 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1080 fssp = PCM512x_FSSP_48KHZ; 1081 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1082 fssp = PCM512x_FSSP_96KHZ; 1083 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1084 fssp = PCM512x_FSSP_192KHZ; 1085 else 1086 fssp = PCM512x_FSSP_384KHZ; 1087 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1088 PCM512x_FSSP, fssp); 1089 if (ret != 0) { 1090 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret); 1091 return ret; 1092 } 1093 1094 dev_dbg(codec->dev, "DSP divider %d\n", dsp_div); 1095 dev_dbg(codec->dev, "DAC divider %d\n", dac_div); 1096 dev_dbg(codec->dev, "NCP divider %d\n", ncp_div); 1097 dev_dbg(codec->dev, "OSR divider %d\n", osr_div); 1098 dev_dbg(codec->dev, "BCK divider %d\n", bclk_div); 1099 dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div); 1100 dev_dbg(codec->dev, "IDAC %d\n", idac); 1101 dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp); 1102 1103 return 0; 1104 } 1105 1106 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1107 struct snd_pcm_hw_params *params, 1108 struct snd_soc_dai *dai) 1109 { 1110 struct snd_soc_codec *codec = dai->codec; 1111 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 1112 int alen; 1113 int gpio; 1114 int clock_output; 1115 int master_mode; 1116 int ret; 1117 1118 dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n", 1119 params_rate(params), 1120 params_channels(params)); 1121 1122 switch (snd_pcm_format_width(params_format(params))) { 1123 case 16: 1124 alen = PCM512x_ALEN_16; 1125 break; 1126 case 20: 1127 alen = PCM512x_ALEN_20; 1128 break; 1129 case 24: 1130 alen = PCM512x_ALEN_24; 1131 break; 1132 case 32: 1133 alen = PCM512x_ALEN_32; 1134 break; 1135 default: 1136 dev_err(codec->dev, "Bad frame size: %d\n", 1137 snd_pcm_format_width(params_format(params))); 1138 return -EINVAL; 1139 } 1140 1141 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1142 case SND_SOC_DAIFMT_CBS_CFS: 1143 ret = regmap_update_bits(pcm512x->regmap, 1144 PCM512x_BCLK_LRCLK_CFG, 1145 PCM512x_BCKP 1146 | PCM512x_BCKO | PCM512x_LRKO, 1147 0); 1148 if (ret != 0) { 1149 dev_err(codec->dev, 1150 "Failed to enable slave mode: %d\n", ret); 1151 return ret; 1152 } 1153 1154 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1155 PCM512x_DCAS, 0); 1156 if (ret != 0) { 1157 dev_err(codec->dev, 1158 "Failed to enable clock divider autoset: %d\n", 1159 ret); 1160 return ret; 1161 } 1162 return 0; 1163 case SND_SOC_DAIFMT_CBM_CFM: 1164 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1165 master_mode = PCM512x_RLRK | PCM512x_RBCK; 1166 break; 1167 case SND_SOC_DAIFMT_CBM_CFS: 1168 clock_output = PCM512x_BCKO; 1169 master_mode = PCM512x_RBCK; 1170 break; 1171 default: 1172 return -EINVAL; 1173 } 1174 1175 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1176 PCM512x_ALEN, alen); 1177 if (ret != 0) { 1178 dev_err(codec->dev, "Failed to set frame size: %d\n", ret); 1179 return ret; 1180 } 1181 1182 if (pcm512x->pll_out) { 1183 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1184 if (ret != 0) { 1185 dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret); 1186 return ret; 1187 } 1188 1189 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1190 if (ret != 0) { 1191 dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret); 1192 return ret; 1193 } 1194 1195 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1196 PCM512x_IDFS | PCM512x_IDBK 1197 | PCM512x_IDSK | PCM512x_IDCH 1198 | PCM512x_IDCM | PCM512x_DCAS 1199 | PCM512x_IPLK, 1200 PCM512x_IDFS | PCM512x_IDBK 1201 | PCM512x_IDSK | PCM512x_IDCH 1202 | PCM512x_DCAS); 1203 if (ret != 0) { 1204 dev_err(codec->dev, 1205 "Failed to ignore auto-clock failures: %d\n", 1206 ret); 1207 return ret; 1208 } 1209 } else { 1210 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1211 PCM512x_IDFS | PCM512x_IDBK 1212 | PCM512x_IDSK | PCM512x_IDCH 1213 | PCM512x_IDCM | PCM512x_DCAS 1214 | PCM512x_IPLK, 1215 PCM512x_IDFS | PCM512x_IDBK 1216 | PCM512x_IDSK | PCM512x_IDCH 1217 | PCM512x_DCAS | PCM512x_IPLK); 1218 if (ret != 0) { 1219 dev_err(codec->dev, 1220 "Failed to ignore auto-clock failures: %d\n", 1221 ret); 1222 return ret; 1223 } 1224 1225 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1226 PCM512x_PLLE, 0); 1227 if (ret != 0) { 1228 dev_err(codec->dev, "Failed to disable pll: %d\n", ret); 1229 return ret; 1230 } 1231 } 1232 1233 ret = pcm512x_set_dividers(dai, params); 1234 if (ret != 0) 1235 return ret; 1236 1237 if (pcm512x->pll_out) { 1238 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1239 PCM512x_SREF, PCM512x_SREF_GPIO); 1240 if (ret != 0) { 1241 dev_err(codec->dev, 1242 "Failed to set gpio as pllref: %d\n", ret); 1243 return ret; 1244 } 1245 1246 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1247 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1248 PCM512x_GREF, gpio); 1249 if (ret != 0) { 1250 dev_err(codec->dev, 1251 "Failed to set gpio %d as pllin: %d\n", 1252 pcm512x->pll_in, ret); 1253 return ret; 1254 } 1255 1256 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1257 PCM512x_PLLE, PCM512x_PLLE); 1258 if (ret != 0) { 1259 dev_err(codec->dev, "Failed to enable pll: %d\n", ret); 1260 return ret; 1261 } 1262 } 1263 1264 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1265 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1266 clock_output); 1267 if (ret != 0) { 1268 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret); 1269 return ret; 1270 } 1271 1272 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1273 PCM512x_RLRK | PCM512x_RBCK, 1274 master_mode); 1275 if (ret != 0) { 1276 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret); 1277 return ret; 1278 } 1279 1280 if (pcm512x->pll_out) { 1281 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1282 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1283 gpio, gpio); 1284 if (ret != 0) { 1285 dev_err(codec->dev, "Failed to enable gpio %d: %d\n", 1286 pcm512x->pll_out, ret); 1287 return ret; 1288 } 1289 1290 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1291 ret = regmap_update_bits(pcm512x->regmap, gpio, 1292 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1293 if (ret != 0) { 1294 dev_err(codec->dev, "Failed to output pll on %d: %d\n", 1295 ret, pcm512x->pll_out); 1296 return ret; 1297 } 1298 } 1299 1300 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1301 PCM512x_RQSY, PCM512x_RQSY_HALT); 1302 if (ret != 0) { 1303 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret); 1304 return ret; 1305 } 1306 1307 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1308 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1309 if (ret != 0) { 1310 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret); 1311 return ret; 1312 } 1313 1314 return 0; 1315 } 1316 1317 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1318 { 1319 struct snd_soc_codec *codec = dai->codec; 1320 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 1321 1322 pcm512x->fmt = fmt; 1323 1324 return 0; 1325 } 1326 1327 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1328 .startup = pcm512x_dai_startup, 1329 .hw_params = pcm512x_hw_params, 1330 .set_fmt = pcm512x_set_fmt, 1331 }; 1332 1333 static struct snd_soc_dai_driver pcm512x_dai = { 1334 .name = "pcm512x-hifi", 1335 .playback = { 1336 .stream_name = "Playback", 1337 .channels_min = 2, 1338 .channels_max = 2, 1339 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1340 .rate_min = 8000, 1341 .rate_max = 384000, 1342 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1343 SNDRV_PCM_FMTBIT_S24_LE | 1344 SNDRV_PCM_FMTBIT_S32_LE 1345 }, 1346 .ops = &pcm512x_dai_ops, 1347 }; 1348 1349 static struct snd_soc_codec_driver pcm512x_codec_driver = { 1350 .set_bias_level = pcm512x_set_bias_level, 1351 .idle_bias_off = true, 1352 1353 .controls = pcm512x_controls, 1354 .num_controls = ARRAY_SIZE(pcm512x_controls), 1355 .dapm_widgets = pcm512x_dapm_widgets, 1356 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1357 .dapm_routes = pcm512x_dapm_routes, 1358 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1359 }; 1360 1361 static const struct regmap_range_cfg pcm512x_range = { 1362 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1363 .range_max = PCM512x_MAX_REGISTER, 1364 .selector_reg = PCM512x_PAGE, 1365 .selector_mask = 0xff, 1366 .window_start = 0, .window_len = 0x100, 1367 }; 1368 1369 const struct regmap_config pcm512x_regmap = { 1370 .reg_bits = 8, 1371 .val_bits = 8, 1372 1373 .readable_reg = pcm512x_readable, 1374 .volatile_reg = pcm512x_volatile, 1375 1376 .ranges = &pcm512x_range, 1377 .num_ranges = 1, 1378 1379 .max_register = PCM512x_MAX_REGISTER, 1380 .reg_defaults = pcm512x_reg_defaults, 1381 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1382 .cache_type = REGCACHE_RBTREE, 1383 }; 1384 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1385 1386 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1387 { 1388 struct pcm512x_priv *pcm512x; 1389 int i, ret; 1390 1391 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1392 if (!pcm512x) 1393 return -ENOMEM; 1394 1395 dev_set_drvdata(dev, pcm512x); 1396 pcm512x->regmap = regmap; 1397 1398 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1399 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1400 1401 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1402 pcm512x->supplies); 1403 if (ret != 0) { 1404 dev_err(dev, "Failed to get supplies: %d\n", ret); 1405 return ret; 1406 } 1407 1408 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1409 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1410 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1411 1412 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1413 ret = regulator_register_notifier(pcm512x->supplies[i].consumer, 1414 &pcm512x->supply_nb[i]); 1415 if (ret != 0) { 1416 dev_err(dev, 1417 "Failed to register regulator notifier: %d\n", 1418 ret); 1419 } 1420 } 1421 1422 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1423 pcm512x->supplies); 1424 if (ret != 0) { 1425 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1426 return ret; 1427 } 1428 1429 /* Reset the device, verifying I/O in the process for I2C */ 1430 ret = regmap_write(regmap, PCM512x_RESET, 1431 PCM512x_RSTM | PCM512x_RSTR); 1432 if (ret != 0) { 1433 dev_err(dev, "Failed to reset device: %d\n", ret); 1434 goto err; 1435 } 1436 1437 ret = regmap_write(regmap, PCM512x_RESET, 0); 1438 if (ret != 0) { 1439 dev_err(dev, "Failed to reset device: %d\n", ret); 1440 goto err; 1441 } 1442 1443 pcm512x->sclk = devm_clk_get(dev, NULL); 1444 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) 1445 return -EPROBE_DEFER; 1446 if (!IS_ERR(pcm512x->sclk)) { 1447 ret = clk_prepare_enable(pcm512x->sclk); 1448 if (ret != 0) { 1449 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1450 return ret; 1451 } 1452 } 1453 1454 /* Default to standby mode */ 1455 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1456 PCM512x_RQST, PCM512x_RQST); 1457 if (ret != 0) { 1458 dev_err(dev, "Failed to request standby: %d\n", 1459 ret); 1460 goto err_clk; 1461 } 1462 1463 pm_runtime_set_active(dev); 1464 pm_runtime_enable(dev); 1465 pm_runtime_idle(dev); 1466 1467 #ifdef CONFIG_OF 1468 if (dev->of_node) { 1469 const struct device_node *np = dev->of_node; 1470 u32 val; 1471 1472 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1473 if (val > 6) { 1474 dev_err(dev, "Invalid pll-in\n"); 1475 ret = -EINVAL; 1476 goto err_clk; 1477 } 1478 pcm512x->pll_in = val; 1479 } 1480 1481 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1482 if (val > 6) { 1483 dev_err(dev, "Invalid pll-out\n"); 1484 ret = -EINVAL; 1485 goto err_clk; 1486 } 1487 pcm512x->pll_out = val; 1488 } 1489 1490 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1491 dev_err(dev, 1492 "Error: both pll-in and pll-out, or none\n"); 1493 ret = -EINVAL; 1494 goto err_clk; 1495 } 1496 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1497 dev_err(dev, "Error: pll-in == pll-out\n"); 1498 ret = -EINVAL; 1499 goto err_clk; 1500 } 1501 } 1502 #endif 1503 1504 ret = snd_soc_register_codec(dev, &pcm512x_codec_driver, 1505 &pcm512x_dai, 1); 1506 if (ret != 0) { 1507 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1508 goto err_pm; 1509 } 1510 1511 return 0; 1512 1513 err_pm: 1514 pm_runtime_disable(dev); 1515 err_clk: 1516 if (!IS_ERR(pcm512x->sclk)) 1517 clk_disable_unprepare(pcm512x->sclk); 1518 err: 1519 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1520 pcm512x->supplies); 1521 return ret; 1522 } 1523 EXPORT_SYMBOL_GPL(pcm512x_probe); 1524 1525 void pcm512x_remove(struct device *dev) 1526 { 1527 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1528 1529 snd_soc_unregister_codec(dev); 1530 pm_runtime_disable(dev); 1531 if (!IS_ERR(pcm512x->sclk)) 1532 clk_disable_unprepare(pcm512x->sclk); 1533 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1534 pcm512x->supplies); 1535 } 1536 EXPORT_SYMBOL_GPL(pcm512x_remove); 1537 1538 #ifdef CONFIG_PM 1539 static int pcm512x_suspend(struct device *dev) 1540 { 1541 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1542 int ret; 1543 1544 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1545 PCM512x_RQPD, PCM512x_RQPD); 1546 if (ret != 0) { 1547 dev_err(dev, "Failed to request power down: %d\n", ret); 1548 return ret; 1549 } 1550 1551 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1552 pcm512x->supplies); 1553 if (ret != 0) { 1554 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1555 return ret; 1556 } 1557 1558 if (!IS_ERR(pcm512x->sclk)) 1559 clk_disable_unprepare(pcm512x->sclk); 1560 1561 return 0; 1562 } 1563 1564 static int pcm512x_resume(struct device *dev) 1565 { 1566 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1567 int ret; 1568 1569 if (!IS_ERR(pcm512x->sclk)) { 1570 ret = clk_prepare_enable(pcm512x->sclk); 1571 if (ret != 0) { 1572 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1573 return ret; 1574 } 1575 } 1576 1577 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1578 pcm512x->supplies); 1579 if (ret != 0) { 1580 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1581 return ret; 1582 } 1583 1584 regcache_cache_only(pcm512x->regmap, false); 1585 ret = regcache_sync(pcm512x->regmap); 1586 if (ret != 0) { 1587 dev_err(dev, "Failed to sync cache: %d\n", ret); 1588 return ret; 1589 } 1590 1591 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1592 PCM512x_RQPD, 0); 1593 if (ret != 0) { 1594 dev_err(dev, "Failed to remove power down: %d\n", ret); 1595 return ret; 1596 } 1597 1598 return 0; 1599 } 1600 #endif 1601 1602 const struct dev_pm_ops pcm512x_pm_ops = { 1603 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1604 }; 1605 EXPORT_SYMBOL_GPL(pcm512x_pm_ops); 1606 1607 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1608 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>"); 1609 MODULE_LICENSE("GPL v2"); 1610