1 /* 2 * Driver for the PCM512x CODECs 3 * 4 * Author: Mark Brown <broonie@kernel.org> 5 * Copyright 2014 Linaro Ltd 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/clk.h> 21 #include <linux/kernel.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/gcd.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/tlv.h> 30 31 #include "pcm512x.h" 32 33 #define PCM512x_NUM_SUPPLIES 3 34 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 35 "AVDD", 36 "DVDD", 37 "CPVDD", 38 }; 39 40 struct pcm512x_priv { 41 struct regmap *regmap; 42 struct clk *sclk; 43 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 44 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 45 int fmt; 46 int pll_in; 47 int pll_out; 48 int pll_r; 49 int pll_j; 50 int pll_d; 51 int pll_p; 52 unsigned long real_pll; 53 unsigned long overclock_pll; 54 unsigned long overclock_dac; 55 unsigned long overclock_dsp; 56 int mute; 57 struct mutex mutex; 58 }; 59 60 /* 61 * We can't use the same notifier block for more than one supply and 62 * there's no way I can see to get from a callback to the caller 63 * except container_of(). 64 */ 65 #define PCM512x_REGULATOR_EVENT(n) \ 66 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 67 unsigned long event, void *data) \ 68 { \ 69 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 70 supply_nb[n]); \ 71 if (event & REGULATOR_EVENT_DISABLE) { \ 72 regcache_mark_dirty(pcm512x->regmap); \ 73 regcache_cache_only(pcm512x->regmap, true); \ 74 } \ 75 return 0; \ 76 } 77 78 PCM512x_REGULATOR_EVENT(0) 79 PCM512x_REGULATOR_EVENT(1) 80 PCM512x_REGULATOR_EVENT(2) 81 82 static const struct reg_default pcm512x_reg_defaults[] = { 83 { PCM512x_RESET, 0x00 }, 84 { PCM512x_POWER, 0x00 }, 85 { PCM512x_MUTE, 0x00 }, 86 { PCM512x_DSP, 0x00 }, 87 { PCM512x_PLL_REF, 0x00 }, 88 { PCM512x_DAC_REF, 0x00 }, 89 { PCM512x_DAC_ROUTING, 0x11 }, 90 { PCM512x_DSP_PROGRAM, 0x01 }, 91 { PCM512x_CLKDET, 0x00 }, 92 { PCM512x_AUTO_MUTE, 0x00 }, 93 { PCM512x_ERROR_DETECT, 0x00 }, 94 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 95 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 96 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 97 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 98 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 99 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 100 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 101 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 102 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 103 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 104 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 105 { PCM512x_VCOM_CTRL_1, 0x00 }, 106 { PCM512x_VCOM_CTRL_2, 0x01 }, 107 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 108 { PCM512x_MASTER_MODE, 0x7c }, 109 { PCM512x_GPIO_DACIN, 0x00 }, 110 { PCM512x_GPIO_PLLIN, 0x00 }, 111 { PCM512x_SYNCHRONIZE, 0x10 }, 112 { PCM512x_PLL_COEFF_0, 0x00 }, 113 { PCM512x_PLL_COEFF_1, 0x00 }, 114 { PCM512x_PLL_COEFF_2, 0x00 }, 115 { PCM512x_PLL_COEFF_3, 0x00 }, 116 { PCM512x_PLL_COEFF_4, 0x00 }, 117 { PCM512x_DSP_CLKDIV, 0x00 }, 118 { PCM512x_DAC_CLKDIV, 0x00 }, 119 { PCM512x_NCP_CLKDIV, 0x00 }, 120 { PCM512x_OSR_CLKDIV, 0x00 }, 121 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 122 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 123 { PCM512x_FS_SPEED_MODE, 0x00 }, 124 { PCM512x_IDAC_1, 0x01 }, 125 { PCM512x_IDAC_2, 0x00 }, 126 }; 127 128 static bool pcm512x_readable(struct device *dev, unsigned int reg) 129 { 130 switch (reg) { 131 case PCM512x_RESET: 132 case PCM512x_POWER: 133 case PCM512x_MUTE: 134 case PCM512x_PLL_EN: 135 case PCM512x_SPI_MISO_FUNCTION: 136 case PCM512x_DSP: 137 case PCM512x_GPIO_EN: 138 case PCM512x_BCLK_LRCLK_CFG: 139 case PCM512x_DSP_GPIO_INPUT: 140 case PCM512x_MASTER_MODE: 141 case PCM512x_PLL_REF: 142 case PCM512x_DAC_REF: 143 case PCM512x_GPIO_DACIN: 144 case PCM512x_GPIO_PLLIN: 145 case PCM512x_SYNCHRONIZE: 146 case PCM512x_PLL_COEFF_0: 147 case PCM512x_PLL_COEFF_1: 148 case PCM512x_PLL_COEFF_2: 149 case PCM512x_PLL_COEFF_3: 150 case PCM512x_PLL_COEFF_4: 151 case PCM512x_DSP_CLKDIV: 152 case PCM512x_DAC_CLKDIV: 153 case PCM512x_NCP_CLKDIV: 154 case PCM512x_OSR_CLKDIV: 155 case PCM512x_MASTER_CLKDIV_1: 156 case PCM512x_MASTER_CLKDIV_2: 157 case PCM512x_FS_SPEED_MODE: 158 case PCM512x_IDAC_1: 159 case PCM512x_IDAC_2: 160 case PCM512x_ERROR_DETECT: 161 case PCM512x_I2S_1: 162 case PCM512x_I2S_2: 163 case PCM512x_DAC_ROUTING: 164 case PCM512x_DSP_PROGRAM: 165 case PCM512x_CLKDET: 166 case PCM512x_AUTO_MUTE: 167 case PCM512x_DIGITAL_VOLUME_1: 168 case PCM512x_DIGITAL_VOLUME_2: 169 case PCM512x_DIGITAL_VOLUME_3: 170 case PCM512x_DIGITAL_MUTE_1: 171 case PCM512x_DIGITAL_MUTE_2: 172 case PCM512x_DIGITAL_MUTE_3: 173 case PCM512x_GPIO_OUTPUT_1: 174 case PCM512x_GPIO_OUTPUT_2: 175 case PCM512x_GPIO_OUTPUT_3: 176 case PCM512x_GPIO_OUTPUT_4: 177 case PCM512x_GPIO_OUTPUT_5: 178 case PCM512x_GPIO_OUTPUT_6: 179 case PCM512x_GPIO_CONTROL_1: 180 case PCM512x_GPIO_CONTROL_2: 181 case PCM512x_OVERFLOW: 182 case PCM512x_RATE_DET_1: 183 case PCM512x_RATE_DET_2: 184 case PCM512x_RATE_DET_3: 185 case PCM512x_RATE_DET_4: 186 case PCM512x_CLOCK_STATUS: 187 case PCM512x_ANALOG_MUTE_DET: 188 case PCM512x_GPIN: 189 case PCM512x_DIGITAL_MUTE_DET: 190 case PCM512x_OUTPUT_AMPLITUDE: 191 case PCM512x_ANALOG_GAIN_CTRL: 192 case PCM512x_UNDERVOLTAGE_PROT: 193 case PCM512x_ANALOG_MUTE_CTRL: 194 case PCM512x_ANALOG_GAIN_BOOST: 195 case PCM512x_VCOM_CTRL_1: 196 case PCM512x_VCOM_CTRL_2: 197 case PCM512x_CRAM_CTRL: 198 case PCM512x_FLEX_A: 199 case PCM512x_FLEX_B: 200 return true; 201 default: 202 /* There are 256 raw register addresses */ 203 return reg < 0xff; 204 } 205 } 206 207 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 208 { 209 switch (reg) { 210 case PCM512x_PLL_EN: 211 case PCM512x_OVERFLOW: 212 case PCM512x_RATE_DET_1: 213 case PCM512x_RATE_DET_2: 214 case PCM512x_RATE_DET_3: 215 case PCM512x_RATE_DET_4: 216 case PCM512x_CLOCK_STATUS: 217 case PCM512x_ANALOG_MUTE_DET: 218 case PCM512x_GPIN: 219 case PCM512x_DIGITAL_MUTE_DET: 220 case PCM512x_CRAM_CTRL: 221 return true; 222 default: 223 /* There are 256 raw register addresses */ 224 return reg < 0xff; 225 } 226 } 227 228 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 229 struct snd_ctl_elem_value *ucontrol) 230 { 231 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 232 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 233 234 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 235 return 0; 236 } 237 238 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 239 struct snd_ctl_elem_value *ucontrol) 240 { 241 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 242 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 243 244 switch (snd_soc_component_get_bias_level(component)) { 245 case SND_SOC_BIAS_OFF: 246 case SND_SOC_BIAS_STANDBY: 247 break; 248 default: 249 return -EBUSY; 250 } 251 252 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 253 return 0; 254 } 255 256 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 257 struct snd_ctl_elem_value *ucontrol) 258 { 259 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 260 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 261 262 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 263 return 0; 264 } 265 266 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 267 struct snd_ctl_elem_value *ucontrol) 268 { 269 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 270 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 271 272 switch (snd_soc_component_get_bias_level(component)) { 273 case SND_SOC_BIAS_OFF: 274 case SND_SOC_BIAS_STANDBY: 275 break; 276 default: 277 return -EBUSY; 278 } 279 280 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 281 return 0; 282 } 283 284 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 285 struct snd_ctl_elem_value *ucontrol) 286 { 287 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 288 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 289 290 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 291 return 0; 292 } 293 294 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 298 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 299 300 switch (snd_soc_component_get_bias_level(component)) { 301 case SND_SOC_BIAS_OFF: 302 case SND_SOC_BIAS_STANDBY: 303 break; 304 default: 305 return -EBUSY; 306 } 307 308 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 309 return 0; 310 } 311 312 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 313 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 314 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 315 316 static const char * const pcm512x_dsp_program_texts[] = { 317 "FIR interpolation with de-emphasis", 318 "Low latency IIR with de-emphasis", 319 "High attenuation with de-emphasis", 320 "Fixed process flow", 321 "Ringing-less low latency FIR", 322 }; 323 324 static const unsigned int pcm512x_dsp_program_values[] = { 325 1, 326 2, 327 3, 328 5, 329 7, 330 }; 331 332 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 333 PCM512x_DSP_PROGRAM, 0, 0x1f, 334 pcm512x_dsp_program_texts, 335 pcm512x_dsp_program_values); 336 337 static const char * const pcm512x_clk_missing_text[] = { 338 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 339 }; 340 341 static const struct soc_enum pcm512x_clk_missing = 342 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 343 344 static const char * const pcm512x_autom_text[] = { 345 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 346 }; 347 348 static const struct soc_enum pcm512x_autom_l = 349 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 350 pcm512x_autom_text); 351 352 static const struct soc_enum pcm512x_autom_r = 353 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 354 pcm512x_autom_text); 355 356 static const char * const pcm512x_ramp_rate_text[] = { 357 "1 sample/update", "2 samples/update", "4 samples/update", 358 "Immediate" 359 }; 360 361 static const struct soc_enum pcm512x_vndf = 362 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 363 pcm512x_ramp_rate_text); 364 365 static const struct soc_enum pcm512x_vnuf = 366 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 367 pcm512x_ramp_rate_text); 368 369 static const struct soc_enum pcm512x_vedf = 370 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 371 pcm512x_ramp_rate_text); 372 373 static const char * const pcm512x_ramp_step_text[] = { 374 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 375 }; 376 377 static const struct soc_enum pcm512x_vnds = 378 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 379 pcm512x_ramp_step_text); 380 381 static const struct soc_enum pcm512x_vnus = 382 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 383 pcm512x_ramp_step_text); 384 385 static const struct soc_enum pcm512x_veds = 386 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 387 pcm512x_ramp_step_text); 388 389 static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) 390 { 391 return regmap_update_bits( 392 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, 393 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) 394 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); 395 } 396 397 static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, 398 struct snd_ctl_elem_value *ucontrol) 399 { 400 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 401 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 402 403 mutex_lock(&pcm512x->mutex); 404 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); 405 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); 406 mutex_unlock(&pcm512x->mutex); 407 408 return 0; 409 } 410 411 static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, 412 struct snd_ctl_elem_value *ucontrol) 413 { 414 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 415 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 416 int ret, changed = 0; 417 418 mutex_lock(&pcm512x->mutex); 419 420 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { 421 pcm512x->mute ^= 0x4; 422 changed = 1; 423 } 424 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { 425 pcm512x->mute ^= 0x2; 426 changed = 1; 427 } 428 429 if (changed) { 430 ret = pcm512x_update_mute(pcm512x); 431 if (ret != 0) { 432 dev_err(component->dev, 433 "Failed to update digital mute: %d\n", ret); 434 mutex_unlock(&pcm512x->mutex); 435 return ret; 436 } 437 } 438 439 mutex_unlock(&pcm512x->mutex); 440 441 return changed; 442 } 443 444 static const struct snd_kcontrol_new pcm512x_controls[] = { 445 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 446 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 447 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 448 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 449 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 450 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 451 { 452 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 453 .name = "Digital Playback Switch", 454 .index = 0, 455 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 456 .info = snd_ctl_boolean_stereo_info, 457 .get = pcm512x_digital_playback_switch_get, 458 .put = pcm512x_digital_playback_switch_put 459 }, 460 461 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 462 SOC_ENUM("DSP Program", pcm512x_dsp_program), 463 464 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 465 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 466 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 467 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 468 PCM512x_ACTL_SHIFT, 1, 0), 469 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 470 PCM512x_AMRE_SHIFT, 1, 0), 471 472 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 473 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 474 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 475 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 476 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 477 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 478 479 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 480 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 481 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 482 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 483 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 484 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 485 }; 486 487 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 488 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 489 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 490 491 SND_SOC_DAPM_OUTPUT("OUTL"), 492 SND_SOC_DAPM_OUTPUT("OUTR"), 493 }; 494 495 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 496 { "DACL", NULL, "Playback" }, 497 { "DACR", NULL, "Playback" }, 498 499 { "OUTL", NULL, "DACL" }, 500 { "OUTR", NULL, "DACR" }, 501 }; 502 503 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 504 { 505 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 506 } 507 508 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 509 { 510 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 511 } 512 513 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 514 unsigned long rate) 515 { 516 return rate + rate * pcm512x->overclock_dac / 100; 517 } 518 519 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 520 { 521 if (!pcm512x->pll_out) 522 return 25000000; 523 return pcm512x_pll_max(pcm512x); 524 } 525 526 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 527 unsigned long dac_rate) 528 { 529 /* 530 * If the DAC is not actually overclocked, use the good old 531 * NCP target rate... 532 */ 533 if (dac_rate <= 6144000) 534 return 1536000; 535 /* 536 * ...but if the DAC is in fact overclocked, bump the NCP target 537 * rate to get the recommended dividers even when overclocking. 538 */ 539 return pcm512x_dac_max(pcm512x, 1536000); 540 } 541 542 static const u32 pcm512x_dai_rates[] = { 543 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 544 88200, 96000, 176400, 192000, 384000, 545 }; 546 547 static const struct snd_pcm_hw_constraint_list constraints_slave = { 548 .count = ARRAY_SIZE(pcm512x_dai_rates), 549 .list = pcm512x_dai_rates, 550 }; 551 552 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 553 struct snd_pcm_hw_rule *rule) 554 { 555 struct pcm512x_priv *pcm512x = rule->private; 556 struct snd_interval ranges[2]; 557 int frame_size; 558 559 frame_size = snd_soc_params_to_frame_size(params); 560 if (frame_size < 0) 561 return frame_size; 562 563 switch (frame_size) { 564 case 32: 565 /* No hole when the frame size is 32. */ 566 return 0; 567 case 48: 568 case 64: 569 /* There is only one hole in the range of supported 570 * rates, but it moves with the frame size. 571 */ 572 memset(ranges, 0, sizeof(ranges)); 573 ranges[0].min = 8000; 574 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 575 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 576 ranges[1].max = 384000; 577 break; 578 default: 579 return -EINVAL; 580 } 581 582 return snd_interval_ranges(hw_param_interval(params, rule->var), 583 ARRAY_SIZE(ranges), ranges, 0); 584 } 585 586 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 587 struct snd_soc_dai *dai) 588 { 589 struct snd_soc_component *component = dai->component; 590 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 591 struct device *dev = dai->dev; 592 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 593 struct snd_ratnum *rats_no_pll; 594 595 if (IS_ERR(pcm512x->sclk)) { 596 dev_err(dev, "Need SCLK for master mode: %ld\n", 597 PTR_ERR(pcm512x->sclk)); 598 return PTR_ERR(pcm512x->sclk); 599 } 600 601 if (pcm512x->pll_out) 602 return snd_pcm_hw_rule_add(substream->runtime, 0, 603 SNDRV_PCM_HW_PARAM_RATE, 604 pcm512x_hw_rule_rate, 605 pcm512x, 606 SNDRV_PCM_HW_PARAM_FRAME_BITS, 607 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 608 609 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 610 GFP_KERNEL); 611 if (!constraints_no_pll) 612 return -ENOMEM; 613 constraints_no_pll->nrats = 1; 614 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 615 if (!rats_no_pll) 616 return -ENOMEM; 617 constraints_no_pll->rats = rats_no_pll; 618 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 619 rats_no_pll->den_min = 1; 620 rats_no_pll->den_max = 128; 621 rats_no_pll->den_step = 1; 622 623 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 624 SNDRV_PCM_HW_PARAM_RATE, 625 constraints_no_pll); 626 } 627 628 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 629 struct snd_soc_dai *dai) 630 { 631 struct snd_soc_component *component = dai->component; 632 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 633 struct device *dev = dai->dev; 634 struct regmap *regmap = pcm512x->regmap; 635 636 if (IS_ERR(pcm512x->sclk)) { 637 dev_info(dev, "No SCLK, using BCLK: %ld\n", 638 PTR_ERR(pcm512x->sclk)); 639 640 /* Disable reporting of missing SCLK as an error */ 641 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 642 PCM512x_IDCH, PCM512x_IDCH); 643 644 /* Switch PLL input to BCLK */ 645 regmap_update_bits(regmap, PCM512x_PLL_REF, 646 PCM512x_SREF, PCM512x_SREF_BCK); 647 } 648 649 return snd_pcm_hw_constraint_list(substream->runtime, 0, 650 SNDRV_PCM_HW_PARAM_RATE, 651 &constraints_slave); 652 } 653 654 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 655 struct snd_soc_dai *dai) 656 { 657 struct snd_soc_component *component = dai->component; 658 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 659 660 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 661 case SND_SOC_DAIFMT_CBM_CFM: 662 case SND_SOC_DAIFMT_CBM_CFS: 663 return pcm512x_dai_startup_master(substream, dai); 664 665 case SND_SOC_DAIFMT_CBS_CFS: 666 return pcm512x_dai_startup_slave(substream, dai); 667 668 default: 669 return -EINVAL; 670 } 671 } 672 673 static int pcm512x_set_bias_level(struct snd_soc_component *component, 674 enum snd_soc_bias_level level) 675 { 676 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev); 677 int ret; 678 679 switch (level) { 680 case SND_SOC_BIAS_ON: 681 case SND_SOC_BIAS_PREPARE: 682 break; 683 684 case SND_SOC_BIAS_STANDBY: 685 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 686 PCM512x_RQST, 0); 687 if (ret != 0) { 688 dev_err(component->dev, "Failed to remove standby: %d\n", 689 ret); 690 return ret; 691 } 692 break; 693 694 case SND_SOC_BIAS_OFF: 695 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 696 PCM512x_RQST, PCM512x_RQST); 697 if (ret != 0) { 698 dev_err(component->dev, "Failed to request standby: %d\n", 699 ret); 700 return ret; 701 } 702 break; 703 } 704 705 return 0; 706 } 707 708 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 709 unsigned long bclk_rate) 710 { 711 struct device *dev = dai->dev; 712 struct snd_soc_component *component = dai->component; 713 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 714 unsigned long sck_rate; 715 int pow2; 716 717 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 718 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 719 720 /* select sck_rate as a multiple of bclk_rate but still with 721 * as many factors of 2 as possible, as that makes it easier 722 * to find a fast DAC rate 723 */ 724 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 725 for (; pow2; pow2 >>= 1) { 726 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 727 bclk_rate * pow2); 728 if (sck_rate >= 16000000) 729 break; 730 } 731 if (!pow2) { 732 dev_err(dev, "Impossible to generate a suitable SCK\n"); 733 return 0; 734 } 735 736 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 737 return sck_rate; 738 } 739 740 /* pll_rate = pllin_rate * R * J.D / P 741 * 1 <= R <= 16 742 * 1 <= J <= 63 743 * 0 <= D <= 9999 744 * 1 <= P <= 15 745 * 64 MHz <= pll_rate <= 100 MHz 746 * if D == 0 747 * 1 MHz <= pllin_rate / P <= 20 MHz 748 * else if D > 0 749 * 6.667 MHz <= pllin_rate / P <= 20 MHz 750 * 4 <= J <= 11 751 * R = 1 752 */ 753 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 754 unsigned long pllin_rate, 755 unsigned long pll_rate) 756 { 757 struct device *dev = dai->dev; 758 struct snd_soc_component *component = dai->component; 759 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 760 unsigned long common; 761 int R, J, D, P; 762 unsigned long K; /* 10000 * J.D */ 763 unsigned long num; 764 unsigned long den; 765 766 common = gcd(pll_rate, pllin_rate); 767 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 768 pll_rate, pllin_rate, common); 769 num = pll_rate / common; 770 den = pllin_rate / common; 771 772 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 773 if (pllin_rate / den > 20000000 && num < 8) { 774 num *= DIV_ROUND_UP(pllin_rate / den, 20000000); 775 den *= DIV_ROUND_UP(pllin_rate / den, 20000000); 776 } 777 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 778 779 P = den; 780 if (den <= 15 && num <= 16 * 63 781 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 782 /* Try the case with D = 0 */ 783 D = 0; 784 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 785 for (R = 16; R; R--) { 786 if (num % R) 787 continue; 788 J = num / R; 789 if (J == 0 || J > 63) 790 continue; 791 792 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 793 pcm512x->real_pll = pll_rate; 794 goto done; 795 } 796 /* no luck */ 797 } 798 799 R = 1; 800 801 if (num > 0xffffffffUL / 10000) 802 goto fallback; 803 804 /* Try to find an exact pll_rate using the D > 0 case */ 805 common = gcd(10000 * num, den); 806 num = 10000 * num / common; 807 den /= common; 808 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 809 810 for (P = den; P <= 15; P++) { 811 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 812 continue; 813 if (num * P % den) 814 continue; 815 K = num * P / den; 816 /* J == 12 is ok if D == 0 */ 817 if (K < 40000 || K > 120000) 818 continue; 819 820 J = K / 10000; 821 D = K % 10000; 822 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 823 pcm512x->real_pll = pll_rate; 824 goto done; 825 } 826 827 /* Fall back to an approximate pll_rate */ 828 829 fallback: 830 /* find smallest possible P */ 831 P = DIV_ROUND_UP(pllin_rate, 20000000); 832 if (!P) 833 P = 1; 834 else if (P > 15) { 835 dev_err(dev, "Need a slower clock as pll-input\n"); 836 return -EINVAL; 837 } 838 if (pllin_rate / P < 6667000) { 839 dev_err(dev, "Need a faster clock as pll-input\n"); 840 return -EINVAL; 841 } 842 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 843 if (K < 40000) 844 K = 40000; 845 /* J == 12 is ok if D == 0 */ 846 if (K > 120000) 847 K = 120000; 848 J = K / 10000; 849 D = K % 10000; 850 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 851 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 852 853 done: 854 pcm512x->pll_r = R; 855 pcm512x->pll_j = J; 856 pcm512x->pll_d = D; 857 pcm512x->pll_p = P; 858 return 0; 859 } 860 861 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 862 unsigned long osr_rate, 863 unsigned long pllin_rate) 864 { 865 struct snd_soc_component *component = dai->component; 866 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 867 unsigned long dac_rate; 868 869 if (!pcm512x->pll_out) 870 return 0; /* no PLL to bypass, force SCK as DAC input */ 871 872 if (pllin_rate % osr_rate) 873 return 0; /* futile, quit early */ 874 875 /* run DAC no faster than 6144000 Hz */ 876 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 877 dac_rate; 878 dac_rate -= osr_rate) { 879 880 if (pllin_rate / dac_rate > 128) 881 return 0; /* DAC divider would be too big */ 882 883 if (!(pllin_rate % dac_rate)) 884 return dac_rate; 885 886 dac_rate -= osr_rate; 887 } 888 889 return 0; 890 } 891 892 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 893 struct snd_pcm_hw_params *params) 894 { 895 struct device *dev = dai->dev; 896 struct snd_soc_component *component = dai->component; 897 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 898 unsigned long pllin_rate = 0; 899 unsigned long pll_rate; 900 unsigned long sck_rate; 901 unsigned long mck_rate; 902 unsigned long bclk_rate; 903 unsigned long sample_rate; 904 unsigned long osr_rate; 905 unsigned long dacsrc_rate; 906 int bclk_div; 907 int lrclk_div; 908 int dsp_div; 909 int dac_div; 910 unsigned long dac_rate; 911 int ncp_div; 912 int osr_div; 913 int ret; 914 int idac; 915 int fssp; 916 int gpio; 917 918 lrclk_div = snd_soc_params_to_frame_size(params); 919 if (lrclk_div == 0) { 920 dev_err(dev, "No LRCLK?\n"); 921 return -EINVAL; 922 } 923 924 if (!pcm512x->pll_out) { 925 sck_rate = clk_get_rate(pcm512x->sclk); 926 bclk_div = params->rate_den * 64 / lrclk_div; 927 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); 928 929 mck_rate = sck_rate; 930 } else { 931 ret = snd_soc_params_to_bclk(params); 932 if (ret < 0) { 933 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 934 return ret; 935 } 936 if (ret == 0) { 937 dev_err(dev, "No BCLK?\n"); 938 return -EINVAL; 939 } 940 bclk_rate = ret; 941 942 pllin_rate = clk_get_rate(pcm512x->sclk); 943 944 sck_rate = pcm512x_find_sck(dai, bclk_rate); 945 if (!sck_rate) 946 return -EINVAL; 947 pll_rate = 4 * sck_rate; 948 949 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 950 if (ret != 0) 951 return ret; 952 953 ret = regmap_write(pcm512x->regmap, 954 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 955 if (ret != 0) { 956 dev_err(dev, "Failed to write PLL P: %d\n", ret); 957 return ret; 958 } 959 960 ret = regmap_write(pcm512x->regmap, 961 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 962 if (ret != 0) { 963 dev_err(dev, "Failed to write PLL J: %d\n", ret); 964 return ret; 965 } 966 967 ret = regmap_write(pcm512x->regmap, 968 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 969 if (ret != 0) { 970 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 971 return ret; 972 } 973 974 ret = regmap_write(pcm512x->regmap, 975 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 976 if (ret != 0) { 977 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 978 return ret; 979 } 980 981 ret = regmap_write(pcm512x->regmap, 982 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 983 if (ret != 0) { 984 dev_err(dev, "Failed to write PLL R: %d\n", ret); 985 return ret; 986 } 987 988 mck_rate = pcm512x->real_pll; 989 990 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 991 } 992 993 if (bclk_div > 128) { 994 dev_err(dev, "Failed to find BCLK divider\n"); 995 return -EINVAL; 996 } 997 998 /* the actual rate */ 999 sample_rate = sck_rate / bclk_div / lrclk_div; 1000 osr_rate = 16 * sample_rate; 1001 1002 /* run DSP no faster than 50 MHz */ 1003 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 1004 1005 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 1006 if (dac_rate) { 1007 /* the desired clock rate is "compatible" with the pll input 1008 * clock, so use that clock as dac input instead of the pll 1009 * output clock since the pll will introduce jitter and thus 1010 * noise. 1011 */ 1012 dev_dbg(dev, "using pll input as dac input\n"); 1013 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1014 PCM512x_SDAC, PCM512x_SDAC_GPIO); 1015 if (ret != 0) { 1016 dev_err(component->dev, 1017 "Failed to set gpio as dacref: %d\n", ret); 1018 return ret; 1019 } 1020 1021 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1022 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 1023 PCM512x_GREF, gpio); 1024 if (ret != 0) { 1025 dev_err(component->dev, 1026 "Failed to set gpio %d as dacin: %d\n", 1027 pcm512x->pll_in, ret); 1028 return ret; 1029 } 1030 1031 dacsrc_rate = pllin_rate; 1032 } else { 1033 /* run DAC no faster than 6144000 Hz */ 1034 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 1035 / osr_rate; 1036 unsigned long sck_mul = sck_rate / osr_rate; 1037 1038 for (; dac_mul; dac_mul--) { 1039 if (!(sck_mul % dac_mul)) 1040 break; 1041 } 1042 if (!dac_mul) { 1043 dev_err(dev, "Failed to find DAC rate\n"); 1044 return -EINVAL; 1045 } 1046 1047 dac_rate = dac_mul * osr_rate; 1048 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 1049 dac_rate, sample_rate); 1050 1051 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1052 PCM512x_SDAC, PCM512x_SDAC_SCK); 1053 if (ret != 0) { 1054 dev_err(component->dev, 1055 "Failed to set sck as dacref: %d\n", ret); 1056 return ret; 1057 } 1058 1059 dacsrc_rate = sck_rate; 1060 } 1061 1062 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1063 if (osr_div > 128) { 1064 dev_err(dev, "Failed to find OSR divider\n"); 1065 return -EINVAL; 1066 } 1067 1068 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1069 if (dac_div > 128) { 1070 dev_err(dev, "Failed to find DAC divider\n"); 1071 return -EINVAL; 1072 } 1073 dac_rate = dacsrc_rate / dac_div; 1074 1075 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1076 pcm512x_ncp_target(pcm512x, dac_rate)); 1077 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1078 /* run NCP no faster than 2048000 Hz, but why? */ 1079 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1080 if (ncp_div > 128) { 1081 dev_err(dev, "Failed to find NCP divider\n"); 1082 return -EINVAL; 1083 } 1084 } 1085 1086 idac = mck_rate / (dsp_div * sample_rate); 1087 1088 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1089 if (ret != 0) { 1090 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1091 return ret; 1092 } 1093 1094 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1095 if (ret != 0) { 1096 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1097 return ret; 1098 } 1099 1100 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1101 if (ret != 0) { 1102 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1103 return ret; 1104 } 1105 1106 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1107 if (ret != 0) { 1108 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1109 return ret; 1110 } 1111 1112 ret = regmap_write(pcm512x->regmap, 1113 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1114 if (ret != 0) { 1115 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1116 return ret; 1117 } 1118 1119 ret = regmap_write(pcm512x->regmap, 1120 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1121 if (ret != 0) { 1122 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1123 return ret; 1124 } 1125 1126 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1127 if (ret != 0) { 1128 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1129 return ret; 1130 } 1131 1132 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1133 if (ret != 0) { 1134 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1135 return ret; 1136 } 1137 1138 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1139 fssp = PCM512x_FSSP_48KHZ; 1140 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1141 fssp = PCM512x_FSSP_96KHZ; 1142 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1143 fssp = PCM512x_FSSP_192KHZ; 1144 else 1145 fssp = PCM512x_FSSP_384KHZ; 1146 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1147 PCM512x_FSSP, fssp); 1148 if (ret != 0) { 1149 dev_err(component->dev, "Failed to set fs speed: %d\n", ret); 1150 return ret; 1151 } 1152 1153 dev_dbg(component->dev, "DSP divider %d\n", dsp_div); 1154 dev_dbg(component->dev, "DAC divider %d\n", dac_div); 1155 dev_dbg(component->dev, "NCP divider %d\n", ncp_div); 1156 dev_dbg(component->dev, "OSR divider %d\n", osr_div); 1157 dev_dbg(component->dev, "BCK divider %d\n", bclk_div); 1158 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div); 1159 dev_dbg(component->dev, "IDAC %d\n", idac); 1160 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp); 1161 1162 return 0; 1163 } 1164 1165 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1166 struct snd_pcm_hw_params *params, 1167 struct snd_soc_dai *dai) 1168 { 1169 struct snd_soc_component *component = dai->component; 1170 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1171 int alen; 1172 int gpio; 1173 int clock_output; 1174 int master_mode; 1175 int ret; 1176 1177 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n", 1178 params_rate(params), 1179 params_channels(params)); 1180 1181 switch (params_width(params)) { 1182 case 16: 1183 alen = PCM512x_ALEN_16; 1184 break; 1185 case 20: 1186 alen = PCM512x_ALEN_20; 1187 break; 1188 case 24: 1189 alen = PCM512x_ALEN_24; 1190 break; 1191 case 32: 1192 alen = PCM512x_ALEN_32; 1193 break; 1194 default: 1195 dev_err(component->dev, "Bad frame size: %d\n", 1196 params_width(params)); 1197 return -EINVAL; 1198 } 1199 1200 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1201 case SND_SOC_DAIFMT_CBS_CFS: 1202 ret = regmap_update_bits(pcm512x->regmap, 1203 PCM512x_BCLK_LRCLK_CFG, 1204 PCM512x_BCKP 1205 | PCM512x_BCKO | PCM512x_LRKO, 1206 0); 1207 if (ret != 0) { 1208 dev_err(component->dev, 1209 "Failed to enable slave mode: %d\n", ret); 1210 return ret; 1211 } 1212 1213 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1214 PCM512x_DCAS, 0); 1215 if (ret != 0) { 1216 dev_err(component->dev, 1217 "Failed to enable clock divider autoset: %d\n", 1218 ret); 1219 return ret; 1220 } 1221 return 0; 1222 case SND_SOC_DAIFMT_CBM_CFM: 1223 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1224 master_mode = PCM512x_RLRK | PCM512x_RBCK; 1225 break; 1226 case SND_SOC_DAIFMT_CBM_CFS: 1227 clock_output = PCM512x_BCKO; 1228 master_mode = PCM512x_RBCK; 1229 break; 1230 default: 1231 return -EINVAL; 1232 } 1233 1234 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1235 PCM512x_ALEN, alen); 1236 if (ret != 0) { 1237 dev_err(component->dev, "Failed to set frame size: %d\n", ret); 1238 return ret; 1239 } 1240 1241 if (pcm512x->pll_out) { 1242 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1243 if (ret != 0) { 1244 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret); 1245 return ret; 1246 } 1247 1248 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1249 if (ret != 0) { 1250 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret); 1251 return ret; 1252 } 1253 1254 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1255 PCM512x_IDFS | PCM512x_IDBK 1256 | PCM512x_IDSK | PCM512x_IDCH 1257 | PCM512x_IDCM | PCM512x_DCAS 1258 | PCM512x_IPLK, 1259 PCM512x_IDFS | PCM512x_IDBK 1260 | PCM512x_IDSK | PCM512x_IDCH 1261 | PCM512x_DCAS); 1262 if (ret != 0) { 1263 dev_err(component->dev, 1264 "Failed to ignore auto-clock failures: %d\n", 1265 ret); 1266 return ret; 1267 } 1268 } else { 1269 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1270 PCM512x_IDFS | PCM512x_IDBK 1271 | PCM512x_IDSK | PCM512x_IDCH 1272 | PCM512x_IDCM | PCM512x_DCAS 1273 | PCM512x_IPLK, 1274 PCM512x_IDFS | PCM512x_IDBK 1275 | PCM512x_IDSK | PCM512x_IDCH 1276 | PCM512x_DCAS | PCM512x_IPLK); 1277 if (ret != 0) { 1278 dev_err(component->dev, 1279 "Failed to ignore auto-clock failures: %d\n", 1280 ret); 1281 return ret; 1282 } 1283 1284 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1285 PCM512x_PLLE, 0); 1286 if (ret != 0) { 1287 dev_err(component->dev, "Failed to disable pll: %d\n", ret); 1288 return ret; 1289 } 1290 } 1291 1292 ret = pcm512x_set_dividers(dai, params); 1293 if (ret != 0) 1294 return ret; 1295 1296 if (pcm512x->pll_out) { 1297 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1298 PCM512x_SREF, PCM512x_SREF_GPIO); 1299 if (ret != 0) { 1300 dev_err(component->dev, 1301 "Failed to set gpio as pllref: %d\n", ret); 1302 return ret; 1303 } 1304 1305 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1306 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1307 PCM512x_GREF, gpio); 1308 if (ret != 0) { 1309 dev_err(component->dev, 1310 "Failed to set gpio %d as pllin: %d\n", 1311 pcm512x->pll_in, ret); 1312 return ret; 1313 } 1314 1315 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1316 PCM512x_PLLE, PCM512x_PLLE); 1317 if (ret != 0) { 1318 dev_err(component->dev, "Failed to enable pll: %d\n", ret); 1319 return ret; 1320 } 1321 } 1322 1323 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1324 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1325 clock_output); 1326 if (ret != 0) { 1327 dev_err(component->dev, "Failed to enable clock output: %d\n", ret); 1328 return ret; 1329 } 1330 1331 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1332 PCM512x_RLRK | PCM512x_RBCK, 1333 master_mode); 1334 if (ret != 0) { 1335 dev_err(component->dev, "Failed to enable master mode: %d\n", ret); 1336 return ret; 1337 } 1338 1339 if (pcm512x->pll_out) { 1340 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1341 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1342 gpio, gpio); 1343 if (ret != 0) { 1344 dev_err(component->dev, "Failed to enable gpio %d: %d\n", 1345 pcm512x->pll_out, ret); 1346 return ret; 1347 } 1348 1349 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1350 ret = regmap_update_bits(pcm512x->regmap, gpio, 1351 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1352 if (ret != 0) { 1353 dev_err(component->dev, "Failed to output pll on %d: %d\n", 1354 ret, pcm512x->pll_out); 1355 return ret; 1356 } 1357 } 1358 1359 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1360 PCM512x_RQSY, PCM512x_RQSY_HALT); 1361 if (ret != 0) { 1362 dev_err(component->dev, "Failed to halt clocks: %d\n", ret); 1363 return ret; 1364 } 1365 1366 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1367 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1368 if (ret != 0) { 1369 dev_err(component->dev, "Failed to resume clocks: %d\n", ret); 1370 return ret; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1377 { 1378 struct snd_soc_component *component = dai->component; 1379 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1380 1381 pcm512x->fmt = fmt; 1382 1383 return 0; 1384 } 1385 1386 static int pcm512x_digital_mute(struct snd_soc_dai *dai, int mute) 1387 { 1388 struct snd_soc_component *component = dai->component; 1389 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1390 int ret; 1391 unsigned int mute_det; 1392 1393 mutex_lock(&pcm512x->mutex); 1394 1395 if (mute) { 1396 pcm512x->mute |= 0x1; 1397 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE, 1398 PCM512x_RQML | PCM512x_RQMR, 1399 PCM512x_RQML | PCM512x_RQMR); 1400 if (ret != 0) { 1401 dev_err(component->dev, 1402 "Failed to set digital mute: %d\n", ret); 1403 mutex_unlock(&pcm512x->mutex); 1404 return ret; 1405 } 1406 1407 regmap_read_poll_timeout(pcm512x->regmap, 1408 PCM512x_ANALOG_MUTE_DET, 1409 mute_det, (mute_det & 0x3) == 0, 1410 200, 10000); 1411 1412 mutex_unlock(&pcm512x->mutex); 1413 } else { 1414 pcm512x->mute &= ~0x1; 1415 ret = pcm512x_update_mute(pcm512x); 1416 if (ret != 0) { 1417 dev_err(component->dev, 1418 "Failed to update digital mute: %d\n", ret); 1419 mutex_unlock(&pcm512x->mutex); 1420 return ret; 1421 } 1422 1423 regmap_read_poll_timeout(pcm512x->regmap, 1424 PCM512x_ANALOG_MUTE_DET, 1425 mute_det, 1426 (mute_det & 0x3) 1427 == ((~pcm512x->mute >> 1) & 0x3), 1428 200, 10000); 1429 } 1430 1431 mutex_unlock(&pcm512x->mutex); 1432 1433 return 0; 1434 } 1435 1436 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1437 .startup = pcm512x_dai_startup, 1438 .hw_params = pcm512x_hw_params, 1439 .set_fmt = pcm512x_set_fmt, 1440 .digital_mute = pcm512x_digital_mute, 1441 }; 1442 1443 static struct snd_soc_dai_driver pcm512x_dai = { 1444 .name = "pcm512x-hifi", 1445 .playback = { 1446 .stream_name = "Playback", 1447 .channels_min = 2, 1448 .channels_max = 2, 1449 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1450 .rate_min = 8000, 1451 .rate_max = 384000, 1452 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1453 SNDRV_PCM_FMTBIT_S24_LE | 1454 SNDRV_PCM_FMTBIT_S32_LE 1455 }, 1456 .ops = &pcm512x_dai_ops, 1457 }; 1458 1459 static const struct snd_soc_component_driver pcm512x_component_driver = { 1460 .set_bias_level = pcm512x_set_bias_level, 1461 .controls = pcm512x_controls, 1462 .num_controls = ARRAY_SIZE(pcm512x_controls), 1463 .dapm_widgets = pcm512x_dapm_widgets, 1464 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1465 .dapm_routes = pcm512x_dapm_routes, 1466 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1467 .use_pmdown_time = 1, 1468 .endianness = 1, 1469 .non_legacy_dai_naming = 1, 1470 }; 1471 1472 static const struct regmap_range_cfg pcm512x_range = { 1473 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1474 .range_max = PCM512x_MAX_REGISTER, 1475 .selector_reg = PCM512x_PAGE, 1476 .selector_mask = 0xff, 1477 .window_start = 0, .window_len = 0x100, 1478 }; 1479 1480 const struct regmap_config pcm512x_regmap = { 1481 .reg_bits = 8, 1482 .val_bits = 8, 1483 1484 .readable_reg = pcm512x_readable, 1485 .volatile_reg = pcm512x_volatile, 1486 1487 .ranges = &pcm512x_range, 1488 .num_ranges = 1, 1489 1490 .max_register = PCM512x_MAX_REGISTER, 1491 .reg_defaults = pcm512x_reg_defaults, 1492 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1493 .cache_type = REGCACHE_RBTREE, 1494 }; 1495 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1496 1497 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1498 { 1499 struct pcm512x_priv *pcm512x; 1500 int i, ret; 1501 1502 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1503 if (!pcm512x) 1504 return -ENOMEM; 1505 1506 mutex_init(&pcm512x->mutex); 1507 1508 dev_set_drvdata(dev, pcm512x); 1509 pcm512x->regmap = regmap; 1510 1511 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1512 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1513 1514 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1515 pcm512x->supplies); 1516 if (ret != 0) { 1517 dev_err(dev, "Failed to get supplies: %d\n", ret); 1518 return ret; 1519 } 1520 1521 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1522 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1523 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1524 1525 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1526 ret = regulator_register_notifier(pcm512x->supplies[i].consumer, 1527 &pcm512x->supply_nb[i]); 1528 if (ret != 0) { 1529 dev_err(dev, 1530 "Failed to register regulator notifier: %d\n", 1531 ret); 1532 } 1533 } 1534 1535 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1536 pcm512x->supplies); 1537 if (ret != 0) { 1538 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1539 return ret; 1540 } 1541 1542 /* Reset the device, verifying I/O in the process for I2C */ 1543 ret = regmap_write(regmap, PCM512x_RESET, 1544 PCM512x_RSTM | PCM512x_RSTR); 1545 if (ret != 0) { 1546 dev_err(dev, "Failed to reset device: %d\n", ret); 1547 goto err; 1548 } 1549 1550 ret = regmap_write(regmap, PCM512x_RESET, 0); 1551 if (ret != 0) { 1552 dev_err(dev, "Failed to reset device: %d\n", ret); 1553 goto err; 1554 } 1555 1556 pcm512x->sclk = devm_clk_get(dev, NULL); 1557 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) 1558 return -EPROBE_DEFER; 1559 if (!IS_ERR(pcm512x->sclk)) { 1560 ret = clk_prepare_enable(pcm512x->sclk); 1561 if (ret != 0) { 1562 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1563 return ret; 1564 } 1565 } 1566 1567 /* Default to standby mode */ 1568 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1569 PCM512x_RQST, PCM512x_RQST); 1570 if (ret != 0) { 1571 dev_err(dev, "Failed to request standby: %d\n", 1572 ret); 1573 goto err_clk; 1574 } 1575 1576 pm_runtime_set_active(dev); 1577 pm_runtime_enable(dev); 1578 pm_runtime_idle(dev); 1579 1580 #ifdef CONFIG_OF 1581 if (dev->of_node) { 1582 const struct device_node *np = dev->of_node; 1583 u32 val; 1584 1585 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1586 if (val > 6) { 1587 dev_err(dev, "Invalid pll-in\n"); 1588 ret = -EINVAL; 1589 goto err_clk; 1590 } 1591 pcm512x->pll_in = val; 1592 } 1593 1594 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1595 if (val > 6) { 1596 dev_err(dev, "Invalid pll-out\n"); 1597 ret = -EINVAL; 1598 goto err_clk; 1599 } 1600 pcm512x->pll_out = val; 1601 } 1602 1603 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1604 dev_err(dev, 1605 "Error: both pll-in and pll-out, or none\n"); 1606 ret = -EINVAL; 1607 goto err_clk; 1608 } 1609 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1610 dev_err(dev, "Error: pll-in == pll-out\n"); 1611 ret = -EINVAL; 1612 goto err_clk; 1613 } 1614 } 1615 #endif 1616 1617 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver, 1618 &pcm512x_dai, 1); 1619 if (ret != 0) { 1620 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1621 goto err_pm; 1622 } 1623 1624 return 0; 1625 1626 err_pm: 1627 pm_runtime_disable(dev); 1628 err_clk: 1629 if (!IS_ERR(pcm512x->sclk)) 1630 clk_disable_unprepare(pcm512x->sclk); 1631 err: 1632 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1633 pcm512x->supplies); 1634 return ret; 1635 } 1636 EXPORT_SYMBOL_GPL(pcm512x_probe); 1637 1638 void pcm512x_remove(struct device *dev) 1639 { 1640 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1641 1642 pm_runtime_disable(dev); 1643 if (!IS_ERR(pcm512x->sclk)) 1644 clk_disable_unprepare(pcm512x->sclk); 1645 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1646 pcm512x->supplies); 1647 } 1648 EXPORT_SYMBOL_GPL(pcm512x_remove); 1649 1650 #ifdef CONFIG_PM 1651 static int pcm512x_suspend(struct device *dev) 1652 { 1653 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1654 int ret; 1655 1656 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1657 PCM512x_RQPD, PCM512x_RQPD); 1658 if (ret != 0) { 1659 dev_err(dev, "Failed to request power down: %d\n", ret); 1660 return ret; 1661 } 1662 1663 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1664 pcm512x->supplies); 1665 if (ret != 0) { 1666 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1667 return ret; 1668 } 1669 1670 if (!IS_ERR(pcm512x->sclk)) 1671 clk_disable_unprepare(pcm512x->sclk); 1672 1673 return 0; 1674 } 1675 1676 static int pcm512x_resume(struct device *dev) 1677 { 1678 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1679 int ret; 1680 1681 if (!IS_ERR(pcm512x->sclk)) { 1682 ret = clk_prepare_enable(pcm512x->sclk); 1683 if (ret != 0) { 1684 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1685 return ret; 1686 } 1687 } 1688 1689 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1690 pcm512x->supplies); 1691 if (ret != 0) { 1692 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1693 return ret; 1694 } 1695 1696 regcache_cache_only(pcm512x->regmap, false); 1697 ret = regcache_sync(pcm512x->regmap); 1698 if (ret != 0) { 1699 dev_err(dev, "Failed to sync cache: %d\n", ret); 1700 return ret; 1701 } 1702 1703 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1704 PCM512x_RQPD, 0); 1705 if (ret != 0) { 1706 dev_err(dev, "Failed to remove power down: %d\n", ret); 1707 return ret; 1708 } 1709 1710 return 0; 1711 } 1712 #endif 1713 1714 const struct dev_pm_ops pcm512x_pm_ops = { 1715 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1716 }; 1717 EXPORT_SYMBOL_GPL(pcm512x_pm_ops); 1718 1719 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1720 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); 1721 MODULE_LICENSE("GPL v2"); 1722