1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the PCM512x CODECs 4 * 5 * Author: Mark Brown <broonie@kernel.org> 6 * Copyright 2014 Linaro Ltd 7 */ 8 9 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/clk.h> 13 #include <linux/kernel.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/gcd.h> 18 #include <sound/soc.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 23 #include "pcm512x.h" 24 25 #define PCM512x_NUM_SUPPLIES 3 26 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 27 "AVDD", 28 "DVDD", 29 "CPVDD", 30 }; 31 32 struct pcm512x_priv { 33 struct regmap *regmap; 34 struct clk *sclk; 35 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 36 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 37 int fmt; 38 int pll_in; 39 int pll_out; 40 int pll_r; 41 int pll_j; 42 int pll_d; 43 int pll_p; 44 unsigned long real_pll; 45 unsigned long overclock_pll; 46 unsigned long overclock_dac; 47 unsigned long overclock_dsp; 48 int mute; 49 struct mutex mutex; 50 unsigned int bclk_ratio; 51 }; 52 53 /* 54 * We can't use the same notifier block for more than one supply and 55 * there's no way I can see to get from a callback to the caller 56 * except container_of(). 57 */ 58 #define PCM512x_REGULATOR_EVENT(n) \ 59 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 60 unsigned long event, void *data) \ 61 { \ 62 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 63 supply_nb[n]); \ 64 if (event & REGULATOR_EVENT_DISABLE) { \ 65 regcache_mark_dirty(pcm512x->regmap); \ 66 regcache_cache_only(pcm512x->regmap, true); \ 67 } \ 68 return 0; \ 69 } 70 71 PCM512x_REGULATOR_EVENT(0) 72 PCM512x_REGULATOR_EVENT(1) 73 PCM512x_REGULATOR_EVENT(2) 74 75 static const struct reg_default pcm512x_reg_defaults[] = { 76 { PCM512x_RESET, 0x00 }, 77 { PCM512x_POWER, 0x00 }, 78 { PCM512x_MUTE, 0x00 }, 79 { PCM512x_DSP, 0x00 }, 80 { PCM512x_PLL_REF, 0x00 }, 81 { PCM512x_DAC_REF, 0x00 }, 82 { PCM512x_DAC_ROUTING, 0x11 }, 83 { PCM512x_DSP_PROGRAM, 0x01 }, 84 { PCM512x_CLKDET, 0x00 }, 85 { PCM512x_AUTO_MUTE, 0x00 }, 86 { PCM512x_ERROR_DETECT, 0x00 }, 87 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 88 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 89 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 90 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 91 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 92 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 93 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 94 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 95 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 96 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 97 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 98 { PCM512x_VCOM_CTRL_1, 0x00 }, 99 { PCM512x_VCOM_CTRL_2, 0x01 }, 100 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 101 { PCM512x_MASTER_MODE, 0x7c }, 102 { PCM512x_GPIO_DACIN, 0x00 }, 103 { PCM512x_GPIO_PLLIN, 0x00 }, 104 { PCM512x_SYNCHRONIZE, 0x10 }, 105 { PCM512x_PLL_COEFF_0, 0x00 }, 106 { PCM512x_PLL_COEFF_1, 0x00 }, 107 { PCM512x_PLL_COEFF_2, 0x00 }, 108 { PCM512x_PLL_COEFF_3, 0x00 }, 109 { PCM512x_PLL_COEFF_4, 0x00 }, 110 { PCM512x_DSP_CLKDIV, 0x00 }, 111 { PCM512x_DAC_CLKDIV, 0x00 }, 112 { PCM512x_NCP_CLKDIV, 0x00 }, 113 { PCM512x_OSR_CLKDIV, 0x00 }, 114 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 115 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 116 { PCM512x_FS_SPEED_MODE, 0x00 }, 117 { PCM512x_IDAC_1, 0x01 }, 118 { PCM512x_IDAC_2, 0x00 }, 119 }; 120 121 static bool pcm512x_readable(struct device *dev, unsigned int reg) 122 { 123 switch (reg) { 124 case PCM512x_RESET: 125 case PCM512x_POWER: 126 case PCM512x_MUTE: 127 case PCM512x_PLL_EN: 128 case PCM512x_SPI_MISO_FUNCTION: 129 case PCM512x_DSP: 130 case PCM512x_GPIO_EN: 131 case PCM512x_BCLK_LRCLK_CFG: 132 case PCM512x_DSP_GPIO_INPUT: 133 case PCM512x_MASTER_MODE: 134 case PCM512x_PLL_REF: 135 case PCM512x_DAC_REF: 136 case PCM512x_GPIO_DACIN: 137 case PCM512x_GPIO_PLLIN: 138 case PCM512x_SYNCHRONIZE: 139 case PCM512x_PLL_COEFF_0: 140 case PCM512x_PLL_COEFF_1: 141 case PCM512x_PLL_COEFF_2: 142 case PCM512x_PLL_COEFF_3: 143 case PCM512x_PLL_COEFF_4: 144 case PCM512x_DSP_CLKDIV: 145 case PCM512x_DAC_CLKDIV: 146 case PCM512x_NCP_CLKDIV: 147 case PCM512x_OSR_CLKDIV: 148 case PCM512x_MASTER_CLKDIV_1: 149 case PCM512x_MASTER_CLKDIV_2: 150 case PCM512x_FS_SPEED_MODE: 151 case PCM512x_IDAC_1: 152 case PCM512x_IDAC_2: 153 case PCM512x_ERROR_DETECT: 154 case PCM512x_I2S_1: 155 case PCM512x_I2S_2: 156 case PCM512x_DAC_ROUTING: 157 case PCM512x_DSP_PROGRAM: 158 case PCM512x_CLKDET: 159 case PCM512x_AUTO_MUTE: 160 case PCM512x_DIGITAL_VOLUME_1: 161 case PCM512x_DIGITAL_VOLUME_2: 162 case PCM512x_DIGITAL_VOLUME_3: 163 case PCM512x_DIGITAL_MUTE_1: 164 case PCM512x_DIGITAL_MUTE_2: 165 case PCM512x_DIGITAL_MUTE_3: 166 case PCM512x_GPIO_OUTPUT_1: 167 case PCM512x_GPIO_OUTPUT_2: 168 case PCM512x_GPIO_OUTPUT_3: 169 case PCM512x_GPIO_OUTPUT_4: 170 case PCM512x_GPIO_OUTPUT_5: 171 case PCM512x_GPIO_OUTPUT_6: 172 case PCM512x_GPIO_CONTROL_1: 173 case PCM512x_GPIO_CONTROL_2: 174 case PCM512x_OVERFLOW: 175 case PCM512x_RATE_DET_1: 176 case PCM512x_RATE_DET_2: 177 case PCM512x_RATE_DET_3: 178 case PCM512x_RATE_DET_4: 179 case PCM512x_CLOCK_STATUS: 180 case PCM512x_ANALOG_MUTE_DET: 181 case PCM512x_GPIN: 182 case PCM512x_DIGITAL_MUTE_DET: 183 case PCM512x_OUTPUT_AMPLITUDE: 184 case PCM512x_ANALOG_GAIN_CTRL: 185 case PCM512x_UNDERVOLTAGE_PROT: 186 case PCM512x_ANALOG_MUTE_CTRL: 187 case PCM512x_ANALOG_GAIN_BOOST: 188 case PCM512x_VCOM_CTRL_1: 189 case PCM512x_VCOM_CTRL_2: 190 case PCM512x_CRAM_CTRL: 191 case PCM512x_FLEX_A: 192 case PCM512x_FLEX_B: 193 return true; 194 default: 195 /* There are 256 raw register addresses */ 196 return reg < 0xff; 197 } 198 } 199 200 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 201 { 202 switch (reg) { 203 case PCM512x_PLL_EN: 204 case PCM512x_OVERFLOW: 205 case PCM512x_RATE_DET_1: 206 case PCM512x_RATE_DET_2: 207 case PCM512x_RATE_DET_3: 208 case PCM512x_RATE_DET_4: 209 case PCM512x_CLOCK_STATUS: 210 case PCM512x_ANALOG_MUTE_DET: 211 case PCM512x_GPIN: 212 case PCM512x_DIGITAL_MUTE_DET: 213 case PCM512x_CRAM_CTRL: 214 return true; 215 default: 216 /* There are 256 raw register addresses */ 217 return reg < 0xff; 218 } 219 } 220 221 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 222 struct snd_ctl_elem_value *ucontrol) 223 { 224 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 225 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 226 227 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 228 return 0; 229 } 230 231 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 232 struct snd_ctl_elem_value *ucontrol) 233 { 234 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 235 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 236 237 switch (snd_soc_component_get_bias_level(component)) { 238 case SND_SOC_BIAS_OFF: 239 case SND_SOC_BIAS_STANDBY: 240 break; 241 default: 242 return -EBUSY; 243 } 244 245 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 246 return 0; 247 } 248 249 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 250 struct snd_ctl_elem_value *ucontrol) 251 { 252 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 253 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 254 255 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 256 return 0; 257 } 258 259 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 260 struct snd_ctl_elem_value *ucontrol) 261 { 262 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 263 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 264 265 switch (snd_soc_component_get_bias_level(component)) { 266 case SND_SOC_BIAS_OFF: 267 case SND_SOC_BIAS_STANDBY: 268 break; 269 default: 270 return -EBUSY; 271 } 272 273 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 274 return 0; 275 } 276 277 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 278 struct snd_ctl_elem_value *ucontrol) 279 { 280 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 281 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 282 283 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 284 return 0; 285 } 286 287 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 288 struct snd_ctl_elem_value *ucontrol) 289 { 290 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 291 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 292 293 switch (snd_soc_component_get_bias_level(component)) { 294 case SND_SOC_BIAS_OFF: 295 case SND_SOC_BIAS_STANDBY: 296 break; 297 default: 298 return -EBUSY; 299 } 300 301 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 302 return 0; 303 } 304 305 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 306 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 307 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 308 309 static const char * const pcm512x_dsp_program_texts[] = { 310 "FIR interpolation with de-emphasis", 311 "Low latency IIR with de-emphasis", 312 "High attenuation with de-emphasis", 313 "Fixed process flow", 314 "Ringing-less low latency FIR", 315 }; 316 317 static const unsigned int pcm512x_dsp_program_values[] = { 318 1, 319 2, 320 3, 321 5, 322 7, 323 }; 324 325 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 326 PCM512x_DSP_PROGRAM, 0, 0x1f, 327 pcm512x_dsp_program_texts, 328 pcm512x_dsp_program_values); 329 330 static const char * const pcm512x_clk_missing_text[] = { 331 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 332 }; 333 334 static const struct soc_enum pcm512x_clk_missing = 335 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 336 337 static const char * const pcm512x_autom_text[] = { 338 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 339 }; 340 341 static const struct soc_enum pcm512x_autom_l = 342 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 343 pcm512x_autom_text); 344 345 static const struct soc_enum pcm512x_autom_r = 346 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 347 pcm512x_autom_text); 348 349 static const char * const pcm512x_ramp_rate_text[] = { 350 "1 sample/update", "2 samples/update", "4 samples/update", 351 "Immediate" 352 }; 353 354 static const struct soc_enum pcm512x_vndf = 355 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 356 pcm512x_ramp_rate_text); 357 358 static const struct soc_enum pcm512x_vnuf = 359 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 360 pcm512x_ramp_rate_text); 361 362 static const struct soc_enum pcm512x_vedf = 363 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 364 pcm512x_ramp_rate_text); 365 366 static const char * const pcm512x_ramp_step_text[] = { 367 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 368 }; 369 370 static const struct soc_enum pcm512x_vnds = 371 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 372 pcm512x_ramp_step_text); 373 374 static const struct soc_enum pcm512x_vnus = 375 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 376 pcm512x_ramp_step_text); 377 378 static const struct soc_enum pcm512x_veds = 379 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 380 pcm512x_ramp_step_text); 381 382 static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) 383 { 384 return regmap_update_bits( 385 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, 386 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) 387 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); 388 } 389 390 static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, 391 struct snd_ctl_elem_value *ucontrol) 392 { 393 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 394 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 395 396 mutex_lock(&pcm512x->mutex); 397 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); 398 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); 399 mutex_unlock(&pcm512x->mutex); 400 401 return 0; 402 } 403 404 static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, 405 struct snd_ctl_elem_value *ucontrol) 406 { 407 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 408 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 409 int ret, changed = 0; 410 411 mutex_lock(&pcm512x->mutex); 412 413 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { 414 pcm512x->mute ^= 0x4; 415 changed = 1; 416 } 417 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { 418 pcm512x->mute ^= 0x2; 419 changed = 1; 420 } 421 422 if (changed) { 423 ret = pcm512x_update_mute(pcm512x); 424 if (ret != 0) { 425 dev_err(component->dev, 426 "Failed to update digital mute: %d\n", ret); 427 mutex_unlock(&pcm512x->mutex); 428 return ret; 429 } 430 } 431 432 mutex_unlock(&pcm512x->mutex); 433 434 return changed; 435 } 436 437 static const struct snd_kcontrol_new pcm512x_controls[] = { 438 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 439 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 440 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 441 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 442 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 443 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 444 { 445 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 446 .name = "Digital Playback Switch", 447 .index = 0, 448 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 449 .info = snd_ctl_boolean_stereo_info, 450 .get = pcm512x_digital_playback_switch_get, 451 .put = pcm512x_digital_playback_switch_put 452 }, 453 454 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 455 SOC_ENUM("DSP Program", pcm512x_dsp_program), 456 457 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 458 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 459 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 460 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 461 PCM512x_ACTL_SHIFT, 1, 0), 462 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 463 PCM512x_AMRE_SHIFT, 1, 0), 464 465 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 466 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 467 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 468 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 469 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 470 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 471 472 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 473 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 474 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 475 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 476 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 477 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 478 }; 479 480 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 481 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 482 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 483 484 SND_SOC_DAPM_OUTPUT("OUTL"), 485 SND_SOC_DAPM_OUTPUT("OUTR"), 486 }; 487 488 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 489 { "DACL", NULL, "Playback" }, 490 { "DACR", NULL, "Playback" }, 491 492 { "OUTL", NULL, "DACL" }, 493 { "OUTR", NULL, "DACR" }, 494 }; 495 496 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 497 { 498 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 499 } 500 501 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 502 { 503 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 504 } 505 506 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 507 unsigned long rate) 508 { 509 return rate + rate * pcm512x->overclock_dac / 100; 510 } 511 512 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 513 { 514 if (!pcm512x->pll_out) 515 return 25000000; 516 return pcm512x_pll_max(pcm512x); 517 } 518 519 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 520 unsigned long dac_rate) 521 { 522 /* 523 * If the DAC is not actually overclocked, use the good old 524 * NCP target rate... 525 */ 526 if (dac_rate <= 6144000) 527 return 1536000; 528 /* 529 * ...but if the DAC is in fact overclocked, bump the NCP target 530 * rate to get the recommended dividers even when overclocking. 531 */ 532 return pcm512x_dac_max(pcm512x, 1536000); 533 } 534 535 static const u32 pcm512x_dai_rates[] = { 536 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 537 88200, 96000, 176400, 192000, 384000, 538 }; 539 540 static const struct snd_pcm_hw_constraint_list constraints_slave = { 541 .count = ARRAY_SIZE(pcm512x_dai_rates), 542 .list = pcm512x_dai_rates, 543 }; 544 545 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 546 struct snd_pcm_hw_rule *rule) 547 { 548 struct pcm512x_priv *pcm512x = rule->private; 549 struct snd_interval ranges[2]; 550 int frame_size; 551 552 frame_size = snd_soc_params_to_frame_size(params); 553 if (frame_size < 0) 554 return frame_size; 555 556 switch (frame_size) { 557 case 32: 558 /* No hole when the frame size is 32. */ 559 return 0; 560 case 48: 561 case 64: 562 /* There is only one hole in the range of supported 563 * rates, but it moves with the frame size. 564 */ 565 memset(ranges, 0, sizeof(ranges)); 566 ranges[0].min = 8000; 567 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 568 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 569 ranges[1].max = 384000; 570 break; 571 default: 572 return -EINVAL; 573 } 574 575 return snd_interval_ranges(hw_param_interval(params, rule->var), 576 ARRAY_SIZE(ranges), ranges, 0); 577 } 578 579 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 580 struct snd_soc_dai *dai) 581 { 582 struct snd_soc_component *component = dai->component; 583 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 584 struct device *dev = dai->dev; 585 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 586 struct snd_ratnum *rats_no_pll; 587 588 if (IS_ERR(pcm512x->sclk)) { 589 dev_err(dev, "Need SCLK for master mode: %ld\n", 590 PTR_ERR(pcm512x->sclk)); 591 return PTR_ERR(pcm512x->sclk); 592 } 593 594 if (pcm512x->pll_out) 595 return snd_pcm_hw_rule_add(substream->runtime, 0, 596 SNDRV_PCM_HW_PARAM_RATE, 597 pcm512x_hw_rule_rate, 598 pcm512x, 599 SNDRV_PCM_HW_PARAM_FRAME_BITS, 600 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 601 602 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 603 GFP_KERNEL); 604 if (!constraints_no_pll) 605 return -ENOMEM; 606 constraints_no_pll->nrats = 1; 607 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 608 if (!rats_no_pll) 609 return -ENOMEM; 610 constraints_no_pll->rats = rats_no_pll; 611 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 612 rats_no_pll->den_min = 1; 613 rats_no_pll->den_max = 128; 614 rats_no_pll->den_step = 1; 615 616 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 617 SNDRV_PCM_HW_PARAM_RATE, 618 constraints_no_pll); 619 } 620 621 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 622 struct snd_soc_dai *dai) 623 { 624 struct snd_soc_component *component = dai->component; 625 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 626 struct device *dev = dai->dev; 627 struct regmap *regmap = pcm512x->regmap; 628 629 if (IS_ERR(pcm512x->sclk)) { 630 dev_info(dev, "No SCLK, using BCLK: %ld\n", 631 PTR_ERR(pcm512x->sclk)); 632 633 /* Disable reporting of missing SCLK as an error */ 634 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 635 PCM512x_IDCH, PCM512x_IDCH); 636 637 /* Switch PLL input to BCLK */ 638 regmap_update_bits(regmap, PCM512x_PLL_REF, 639 PCM512x_SREF, PCM512x_SREF_BCK); 640 } 641 642 return snd_pcm_hw_constraint_list(substream->runtime, 0, 643 SNDRV_PCM_HW_PARAM_RATE, 644 &constraints_slave); 645 } 646 647 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 648 struct snd_soc_dai *dai) 649 { 650 struct snd_soc_component *component = dai->component; 651 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 652 653 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 654 case SND_SOC_DAIFMT_CBM_CFM: 655 case SND_SOC_DAIFMT_CBM_CFS: 656 return pcm512x_dai_startup_master(substream, dai); 657 658 case SND_SOC_DAIFMT_CBS_CFS: 659 return pcm512x_dai_startup_slave(substream, dai); 660 661 default: 662 return -EINVAL; 663 } 664 } 665 666 static int pcm512x_set_bias_level(struct snd_soc_component *component, 667 enum snd_soc_bias_level level) 668 { 669 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev); 670 int ret; 671 672 switch (level) { 673 case SND_SOC_BIAS_ON: 674 case SND_SOC_BIAS_PREPARE: 675 break; 676 677 case SND_SOC_BIAS_STANDBY: 678 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 679 PCM512x_RQST, 0); 680 if (ret != 0) { 681 dev_err(component->dev, "Failed to remove standby: %d\n", 682 ret); 683 return ret; 684 } 685 break; 686 687 case SND_SOC_BIAS_OFF: 688 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 689 PCM512x_RQST, PCM512x_RQST); 690 if (ret != 0) { 691 dev_err(component->dev, "Failed to request standby: %d\n", 692 ret); 693 return ret; 694 } 695 break; 696 } 697 698 return 0; 699 } 700 701 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 702 unsigned long bclk_rate) 703 { 704 struct device *dev = dai->dev; 705 struct snd_soc_component *component = dai->component; 706 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 707 unsigned long sck_rate; 708 int pow2; 709 710 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 711 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 712 713 /* select sck_rate as a multiple of bclk_rate but still with 714 * as many factors of 2 as possible, as that makes it easier 715 * to find a fast DAC rate 716 */ 717 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 718 for (; pow2; pow2 >>= 1) { 719 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 720 bclk_rate * pow2); 721 if (sck_rate >= 16000000) 722 break; 723 } 724 if (!pow2) { 725 dev_err(dev, "Impossible to generate a suitable SCK\n"); 726 return 0; 727 } 728 729 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 730 return sck_rate; 731 } 732 733 /* pll_rate = pllin_rate * R * J.D / P 734 * 1 <= R <= 16 735 * 1 <= J <= 63 736 * 0 <= D <= 9999 737 * 1 <= P <= 15 738 * 64 MHz <= pll_rate <= 100 MHz 739 * if D == 0 740 * 1 MHz <= pllin_rate / P <= 20 MHz 741 * else if D > 0 742 * 6.667 MHz <= pllin_rate / P <= 20 MHz 743 * 4 <= J <= 11 744 * R = 1 745 */ 746 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 747 unsigned long pllin_rate, 748 unsigned long pll_rate) 749 { 750 struct device *dev = dai->dev; 751 struct snd_soc_component *component = dai->component; 752 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 753 unsigned long common; 754 int R, J, D, P; 755 unsigned long K; /* 10000 * J.D */ 756 unsigned long num; 757 unsigned long den; 758 759 common = gcd(pll_rate, pllin_rate); 760 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 761 pll_rate, pllin_rate, common); 762 num = pll_rate / common; 763 den = pllin_rate / common; 764 765 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 766 if (pllin_rate / den > 20000000 && num < 8) { 767 num *= DIV_ROUND_UP(pllin_rate / den, 20000000); 768 den *= DIV_ROUND_UP(pllin_rate / den, 20000000); 769 } 770 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 771 772 P = den; 773 if (den <= 15 && num <= 16 * 63 774 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 775 /* Try the case with D = 0 */ 776 D = 0; 777 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 778 for (R = 16; R; R--) { 779 if (num % R) 780 continue; 781 J = num / R; 782 if (J == 0 || J > 63) 783 continue; 784 785 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 786 pcm512x->real_pll = pll_rate; 787 goto done; 788 } 789 /* no luck */ 790 } 791 792 R = 1; 793 794 if (num > 0xffffffffUL / 10000) 795 goto fallback; 796 797 /* Try to find an exact pll_rate using the D > 0 case */ 798 common = gcd(10000 * num, den); 799 num = 10000 * num / common; 800 den /= common; 801 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 802 803 for (P = den; P <= 15; P++) { 804 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 805 continue; 806 if (num * P % den) 807 continue; 808 K = num * P / den; 809 /* J == 12 is ok if D == 0 */ 810 if (K < 40000 || K > 120000) 811 continue; 812 813 J = K / 10000; 814 D = K % 10000; 815 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 816 pcm512x->real_pll = pll_rate; 817 goto done; 818 } 819 820 /* Fall back to an approximate pll_rate */ 821 822 fallback: 823 /* find smallest possible P */ 824 P = DIV_ROUND_UP(pllin_rate, 20000000); 825 if (!P) 826 P = 1; 827 else if (P > 15) { 828 dev_err(dev, "Need a slower clock as pll-input\n"); 829 return -EINVAL; 830 } 831 if (pllin_rate / P < 6667000) { 832 dev_err(dev, "Need a faster clock as pll-input\n"); 833 return -EINVAL; 834 } 835 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 836 if (K < 40000) 837 K = 40000; 838 /* J == 12 is ok if D == 0 */ 839 if (K > 120000) 840 K = 120000; 841 J = K / 10000; 842 D = K % 10000; 843 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 844 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 845 846 done: 847 pcm512x->pll_r = R; 848 pcm512x->pll_j = J; 849 pcm512x->pll_d = D; 850 pcm512x->pll_p = P; 851 return 0; 852 } 853 854 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 855 unsigned long osr_rate, 856 unsigned long pllin_rate) 857 { 858 struct snd_soc_component *component = dai->component; 859 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 860 unsigned long dac_rate; 861 862 if (!pcm512x->pll_out) 863 return 0; /* no PLL to bypass, force SCK as DAC input */ 864 865 if (pllin_rate % osr_rate) 866 return 0; /* futile, quit early */ 867 868 /* run DAC no faster than 6144000 Hz */ 869 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 870 dac_rate; 871 dac_rate -= osr_rate) { 872 873 if (pllin_rate / dac_rate > 128) 874 return 0; /* DAC divider would be too big */ 875 876 if (!(pllin_rate % dac_rate)) 877 return dac_rate; 878 879 dac_rate -= osr_rate; 880 } 881 882 return 0; 883 } 884 885 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 886 struct snd_pcm_hw_params *params) 887 { 888 struct device *dev = dai->dev; 889 struct snd_soc_component *component = dai->component; 890 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 891 unsigned long pllin_rate = 0; 892 unsigned long pll_rate; 893 unsigned long sck_rate; 894 unsigned long mck_rate; 895 unsigned long bclk_rate; 896 unsigned long sample_rate; 897 unsigned long osr_rate; 898 unsigned long dacsrc_rate; 899 int bclk_div; 900 int lrclk_div; 901 int dsp_div; 902 int dac_div; 903 unsigned long dac_rate; 904 int ncp_div; 905 int osr_div; 906 int ret; 907 int idac; 908 int fssp; 909 int gpio; 910 911 if (pcm512x->bclk_ratio > 0) { 912 lrclk_div = pcm512x->bclk_ratio; 913 } else { 914 lrclk_div = snd_soc_params_to_frame_size(params); 915 916 if (lrclk_div == 0) { 917 dev_err(dev, "No LRCLK?\n"); 918 return -EINVAL; 919 } 920 } 921 922 if (!pcm512x->pll_out) { 923 sck_rate = clk_get_rate(pcm512x->sclk); 924 bclk_rate = params_rate(params) * lrclk_div; 925 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 926 927 mck_rate = sck_rate; 928 } else { 929 ret = snd_soc_params_to_bclk(params); 930 if (ret < 0) { 931 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 932 return ret; 933 } 934 if (ret == 0) { 935 dev_err(dev, "No BCLK?\n"); 936 return -EINVAL; 937 } 938 bclk_rate = ret; 939 940 pllin_rate = clk_get_rate(pcm512x->sclk); 941 942 sck_rate = pcm512x_find_sck(dai, bclk_rate); 943 if (!sck_rate) 944 return -EINVAL; 945 pll_rate = 4 * sck_rate; 946 947 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 948 if (ret != 0) 949 return ret; 950 951 ret = regmap_write(pcm512x->regmap, 952 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 953 if (ret != 0) { 954 dev_err(dev, "Failed to write PLL P: %d\n", ret); 955 return ret; 956 } 957 958 ret = regmap_write(pcm512x->regmap, 959 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 960 if (ret != 0) { 961 dev_err(dev, "Failed to write PLL J: %d\n", ret); 962 return ret; 963 } 964 965 ret = regmap_write(pcm512x->regmap, 966 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 967 if (ret != 0) { 968 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 969 return ret; 970 } 971 972 ret = regmap_write(pcm512x->regmap, 973 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 974 if (ret != 0) { 975 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 976 return ret; 977 } 978 979 ret = regmap_write(pcm512x->regmap, 980 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 981 if (ret != 0) { 982 dev_err(dev, "Failed to write PLL R: %d\n", ret); 983 return ret; 984 } 985 986 mck_rate = pcm512x->real_pll; 987 988 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 989 } 990 991 if (bclk_div > 128) { 992 dev_err(dev, "Failed to find BCLK divider\n"); 993 return -EINVAL; 994 } 995 996 /* the actual rate */ 997 sample_rate = sck_rate / bclk_div / lrclk_div; 998 osr_rate = 16 * sample_rate; 999 1000 /* run DSP no faster than 50 MHz */ 1001 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 1002 1003 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 1004 if (dac_rate) { 1005 /* the desired clock rate is "compatible" with the pll input 1006 * clock, so use that clock as dac input instead of the pll 1007 * output clock since the pll will introduce jitter and thus 1008 * noise. 1009 */ 1010 dev_dbg(dev, "using pll input as dac input\n"); 1011 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1012 PCM512x_SDAC, PCM512x_SDAC_GPIO); 1013 if (ret != 0) { 1014 dev_err(component->dev, 1015 "Failed to set gpio as dacref: %d\n", ret); 1016 return ret; 1017 } 1018 1019 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1020 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 1021 PCM512x_GREF, gpio); 1022 if (ret != 0) { 1023 dev_err(component->dev, 1024 "Failed to set gpio %d as dacin: %d\n", 1025 pcm512x->pll_in, ret); 1026 return ret; 1027 } 1028 1029 dacsrc_rate = pllin_rate; 1030 } else { 1031 /* run DAC no faster than 6144000 Hz */ 1032 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 1033 / osr_rate; 1034 unsigned long sck_mul = sck_rate / osr_rate; 1035 1036 for (; dac_mul; dac_mul--) { 1037 if (!(sck_mul % dac_mul)) 1038 break; 1039 } 1040 if (!dac_mul) { 1041 dev_err(dev, "Failed to find DAC rate\n"); 1042 return -EINVAL; 1043 } 1044 1045 dac_rate = dac_mul * osr_rate; 1046 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 1047 dac_rate, sample_rate); 1048 1049 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1050 PCM512x_SDAC, PCM512x_SDAC_SCK); 1051 if (ret != 0) { 1052 dev_err(component->dev, 1053 "Failed to set sck as dacref: %d\n", ret); 1054 return ret; 1055 } 1056 1057 dacsrc_rate = sck_rate; 1058 } 1059 1060 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1061 if (osr_div > 128) { 1062 dev_err(dev, "Failed to find OSR divider\n"); 1063 return -EINVAL; 1064 } 1065 1066 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1067 if (dac_div > 128) { 1068 dev_err(dev, "Failed to find DAC divider\n"); 1069 return -EINVAL; 1070 } 1071 dac_rate = dacsrc_rate / dac_div; 1072 1073 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1074 pcm512x_ncp_target(pcm512x, dac_rate)); 1075 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1076 /* run NCP no faster than 2048000 Hz, but why? */ 1077 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1078 if (ncp_div > 128) { 1079 dev_err(dev, "Failed to find NCP divider\n"); 1080 return -EINVAL; 1081 } 1082 } 1083 1084 idac = mck_rate / (dsp_div * sample_rate); 1085 1086 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1087 if (ret != 0) { 1088 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1089 return ret; 1090 } 1091 1092 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1093 if (ret != 0) { 1094 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1095 return ret; 1096 } 1097 1098 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1099 if (ret != 0) { 1100 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1101 return ret; 1102 } 1103 1104 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1105 if (ret != 0) { 1106 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1107 return ret; 1108 } 1109 1110 ret = regmap_write(pcm512x->regmap, 1111 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1112 if (ret != 0) { 1113 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1114 return ret; 1115 } 1116 1117 ret = regmap_write(pcm512x->regmap, 1118 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1119 if (ret != 0) { 1120 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1121 return ret; 1122 } 1123 1124 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1125 if (ret != 0) { 1126 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1127 return ret; 1128 } 1129 1130 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1131 if (ret != 0) { 1132 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1133 return ret; 1134 } 1135 1136 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1137 fssp = PCM512x_FSSP_48KHZ; 1138 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1139 fssp = PCM512x_FSSP_96KHZ; 1140 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1141 fssp = PCM512x_FSSP_192KHZ; 1142 else 1143 fssp = PCM512x_FSSP_384KHZ; 1144 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1145 PCM512x_FSSP, fssp); 1146 if (ret != 0) { 1147 dev_err(component->dev, "Failed to set fs speed: %d\n", ret); 1148 return ret; 1149 } 1150 1151 dev_dbg(component->dev, "DSP divider %d\n", dsp_div); 1152 dev_dbg(component->dev, "DAC divider %d\n", dac_div); 1153 dev_dbg(component->dev, "NCP divider %d\n", ncp_div); 1154 dev_dbg(component->dev, "OSR divider %d\n", osr_div); 1155 dev_dbg(component->dev, "BCK divider %d\n", bclk_div); 1156 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div); 1157 dev_dbg(component->dev, "IDAC %d\n", idac); 1158 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp); 1159 1160 return 0; 1161 } 1162 1163 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1164 struct snd_pcm_hw_params *params, 1165 struct snd_soc_dai *dai) 1166 { 1167 struct snd_soc_component *component = dai->component; 1168 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1169 int alen; 1170 int gpio; 1171 int clock_output; 1172 int master_mode; 1173 int ret; 1174 1175 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n", 1176 params_rate(params), 1177 params_channels(params)); 1178 1179 switch (params_width(params)) { 1180 case 16: 1181 alen = PCM512x_ALEN_16; 1182 break; 1183 case 20: 1184 alen = PCM512x_ALEN_20; 1185 break; 1186 case 24: 1187 alen = PCM512x_ALEN_24; 1188 break; 1189 case 32: 1190 alen = PCM512x_ALEN_32; 1191 break; 1192 default: 1193 dev_err(component->dev, "Bad frame size: %d\n", 1194 params_width(params)); 1195 return -EINVAL; 1196 } 1197 1198 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1199 case SND_SOC_DAIFMT_CBS_CFS: 1200 ret = regmap_update_bits(pcm512x->regmap, 1201 PCM512x_BCLK_LRCLK_CFG, 1202 PCM512x_BCKP 1203 | PCM512x_BCKO | PCM512x_LRKO, 1204 0); 1205 if (ret != 0) { 1206 dev_err(component->dev, 1207 "Failed to enable slave mode: %d\n", ret); 1208 return ret; 1209 } 1210 1211 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1212 PCM512x_DCAS, 0); 1213 if (ret != 0) { 1214 dev_err(component->dev, 1215 "Failed to enable clock divider autoset: %d\n", 1216 ret); 1217 return ret; 1218 } 1219 return 0; 1220 case SND_SOC_DAIFMT_CBM_CFM: 1221 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1222 master_mode = PCM512x_RLRK | PCM512x_RBCK; 1223 break; 1224 case SND_SOC_DAIFMT_CBM_CFS: 1225 clock_output = PCM512x_BCKO; 1226 master_mode = PCM512x_RBCK; 1227 break; 1228 default: 1229 return -EINVAL; 1230 } 1231 1232 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1233 PCM512x_ALEN, alen); 1234 if (ret != 0) { 1235 dev_err(component->dev, "Failed to set frame size: %d\n", ret); 1236 return ret; 1237 } 1238 1239 if (pcm512x->pll_out) { 1240 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1241 if (ret != 0) { 1242 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret); 1243 return ret; 1244 } 1245 1246 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1247 if (ret != 0) { 1248 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret); 1249 return ret; 1250 } 1251 1252 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1253 PCM512x_IDFS | PCM512x_IDBK 1254 | PCM512x_IDSK | PCM512x_IDCH 1255 | PCM512x_IDCM | PCM512x_DCAS 1256 | PCM512x_IPLK, 1257 PCM512x_IDFS | PCM512x_IDBK 1258 | PCM512x_IDSK | PCM512x_IDCH 1259 | PCM512x_DCAS); 1260 if (ret != 0) { 1261 dev_err(component->dev, 1262 "Failed to ignore auto-clock failures: %d\n", 1263 ret); 1264 return ret; 1265 } 1266 } else { 1267 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1268 PCM512x_IDFS | PCM512x_IDBK 1269 | PCM512x_IDSK | PCM512x_IDCH 1270 | PCM512x_IDCM | PCM512x_DCAS 1271 | PCM512x_IPLK, 1272 PCM512x_IDFS | PCM512x_IDBK 1273 | PCM512x_IDSK | PCM512x_IDCH 1274 | PCM512x_DCAS | PCM512x_IPLK); 1275 if (ret != 0) { 1276 dev_err(component->dev, 1277 "Failed to ignore auto-clock failures: %d\n", 1278 ret); 1279 return ret; 1280 } 1281 1282 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1283 PCM512x_PLLE, 0); 1284 if (ret != 0) { 1285 dev_err(component->dev, "Failed to disable pll: %d\n", ret); 1286 return ret; 1287 } 1288 } 1289 1290 ret = pcm512x_set_dividers(dai, params); 1291 if (ret != 0) 1292 return ret; 1293 1294 if (pcm512x->pll_out) { 1295 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1296 PCM512x_SREF, PCM512x_SREF_GPIO); 1297 if (ret != 0) { 1298 dev_err(component->dev, 1299 "Failed to set gpio as pllref: %d\n", ret); 1300 return ret; 1301 } 1302 1303 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1304 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1305 PCM512x_GREF, gpio); 1306 if (ret != 0) { 1307 dev_err(component->dev, 1308 "Failed to set gpio %d as pllin: %d\n", 1309 pcm512x->pll_in, ret); 1310 return ret; 1311 } 1312 1313 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1314 PCM512x_PLLE, PCM512x_PLLE); 1315 if (ret != 0) { 1316 dev_err(component->dev, "Failed to enable pll: %d\n", ret); 1317 return ret; 1318 } 1319 } 1320 1321 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1322 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1323 clock_output); 1324 if (ret != 0) { 1325 dev_err(component->dev, "Failed to enable clock output: %d\n", ret); 1326 return ret; 1327 } 1328 1329 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1330 PCM512x_RLRK | PCM512x_RBCK, 1331 master_mode); 1332 if (ret != 0) { 1333 dev_err(component->dev, "Failed to enable master mode: %d\n", ret); 1334 return ret; 1335 } 1336 1337 if (pcm512x->pll_out) { 1338 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1339 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1340 gpio, gpio); 1341 if (ret != 0) { 1342 dev_err(component->dev, "Failed to enable gpio %d: %d\n", 1343 pcm512x->pll_out, ret); 1344 return ret; 1345 } 1346 1347 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1348 ret = regmap_update_bits(pcm512x->regmap, gpio, 1349 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1350 if (ret != 0) { 1351 dev_err(component->dev, "Failed to output pll on %d: %d\n", 1352 ret, pcm512x->pll_out); 1353 return ret; 1354 } 1355 } 1356 1357 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1358 PCM512x_RQSY, PCM512x_RQSY_HALT); 1359 if (ret != 0) { 1360 dev_err(component->dev, "Failed to halt clocks: %d\n", ret); 1361 return ret; 1362 } 1363 1364 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1365 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1366 if (ret != 0) { 1367 dev_err(component->dev, "Failed to resume clocks: %d\n", ret); 1368 return ret; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1375 { 1376 struct snd_soc_component *component = dai->component; 1377 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1378 1379 pcm512x->fmt = fmt; 1380 1381 return 0; 1382 } 1383 1384 static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 1385 { 1386 struct snd_soc_component *component = dai->component; 1387 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1388 1389 if (ratio > 256) 1390 return -EINVAL; 1391 1392 pcm512x->bclk_ratio = ratio; 1393 1394 return 0; 1395 } 1396 1397 static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction) 1398 { 1399 struct snd_soc_component *component = dai->component; 1400 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1401 int ret; 1402 unsigned int mute_det; 1403 1404 mutex_lock(&pcm512x->mutex); 1405 1406 if (mute) { 1407 pcm512x->mute |= 0x1; 1408 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE, 1409 PCM512x_RQML | PCM512x_RQMR, 1410 PCM512x_RQML | PCM512x_RQMR); 1411 if (ret != 0) { 1412 dev_err(component->dev, 1413 "Failed to set digital mute: %d\n", ret); 1414 goto unlock; 1415 } 1416 1417 regmap_read_poll_timeout(pcm512x->regmap, 1418 PCM512x_ANALOG_MUTE_DET, 1419 mute_det, (mute_det & 0x3) == 0, 1420 200, 10000); 1421 } else { 1422 pcm512x->mute &= ~0x1; 1423 ret = pcm512x_update_mute(pcm512x); 1424 if (ret != 0) { 1425 dev_err(component->dev, 1426 "Failed to update digital mute: %d\n", ret); 1427 goto unlock; 1428 } 1429 1430 regmap_read_poll_timeout(pcm512x->regmap, 1431 PCM512x_ANALOG_MUTE_DET, 1432 mute_det, 1433 (mute_det & 0x3) 1434 == ((~pcm512x->mute >> 1) & 0x3), 1435 200, 10000); 1436 } 1437 1438 unlock: 1439 mutex_unlock(&pcm512x->mutex); 1440 1441 return ret; 1442 } 1443 1444 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1445 .startup = pcm512x_dai_startup, 1446 .hw_params = pcm512x_hw_params, 1447 .set_fmt = pcm512x_set_fmt, 1448 .mute_stream = pcm512x_mute, 1449 .set_bclk_ratio = pcm512x_set_bclk_ratio, 1450 .no_capture_mute = 1, 1451 }; 1452 1453 static struct snd_soc_dai_driver pcm512x_dai = { 1454 .name = "pcm512x-hifi", 1455 .playback = { 1456 .stream_name = "Playback", 1457 .channels_min = 2, 1458 .channels_max = 2, 1459 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1460 .rate_min = 8000, 1461 .rate_max = 384000, 1462 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1463 SNDRV_PCM_FMTBIT_S24_LE | 1464 SNDRV_PCM_FMTBIT_S32_LE 1465 }, 1466 .ops = &pcm512x_dai_ops, 1467 }; 1468 1469 static const struct snd_soc_component_driver pcm512x_component_driver = { 1470 .set_bias_level = pcm512x_set_bias_level, 1471 .controls = pcm512x_controls, 1472 .num_controls = ARRAY_SIZE(pcm512x_controls), 1473 .dapm_widgets = pcm512x_dapm_widgets, 1474 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1475 .dapm_routes = pcm512x_dapm_routes, 1476 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1477 .use_pmdown_time = 1, 1478 .endianness = 1, 1479 .non_legacy_dai_naming = 1, 1480 }; 1481 1482 static const struct regmap_range_cfg pcm512x_range = { 1483 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1484 .range_max = PCM512x_MAX_REGISTER, 1485 .selector_reg = PCM512x_PAGE, 1486 .selector_mask = 0xff, 1487 .window_start = 0, .window_len = 0x100, 1488 }; 1489 1490 const struct regmap_config pcm512x_regmap = { 1491 .reg_bits = 8, 1492 .val_bits = 8, 1493 1494 .readable_reg = pcm512x_readable, 1495 .volatile_reg = pcm512x_volatile, 1496 1497 .ranges = &pcm512x_range, 1498 .num_ranges = 1, 1499 1500 .max_register = PCM512x_MAX_REGISTER, 1501 .reg_defaults = pcm512x_reg_defaults, 1502 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1503 .cache_type = REGCACHE_RBTREE, 1504 }; 1505 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1506 1507 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1508 { 1509 struct pcm512x_priv *pcm512x; 1510 int i, ret; 1511 1512 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1513 if (!pcm512x) 1514 return -ENOMEM; 1515 1516 mutex_init(&pcm512x->mutex); 1517 1518 dev_set_drvdata(dev, pcm512x); 1519 pcm512x->regmap = regmap; 1520 1521 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1522 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1523 1524 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1525 pcm512x->supplies); 1526 if (ret != 0) { 1527 dev_err(dev, "Failed to get supplies: %d\n", ret); 1528 return ret; 1529 } 1530 1531 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1532 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1533 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1534 1535 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1536 ret = devm_regulator_register_notifier( 1537 pcm512x->supplies[i].consumer, 1538 &pcm512x->supply_nb[i]); 1539 if (ret != 0) { 1540 dev_err(dev, 1541 "Failed to register regulator notifier: %d\n", 1542 ret); 1543 } 1544 } 1545 1546 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1547 pcm512x->supplies); 1548 if (ret != 0) { 1549 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1550 return ret; 1551 } 1552 1553 /* Reset the device, verifying I/O in the process for I2C */ 1554 ret = regmap_write(regmap, PCM512x_RESET, 1555 PCM512x_RSTM | PCM512x_RSTR); 1556 if (ret != 0) { 1557 dev_err(dev, "Failed to reset device: %d\n", ret); 1558 goto err; 1559 } 1560 1561 ret = regmap_write(regmap, PCM512x_RESET, 0); 1562 if (ret != 0) { 1563 dev_err(dev, "Failed to reset device: %d\n", ret); 1564 goto err; 1565 } 1566 1567 pcm512x->sclk = devm_clk_get(dev, NULL); 1568 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) { 1569 ret = -EPROBE_DEFER; 1570 goto err; 1571 } 1572 if (!IS_ERR(pcm512x->sclk)) { 1573 ret = clk_prepare_enable(pcm512x->sclk); 1574 if (ret != 0) { 1575 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1576 goto err; 1577 } 1578 } 1579 1580 /* Default to standby mode */ 1581 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1582 PCM512x_RQST, PCM512x_RQST); 1583 if (ret != 0) { 1584 dev_err(dev, "Failed to request standby: %d\n", 1585 ret); 1586 goto err_clk; 1587 } 1588 1589 pm_runtime_set_active(dev); 1590 pm_runtime_enable(dev); 1591 pm_runtime_idle(dev); 1592 1593 #ifdef CONFIG_OF 1594 if (dev->of_node) { 1595 const struct device_node *np = dev->of_node; 1596 u32 val; 1597 1598 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1599 if (val > 6) { 1600 dev_err(dev, "Invalid pll-in\n"); 1601 ret = -EINVAL; 1602 goto err_clk; 1603 } 1604 pcm512x->pll_in = val; 1605 } 1606 1607 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1608 if (val > 6) { 1609 dev_err(dev, "Invalid pll-out\n"); 1610 ret = -EINVAL; 1611 goto err_clk; 1612 } 1613 pcm512x->pll_out = val; 1614 } 1615 1616 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1617 dev_err(dev, 1618 "Error: both pll-in and pll-out, or none\n"); 1619 ret = -EINVAL; 1620 goto err_clk; 1621 } 1622 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1623 dev_err(dev, "Error: pll-in == pll-out\n"); 1624 ret = -EINVAL; 1625 goto err_clk; 1626 } 1627 } 1628 #endif 1629 1630 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver, 1631 &pcm512x_dai, 1); 1632 if (ret != 0) { 1633 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1634 goto err_pm; 1635 } 1636 1637 return 0; 1638 1639 err_pm: 1640 pm_runtime_disable(dev); 1641 err_clk: 1642 if (!IS_ERR(pcm512x->sclk)) 1643 clk_disable_unprepare(pcm512x->sclk); 1644 err: 1645 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1646 pcm512x->supplies); 1647 return ret; 1648 } 1649 EXPORT_SYMBOL_GPL(pcm512x_probe); 1650 1651 void pcm512x_remove(struct device *dev) 1652 { 1653 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1654 1655 pm_runtime_disable(dev); 1656 if (!IS_ERR(pcm512x->sclk)) 1657 clk_disable_unprepare(pcm512x->sclk); 1658 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1659 pcm512x->supplies); 1660 } 1661 EXPORT_SYMBOL_GPL(pcm512x_remove); 1662 1663 #ifdef CONFIG_PM 1664 static int pcm512x_suspend(struct device *dev) 1665 { 1666 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1667 int ret; 1668 1669 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1670 PCM512x_RQPD, PCM512x_RQPD); 1671 if (ret != 0) { 1672 dev_err(dev, "Failed to request power down: %d\n", ret); 1673 return ret; 1674 } 1675 1676 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1677 pcm512x->supplies); 1678 if (ret != 0) { 1679 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1680 return ret; 1681 } 1682 1683 if (!IS_ERR(pcm512x->sclk)) 1684 clk_disable_unprepare(pcm512x->sclk); 1685 1686 return 0; 1687 } 1688 1689 static int pcm512x_resume(struct device *dev) 1690 { 1691 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1692 int ret; 1693 1694 if (!IS_ERR(pcm512x->sclk)) { 1695 ret = clk_prepare_enable(pcm512x->sclk); 1696 if (ret != 0) { 1697 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1698 return ret; 1699 } 1700 } 1701 1702 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1703 pcm512x->supplies); 1704 if (ret != 0) { 1705 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1706 return ret; 1707 } 1708 1709 regcache_cache_only(pcm512x->regmap, false); 1710 ret = regcache_sync(pcm512x->regmap); 1711 if (ret != 0) { 1712 dev_err(dev, "Failed to sync cache: %d\n", ret); 1713 return ret; 1714 } 1715 1716 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1717 PCM512x_RQPD, 0); 1718 if (ret != 0) { 1719 dev_err(dev, "Failed to remove power down: %d\n", ret); 1720 return ret; 1721 } 1722 1723 return 0; 1724 } 1725 #endif 1726 1727 const struct dev_pm_ops pcm512x_pm_ops = { 1728 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1729 }; 1730 EXPORT_SYMBOL_GPL(pcm512x_pm_ops); 1731 1732 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1733 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); 1734 MODULE_LICENSE("GPL v2"); 1735