1 /* 2 * Driver for the PCM512x CODECs 3 * 4 * Author: Mark Brown <broonie@linaro.org> 5 * Copyright 2014 Linaro Ltd 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gcd.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/tlv.h> 29 30 #include "pcm512x.h" 31 32 #define DIV_ROUND_DOWN_ULL(ll, d) \ 33 ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) 34 #define DIV_ROUND_CLOSEST_ULL(ll, d) \ 35 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) 36 37 #define PCM512x_NUM_SUPPLIES 3 38 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 39 "AVDD", 40 "DVDD", 41 "CPVDD", 42 }; 43 44 struct pcm512x_priv { 45 struct regmap *regmap; 46 struct clk *sclk; 47 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 48 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 49 int fmt; 50 int pll_in; 51 int pll_out; 52 int pll_r; 53 int pll_j; 54 int pll_d; 55 int pll_p; 56 unsigned long real_pll; 57 unsigned long overclock_pll; 58 unsigned long overclock_dac; 59 unsigned long overclock_dsp; 60 }; 61 62 /* 63 * We can't use the same notifier block for more than one supply and 64 * there's no way I can see to get from a callback to the caller 65 * except container_of(). 66 */ 67 #define PCM512x_REGULATOR_EVENT(n) \ 68 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 69 unsigned long event, void *data) \ 70 { \ 71 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 72 supply_nb[n]); \ 73 if (event & REGULATOR_EVENT_DISABLE) { \ 74 regcache_mark_dirty(pcm512x->regmap); \ 75 regcache_cache_only(pcm512x->regmap, true); \ 76 } \ 77 return 0; \ 78 } 79 80 PCM512x_REGULATOR_EVENT(0) 81 PCM512x_REGULATOR_EVENT(1) 82 PCM512x_REGULATOR_EVENT(2) 83 84 static const struct reg_default pcm512x_reg_defaults[] = { 85 { PCM512x_RESET, 0x00 }, 86 { PCM512x_POWER, 0x00 }, 87 { PCM512x_MUTE, 0x00 }, 88 { PCM512x_DSP, 0x00 }, 89 { PCM512x_PLL_REF, 0x00 }, 90 { PCM512x_DAC_REF, 0x00 }, 91 { PCM512x_DAC_ROUTING, 0x11 }, 92 { PCM512x_DSP_PROGRAM, 0x01 }, 93 { PCM512x_CLKDET, 0x00 }, 94 { PCM512x_AUTO_MUTE, 0x00 }, 95 { PCM512x_ERROR_DETECT, 0x00 }, 96 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 97 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 98 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 99 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 100 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 101 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 102 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 103 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 104 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 105 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 106 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 107 { PCM512x_VCOM_CTRL_1, 0x00 }, 108 { PCM512x_VCOM_CTRL_2, 0x01 }, 109 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 110 { PCM512x_MASTER_MODE, 0x7c }, 111 { PCM512x_GPIO_DACIN, 0x00 }, 112 { PCM512x_GPIO_PLLIN, 0x00 }, 113 { PCM512x_SYNCHRONIZE, 0x10 }, 114 { PCM512x_PLL_COEFF_0, 0x00 }, 115 { PCM512x_PLL_COEFF_1, 0x00 }, 116 { PCM512x_PLL_COEFF_2, 0x00 }, 117 { PCM512x_PLL_COEFF_3, 0x00 }, 118 { PCM512x_PLL_COEFF_4, 0x00 }, 119 { PCM512x_DSP_CLKDIV, 0x00 }, 120 { PCM512x_DAC_CLKDIV, 0x00 }, 121 { PCM512x_NCP_CLKDIV, 0x00 }, 122 { PCM512x_OSR_CLKDIV, 0x00 }, 123 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 124 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 125 { PCM512x_FS_SPEED_MODE, 0x00 }, 126 { PCM512x_IDAC_1, 0x01 }, 127 { PCM512x_IDAC_2, 0x00 }, 128 }; 129 130 static bool pcm512x_readable(struct device *dev, unsigned int reg) 131 { 132 switch (reg) { 133 case PCM512x_RESET: 134 case PCM512x_POWER: 135 case PCM512x_MUTE: 136 case PCM512x_PLL_EN: 137 case PCM512x_SPI_MISO_FUNCTION: 138 case PCM512x_DSP: 139 case PCM512x_GPIO_EN: 140 case PCM512x_BCLK_LRCLK_CFG: 141 case PCM512x_DSP_GPIO_INPUT: 142 case PCM512x_MASTER_MODE: 143 case PCM512x_PLL_REF: 144 case PCM512x_DAC_REF: 145 case PCM512x_GPIO_DACIN: 146 case PCM512x_GPIO_PLLIN: 147 case PCM512x_SYNCHRONIZE: 148 case PCM512x_PLL_COEFF_0: 149 case PCM512x_PLL_COEFF_1: 150 case PCM512x_PLL_COEFF_2: 151 case PCM512x_PLL_COEFF_3: 152 case PCM512x_PLL_COEFF_4: 153 case PCM512x_DSP_CLKDIV: 154 case PCM512x_DAC_CLKDIV: 155 case PCM512x_NCP_CLKDIV: 156 case PCM512x_OSR_CLKDIV: 157 case PCM512x_MASTER_CLKDIV_1: 158 case PCM512x_MASTER_CLKDIV_2: 159 case PCM512x_FS_SPEED_MODE: 160 case PCM512x_IDAC_1: 161 case PCM512x_IDAC_2: 162 case PCM512x_ERROR_DETECT: 163 case PCM512x_I2S_1: 164 case PCM512x_I2S_2: 165 case PCM512x_DAC_ROUTING: 166 case PCM512x_DSP_PROGRAM: 167 case PCM512x_CLKDET: 168 case PCM512x_AUTO_MUTE: 169 case PCM512x_DIGITAL_VOLUME_1: 170 case PCM512x_DIGITAL_VOLUME_2: 171 case PCM512x_DIGITAL_VOLUME_3: 172 case PCM512x_DIGITAL_MUTE_1: 173 case PCM512x_DIGITAL_MUTE_2: 174 case PCM512x_DIGITAL_MUTE_3: 175 case PCM512x_GPIO_OUTPUT_1: 176 case PCM512x_GPIO_OUTPUT_2: 177 case PCM512x_GPIO_OUTPUT_3: 178 case PCM512x_GPIO_OUTPUT_4: 179 case PCM512x_GPIO_OUTPUT_5: 180 case PCM512x_GPIO_OUTPUT_6: 181 case PCM512x_GPIO_CONTROL_1: 182 case PCM512x_GPIO_CONTROL_2: 183 case PCM512x_OVERFLOW: 184 case PCM512x_RATE_DET_1: 185 case PCM512x_RATE_DET_2: 186 case PCM512x_RATE_DET_3: 187 case PCM512x_RATE_DET_4: 188 case PCM512x_CLOCK_STATUS: 189 case PCM512x_ANALOG_MUTE_DET: 190 case PCM512x_GPIN: 191 case PCM512x_DIGITAL_MUTE_DET: 192 case PCM512x_OUTPUT_AMPLITUDE: 193 case PCM512x_ANALOG_GAIN_CTRL: 194 case PCM512x_UNDERVOLTAGE_PROT: 195 case PCM512x_ANALOG_MUTE_CTRL: 196 case PCM512x_ANALOG_GAIN_BOOST: 197 case PCM512x_VCOM_CTRL_1: 198 case PCM512x_VCOM_CTRL_2: 199 case PCM512x_CRAM_CTRL: 200 case PCM512x_FLEX_A: 201 case PCM512x_FLEX_B: 202 return true; 203 default: 204 /* There are 256 raw register addresses */ 205 return reg < 0xff; 206 } 207 } 208 209 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 210 { 211 switch (reg) { 212 case PCM512x_PLL_EN: 213 case PCM512x_OVERFLOW: 214 case PCM512x_RATE_DET_1: 215 case PCM512x_RATE_DET_2: 216 case PCM512x_RATE_DET_3: 217 case PCM512x_RATE_DET_4: 218 case PCM512x_CLOCK_STATUS: 219 case PCM512x_ANALOG_MUTE_DET: 220 case PCM512x_GPIN: 221 case PCM512x_DIGITAL_MUTE_DET: 222 case PCM512x_CRAM_CTRL: 223 return true; 224 default: 225 /* There are 256 raw register addresses */ 226 return reg < 0xff; 227 } 228 } 229 230 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 231 struct snd_ctl_elem_value *ucontrol) 232 { 233 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 234 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 235 236 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 237 return 0; 238 } 239 240 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 241 struct snd_ctl_elem_value *ucontrol) 242 { 243 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 244 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 245 246 switch (codec->dapm.bias_level) { 247 case SND_SOC_BIAS_OFF: 248 case SND_SOC_BIAS_STANDBY: 249 break; 250 default: 251 return -EBUSY; 252 } 253 254 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 255 return 0; 256 } 257 258 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 259 struct snd_ctl_elem_value *ucontrol) 260 { 261 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 262 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 263 264 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 265 return 0; 266 } 267 268 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 269 struct snd_ctl_elem_value *ucontrol) 270 { 271 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 272 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 273 274 switch (codec->dapm.bias_level) { 275 case SND_SOC_BIAS_OFF: 276 case SND_SOC_BIAS_STANDBY: 277 break; 278 default: 279 return -EBUSY; 280 } 281 282 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 283 return 0; 284 } 285 286 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 287 struct snd_ctl_elem_value *ucontrol) 288 { 289 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 290 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 291 292 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 293 return 0; 294 } 295 296 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 300 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 301 302 switch (codec->dapm.bias_level) { 303 case SND_SOC_BIAS_OFF: 304 case SND_SOC_BIAS_STANDBY: 305 break; 306 default: 307 return -EBUSY; 308 } 309 310 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 311 return 0; 312 } 313 314 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 315 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 316 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 317 318 static const char * const pcm512x_dsp_program_texts[] = { 319 "FIR interpolation with de-emphasis", 320 "Low latency IIR with de-emphasis", 321 "High attenuation with de-emphasis", 322 "Fixed process flow", 323 "Ringing-less low latency FIR", 324 }; 325 326 static const unsigned int pcm512x_dsp_program_values[] = { 327 1, 328 2, 329 3, 330 5, 331 7, 332 }; 333 334 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 335 PCM512x_DSP_PROGRAM, 0, 0x1f, 336 pcm512x_dsp_program_texts, 337 pcm512x_dsp_program_values); 338 339 static const char * const pcm512x_clk_missing_text[] = { 340 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 341 }; 342 343 static const struct soc_enum pcm512x_clk_missing = 344 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 345 346 static const char * const pcm512x_autom_text[] = { 347 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 348 }; 349 350 static const struct soc_enum pcm512x_autom_l = 351 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 352 pcm512x_autom_text); 353 354 static const struct soc_enum pcm512x_autom_r = 355 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 356 pcm512x_autom_text); 357 358 static const char * const pcm512x_ramp_rate_text[] = { 359 "1 sample/update", "2 samples/update", "4 samples/update", 360 "Immediate" 361 }; 362 363 static const struct soc_enum pcm512x_vndf = 364 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 365 pcm512x_ramp_rate_text); 366 367 static const struct soc_enum pcm512x_vnuf = 368 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 369 pcm512x_ramp_rate_text); 370 371 static const struct soc_enum pcm512x_vedf = 372 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 373 pcm512x_ramp_rate_text); 374 375 static const char * const pcm512x_ramp_step_text[] = { 376 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 377 }; 378 379 static const struct soc_enum pcm512x_vnds = 380 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 381 pcm512x_ramp_step_text); 382 383 static const struct soc_enum pcm512x_vnus = 384 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 385 pcm512x_ramp_step_text); 386 387 static const struct soc_enum pcm512x_veds = 388 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 389 pcm512x_ramp_step_text); 390 391 static const struct snd_kcontrol_new pcm512x_controls[] = { 392 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 393 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 394 SOC_DOUBLE_TLV("Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 395 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 396 SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 397 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 398 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT, 399 PCM512x_RQMR_SHIFT, 1, 1), 400 401 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 402 SOC_ENUM("DSP Program", pcm512x_dsp_program), 403 404 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 405 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 406 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 407 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 408 PCM512x_ACTL_SHIFT, 1, 0), 409 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 410 PCM512x_AMRE_SHIFT, 1, 0), 411 412 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 413 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 414 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 415 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 416 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 417 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 418 419 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 420 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 421 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 422 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 423 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 424 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 425 }; 426 427 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 428 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 429 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 430 431 SND_SOC_DAPM_OUTPUT("OUTL"), 432 SND_SOC_DAPM_OUTPUT("OUTR"), 433 }; 434 435 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 436 { "DACL", NULL, "Playback" }, 437 { "DACR", NULL, "Playback" }, 438 439 { "OUTL", NULL, "DACL" }, 440 { "OUTR", NULL, "DACR" }, 441 }; 442 443 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 444 { 445 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 446 } 447 448 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 449 { 450 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 451 } 452 453 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 454 unsigned long rate) 455 { 456 return rate + rate * pcm512x->overclock_dac / 100; 457 } 458 459 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 460 { 461 if (!pcm512x->pll_out) 462 return 25000000; 463 return pcm512x_pll_max(pcm512x); 464 } 465 466 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 467 unsigned long dac_rate) 468 { 469 /* 470 * If the DAC is not actually overclocked, use the good old 471 * NCP target rate... 472 */ 473 if (dac_rate <= 6144000) 474 return 1536000; 475 /* 476 * ...but if the DAC is in fact overclocked, bump the NCP target 477 * rate to get the recommended dividers even when overclocking. 478 */ 479 return pcm512x_dac_max(pcm512x, 1536000); 480 } 481 482 static const u32 pcm512x_dai_rates[] = { 483 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 484 88200, 96000, 176400, 192000, 384000, 485 }; 486 487 static const struct snd_pcm_hw_constraint_list constraints_slave = { 488 .count = ARRAY_SIZE(pcm512x_dai_rates), 489 .list = pcm512x_dai_rates, 490 }; 491 492 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 493 struct snd_pcm_hw_rule *rule) 494 { 495 struct pcm512x_priv *pcm512x = rule->private; 496 struct snd_interval ranges[2]; 497 int frame_size; 498 499 frame_size = snd_soc_params_to_frame_size(params); 500 if (frame_size < 0) 501 return frame_size; 502 503 switch (frame_size) { 504 case 32: 505 /* No hole when the frame size is 32. */ 506 return 0; 507 case 48: 508 case 64: 509 /* There is only one hole in the range of supported 510 * rates, but it moves with the frame size. 511 */ 512 memset(ranges, 0, sizeof(ranges)); 513 ranges[0].min = 8000; 514 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 515 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 516 ranges[1].max = 384000; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 return snd_interval_ranges(hw_param_interval(params, rule->var), 523 ARRAY_SIZE(ranges), ranges, 0); 524 } 525 526 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 527 struct snd_soc_dai *dai) 528 { 529 struct snd_soc_codec *codec = dai->codec; 530 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 531 struct device *dev = dai->dev; 532 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 533 struct snd_ratnum *rats_no_pll; 534 535 if (IS_ERR(pcm512x->sclk)) { 536 dev_err(dev, "Need SCLK for master mode: %ld\n", 537 PTR_ERR(pcm512x->sclk)); 538 return PTR_ERR(pcm512x->sclk); 539 } 540 541 if (pcm512x->pll_out) 542 return snd_pcm_hw_rule_add(substream->runtime, 0, 543 SNDRV_PCM_HW_PARAM_RATE, 544 pcm512x_hw_rule_rate, 545 pcm512x, 546 SNDRV_PCM_HW_PARAM_FRAME_BITS, 547 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 548 549 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 550 GFP_KERNEL); 551 if (!constraints_no_pll) 552 return -ENOMEM; 553 constraints_no_pll->nrats = 1; 554 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 555 if (!rats_no_pll) 556 return -ENOMEM; 557 constraints_no_pll->rats = rats_no_pll; 558 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 559 rats_no_pll->den_min = 1; 560 rats_no_pll->den_max = 128; 561 rats_no_pll->den_step = 1; 562 563 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 564 SNDRV_PCM_HW_PARAM_RATE, 565 constraints_no_pll); 566 } 567 568 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 569 struct snd_soc_dai *dai) 570 { 571 struct snd_soc_codec *codec = dai->codec; 572 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 573 struct device *dev = dai->dev; 574 struct regmap *regmap = pcm512x->regmap; 575 576 if (IS_ERR(pcm512x->sclk)) { 577 dev_info(dev, "No SCLK, using BCLK: %ld\n", 578 PTR_ERR(pcm512x->sclk)); 579 580 /* Disable reporting of missing SCLK as an error */ 581 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 582 PCM512x_IDCH, PCM512x_IDCH); 583 584 /* Switch PLL input to BCLK */ 585 regmap_update_bits(regmap, PCM512x_PLL_REF, 586 PCM512x_SREF, PCM512x_SREF_BCK); 587 } 588 589 return snd_pcm_hw_constraint_list(substream->runtime, 0, 590 SNDRV_PCM_HW_PARAM_RATE, 591 &constraints_slave); 592 } 593 594 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 595 struct snd_soc_dai *dai) 596 { 597 struct snd_soc_codec *codec = dai->codec; 598 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 599 600 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 601 case SND_SOC_DAIFMT_CBM_CFM: 602 case SND_SOC_DAIFMT_CBM_CFS: 603 return pcm512x_dai_startup_master(substream, dai); 604 605 case SND_SOC_DAIFMT_CBS_CFS: 606 return pcm512x_dai_startup_slave(substream, dai); 607 608 default: 609 return -EINVAL; 610 } 611 } 612 613 static int pcm512x_set_bias_level(struct snd_soc_codec *codec, 614 enum snd_soc_bias_level level) 615 { 616 struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev); 617 int ret; 618 619 switch (level) { 620 case SND_SOC_BIAS_ON: 621 case SND_SOC_BIAS_PREPARE: 622 break; 623 624 case SND_SOC_BIAS_STANDBY: 625 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 626 PCM512x_RQST, 0); 627 if (ret != 0) { 628 dev_err(codec->dev, "Failed to remove standby: %d\n", 629 ret); 630 return ret; 631 } 632 break; 633 634 case SND_SOC_BIAS_OFF: 635 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 636 PCM512x_RQST, PCM512x_RQST); 637 if (ret != 0) { 638 dev_err(codec->dev, "Failed to request standby: %d\n", 639 ret); 640 return ret; 641 } 642 break; 643 } 644 645 codec->dapm.bias_level = level; 646 647 return 0; 648 } 649 650 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 651 unsigned long bclk_rate) 652 { 653 struct device *dev = dai->dev; 654 struct snd_soc_codec *codec = dai->codec; 655 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 656 unsigned long sck_rate; 657 int pow2; 658 659 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 660 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 661 662 /* select sck_rate as a multiple of bclk_rate but still with 663 * as many factors of 2 as possible, as that makes it easier 664 * to find a fast DAC rate 665 */ 666 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 667 for (; pow2; pow2 >>= 1) { 668 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 669 bclk_rate * pow2); 670 if (sck_rate >= 16000000) 671 break; 672 } 673 if (!pow2) { 674 dev_err(dev, "Impossible to generate a suitable SCK\n"); 675 return 0; 676 } 677 678 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 679 return sck_rate; 680 } 681 682 /* pll_rate = pllin_rate * R * J.D / P 683 * 1 <= R <= 16 684 * 1 <= J <= 63 685 * 0 <= D <= 9999 686 * 1 <= P <= 15 687 * 64 MHz <= pll_rate <= 100 MHz 688 * if D == 0 689 * 1 MHz <= pllin_rate / P <= 20 MHz 690 * else if D > 0 691 * 6.667 MHz <= pllin_rate / P <= 20 MHz 692 * 4 <= J <= 11 693 * R = 1 694 */ 695 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 696 unsigned long pllin_rate, 697 unsigned long pll_rate) 698 { 699 struct device *dev = dai->dev; 700 struct snd_soc_codec *codec = dai->codec; 701 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 702 unsigned long common; 703 int R, J, D, P; 704 unsigned long K; /* 10000 * J.D */ 705 unsigned long num; 706 unsigned long den; 707 708 common = gcd(pll_rate, pllin_rate); 709 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 710 pll_rate, pllin_rate, common); 711 num = pll_rate / common; 712 den = pllin_rate / common; 713 714 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 715 if (pllin_rate / den > 20000000 && num < 8) { 716 num *= 20000000 / (pllin_rate / den); 717 den *= 20000000 / (pllin_rate / den); 718 } 719 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 720 721 P = den; 722 if (den <= 15 && num <= 16 * 63 723 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 724 /* Try the case with D = 0 */ 725 D = 0; 726 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 727 for (R = 16; R; R--) { 728 if (num % R) 729 continue; 730 J = num / R; 731 if (J == 0 || J > 63) 732 continue; 733 734 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 735 pcm512x->real_pll = pll_rate; 736 goto done; 737 } 738 /* no luck */ 739 } 740 741 R = 1; 742 743 if (num > 0xffffffffUL / 10000) 744 goto fallback; 745 746 /* Try to find an exact pll_rate using the D > 0 case */ 747 common = gcd(10000 * num, den); 748 num = 10000 * num / common; 749 den /= common; 750 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 751 752 for (P = den; P <= 15; P++) { 753 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 754 continue; 755 if (num * P % den) 756 continue; 757 K = num * P / den; 758 /* J == 12 is ok if D == 0 */ 759 if (K < 40000 || K > 120000) 760 continue; 761 762 J = K / 10000; 763 D = K % 10000; 764 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 765 pcm512x->real_pll = pll_rate; 766 goto done; 767 } 768 769 /* Fall back to an approximate pll_rate */ 770 771 fallback: 772 /* find smallest possible P */ 773 P = DIV_ROUND_UP(pllin_rate, 20000000); 774 if (!P) 775 P = 1; 776 else if (P > 15) { 777 dev_err(dev, "Need a slower clock as pll-input\n"); 778 return -EINVAL; 779 } 780 if (pllin_rate / P < 6667000) { 781 dev_err(dev, "Need a faster clock as pll-input\n"); 782 return -EINVAL; 783 } 784 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 785 if (K < 40000) 786 K = 40000; 787 /* J == 12 is ok if D == 0 */ 788 if (K > 120000) 789 K = 120000; 790 J = K / 10000; 791 D = K % 10000; 792 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 793 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 794 795 done: 796 pcm512x->pll_r = R; 797 pcm512x->pll_j = J; 798 pcm512x->pll_d = D; 799 pcm512x->pll_p = P; 800 return 0; 801 } 802 803 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 804 unsigned long osr_rate, 805 unsigned long pllin_rate) 806 { 807 struct snd_soc_codec *codec = dai->codec; 808 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 809 unsigned long dac_rate; 810 811 if (!pcm512x->pll_out) 812 return 0; /* no PLL to bypass, force SCK as DAC input */ 813 814 if (pllin_rate % osr_rate) 815 return 0; /* futile, quit early */ 816 817 /* run DAC no faster than 6144000 Hz */ 818 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 819 dac_rate; 820 dac_rate -= osr_rate) { 821 822 if (pllin_rate / dac_rate > 128) 823 return 0; /* DAC divider would be too big */ 824 825 if (!(pllin_rate % dac_rate)) 826 return dac_rate; 827 828 dac_rate -= osr_rate; 829 } 830 831 return 0; 832 } 833 834 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 835 struct snd_pcm_hw_params *params) 836 { 837 struct device *dev = dai->dev; 838 struct snd_soc_codec *codec = dai->codec; 839 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 840 unsigned long pllin_rate = 0; 841 unsigned long pll_rate; 842 unsigned long sck_rate; 843 unsigned long mck_rate; 844 unsigned long bclk_rate; 845 unsigned long sample_rate; 846 unsigned long osr_rate; 847 unsigned long dacsrc_rate; 848 int bclk_div; 849 int lrclk_div; 850 int dsp_div; 851 int dac_div; 852 unsigned long dac_rate; 853 int ncp_div; 854 int osr_div; 855 int ret; 856 int idac; 857 int fssp; 858 int gpio; 859 860 lrclk_div = snd_soc_params_to_frame_size(params); 861 if (lrclk_div == 0) { 862 dev_err(dev, "No LRCLK?\n"); 863 return -EINVAL; 864 } 865 866 if (!pcm512x->pll_out) { 867 sck_rate = clk_get_rate(pcm512x->sclk); 868 bclk_div = params->rate_den * 64 / lrclk_div; 869 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); 870 871 mck_rate = sck_rate; 872 } else { 873 ret = snd_soc_params_to_bclk(params); 874 if (ret < 0) { 875 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 876 return ret; 877 } 878 if (ret == 0) { 879 dev_err(dev, "No BCLK?\n"); 880 return -EINVAL; 881 } 882 bclk_rate = ret; 883 884 pllin_rate = clk_get_rate(pcm512x->sclk); 885 886 sck_rate = pcm512x_find_sck(dai, bclk_rate); 887 if (!sck_rate) 888 return -EINVAL; 889 pll_rate = 4 * sck_rate; 890 891 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 892 if (ret != 0) 893 return ret; 894 895 ret = regmap_write(pcm512x->regmap, 896 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 897 if (ret != 0) { 898 dev_err(dev, "Failed to write PLL P: %d\n", ret); 899 return ret; 900 } 901 902 ret = regmap_write(pcm512x->regmap, 903 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 904 if (ret != 0) { 905 dev_err(dev, "Failed to write PLL J: %d\n", ret); 906 return ret; 907 } 908 909 ret = regmap_write(pcm512x->regmap, 910 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 911 if (ret != 0) { 912 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 913 return ret; 914 } 915 916 ret = regmap_write(pcm512x->regmap, 917 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 918 if (ret != 0) { 919 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 920 return ret; 921 } 922 923 ret = regmap_write(pcm512x->regmap, 924 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 925 if (ret != 0) { 926 dev_err(dev, "Failed to write PLL R: %d\n", ret); 927 return ret; 928 } 929 930 mck_rate = pcm512x->real_pll; 931 932 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 933 } 934 935 if (bclk_div > 128) { 936 dev_err(dev, "Failed to find BCLK divider\n"); 937 return -EINVAL; 938 } 939 940 /* the actual rate */ 941 sample_rate = sck_rate / bclk_div / lrclk_div; 942 osr_rate = 16 * sample_rate; 943 944 /* run DSP no faster than 50 MHz */ 945 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 946 947 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 948 if (dac_rate) { 949 /* the desired clock rate is "compatible" with the pll input 950 * clock, so use that clock as dac input instead of the pll 951 * output clock since the pll will introduce jitter and thus 952 * noise. 953 */ 954 dev_dbg(dev, "using pll input as dac input\n"); 955 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 956 PCM512x_SDAC, PCM512x_SDAC_GPIO); 957 if (ret != 0) { 958 dev_err(codec->dev, 959 "Failed to set gpio as dacref: %d\n", ret); 960 return ret; 961 } 962 963 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 964 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 965 PCM512x_GREF, gpio); 966 if (ret != 0) { 967 dev_err(codec->dev, 968 "Failed to set gpio %d as dacin: %d\n", 969 pcm512x->pll_in, ret); 970 return ret; 971 } 972 973 dacsrc_rate = pllin_rate; 974 } else { 975 /* run DAC no faster than 6144000 Hz */ 976 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 977 / osr_rate; 978 unsigned long sck_mul = sck_rate / osr_rate; 979 980 for (; dac_mul; dac_mul--) { 981 if (!(sck_mul % dac_mul)) 982 break; 983 } 984 if (!dac_mul) { 985 dev_err(dev, "Failed to find DAC rate\n"); 986 return -EINVAL; 987 } 988 989 dac_rate = dac_mul * osr_rate; 990 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 991 dac_rate, sample_rate); 992 993 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 994 PCM512x_SDAC, PCM512x_SDAC_SCK); 995 if (ret != 0) { 996 dev_err(codec->dev, 997 "Failed to set sck as dacref: %d\n", ret); 998 return ret; 999 } 1000 1001 dacsrc_rate = sck_rate; 1002 } 1003 1004 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1005 if (osr_div > 128) { 1006 dev_err(dev, "Failed to find OSR divider\n"); 1007 return -EINVAL; 1008 } 1009 1010 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1011 if (dac_div > 128) { 1012 dev_err(dev, "Failed to find DAC divider\n"); 1013 return -EINVAL; 1014 } 1015 dac_rate = dacsrc_rate / dac_div; 1016 1017 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1018 pcm512x_ncp_target(pcm512x, dac_rate)); 1019 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1020 /* run NCP no faster than 2048000 Hz, but why? */ 1021 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1022 if (ncp_div > 128) { 1023 dev_err(dev, "Failed to find NCP divider\n"); 1024 return -EINVAL; 1025 } 1026 } 1027 1028 idac = mck_rate / (dsp_div * sample_rate); 1029 1030 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1031 if (ret != 0) { 1032 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1033 return ret; 1034 } 1035 1036 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1037 if (ret != 0) { 1038 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1039 return ret; 1040 } 1041 1042 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1043 if (ret != 0) { 1044 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1045 return ret; 1046 } 1047 1048 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1049 if (ret != 0) { 1050 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1051 return ret; 1052 } 1053 1054 ret = regmap_write(pcm512x->regmap, 1055 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1056 if (ret != 0) { 1057 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1058 return ret; 1059 } 1060 1061 ret = regmap_write(pcm512x->regmap, 1062 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1063 if (ret != 0) { 1064 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1065 return ret; 1066 } 1067 1068 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1069 if (ret != 0) { 1070 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1071 return ret; 1072 } 1073 1074 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1075 if (ret != 0) { 1076 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1077 return ret; 1078 } 1079 1080 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1081 fssp = PCM512x_FSSP_48KHZ; 1082 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1083 fssp = PCM512x_FSSP_96KHZ; 1084 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1085 fssp = PCM512x_FSSP_192KHZ; 1086 else 1087 fssp = PCM512x_FSSP_384KHZ; 1088 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1089 PCM512x_FSSP, fssp); 1090 if (ret != 0) { 1091 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret); 1092 return ret; 1093 } 1094 1095 dev_dbg(codec->dev, "DSP divider %d\n", dsp_div); 1096 dev_dbg(codec->dev, "DAC divider %d\n", dac_div); 1097 dev_dbg(codec->dev, "NCP divider %d\n", ncp_div); 1098 dev_dbg(codec->dev, "OSR divider %d\n", osr_div); 1099 dev_dbg(codec->dev, "BCK divider %d\n", bclk_div); 1100 dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div); 1101 dev_dbg(codec->dev, "IDAC %d\n", idac); 1102 dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp); 1103 1104 return 0; 1105 } 1106 1107 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1108 struct snd_pcm_hw_params *params, 1109 struct snd_soc_dai *dai) 1110 { 1111 struct snd_soc_codec *codec = dai->codec; 1112 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 1113 int alen; 1114 int gpio; 1115 int clock_output; 1116 int master_mode; 1117 int ret; 1118 1119 dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n", 1120 params_rate(params), 1121 params_channels(params)); 1122 1123 switch (snd_pcm_format_width(params_format(params))) { 1124 case 16: 1125 alen = PCM512x_ALEN_16; 1126 break; 1127 case 20: 1128 alen = PCM512x_ALEN_20; 1129 break; 1130 case 24: 1131 alen = PCM512x_ALEN_24; 1132 break; 1133 case 32: 1134 alen = PCM512x_ALEN_32; 1135 break; 1136 default: 1137 dev_err(codec->dev, "Bad frame size: %d\n", 1138 snd_pcm_format_width(params_format(params))); 1139 return -EINVAL; 1140 } 1141 1142 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1143 case SND_SOC_DAIFMT_CBS_CFS: 1144 ret = regmap_update_bits(pcm512x->regmap, 1145 PCM512x_BCLK_LRCLK_CFG, 1146 PCM512x_BCKP 1147 | PCM512x_BCKO | PCM512x_LRKO, 1148 0); 1149 if (ret != 0) { 1150 dev_err(codec->dev, 1151 "Failed to enable slave mode: %d\n", ret); 1152 return ret; 1153 } 1154 1155 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1156 PCM512x_DCAS, 0); 1157 if (ret != 0) { 1158 dev_err(codec->dev, 1159 "Failed to enable clock divider autoset: %d\n", 1160 ret); 1161 return ret; 1162 } 1163 return 0; 1164 case SND_SOC_DAIFMT_CBM_CFM: 1165 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1166 master_mode = PCM512x_RLRK | PCM512x_RBCK; 1167 break; 1168 case SND_SOC_DAIFMT_CBM_CFS: 1169 clock_output = PCM512x_BCKO; 1170 master_mode = PCM512x_RBCK; 1171 break; 1172 default: 1173 return -EINVAL; 1174 } 1175 1176 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1177 PCM512x_ALEN, alen); 1178 if (ret != 0) { 1179 dev_err(codec->dev, "Failed to set frame size: %d\n", ret); 1180 return ret; 1181 } 1182 1183 if (pcm512x->pll_out) { 1184 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1185 if (ret != 0) { 1186 dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret); 1187 return ret; 1188 } 1189 1190 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1191 if (ret != 0) { 1192 dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret); 1193 return ret; 1194 } 1195 1196 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1197 PCM512x_IDFS | PCM512x_IDBK 1198 | PCM512x_IDSK | PCM512x_IDCH 1199 | PCM512x_IDCM | PCM512x_DCAS 1200 | PCM512x_IPLK, 1201 PCM512x_IDFS | PCM512x_IDBK 1202 | PCM512x_IDSK | PCM512x_IDCH 1203 | PCM512x_DCAS); 1204 if (ret != 0) { 1205 dev_err(codec->dev, 1206 "Failed to ignore auto-clock failures: %d\n", 1207 ret); 1208 return ret; 1209 } 1210 } else { 1211 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1212 PCM512x_IDFS | PCM512x_IDBK 1213 | PCM512x_IDSK | PCM512x_IDCH 1214 | PCM512x_IDCM | PCM512x_DCAS 1215 | PCM512x_IPLK, 1216 PCM512x_IDFS | PCM512x_IDBK 1217 | PCM512x_IDSK | PCM512x_IDCH 1218 | PCM512x_DCAS | PCM512x_IPLK); 1219 if (ret != 0) { 1220 dev_err(codec->dev, 1221 "Failed to ignore auto-clock failures: %d\n", 1222 ret); 1223 return ret; 1224 } 1225 1226 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1227 PCM512x_PLLE, 0); 1228 if (ret != 0) { 1229 dev_err(codec->dev, "Failed to disable pll: %d\n", ret); 1230 return ret; 1231 } 1232 } 1233 1234 ret = pcm512x_set_dividers(dai, params); 1235 if (ret != 0) 1236 return ret; 1237 1238 if (pcm512x->pll_out) { 1239 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1240 PCM512x_SREF, PCM512x_SREF_GPIO); 1241 if (ret != 0) { 1242 dev_err(codec->dev, 1243 "Failed to set gpio as pllref: %d\n", ret); 1244 return ret; 1245 } 1246 1247 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1248 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1249 PCM512x_GREF, gpio); 1250 if (ret != 0) { 1251 dev_err(codec->dev, 1252 "Failed to set gpio %d as pllin: %d\n", 1253 pcm512x->pll_in, ret); 1254 return ret; 1255 } 1256 1257 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1258 PCM512x_PLLE, PCM512x_PLLE); 1259 if (ret != 0) { 1260 dev_err(codec->dev, "Failed to enable pll: %d\n", ret); 1261 return ret; 1262 } 1263 } 1264 1265 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1266 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1267 clock_output); 1268 if (ret != 0) { 1269 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret); 1270 return ret; 1271 } 1272 1273 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1274 PCM512x_RLRK | PCM512x_RBCK, 1275 master_mode); 1276 if (ret != 0) { 1277 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret); 1278 return ret; 1279 } 1280 1281 if (pcm512x->pll_out) { 1282 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1283 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1284 gpio, gpio); 1285 if (ret != 0) { 1286 dev_err(codec->dev, "Failed to enable gpio %d: %d\n", 1287 pcm512x->pll_out, ret); 1288 return ret; 1289 } 1290 1291 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1292 ret = regmap_update_bits(pcm512x->regmap, gpio, 1293 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1294 if (ret != 0) { 1295 dev_err(codec->dev, "Failed to output pll on %d: %d\n", 1296 ret, pcm512x->pll_out); 1297 return ret; 1298 } 1299 1300 gpio = PCM512x_G1OE << (4 - 1); 1301 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1302 gpio, gpio); 1303 if (ret != 0) { 1304 dev_err(codec->dev, "Failed to enable gpio %d: %d\n", 1305 4, ret); 1306 return ret; 1307 } 1308 1309 gpio = PCM512x_GPIO_OUTPUT_1 + 4 - 1; 1310 ret = regmap_update_bits(pcm512x->regmap, gpio, 1311 PCM512x_GxSL, PCM512x_GxSL_PLLLK); 1312 if (ret != 0) { 1313 dev_err(codec->dev, 1314 "Failed to output pll lock on %d: %d\n", 1315 ret, 4); 1316 return ret; 1317 } 1318 } 1319 1320 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1321 PCM512x_RQSY, PCM512x_RQSY_HALT); 1322 if (ret != 0) { 1323 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret); 1324 return ret; 1325 } 1326 1327 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1328 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1329 if (ret != 0) { 1330 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret); 1331 return ret; 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1338 { 1339 struct snd_soc_codec *codec = dai->codec; 1340 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); 1341 1342 pcm512x->fmt = fmt; 1343 1344 return 0; 1345 } 1346 1347 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1348 .startup = pcm512x_dai_startup, 1349 .hw_params = pcm512x_hw_params, 1350 .set_fmt = pcm512x_set_fmt, 1351 }; 1352 1353 static struct snd_soc_dai_driver pcm512x_dai = { 1354 .name = "pcm512x-hifi", 1355 .playback = { 1356 .stream_name = "Playback", 1357 .channels_min = 2, 1358 .channels_max = 2, 1359 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1360 .rate_min = 8000, 1361 .rate_max = 384000, 1362 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1363 SNDRV_PCM_FMTBIT_S24_LE | 1364 SNDRV_PCM_FMTBIT_S32_LE 1365 }, 1366 .ops = &pcm512x_dai_ops, 1367 }; 1368 1369 static struct snd_soc_codec_driver pcm512x_codec_driver = { 1370 .set_bias_level = pcm512x_set_bias_level, 1371 .idle_bias_off = true, 1372 1373 .controls = pcm512x_controls, 1374 .num_controls = ARRAY_SIZE(pcm512x_controls), 1375 .dapm_widgets = pcm512x_dapm_widgets, 1376 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1377 .dapm_routes = pcm512x_dapm_routes, 1378 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1379 }; 1380 1381 static const struct regmap_range_cfg pcm512x_range = { 1382 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1383 .range_max = PCM512x_MAX_REGISTER, 1384 .selector_reg = PCM512x_PAGE, 1385 .selector_mask = 0xff, 1386 .window_start = 0, .window_len = 0x100, 1387 }; 1388 1389 const struct regmap_config pcm512x_regmap = { 1390 .reg_bits = 8, 1391 .val_bits = 8, 1392 1393 .readable_reg = pcm512x_readable, 1394 .volatile_reg = pcm512x_volatile, 1395 1396 .ranges = &pcm512x_range, 1397 .num_ranges = 1, 1398 1399 .max_register = PCM512x_MAX_REGISTER, 1400 .reg_defaults = pcm512x_reg_defaults, 1401 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1402 .cache_type = REGCACHE_RBTREE, 1403 }; 1404 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1405 1406 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1407 { 1408 struct pcm512x_priv *pcm512x; 1409 int i, ret; 1410 1411 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1412 if (!pcm512x) 1413 return -ENOMEM; 1414 1415 dev_set_drvdata(dev, pcm512x); 1416 pcm512x->regmap = regmap; 1417 1418 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1419 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1420 1421 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1422 pcm512x->supplies); 1423 if (ret != 0) { 1424 dev_err(dev, "Failed to get supplies: %d\n", ret); 1425 return ret; 1426 } 1427 1428 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1429 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1430 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1431 1432 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1433 ret = regulator_register_notifier(pcm512x->supplies[i].consumer, 1434 &pcm512x->supply_nb[i]); 1435 if (ret != 0) { 1436 dev_err(dev, 1437 "Failed to register regulator notifier: %d\n", 1438 ret); 1439 } 1440 } 1441 1442 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1443 pcm512x->supplies); 1444 if (ret != 0) { 1445 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1446 return ret; 1447 } 1448 1449 /* Reset the device, verifying I/O in the process for I2C */ 1450 ret = regmap_write(regmap, PCM512x_RESET, 1451 PCM512x_RSTM | PCM512x_RSTR); 1452 if (ret != 0) { 1453 dev_err(dev, "Failed to reset device: %d\n", ret); 1454 goto err; 1455 } 1456 1457 ret = regmap_write(regmap, PCM512x_RESET, 0); 1458 if (ret != 0) { 1459 dev_err(dev, "Failed to reset device: %d\n", ret); 1460 goto err; 1461 } 1462 1463 pcm512x->sclk = devm_clk_get(dev, NULL); 1464 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) 1465 return -EPROBE_DEFER; 1466 if (!IS_ERR(pcm512x->sclk)) { 1467 ret = clk_prepare_enable(pcm512x->sclk); 1468 if (ret != 0) { 1469 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1470 return ret; 1471 } 1472 } 1473 1474 /* Default to standby mode */ 1475 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1476 PCM512x_RQST, PCM512x_RQST); 1477 if (ret != 0) { 1478 dev_err(dev, "Failed to request standby: %d\n", 1479 ret); 1480 goto err_clk; 1481 } 1482 1483 pm_runtime_set_active(dev); 1484 pm_runtime_enable(dev); 1485 pm_runtime_idle(dev); 1486 1487 #ifdef CONFIG_OF 1488 if (dev->of_node) { 1489 const struct device_node *np = dev->of_node; 1490 u32 val; 1491 1492 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1493 if (val > 6) { 1494 dev_err(dev, "Invalid pll-in\n"); 1495 ret = -EINVAL; 1496 goto err_clk; 1497 } 1498 pcm512x->pll_in = val; 1499 } 1500 1501 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1502 if (val > 6) { 1503 dev_err(dev, "Invalid pll-out\n"); 1504 ret = -EINVAL; 1505 goto err_clk; 1506 } 1507 pcm512x->pll_out = val; 1508 } 1509 1510 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1511 dev_err(dev, 1512 "Error: both pll-in and pll-out, or none\n"); 1513 ret = -EINVAL; 1514 goto err_clk; 1515 } 1516 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1517 dev_err(dev, "Error: pll-in == pll-out\n"); 1518 ret = -EINVAL; 1519 goto err_clk; 1520 } 1521 } 1522 #endif 1523 1524 ret = snd_soc_register_codec(dev, &pcm512x_codec_driver, 1525 &pcm512x_dai, 1); 1526 if (ret != 0) { 1527 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1528 goto err_pm; 1529 } 1530 1531 return 0; 1532 1533 err_pm: 1534 pm_runtime_disable(dev); 1535 err_clk: 1536 if (!IS_ERR(pcm512x->sclk)) 1537 clk_disable_unprepare(pcm512x->sclk); 1538 err: 1539 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1540 pcm512x->supplies); 1541 return ret; 1542 } 1543 EXPORT_SYMBOL_GPL(pcm512x_probe); 1544 1545 void pcm512x_remove(struct device *dev) 1546 { 1547 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1548 1549 snd_soc_unregister_codec(dev); 1550 pm_runtime_disable(dev); 1551 if (!IS_ERR(pcm512x->sclk)) 1552 clk_disable_unprepare(pcm512x->sclk); 1553 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1554 pcm512x->supplies); 1555 } 1556 EXPORT_SYMBOL_GPL(pcm512x_remove); 1557 1558 #ifdef CONFIG_PM 1559 static int pcm512x_suspend(struct device *dev) 1560 { 1561 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1562 int ret; 1563 1564 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1565 PCM512x_RQPD, PCM512x_RQPD); 1566 if (ret != 0) { 1567 dev_err(dev, "Failed to request power down: %d\n", ret); 1568 return ret; 1569 } 1570 1571 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1572 pcm512x->supplies); 1573 if (ret != 0) { 1574 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1575 return ret; 1576 } 1577 1578 if (!IS_ERR(pcm512x->sclk)) 1579 clk_disable_unprepare(pcm512x->sclk); 1580 1581 return 0; 1582 } 1583 1584 static int pcm512x_resume(struct device *dev) 1585 { 1586 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1587 int ret; 1588 1589 if (!IS_ERR(pcm512x->sclk)) { 1590 ret = clk_prepare_enable(pcm512x->sclk); 1591 if (ret != 0) { 1592 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1593 return ret; 1594 } 1595 } 1596 1597 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1598 pcm512x->supplies); 1599 if (ret != 0) { 1600 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1601 return ret; 1602 } 1603 1604 regcache_cache_only(pcm512x->regmap, false); 1605 ret = regcache_sync(pcm512x->regmap); 1606 if (ret != 0) { 1607 dev_err(dev, "Failed to sync cache: %d\n", ret); 1608 return ret; 1609 } 1610 1611 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1612 PCM512x_RQPD, 0); 1613 if (ret != 0) { 1614 dev_err(dev, "Failed to remove power down: %d\n", ret); 1615 return ret; 1616 } 1617 1618 return 0; 1619 } 1620 #endif 1621 1622 const struct dev_pm_ops pcm512x_pm_ops = { 1623 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1624 }; 1625 EXPORT_SYMBOL_GPL(pcm512x_pm_ops); 1626 1627 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1628 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>"); 1629 MODULE_LICENSE("GPL v2"); 1630