1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCM3168A codec driver 4 * 5 * Copyright (C) 2015 Imagination Technologies Ltd. 6 * 7 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "pcm3168a.h" 21 22 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 23 SNDRV_PCM_FMTBIT_S24_3LE | \ 24 SNDRV_PCM_FMTBIT_S24_LE | \ 25 SNDRV_PCM_FMTBIT_S32_LE) 26 27 #define PCM3168A_FMT_I2S 0x0 28 #define PCM3168A_FMT_LEFT_J 0x1 29 #define PCM3168A_FMT_RIGHT_J 0x2 30 #define PCM3168A_FMT_RIGHT_J_16 0x3 31 #define PCM3168A_FMT_DSP_A 0x4 32 #define PCM3168A_FMT_DSP_B 0x5 33 #define PCM3168A_FMT_I2S_TDM 0x6 34 #define PCM3168A_FMT_LEFT_J_TDM 0x7 35 #define PCM3168A_FMT_DSP_MASK 0x4 36 37 #define PCM3168A_NUM_SUPPLIES 6 38 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 39 "VDD1", 40 "VDD2", 41 "VCCAD1", 42 "VCCAD2", 43 "VCCDA1", 44 "VCCDA2" 45 }; 46 47 struct pcm3168a_priv { 48 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 49 struct regmap *regmap; 50 struct clk *scki; 51 bool adc_master_mode; 52 bool dac_master_mode; 53 unsigned long sysclk; 54 unsigned int adc_fmt; 55 unsigned int dac_fmt; 56 int tdm_slots; 57 u32 tdm_mask[2]; 58 int slot_width; 59 }; 60 61 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 62 63 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 64 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 65 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 66 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 67 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 68 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 69 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 70 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 71 72 static const char *const pcm3168a_volume_type[] = { 73 "Individual", "Master + Individual" }; 74 75 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 76 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 77 78 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 79 80 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 81 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 82 83 static const char *const pcm3168a_demp[] = { 84 "Disabled", "48khz", "44.1khz", "32khz" }; 85 86 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 87 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 88 89 static const char *const pcm3168a_zf_func[] = { 90 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 91 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 92 93 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 94 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 95 96 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 97 98 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 99 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 100 101 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 102 103 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 104 0, 1, pcm3168a_con); 105 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 106 2, 3, pcm3168a_con); 107 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 108 4, 5, pcm3168a_con); 109 110 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 111 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 112 113 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 114 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 115 116 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 117 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 118 119 /* -100db to 0db, register values 0-54 cause mute */ 120 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 121 122 /* -100db to 20db, register values 0-14 cause mute */ 123 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 124 125 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 126 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 127 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 128 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 129 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 130 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 131 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 132 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 133 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 134 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 135 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 136 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 137 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 138 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 139 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 140 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 141 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 142 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 143 pcm3168a_dac_tlv), 144 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 145 PCM3168A_DAC_VOL_CHAN_START, 146 PCM3168A_DAC_VOL_CHAN_START + 1, 147 0, 54, 255, 0, pcm3168a_dac_tlv), 148 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 149 PCM3168A_DAC_VOL_CHAN_START + 2, 150 PCM3168A_DAC_VOL_CHAN_START + 3, 151 0, 54, 255, 0, pcm3168a_dac_tlv), 152 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 153 PCM3168A_DAC_VOL_CHAN_START + 4, 154 PCM3168A_DAC_VOL_CHAN_START + 5, 155 0, 54, 255, 0, pcm3168a_dac_tlv), 156 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 157 PCM3168A_DAC_VOL_CHAN_START + 6, 158 PCM3168A_DAC_VOL_CHAN_START + 7, 159 0, 54, 255, 0, pcm3168a_dac_tlv), 160 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 161 PCM3168A_ADC_BYP_SHIFT, 1, 1), 162 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 163 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 164 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 165 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 166 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 167 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 168 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 169 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 170 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 171 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 172 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 173 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 174 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 175 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 176 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 177 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 178 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 179 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 180 pcm3168a_adc_tlv), 181 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 182 PCM3168A_ADC_VOL_CHAN_START, 183 PCM3168A_ADC_VOL_CHAN_START + 1, 184 0, 14, 255, 0, pcm3168a_adc_tlv), 185 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 186 PCM3168A_ADC_VOL_CHAN_START + 2, 187 PCM3168A_ADC_VOL_CHAN_START + 3, 188 0, 14, 255, 0, pcm3168a_adc_tlv), 189 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 190 PCM3168A_ADC_VOL_CHAN_START + 4, 191 PCM3168A_ADC_VOL_CHAN_START + 5, 192 0, 14, 255, 0, pcm3168a_adc_tlv) 193 }; 194 195 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 196 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 197 PCM3168A_DAC_OPEDA_SHIFT, 1), 198 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 199 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 200 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 201 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 202 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 203 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 204 205 SND_SOC_DAPM_OUTPUT("AOUT1L"), 206 SND_SOC_DAPM_OUTPUT("AOUT1R"), 207 SND_SOC_DAPM_OUTPUT("AOUT2L"), 208 SND_SOC_DAPM_OUTPUT("AOUT2R"), 209 SND_SOC_DAPM_OUTPUT("AOUT3L"), 210 SND_SOC_DAPM_OUTPUT("AOUT3R"), 211 SND_SOC_DAPM_OUTPUT("AOUT4L"), 212 SND_SOC_DAPM_OUTPUT("AOUT4R"), 213 214 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 215 PCM3168A_ADC_PSVAD_SHIFT, 1), 216 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 217 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 218 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 219 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 220 221 SND_SOC_DAPM_INPUT("AIN1L"), 222 SND_SOC_DAPM_INPUT("AIN1R"), 223 SND_SOC_DAPM_INPUT("AIN2L"), 224 SND_SOC_DAPM_INPUT("AIN2R"), 225 SND_SOC_DAPM_INPUT("AIN3L"), 226 SND_SOC_DAPM_INPUT("AIN3R") 227 }; 228 229 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 230 /* Playback */ 231 { "AOUT1L", NULL, "DAC1" }, 232 { "AOUT1R", NULL, "DAC1" }, 233 234 { "AOUT2L", NULL, "DAC2" }, 235 { "AOUT2R", NULL, "DAC2" }, 236 237 { "AOUT3L", NULL, "DAC3" }, 238 { "AOUT3R", NULL, "DAC3" }, 239 240 { "AOUT4L", NULL, "DAC4" }, 241 { "AOUT4R", NULL, "DAC4" }, 242 243 /* Capture */ 244 { "ADC1", NULL, "AIN1L" }, 245 { "ADC1", NULL, "AIN1R" }, 246 247 { "ADC2", NULL, "AIN2L" }, 248 { "ADC2", NULL, "AIN2R" }, 249 250 { "ADC3", NULL, "AIN3L" }, 251 { "ADC3", NULL, "AIN3R" } 252 }; 253 254 static unsigned int pcm3168a_scki_ratios[] = { 255 768, 256 512, 257 384, 258 256, 259 192, 260 128 261 }; 262 263 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 264 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 265 266 #define PCM1368A_MAX_SYSCLK 36864000 267 268 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 269 { 270 int ret; 271 272 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 273 if (ret) 274 return ret; 275 276 /* Internal reset is de-asserted after 3846 SCKI cycles */ 277 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 278 279 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 280 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 281 } 282 283 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) 284 { 285 struct snd_soc_component *component = dai->component; 286 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 287 288 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 289 290 return 0; 291 } 292 293 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 294 int clk_id, unsigned int freq, int dir) 295 { 296 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 297 int ret; 298 299 if (freq > PCM1368A_MAX_SYSCLK) 300 return -EINVAL; 301 302 ret = clk_set_rate(pcm3168a->scki, freq); 303 if (ret) 304 return ret; 305 306 pcm3168a->sysclk = freq; 307 308 return 0; 309 } 310 311 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, 312 unsigned int format, bool dac) 313 { 314 struct snd_soc_component *component = dai->component; 315 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 316 u32 fmt, reg, mask, shift; 317 bool master_mode; 318 319 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 320 case SND_SOC_DAIFMT_LEFT_J: 321 fmt = PCM3168A_FMT_LEFT_J; 322 break; 323 case SND_SOC_DAIFMT_I2S: 324 fmt = PCM3168A_FMT_I2S; 325 break; 326 case SND_SOC_DAIFMT_RIGHT_J: 327 fmt = PCM3168A_FMT_RIGHT_J; 328 break; 329 case SND_SOC_DAIFMT_DSP_A: 330 fmt = PCM3168A_FMT_DSP_A; 331 break; 332 case SND_SOC_DAIFMT_DSP_B: 333 fmt = PCM3168A_FMT_DSP_B; 334 break; 335 default: 336 dev_err(component->dev, "unsupported dai format\n"); 337 return -EINVAL; 338 } 339 340 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 341 case SND_SOC_DAIFMT_CBS_CFS: 342 master_mode = false; 343 break; 344 case SND_SOC_DAIFMT_CBM_CFM: 345 master_mode = true; 346 break; 347 default: 348 dev_err(component->dev, "unsupported master/slave mode\n"); 349 return -EINVAL; 350 } 351 352 switch (format & SND_SOC_DAIFMT_INV_MASK) { 353 case SND_SOC_DAIFMT_NB_NF: 354 break; 355 default: 356 return -EINVAL; 357 } 358 359 if (dac) { 360 reg = PCM3168A_DAC_PWR_MST_FMT; 361 mask = PCM3168A_DAC_FMT_MASK; 362 shift = PCM3168A_DAC_FMT_SHIFT; 363 pcm3168a->dac_master_mode = master_mode; 364 pcm3168a->dac_fmt = fmt; 365 } else { 366 reg = PCM3168A_ADC_MST_FMT; 367 mask = PCM3168A_ADC_FMTAD_MASK; 368 shift = PCM3168A_ADC_FMTAD_SHIFT; 369 pcm3168a->adc_master_mode = master_mode; 370 pcm3168a->adc_fmt = fmt; 371 } 372 373 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 374 375 return 0; 376 } 377 378 static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai, 379 unsigned int format) 380 { 381 return pcm3168a_set_dai_fmt(dai, format, true); 382 } 383 384 static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai, 385 unsigned int format) 386 { 387 return pcm3168a_set_dai_fmt(dai, format, false); 388 } 389 390 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 391 unsigned int rx_mask, int slots, 392 int slot_width) 393 { 394 struct snd_soc_component *component = dai->component; 395 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 396 397 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 398 dev_err(component->dev, 399 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 400 tx_mask, rx_mask, slots); 401 return -EINVAL; 402 } 403 404 if (slot_width && 405 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) { 406 dev_err(component->dev, "Unsupported slot_width %d\n", 407 slot_width); 408 return -EINVAL; 409 } 410 411 if (pcm3168a->tdm_slots && pcm3168a->tdm_slots != slots) { 412 dev_err(component->dev, "Not matching slots %d vs %d\n", 413 pcm3168a->tdm_slots, slots); 414 return -EINVAL; 415 } 416 417 if (pcm3168a->slot_width && pcm3168a->slot_width != slot_width) { 418 dev_err(component->dev, "Not matching slot_width %d vs %d\n", 419 pcm3168a->slot_width, slot_width); 420 return -EINVAL; 421 } 422 423 pcm3168a->tdm_slots = slots; 424 pcm3168a->slot_width = slot_width; 425 pcm3168a->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 426 pcm3168a->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 427 428 return 0; 429 } 430 431 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 432 struct snd_pcm_hw_params *params, 433 struct snd_soc_dai *dai) 434 { 435 struct snd_soc_component *component = dai->component; 436 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 437 bool tx, master_mode; 438 u32 val, mask, shift, reg; 439 unsigned int rate, fmt, ratio, max_ratio; 440 unsigned int tdm_slots; 441 int i, slot_width; 442 443 rate = params_rate(params); 444 445 ratio = pcm3168a->sysclk / rate; 446 447 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 448 if (tx) { 449 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 450 reg = PCM3168A_DAC_PWR_MST_FMT; 451 mask = PCM3168A_DAC_MSDA_MASK; 452 shift = PCM3168A_DAC_MSDA_SHIFT; 453 master_mode = pcm3168a->dac_master_mode; 454 fmt = pcm3168a->dac_fmt; 455 } else { 456 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 457 reg = PCM3168A_ADC_MST_FMT; 458 mask = PCM3168A_ADC_MSAD_MASK; 459 shift = PCM3168A_ADC_MSAD_SHIFT; 460 master_mode = pcm3168a->adc_master_mode; 461 fmt = pcm3168a->adc_fmt; 462 } 463 464 for (i = 0; i < max_ratio; i++) { 465 if (pcm3168a_scki_ratios[i] == ratio) 466 break; 467 } 468 469 if (i == max_ratio) { 470 dev_err(component->dev, "unsupported sysclk ratio\n"); 471 return -EINVAL; 472 } 473 474 if (pcm3168a->slot_width) 475 slot_width = pcm3168a->slot_width; 476 else 477 slot_width = params_width(params); 478 479 switch (slot_width) { 480 case 16: 481 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 482 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n"); 483 return -EINVAL; 484 } 485 fmt = PCM3168A_FMT_RIGHT_J_16; 486 break; 487 case 24: 488 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 489 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n"); 490 return -EINVAL; 491 } 492 break; 493 case 32: 494 break; 495 default: 496 dev_err(component->dev, "unsupported frame size: %d\n", slot_width); 497 return -EINVAL; 498 } 499 500 if (pcm3168a->tdm_slots) 501 tdm_slots = pcm3168a->tdm_slots; 502 else 503 tdm_slots = params_channels(params); 504 505 /* 506 * Switch the codec to TDM mode when more than 2 TDM slots are needed 507 * for the stream. 508 * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually) 509 * then DIN1/DOUT1 is used in TDM mode. 510 * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is 511 * used in normal mode, no need to switch to TDM modes. 512 */ 513 if (tdm_slots > 2) { 514 switch (fmt) { 515 case PCM3168A_FMT_I2S: 516 case PCM3168A_FMT_DSP_A: 517 fmt = PCM3168A_FMT_I2S_TDM; 518 break; 519 case PCM3168A_FMT_LEFT_J: 520 case PCM3168A_FMT_DSP_B: 521 fmt = PCM3168A_FMT_LEFT_J_TDM; 522 break; 523 default: 524 dev_err(component->dev, 525 "TDM is supported under DSP/I2S/Left_J only\n"); 526 return -EINVAL; 527 } 528 } 529 530 if (master_mode) 531 val = ((i + 1) << shift); 532 else 533 val = 0; 534 535 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 536 537 if (tx) { 538 mask = PCM3168A_DAC_FMT_MASK; 539 shift = PCM3168A_DAC_FMT_SHIFT; 540 } else { 541 mask = PCM3168A_ADC_FMTAD_MASK; 542 shift = PCM3168A_ADC_FMTAD_SHIFT; 543 } 544 545 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 546 547 return 0; 548 } 549 550 static int pcm3168a_startup(struct snd_pcm_substream *substream, 551 struct snd_soc_dai *dai) 552 { 553 struct snd_soc_component *component = dai->component; 554 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 555 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 556 unsigned int fmt; 557 unsigned int sample_min; 558 unsigned int channel_max; 559 unsigned int channel_maxs[] = { 560 6, /* rx */ 561 8 /* tx */ 562 }; 563 564 if (tx) 565 fmt = pcm3168a->dac_fmt; 566 else 567 fmt = pcm3168a->adc_fmt; 568 569 /* 570 * Available Data Bits 571 * 572 * RIGHT_J : 24 / 16 573 * LEFT_J : 24 574 * I2S : 24 575 * 576 * TDM available 577 * 578 * I2S 579 * LEFT_J 580 */ 581 switch (fmt) { 582 case PCM3168A_FMT_RIGHT_J: 583 sample_min = 16; 584 channel_max = 2; 585 break; 586 case PCM3168A_FMT_LEFT_J: 587 case PCM3168A_FMT_I2S: 588 case PCM3168A_FMT_DSP_A: 589 case PCM3168A_FMT_DSP_B: 590 sample_min = 24; 591 channel_max = channel_maxs[tx]; 592 break; 593 default: 594 sample_min = 24; 595 channel_max = 2; 596 } 597 598 snd_pcm_hw_constraint_minmax(substream->runtime, 599 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 600 sample_min, 32); 601 602 snd_pcm_hw_constraint_minmax(substream->runtime, 603 SNDRV_PCM_HW_PARAM_CHANNELS, 604 2, channel_max); 605 606 return 0; 607 } 608 static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = { 609 .startup = pcm3168a_startup, 610 .set_fmt = pcm3168a_set_dai_fmt_dac, 611 .set_sysclk = pcm3168a_set_dai_sysclk, 612 .hw_params = pcm3168a_hw_params, 613 .digital_mute = pcm3168a_digital_mute, 614 .set_tdm_slot = pcm3168a_set_tdm_slot, 615 }; 616 617 static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = { 618 .startup = pcm3168a_startup, 619 .set_fmt = pcm3168a_set_dai_fmt_adc, 620 .set_sysclk = pcm3168a_set_dai_sysclk, 621 .hw_params = pcm3168a_hw_params, 622 .set_tdm_slot = pcm3168a_set_tdm_slot, 623 }; 624 625 static struct snd_soc_dai_driver pcm3168a_dais[] = { 626 { 627 .name = "pcm3168a-dac", 628 .playback = { 629 .stream_name = "Playback", 630 .channels_min = 1, 631 .channels_max = 8, 632 .rates = SNDRV_PCM_RATE_8000_192000, 633 .formats = PCM3168A_FORMATS 634 }, 635 .ops = &pcm3168a_dac_dai_ops 636 }, 637 { 638 .name = "pcm3168a-adc", 639 .capture = { 640 .stream_name = "Capture", 641 .channels_min = 1, 642 .channels_max = 6, 643 .rates = SNDRV_PCM_RATE_8000_96000, 644 .formats = PCM3168A_FORMATS 645 }, 646 .ops = &pcm3168a_adc_dai_ops 647 }, 648 }; 649 650 static const struct reg_default pcm3168a_reg_default[] = { 651 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 652 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 653 { PCM3168A_DAC_OP_FLT, 0x00 }, 654 { PCM3168A_DAC_INV, 0x00 }, 655 { PCM3168A_DAC_MUTE, 0x00 }, 656 { PCM3168A_DAC_ZERO, 0x00 }, 657 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 658 { PCM3168A_DAC_VOL_MASTER, 0xff }, 659 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 660 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 661 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 662 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 663 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 664 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 665 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 666 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 667 { PCM3168A_ADC_SMODE, 0x00 }, 668 { PCM3168A_ADC_MST_FMT, 0x00 }, 669 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 670 { PCM3168A_ADC_SEAD, 0x00 }, 671 { PCM3168A_ADC_INV, 0x00 }, 672 { PCM3168A_ADC_MUTE, 0x00 }, 673 { PCM3168A_ADC_OV, 0x00 }, 674 { PCM3168A_ADC_ATT_OVF, 0x00 }, 675 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 676 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 677 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 678 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 679 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 680 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 681 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 682 }; 683 684 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 685 { 686 if (reg >= PCM3168A_RST_SMODE) 687 return true; 688 else 689 return false; 690 } 691 692 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 693 { 694 switch (reg) { 695 case PCM3168A_DAC_ZERO: 696 case PCM3168A_ADC_OV: 697 return true; 698 default: 699 return false; 700 } 701 } 702 703 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 704 { 705 if (reg < PCM3168A_RST_SMODE) 706 return false; 707 708 switch (reg) { 709 case PCM3168A_DAC_ZERO: 710 case PCM3168A_ADC_OV: 711 return false; 712 default: 713 return true; 714 } 715 } 716 717 const struct regmap_config pcm3168a_regmap = { 718 .reg_bits = 8, 719 .val_bits = 8, 720 721 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 722 .reg_defaults = pcm3168a_reg_default, 723 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 724 .readable_reg = pcm3168a_readable_register, 725 .volatile_reg = pcm3168a_volatile_register, 726 .writeable_reg = pcm3168a_writeable_register, 727 .cache_type = REGCACHE_FLAT 728 }; 729 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 730 731 static const struct snd_soc_component_driver pcm3168a_driver = { 732 .controls = pcm3168a_snd_controls, 733 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 734 .dapm_widgets = pcm3168a_dapm_widgets, 735 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 736 .dapm_routes = pcm3168a_dapm_routes, 737 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 738 .use_pmdown_time = 1, 739 .endianness = 1, 740 .non_legacy_dai_naming = 1, 741 }; 742 743 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 744 { 745 struct pcm3168a_priv *pcm3168a; 746 int ret, i; 747 748 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 749 if (pcm3168a == NULL) 750 return -ENOMEM; 751 752 dev_set_drvdata(dev, pcm3168a); 753 754 pcm3168a->scki = devm_clk_get(dev, "scki"); 755 if (IS_ERR(pcm3168a->scki)) { 756 ret = PTR_ERR(pcm3168a->scki); 757 if (ret != -EPROBE_DEFER) 758 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 759 return ret; 760 } 761 762 ret = clk_prepare_enable(pcm3168a->scki); 763 if (ret) { 764 dev_err(dev, "Failed to enable mclk: %d\n", ret); 765 return ret; 766 } 767 768 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 769 770 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 771 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 772 773 ret = devm_regulator_bulk_get(dev, 774 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 775 if (ret) { 776 if (ret != -EPROBE_DEFER) 777 dev_err(dev, "failed to request supplies: %d\n", ret); 778 goto err_clk; 779 } 780 781 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 782 pcm3168a->supplies); 783 if (ret) { 784 dev_err(dev, "failed to enable supplies: %d\n", ret); 785 goto err_clk; 786 } 787 788 pcm3168a->regmap = regmap; 789 if (IS_ERR(pcm3168a->regmap)) { 790 ret = PTR_ERR(pcm3168a->regmap); 791 dev_err(dev, "failed to allocate regmap: %d\n", ret); 792 goto err_regulator; 793 } 794 795 ret = pcm3168a_reset(pcm3168a); 796 if (ret) { 797 dev_err(dev, "Failed to reset device: %d\n", ret); 798 goto err_regulator; 799 } 800 801 pm_runtime_set_active(dev); 802 pm_runtime_enable(dev); 803 pm_runtime_idle(dev); 804 805 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais, 806 ARRAY_SIZE(pcm3168a_dais)); 807 if (ret) { 808 dev_err(dev, "failed to register component: %d\n", ret); 809 goto err_regulator; 810 } 811 812 return 0; 813 814 err_regulator: 815 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 816 pcm3168a->supplies); 817 err_clk: 818 clk_disable_unprepare(pcm3168a->scki); 819 820 return ret; 821 } 822 EXPORT_SYMBOL_GPL(pcm3168a_probe); 823 824 static void pcm3168a_disable(struct device *dev) 825 { 826 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 827 828 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 829 pcm3168a->supplies); 830 clk_disable_unprepare(pcm3168a->scki); 831 } 832 833 void pcm3168a_remove(struct device *dev) 834 { 835 pm_runtime_disable(dev); 836 #ifndef CONFIG_PM 837 pcm3168a_disable(dev); 838 #endif 839 } 840 EXPORT_SYMBOL_GPL(pcm3168a_remove); 841 842 #ifdef CONFIG_PM 843 static int pcm3168a_rt_resume(struct device *dev) 844 { 845 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 846 int ret; 847 848 ret = clk_prepare_enable(pcm3168a->scki); 849 if (ret) { 850 dev_err(dev, "Failed to enable mclk: %d\n", ret); 851 return ret; 852 } 853 854 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 855 pcm3168a->supplies); 856 if (ret) { 857 dev_err(dev, "Failed to enable supplies: %d\n", ret); 858 goto err_clk; 859 } 860 861 ret = pcm3168a_reset(pcm3168a); 862 if (ret) { 863 dev_err(dev, "Failed to reset device: %d\n", ret); 864 goto err_regulator; 865 } 866 867 regcache_cache_only(pcm3168a->regmap, false); 868 869 regcache_mark_dirty(pcm3168a->regmap); 870 871 ret = regcache_sync(pcm3168a->regmap); 872 if (ret) { 873 dev_err(dev, "Failed to sync regmap: %d\n", ret); 874 goto err_regulator; 875 } 876 877 return 0; 878 879 err_regulator: 880 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 881 pcm3168a->supplies); 882 err_clk: 883 clk_disable_unprepare(pcm3168a->scki); 884 885 return ret; 886 } 887 888 static int pcm3168a_rt_suspend(struct device *dev) 889 { 890 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 891 892 regcache_cache_only(pcm3168a->regmap, true); 893 894 pcm3168a_disable(dev); 895 896 return 0; 897 } 898 #endif 899 900 const struct dev_pm_ops pcm3168a_pm_ops = { 901 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 902 }; 903 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 904 905 MODULE_DESCRIPTION("PCM3168A codec driver"); 906 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 907 MODULE_LICENSE("GPL v2"); 908