1 /* 2 * PCM3168A codec driver 3 * 4 * Copyright (C) 2015 Imagination Technologies Ltd. 5 * 6 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "pcm3168a.h" 24 25 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 26 SNDRV_PCM_FMTBIT_S24_3LE | \ 27 SNDRV_PCM_FMTBIT_S24_LE | \ 28 SNDRV_PCM_FMTBIT_S32_LE) 29 30 #define PCM3168A_FMT_I2S 0x0 31 #define PCM3168A_FMT_LEFT_J 0x1 32 #define PCM3168A_FMT_RIGHT_J 0x2 33 #define PCM3168A_FMT_RIGHT_J_16 0x3 34 #define PCM3168A_FMT_DSP_A 0x4 35 #define PCM3168A_FMT_DSP_B 0x5 36 #define PCM3168A_FMT_I2S_TDM 0x6 37 #define PCM3168A_FMT_LEFT_J_TDM 0x7 38 #define PCM3168A_FMT_DSP_MASK 0x4 39 40 #define PCM3168A_NUM_SUPPLIES 6 41 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 42 "VDD1", 43 "VDD2", 44 "VCCAD1", 45 "VCCAD2", 46 "VCCDA1", 47 "VCCDA2" 48 }; 49 50 struct pcm3168a_priv { 51 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 52 struct regmap *regmap; 53 struct clk *scki; 54 bool adc_master_mode; 55 bool dac_master_mode; 56 unsigned long sysclk; 57 unsigned int adc_fmt; 58 unsigned int dac_fmt; 59 int tdm_slots; 60 u32 tdm_mask[2]; 61 int slot_width; 62 }; 63 64 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 65 66 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 67 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 68 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 69 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 70 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 71 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 72 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 73 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 74 75 static const char *const pcm3168a_volume_type[] = { 76 "Individual", "Master + Individual" }; 77 78 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 79 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 80 81 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 82 83 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 84 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 85 86 static const char *const pcm3168a_demp[] = { 87 "Disabled", "48khz", "44.1khz", "32khz" }; 88 89 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 90 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 91 92 static const char *const pcm3168a_zf_func[] = { 93 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 94 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 95 96 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 97 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 98 99 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 100 101 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 102 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 103 104 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 105 106 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 107 0, 1, pcm3168a_con); 108 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 109 2, 3, pcm3168a_con); 110 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 111 4, 5, pcm3168a_con); 112 113 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 114 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 115 116 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 117 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 118 119 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 120 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 121 122 /* -100db to 0db, register values 0-54 cause mute */ 123 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 124 125 /* -100db to 20db, register values 0-14 cause mute */ 126 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 127 128 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 129 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 130 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 131 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 132 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 133 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 134 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 135 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 136 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 137 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 138 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 139 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 140 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 141 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 142 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 143 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 144 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 145 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 146 pcm3168a_dac_tlv), 147 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 148 PCM3168A_DAC_VOL_CHAN_START, 149 PCM3168A_DAC_VOL_CHAN_START + 1, 150 0, 54, 255, 0, pcm3168a_dac_tlv), 151 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 152 PCM3168A_DAC_VOL_CHAN_START + 2, 153 PCM3168A_DAC_VOL_CHAN_START + 3, 154 0, 54, 255, 0, pcm3168a_dac_tlv), 155 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 156 PCM3168A_DAC_VOL_CHAN_START + 4, 157 PCM3168A_DAC_VOL_CHAN_START + 5, 158 0, 54, 255, 0, pcm3168a_dac_tlv), 159 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 160 PCM3168A_DAC_VOL_CHAN_START + 6, 161 PCM3168A_DAC_VOL_CHAN_START + 7, 162 0, 54, 255, 0, pcm3168a_dac_tlv), 163 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 164 PCM3168A_ADC_BYP_SHIFT, 1, 1), 165 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 166 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 167 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 168 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 169 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 170 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 171 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 172 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 173 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 174 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 175 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 176 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 177 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 178 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 179 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 180 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 181 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 182 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 183 pcm3168a_adc_tlv), 184 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 185 PCM3168A_ADC_VOL_CHAN_START, 186 PCM3168A_ADC_VOL_CHAN_START + 1, 187 0, 14, 255, 0, pcm3168a_adc_tlv), 188 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 189 PCM3168A_ADC_VOL_CHAN_START + 2, 190 PCM3168A_ADC_VOL_CHAN_START + 3, 191 0, 14, 255, 0, pcm3168a_adc_tlv), 192 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 193 PCM3168A_ADC_VOL_CHAN_START + 4, 194 PCM3168A_ADC_VOL_CHAN_START + 5, 195 0, 14, 255, 0, pcm3168a_adc_tlv) 196 }; 197 198 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 199 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 200 PCM3168A_DAC_OPEDA_SHIFT, 1), 201 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 202 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 203 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 204 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 205 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 206 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 207 208 SND_SOC_DAPM_OUTPUT("AOUT1L"), 209 SND_SOC_DAPM_OUTPUT("AOUT1R"), 210 SND_SOC_DAPM_OUTPUT("AOUT2L"), 211 SND_SOC_DAPM_OUTPUT("AOUT2R"), 212 SND_SOC_DAPM_OUTPUT("AOUT3L"), 213 SND_SOC_DAPM_OUTPUT("AOUT3R"), 214 SND_SOC_DAPM_OUTPUT("AOUT4L"), 215 SND_SOC_DAPM_OUTPUT("AOUT4R"), 216 217 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 218 PCM3168A_ADC_PSVAD_SHIFT, 1), 219 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 220 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 221 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 222 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 223 224 SND_SOC_DAPM_INPUT("AIN1L"), 225 SND_SOC_DAPM_INPUT("AIN1R"), 226 SND_SOC_DAPM_INPUT("AIN2L"), 227 SND_SOC_DAPM_INPUT("AIN2R"), 228 SND_SOC_DAPM_INPUT("AIN3L"), 229 SND_SOC_DAPM_INPUT("AIN3R") 230 }; 231 232 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 233 /* Playback */ 234 { "AOUT1L", NULL, "DAC1" }, 235 { "AOUT1R", NULL, "DAC1" }, 236 237 { "AOUT2L", NULL, "DAC2" }, 238 { "AOUT2R", NULL, "DAC2" }, 239 240 { "AOUT3L", NULL, "DAC3" }, 241 { "AOUT3R", NULL, "DAC3" }, 242 243 { "AOUT4L", NULL, "DAC4" }, 244 { "AOUT4R", NULL, "DAC4" }, 245 246 /* Capture */ 247 { "ADC1", NULL, "AIN1L" }, 248 { "ADC1", NULL, "AIN1R" }, 249 250 { "ADC2", NULL, "AIN2L" }, 251 { "ADC2", NULL, "AIN2R" }, 252 253 { "ADC3", NULL, "AIN3L" }, 254 { "ADC3", NULL, "AIN3R" } 255 }; 256 257 static unsigned int pcm3168a_scki_ratios[] = { 258 768, 259 512, 260 384, 261 256, 262 192, 263 128 264 }; 265 266 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 267 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 268 269 #define PCM1368A_MAX_SYSCLK 36864000 270 271 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 272 { 273 int ret; 274 275 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 276 if (ret) 277 return ret; 278 279 /* Internal reset is de-asserted after 3846 SCKI cycles */ 280 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 281 282 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 283 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 284 } 285 286 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) 287 { 288 struct snd_soc_component *component = dai->component; 289 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 290 291 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 292 293 return 0; 294 } 295 296 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 297 int clk_id, unsigned int freq, int dir) 298 { 299 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 300 int ret; 301 302 if (freq > PCM1368A_MAX_SYSCLK) 303 return -EINVAL; 304 305 ret = clk_set_rate(pcm3168a->scki, freq); 306 if (ret) 307 return ret; 308 309 pcm3168a->sysclk = freq; 310 311 return 0; 312 } 313 314 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, 315 unsigned int format, bool dac) 316 { 317 struct snd_soc_component *component = dai->component; 318 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 319 u32 fmt, reg, mask, shift; 320 bool master_mode; 321 322 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 323 case SND_SOC_DAIFMT_LEFT_J: 324 fmt = PCM3168A_FMT_LEFT_J; 325 break; 326 case SND_SOC_DAIFMT_I2S: 327 fmt = PCM3168A_FMT_I2S; 328 break; 329 case SND_SOC_DAIFMT_RIGHT_J: 330 fmt = PCM3168A_FMT_RIGHT_J; 331 break; 332 case SND_SOC_DAIFMT_DSP_A: 333 fmt = PCM3168A_FMT_DSP_A; 334 break; 335 case SND_SOC_DAIFMT_DSP_B: 336 fmt = PCM3168A_FMT_DSP_B; 337 break; 338 default: 339 dev_err(component->dev, "unsupported dai format\n"); 340 return -EINVAL; 341 } 342 343 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 344 case SND_SOC_DAIFMT_CBS_CFS: 345 master_mode = false; 346 break; 347 case SND_SOC_DAIFMT_CBM_CFM: 348 master_mode = true; 349 break; 350 default: 351 dev_err(component->dev, "unsupported master/slave mode\n"); 352 return -EINVAL; 353 } 354 355 switch (format & SND_SOC_DAIFMT_INV_MASK) { 356 case SND_SOC_DAIFMT_NB_NF: 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 if (dac) { 363 reg = PCM3168A_DAC_PWR_MST_FMT; 364 mask = PCM3168A_DAC_FMT_MASK; 365 shift = PCM3168A_DAC_FMT_SHIFT; 366 pcm3168a->dac_master_mode = master_mode; 367 pcm3168a->dac_fmt = fmt; 368 } else { 369 reg = PCM3168A_ADC_MST_FMT; 370 mask = PCM3168A_ADC_FMTAD_MASK; 371 shift = PCM3168A_ADC_FMTAD_SHIFT; 372 pcm3168a->adc_master_mode = master_mode; 373 pcm3168a->adc_fmt = fmt; 374 } 375 376 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 377 378 return 0; 379 } 380 381 static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai, 382 unsigned int format) 383 { 384 return pcm3168a_set_dai_fmt(dai, format, true); 385 } 386 387 static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai, 388 unsigned int format) 389 { 390 return pcm3168a_set_dai_fmt(dai, format, false); 391 } 392 393 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 394 unsigned int rx_mask, int slots, 395 int slot_width) 396 { 397 struct snd_soc_component *component = dai->component; 398 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 399 400 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 401 dev_err(component->dev, 402 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 403 tx_mask, rx_mask, slots); 404 return -EINVAL; 405 } 406 407 if (slot_width && 408 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) { 409 dev_err(component->dev, "Unsupported slot_width %d\n", 410 slot_width); 411 return -EINVAL; 412 } 413 414 pcm3168a->tdm_slots = slots; 415 pcm3168a->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 416 pcm3168a->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 417 418 if (pcm3168a->slot_width && pcm3168a->slot_width != slot_width) { 419 dev_err(component->dev, "Not matching slot_width %d vs %d\n", 420 pcm3168a->slot_width, slot_width); 421 return -EINVAL; 422 } 423 424 pcm3168a->slot_width = slot_width; 425 return 0; 426 } 427 428 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 429 struct snd_pcm_hw_params *params, 430 struct snd_soc_dai *dai) 431 { 432 struct snd_soc_component *component = dai->component; 433 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 434 bool tx, master_mode; 435 u32 val, mask, shift, reg; 436 unsigned int rate, fmt, ratio, max_ratio; 437 unsigned int chan; 438 int i, min_frame_size; 439 440 rate = params_rate(params); 441 chan = params_channels(params); 442 443 ratio = pcm3168a->sysclk / rate; 444 445 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 446 if (tx) { 447 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 448 reg = PCM3168A_DAC_PWR_MST_FMT; 449 mask = PCM3168A_DAC_MSDA_MASK; 450 shift = PCM3168A_DAC_MSDA_SHIFT; 451 master_mode = pcm3168a->dac_master_mode; 452 fmt = pcm3168a->dac_fmt; 453 } else { 454 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 455 reg = PCM3168A_ADC_MST_FMT; 456 mask = PCM3168A_ADC_MSAD_MASK; 457 shift = PCM3168A_ADC_MSAD_SHIFT; 458 master_mode = pcm3168a->adc_master_mode; 459 fmt = pcm3168a->adc_fmt; 460 } 461 462 for (i = 0; i < max_ratio; i++) { 463 if (pcm3168a_scki_ratios[i] == ratio) 464 break; 465 } 466 467 if (i == max_ratio) { 468 dev_err(component->dev, "unsupported sysclk ratio\n"); 469 return -EINVAL; 470 } 471 472 if (pcm3168a->slot_width) 473 min_frame_size = pcm3168a->slot_width; 474 else 475 min_frame_size = params_width(params); 476 477 switch (min_frame_size) { 478 case 16: 479 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 480 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n"); 481 return -EINVAL; 482 } 483 fmt = PCM3168A_FMT_RIGHT_J_16; 484 break; 485 case 24: 486 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 487 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n"); 488 return -EINVAL; 489 } 490 break; 491 case 32: 492 break; 493 default: 494 dev_err(component->dev, "unsupported frame size: %d\n", min_frame_size); 495 return -EINVAL; 496 } 497 498 /* for TDM */ 499 if (chan > 2) { 500 switch (fmt) { 501 case PCM3168A_FMT_I2S: 502 case PCM3168A_FMT_DSP_A: 503 fmt = PCM3168A_FMT_I2S_TDM; 504 break; 505 case PCM3168A_FMT_LEFT_J: 506 case PCM3168A_FMT_DSP_B: 507 fmt = PCM3168A_FMT_LEFT_J_TDM; 508 break; 509 default: 510 dev_err(component->dev, 511 "TDM is supported under DSP/I2S/Left_J only\n"); 512 return -EINVAL; 513 } 514 } 515 516 if (master_mode) 517 val = ((i + 1) << shift); 518 else 519 val = 0; 520 521 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 522 523 if (tx) { 524 mask = PCM3168A_DAC_FMT_MASK; 525 shift = PCM3168A_DAC_FMT_SHIFT; 526 } else { 527 mask = PCM3168A_ADC_FMTAD_MASK; 528 shift = PCM3168A_ADC_FMTAD_SHIFT; 529 } 530 531 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 532 533 return 0; 534 } 535 536 static int pcm3168a_startup(struct snd_pcm_substream *substream, 537 struct snd_soc_dai *dai) 538 { 539 struct snd_soc_component *component = dai->component; 540 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 541 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 542 unsigned int fmt; 543 unsigned int sample_min; 544 unsigned int channel_max; 545 unsigned int channel_maxs[] = { 546 6, /* rx */ 547 8 /* tx */ 548 }; 549 550 if (tx) 551 fmt = pcm3168a->dac_fmt; 552 else 553 fmt = pcm3168a->adc_fmt; 554 555 /* 556 * Available Data Bits 557 * 558 * RIGHT_J : 24 / 16 559 * LEFT_J : 24 560 * I2S : 24 561 * 562 * TDM available 563 * 564 * I2S 565 * LEFT_J 566 */ 567 switch (fmt) { 568 case PCM3168A_FMT_RIGHT_J: 569 sample_min = 16; 570 channel_max = 2; 571 break; 572 case PCM3168A_FMT_LEFT_J: 573 case PCM3168A_FMT_I2S: 574 case PCM3168A_FMT_DSP_A: 575 case PCM3168A_FMT_DSP_B: 576 sample_min = 24; 577 channel_max = channel_maxs[tx]; 578 break; 579 default: 580 sample_min = 24; 581 channel_max = 2; 582 } 583 584 snd_pcm_hw_constraint_minmax(substream->runtime, 585 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 586 sample_min, 32); 587 588 snd_pcm_hw_constraint_minmax(substream->runtime, 589 SNDRV_PCM_HW_PARAM_CHANNELS, 590 2, channel_max); 591 592 return 0; 593 } 594 static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = { 595 .startup = pcm3168a_startup, 596 .set_fmt = pcm3168a_set_dai_fmt_dac, 597 .set_sysclk = pcm3168a_set_dai_sysclk, 598 .hw_params = pcm3168a_hw_params, 599 .digital_mute = pcm3168a_digital_mute, 600 .set_tdm_slot = pcm3168a_set_tdm_slot, 601 }; 602 603 static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = { 604 .startup = pcm3168a_startup, 605 .set_fmt = pcm3168a_set_dai_fmt_adc, 606 .set_sysclk = pcm3168a_set_dai_sysclk, 607 .hw_params = pcm3168a_hw_params, 608 .set_tdm_slot = pcm3168a_set_tdm_slot, 609 }; 610 611 static struct snd_soc_dai_driver pcm3168a_dais[] = { 612 { 613 .name = "pcm3168a-dac", 614 .playback = { 615 .stream_name = "Playback", 616 .channels_min = 1, 617 .channels_max = 8, 618 .rates = SNDRV_PCM_RATE_8000_192000, 619 .formats = PCM3168A_FORMATS 620 }, 621 .ops = &pcm3168a_dac_dai_ops 622 }, 623 { 624 .name = "pcm3168a-adc", 625 .capture = { 626 .stream_name = "Capture", 627 .channels_min = 1, 628 .channels_max = 6, 629 .rates = SNDRV_PCM_RATE_8000_96000, 630 .formats = PCM3168A_FORMATS 631 }, 632 .ops = &pcm3168a_adc_dai_ops 633 }, 634 }; 635 636 static const struct reg_default pcm3168a_reg_default[] = { 637 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 638 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 639 { PCM3168A_DAC_OP_FLT, 0x00 }, 640 { PCM3168A_DAC_INV, 0x00 }, 641 { PCM3168A_DAC_MUTE, 0x00 }, 642 { PCM3168A_DAC_ZERO, 0x00 }, 643 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 644 { PCM3168A_DAC_VOL_MASTER, 0xff }, 645 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 646 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 647 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 648 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 649 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 650 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 651 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 652 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 653 { PCM3168A_ADC_SMODE, 0x00 }, 654 { PCM3168A_ADC_MST_FMT, 0x00 }, 655 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 656 { PCM3168A_ADC_SEAD, 0x00 }, 657 { PCM3168A_ADC_INV, 0x00 }, 658 { PCM3168A_ADC_MUTE, 0x00 }, 659 { PCM3168A_ADC_OV, 0x00 }, 660 { PCM3168A_ADC_ATT_OVF, 0x00 }, 661 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 662 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 663 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 664 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 665 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 666 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 667 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 668 }; 669 670 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 671 { 672 if (reg >= PCM3168A_RST_SMODE) 673 return true; 674 else 675 return false; 676 } 677 678 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 679 { 680 switch (reg) { 681 case PCM3168A_DAC_ZERO: 682 case PCM3168A_ADC_OV: 683 return true; 684 default: 685 return false; 686 } 687 } 688 689 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 690 { 691 if (reg < PCM3168A_RST_SMODE) 692 return false; 693 694 switch (reg) { 695 case PCM3168A_DAC_ZERO: 696 case PCM3168A_ADC_OV: 697 return false; 698 default: 699 return true; 700 } 701 } 702 703 const struct regmap_config pcm3168a_regmap = { 704 .reg_bits = 8, 705 .val_bits = 8, 706 707 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 708 .reg_defaults = pcm3168a_reg_default, 709 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 710 .readable_reg = pcm3168a_readable_register, 711 .volatile_reg = pcm3168a_volatile_register, 712 .writeable_reg = pcm3168a_writeable_register, 713 .cache_type = REGCACHE_FLAT 714 }; 715 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 716 717 static const struct snd_soc_component_driver pcm3168a_driver = { 718 .controls = pcm3168a_snd_controls, 719 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 720 .dapm_widgets = pcm3168a_dapm_widgets, 721 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 722 .dapm_routes = pcm3168a_dapm_routes, 723 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 724 .use_pmdown_time = 1, 725 .endianness = 1, 726 .non_legacy_dai_naming = 1, 727 }; 728 729 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 730 { 731 struct pcm3168a_priv *pcm3168a; 732 int ret, i; 733 734 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 735 if (pcm3168a == NULL) 736 return -ENOMEM; 737 738 dev_set_drvdata(dev, pcm3168a); 739 740 pcm3168a->scki = devm_clk_get(dev, "scki"); 741 if (IS_ERR(pcm3168a->scki)) { 742 ret = PTR_ERR(pcm3168a->scki); 743 if (ret != -EPROBE_DEFER) 744 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 745 return ret; 746 } 747 748 ret = clk_prepare_enable(pcm3168a->scki); 749 if (ret) { 750 dev_err(dev, "Failed to enable mclk: %d\n", ret); 751 return ret; 752 } 753 754 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 755 756 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 757 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 758 759 ret = devm_regulator_bulk_get(dev, 760 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 761 if (ret) { 762 if (ret != -EPROBE_DEFER) 763 dev_err(dev, "failed to request supplies: %d\n", ret); 764 goto err_clk; 765 } 766 767 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 768 pcm3168a->supplies); 769 if (ret) { 770 dev_err(dev, "failed to enable supplies: %d\n", ret); 771 goto err_clk; 772 } 773 774 pcm3168a->regmap = regmap; 775 if (IS_ERR(pcm3168a->regmap)) { 776 ret = PTR_ERR(pcm3168a->regmap); 777 dev_err(dev, "failed to allocate regmap: %d\n", ret); 778 goto err_regulator; 779 } 780 781 ret = pcm3168a_reset(pcm3168a); 782 if (ret) { 783 dev_err(dev, "Failed to reset device: %d\n", ret); 784 goto err_regulator; 785 } 786 787 pm_runtime_set_active(dev); 788 pm_runtime_enable(dev); 789 pm_runtime_idle(dev); 790 791 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais, 792 ARRAY_SIZE(pcm3168a_dais)); 793 if (ret) { 794 dev_err(dev, "failed to register component: %d\n", ret); 795 goto err_regulator; 796 } 797 798 return 0; 799 800 err_regulator: 801 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 802 pcm3168a->supplies); 803 err_clk: 804 clk_disable_unprepare(pcm3168a->scki); 805 806 return ret; 807 } 808 EXPORT_SYMBOL_GPL(pcm3168a_probe); 809 810 static void pcm3168a_disable(struct device *dev) 811 { 812 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 813 814 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 815 pcm3168a->supplies); 816 clk_disable_unprepare(pcm3168a->scki); 817 } 818 819 void pcm3168a_remove(struct device *dev) 820 { 821 pm_runtime_disable(dev); 822 #ifndef CONFIG_PM 823 pcm3168a_disable(dev); 824 #endif 825 } 826 EXPORT_SYMBOL_GPL(pcm3168a_remove); 827 828 #ifdef CONFIG_PM 829 static int pcm3168a_rt_resume(struct device *dev) 830 { 831 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 832 int ret; 833 834 ret = clk_prepare_enable(pcm3168a->scki); 835 if (ret) { 836 dev_err(dev, "Failed to enable mclk: %d\n", ret); 837 return ret; 838 } 839 840 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 841 pcm3168a->supplies); 842 if (ret) { 843 dev_err(dev, "Failed to enable supplies: %d\n", ret); 844 goto err_clk; 845 } 846 847 ret = pcm3168a_reset(pcm3168a); 848 if (ret) { 849 dev_err(dev, "Failed to reset device: %d\n", ret); 850 goto err_regulator; 851 } 852 853 regcache_cache_only(pcm3168a->regmap, false); 854 855 regcache_mark_dirty(pcm3168a->regmap); 856 857 ret = regcache_sync(pcm3168a->regmap); 858 if (ret) { 859 dev_err(dev, "Failed to sync regmap: %d\n", ret); 860 goto err_regulator; 861 } 862 863 return 0; 864 865 err_regulator: 866 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 867 pcm3168a->supplies); 868 err_clk: 869 clk_disable_unprepare(pcm3168a->scki); 870 871 return ret; 872 } 873 874 static int pcm3168a_rt_suspend(struct device *dev) 875 { 876 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 877 878 regcache_cache_only(pcm3168a->regmap, true); 879 880 pcm3168a_disable(dev); 881 882 return 0; 883 } 884 #endif 885 886 const struct dev_pm_ops pcm3168a_pm_ops = { 887 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 888 }; 889 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 890 891 MODULE_DESCRIPTION("PCM3168A codec driver"); 892 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 893 MODULE_LICENSE("GPL v2"); 894