1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCM3168A codec driver 4 * 5 * Copyright (C) 2015 Imagination Technologies Ltd. 6 * 7 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/of_gpio.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 #include <sound/tlv.h> 21 22 #include "pcm3168a.h" 23 24 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 25 SNDRV_PCM_FMTBIT_S24_3LE | \ 26 SNDRV_PCM_FMTBIT_S24_LE) 27 28 #define PCM3168A_FMT_I2S 0x0 29 #define PCM3168A_FMT_LEFT_J 0x1 30 #define PCM3168A_FMT_RIGHT_J 0x2 31 #define PCM3168A_FMT_RIGHT_J_16 0x3 32 #define PCM3168A_FMT_DSP_A 0x4 33 #define PCM3168A_FMT_DSP_B 0x5 34 #define PCM3168A_FMT_I2S_TDM 0x6 35 #define PCM3168A_FMT_LEFT_J_TDM 0x7 36 #define PCM3168A_FMT_DSP_MASK 0x4 37 38 #define PCM3168A_NUM_SUPPLIES 6 39 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 40 "VDD1", 41 "VDD2", 42 "VCCAD1", 43 "VCCAD2", 44 "VCCDA1", 45 "VCCDA2" 46 }; 47 48 #define PCM3168A_DAI_DAC 0 49 #define PCM3168A_DAI_ADC 1 50 51 /* ADC/DAC side parameters */ 52 struct pcm3168a_io_params { 53 bool master_mode; 54 unsigned int fmt; 55 int tdm_slots; 56 u32 tdm_mask; 57 int slot_width; 58 }; 59 60 struct pcm3168a_priv { 61 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 62 struct regmap *regmap; 63 struct clk *scki; 64 struct gpio_desc *gpio_rst; 65 unsigned long sysclk; 66 67 struct pcm3168a_io_params io_params[2]; 68 struct snd_soc_dai_driver dai_drv[2]; 69 }; 70 71 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 72 73 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 74 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 75 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 76 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 77 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 78 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 79 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 80 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 81 82 static const char *const pcm3168a_volume_type[] = { 83 "Individual", "Master + Individual" }; 84 85 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 86 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 87 88 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 89 90 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 91 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 92 93 static const char *const pcm3168a_demp[] = { 94 "Disabled", "48khz", "44.1khz", "32khz" }; 95 96 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 97 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 98 99 static const char *const pcm3168a_zf_func[] = { 100 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 101 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 102 103 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 104 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 105 106 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 107 108 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 109 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 110 111 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 112 113 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 114 0, 1, pcm3168a_con); 115 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 116 2, 3, pcm3168a_con); 117 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 118 4, 5, pcm3168a_con); 119 120 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 121 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 122 123 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 124 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 125 126 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 127 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 128 129 /* -100db to 0db, register values 0-54 cause mute */ 130 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 131 132 /* -100db to 20db, register values 0-14 cause mute */ 133 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 134 135 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 136 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 137 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 138 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 139 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 140 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 141 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 142 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 143 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 144 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 145 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 146 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 147 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 148 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 149 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 150 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 151 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 152 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 153 pcm3168a_dac_tlv), 154 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 155 PCM3168A_DAC_VOL_CHAN_START, 156 PCM3168A_DAC_VOL_CHAN_START + 1, 157 0, 54, 255, 0, pcm3168a_dac_tlv), 158 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 159 PCM3168A_DAC_VOL_CHAN_START + 2, 160 PCM3168A_DAC_VOL_CHAN_START + 3, 161 0, 54, 255, 0, pcm3168a_dac_tlv), 162 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 163 PCM3168A_DAC_VOL_CHAN_START + 4, 164 PCM3168A_DAC_VOL_CHAN_START + 5, 165 0, 54, 255, 0, pcm3168a_dac_tlv), 166 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 167 PCM3168A_DAC_VOL_CHAN_START + 6, 168 PCM3168A_DAC_VOL_CHAN_START + 7, 169 0, 54, 255, 0, pcm3168a_dac_tlv), 170 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 171 PCM3168A_ADC_BYP_SHIFT, 1, 1), 172 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 173 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 174 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 175 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 176 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 177 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 178 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 179 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 180 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 181 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 182 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 183 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 184 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 185 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 186 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 187 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 188 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 189 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 190 pcm3168a_adc_tlv), 191 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 192 PCM3168A_ADC_VOL_CHAN_START, 193 PCM3168A_ADC_VOL_CHAN_START + 1, 194 0, 14, 255, 0, pcm3168a_adc_tlv), 195 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 196 PCM3168A_ADC_VOL_CHAN_START + 2, 197 PCM3168A_ADC_VOL_CHAN_START + 3, 198 0, 14, 255, 0, pcm3168a_adc_tlv), 199 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 200 PCM3168A_ADC_VOL_CHAN_START + 4, 201 PCM3168A_ADC_VOL_CHAN_START + 5, 202 0, 14, 255, 0, pcm3168a_adc_tlv) 203 }; 204 205 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 206 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 207 PCM3168A_DAC_OPEDA_SHIFT, 1), 208 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 209 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 210 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 211 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 212 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 213 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 214 215 SND_SOC_DAPM_OUTPUT("AOUT1L"), 216 SND_SOC_DAPM_OUTPUT("AOUT1R"), 217 SND_SOC_DAPM_OUTPUT("AOUT2L"), 218 SND_SOC_DAPM_OUTPUT("AOUT2R"), 219 SND_SOC_DAPM_OUTPUT("AOUT3L"), 220 SND_SOC_DAPM_OUTPUT("AOUT3R"), 221 SND_SOC_DAPM_OUTPUT("AOUT4L"), 222 SND_SOC_DAPM_OUTPUT("AOUT4R"), 223 224 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 225 PCM3168A_ADC_PSVAD_SHIFT, 1), 226 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 227 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 228 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 229 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 230 231 SND_SOC_DAPM_INPUT("AIN1L"), 232 SND_SOC_DAPM_INPUT("AIN1R"), 233 SND_SOC_DAPM_INPUT("AIN2L"), 234 SND_SOC_DAPM_INPUT("AIN2R"), 235 SND_SOC_DAPM_INPUT("AIN3L"), 236 SND_SOC_DAPM_INPUT("AIN3R") 237 }; 238 239 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 240 /* Playback */ 241 { "AOUT1L", NULL, "DAC1" }, 242 { "AOUT1R", NULL, "DAC1" }, 243 244 { "AOUT2L", NULL, "DAC2" }, 245 { "AOUT2R", NULL, "DAC2" }, 246 247 { "AOUT3L", NULL, "DAC3" }, 248 { "AOUT3R", NULL, "DAC3" }, 249 250 { "AOUT4L", NULL, "DAC4" }, 251 { "AOUT4R", NULL, "DAC4" }, 252 253 /* Capture */ 254 { "ADC1", NULL, "AIN1L" }, 255 { "ADC1", NULL, "AIN1R" }, 256 257 { "ADC2", NULL, "AIN2L" }, 258 { "ADC2", NULL, "AIN2R" }, 259 260 { "ADC3", NULL, "AIN3L" }, 261 { "ADC3", NULL, "AIN3R" } 262 }; 263 264 static unsigned int pcm3168a_scki_ratios[] = { 265 768, 266 512, 267 384, 268 256, 269 192, 270 128 271 }; 272 273 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 274 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 275 276 #define PCM3168A_MAX_SYSCLK 36864000 277 278 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 279 { 280 int ret; 281 282 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 283 if (ret) 284 return ret; 285 286 /* Internal reset is de-asserted after 3846 SCKI cycles */ 287 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 288 289 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 290 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 291 } 292 293 static int pcm3168a_mute(struct snd_soc_dai *dai, int mute, int direction) 294 { 295 struct snd_soc_component *component = dai->component; 296 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 297 298 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 299 300 return 0; 301 } 302 303 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 304 int clk_id, unsigned int freq, int dir) 305 { 306 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 307 int ret; 308 309 if (freq > PCM3168A_MAX_SYSCLK) 310 return -EINVAL; 311 312 ret = clk_set_rate(pcm3168a->scki, freq); 313 if (ret) 314 return ret; 315 316 pcm3168a->sysclk = freq; 317 318 return 0; 319 } 320 321 static void pcm3168a_update_fixup_pcm_stream(struct snd_soc_dai *dai) 322 { 323 struct snd_soc_component *component = dai->component; 324 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 325 u64 formats = SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE; 326 unsigned int channel_max = dai->id == PCM3168A_DAI_DAC ? 8 : 6; 327 328 if (pcm3168a->io_params[dai->id].fmt == PCM3168A_FMT_RIGHT_J) { 329 /* S16_LE is only supported in RIGHT_J mode */ 330 formats |= SNDRV_PCM_FMTBIT_S16_LE; 331 332 /* 333 * If multi DIN/DOUT is not selected, RIGHT_J can only support 334 * two channels (no TDM support) 335 */ 336 if (pcm3168a->io_params[dai->id].tdm_slots != 2) 337 channel_max = 2; 338 } 339 340 if (dai->id == PCM3168A_DAI_DAC) { 341 dai->driver->playback.channels_max = channel_max; 342 dai->driver->playback.formats = formats; 343 } else { 344 dai->driver->capture.channels_max = channel_max; 345 dai->driver->capture.formats = formats; 346 } 347 } 348 349 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format) 350 { 351 struct snd_soc_component *component = dai->component; 352 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 353 u32 fmt, reg, mask, shift; 354 bool master_mode; 355 356 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 357 case SND_SOC_DAIFMT_LEFT_J: 358 fmt = PCM3168A_FMT_LEFT_J; 359 break; 360 case SND_SOC_DAIFMT_I2S: 361 fmt = PCM3168A_FMT_I2S; 362 break; 363 case SND_SOC_DAIFMT_RIGHT_J: 364 fmt = PCM3168A_FMT_RIGHT_J; 365 break; 366 case SND_SOC_DAIFMT_DSP_A: 367 fmt = PCM3168A_FMT_DSP_A; 368 break; 369 case SND_SOC_DAIFMT_DSP_B: 370 fmt = PCM3168A_FMT_DSP_B; 371 break; 372 default: 373 dev_err(component->dev, "unsupported dai format\n"); 374 return -EINVAL; 375 } 376 377 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 378 case SND_SOC_DAIFMT_CBS_CFS: 379 master_mode = false; 380 break; 381 case SND_SOC_DAIFMT_CBM_CFM: 382 master_mode = true; 383 break; 384 default: 385 dev_err(component->dev, "unsupported master/slave mode\n"); 386 return -EINVAL; 387 } 388 389 switch (format & SND_SOC_DAIFMT_INV_MASK) { 390 case SND_SOC_DAIFMT_NB_NF: 391 break; 392 default: 393 return -EINVAL; 394 } 395 396 if (dai->id == PCM3168A_DAI_DAC) { 397 reg = PCM3168A_DAC_PWR_MST_FMT; 398 mask = PCM3168A_DAC_FMT_MASK; 399 shift = PCM3168A_DAC_FMT_SHIFT; 400 } else { 401 reg = PCM3168A_ADC_MST_FMT; 402 mask = PCM3168A_ADC_FMTAD_MASK; 403 shift = PCM3168A_ADC_FMTAD_SHIFT; 404 } 405 406 pcm3168a->io_params[dai->id].master_mode = master_mode; 407 pcm3168a->io_params[dai->id].fmt = fmt; 408 409 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 410 411 pcm3168a_update_fixup_pcm_stream(dai); 412 413 return 0; 414 } 415 416 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 417 unsigned int rx_mask, int slots, 418 int slot_width) 419 { 420 struct snd_soc_component *component = dai->component; 421 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 422 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 423 424 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 425 dev_err(component->dev, 426 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 427 tx_mask, rx_mask, slots); 428 return -EINVAL; 429 } 430 431 if (slot_width && 432 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) { 433 dev_err(component->dev, "Unsupported slot_width %d\n", 434 slot_width); 435 return -EINVAL; 436 } 437 438 io_params->tdm_slots = slots; 439 io_params->slot_width = slot_width; 440 /* Ignore the not relevant mask for the DAI/direction */ 441 if (dai->id == PCM3168A_DAI_DAC) 442 io_params->tdm_mask = tx_mask; 443 else 444 io_params->tdm_mask = rx_mask; 445 446 pcm3168a_update_fixup_pcm_stream(dai); 447 448 return 0; 449 } 450 451 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 452 struct snd_pcm_hw_params *params, 453 struct snd_soc_dai *dai) 454 { 455 struct snd_soc_component *component = dai->component; 456 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 457 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 458 bool master_mode; 459 u32 val, mask, shift, reg; 460 unsigned int rate, fmt, ratio, max_ratio; 461 unsigned int tdm_slots; 462 int i, slot_width; 463 464 rate = params_rate(params); 465 466 ratio = pcm3168a->sysclk / rate; 467 468 if (dai->id == PCM3168A_DAI_DAC) { 469 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 470 reg = PCM3168A_DAC_PWR_MST_FMT; 471 mask = PCM3168A_DAC_MSDA_MASK; 472 shift = PCM3168A_DAC_MSDA_SHIFT; 473 } else { 474 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 475 reg = PCM3168A_ADC_MST_FMT; 476 mask = PCM3168A_ADC_MSAD_MASK; 477 shift = PCM3168A_ADC_MSAD_SHIFT; 478 } 479 480 master_mode = io_params->master_mode; 481 fmt = io_params->fmt; 482 483 for (i = 0; i < max_ratio; i++) { 484 if (pcm3168a_scki_ratios[i] == ratio) 485 break; 486 } 487 488 if (i == max_ratio) { 489 dev_err(component->dev, "unsupported sysclk ratio\n"); 490 return -EINVAL; 491 } 492 493 if (io_params->slot_width) 494 slot_width = io_params->slot_width; 495 else 496 slot_width = params_width(params); 497 498 switch (slot_width) { 499 case 16: 500 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 501 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n"); 502 return -EINVAL; 503 } 504 fmt = PCM3168A_FMT_RIGHT_J_16; 505 break; 506 case 24: 507 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 508 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n"); 509 return -EINVAL; 510 } 511 break; 512 case 32: 513 break; 514 default: 515 dev_err(component->dev, "unsupported frame size: %d\n", slot_width); 516 return -EINVAL; 517 } 518 519 if (io_params->tdm_slots) 520 tdm_slots = io_params->tdm_slots; 521 else 522 tdm_slots = params_channels(params); 523 524 /* 525 * Switch the codec to TDM mode when more than 2 TDM slots are needed 526 * for the stream. 527 * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually) 528 * then DIN1/DOUT1 is used in TDM mode. 529 * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is 530 * used in normal mode, no need to switch to TDM modes. 531 */ 532 if (tdm_slots > 2) { 533 switch (fmt) { 534 case PCM3168A_FMT_I2S: 535 case PCM3168A_FMT_DSP_A: 536 fmt = PCM3168A_FMT_I2S_TDM; 537 break; 538 case PCM3168A_FMT_LEFT_J: 539 case PCM3168A_FMT_DSP_B: 540 fmt = PCM3168A_FMT_LEFT_J_TDM; 541 break; 542 default: 543 dev_err(component->dev, 544 "TDM is supported under DSP/I2S/Left_J only\n"); 545 return -EINVAL; 546 } 547 } 548 549 if (master_mode) 550 val = ((i + 1) << shift); 551 else 552 val = 0; 553 554 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 555 556 if (dai->id == PCM3168A_DAI_DAC) { 557 mask = PCM3168A_DAC_FMT_MASK; 558 shift = PCM3168A_DAC_FMT_SHIFT; 559 } else { 560 mask = PCM3168A_ADC_FMTAD_MASK; 561 shift = PCM3168A_ADC_FMTAD_SHIFT; 562 } 563 564 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 565 566 return 0; 567 } 568 569 static const struct snd_soc_dai_ops pcm3168a_dai_ops = { 570 .set_fmt = pcm3168a_set_dai_fmt, 571 .set_sysclk = pcm3168a_set_dai_sysclk, 572 .hw_params = pcm3168a_hw_params, 573 .mute_stream = pcm3168a_mute, 574 .set_tdm_slot = pcm3168a_set_tdm_slot, 575 .no_capture_mute = 1, 576 }; 577 578 static struct snd_soc_dai_driver pcm3168a_dais[] = { 579 { 580 .name = "pcm3168a-dac", 581 .id = PCM3168A_DAI_DAC, 582 .playback = { 583 .stream_name = "Playback", 584 .channels_min = 1, 585 .channels_max = 8, 586 .rates = SNDRV_PCM_RATE_8000_192000, 587 .formats = PCM3168A_FORMATS 588 }, 589 .ops = &pcm3168a_dai_ops 590 }, 591 { 592 .name = "pcm3168a-adc", 593 .id = PCM3168A_DAI_ADC, 594 .capture = { 595 .stream_name = "Capture", 596 .channels_min = 1, 597 .channels_max = 6, 598 .rates = SNDRV_PCM_RATE_8000_96000, 599 .formats = PCM3168A_FORMATS 600 }, 601 .ops = &pcm3168a_dai_ops 602 }, 603 }; 604 605 static const struct reg_default pcm3168a_reg_default[] = { 606 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 607 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 608 { PCM3168A_DAC_OP_FLT, 0x00 }, 609 { PCM3168A_DAC_INV, 0x00 }, 610 { PCM3168A_DAC_MUTE, 0x00 }, 611 { PCM3168A_DAC_ZERO, 0x00 }, 612 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 613 { PCM3168A_DAC_VOL_MASTER, 0xff }, 614 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 615 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 616 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 617 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 618 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 619 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 620 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 621 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 622 { PCM3168A_ADC_SMODE, 0x00 }, 623 { PCM3168A_ADC_MST_FMT, 0x00 }, 624 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 625 { PCM3168A_ADC_SEAD, 0x00 }, 626 { PCM3168A_ADC_INV, 0x00 }, 627 { PCM3168A_ADC_MUTE, 0x00 }, 628 { PCM3168A_ADC_OV, 0x00 }, 629 { PCM3168A_ADC_ATT_OVF, 0x00 }, 630 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 631 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 632 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 633 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 634 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 635 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 636 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 637 }; 638 639 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 640 { 641 if (reg >= PCM3168A_RST_SMODE) 642 return true; 643 else 644 return false; 645 } 646 647 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 648 { 649 switch (reg) { 650 case PCM3168A_RST_SMODE: 651 case PCM3168A_DAC_ZERO: 652 case PCM3168A_ADC_OV: 653 return true; 654 default: 655 return false; 656 } 657 } 658 659 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 660 { 661 if (reg < PCM3168A_RST_SMODE) 662 return false; 663 664 switch (reg) { 665 case PCM3168A_DAC_ZERO: 666 case PCM3168A_ADC_OV: 667 return false; 668 default: 669 return true; 670 } 671 } 672 673 const struct regmap_config pcm3168a_regmap = { 674 .reg_bits = 8, 675 .val_bits = 8, 676 677 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 678 .reg_defaults = pcm3168a_reg_default, 679 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 680 .readable_reg = pcm3168a_readable_register, 681 .volatile_reg = pcm3168a_volatile_register, 682 .writeable_reg = pcm3168a_writeable_register, 683 .cache_type = REGCACHE_FLAT 684 }; 685 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 686 687 static const struct snd_soc_component_driver pcm3168a_driver = { 688 .controls = pcm3168a_snd_controls, 689 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 690 .dapm_widgets = pcm3168a_dapm_widgets, 691 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 692 .dapm_routes = pcm3168a_dapm_routes, 693 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 694 .use_pmdown_time = 1, 695 .endianness = 1, 696 .non_legacy_dai_naming = 1, 697 }; 698 699 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 700 { 701 struct pcm3168a_priv *pcm3168a; 702 int ret, i; 703 704 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 705 if (pcm3168a == NULL) 706 return -ENOMEM; 707 708 dev_set_drvdata(dev, pcm3168a); 709 710 /* 711 * Request the reset (connected to RST pin) gpio line as non exclusive 712 * as the same reset line might be connected to multiple pcm3168a codec 713 * 714 * The RST is low active, we want the GPIO line to be high initially, so 715 * request the initial level to LOW which in practice means DEASSERTED: 716 * The deasserted level of GPIO_ACTIVE_LOW is HIGH. 717 */ 718 pcm3168a->gpio_rst = devm_gpiod_get_optional(dev, "reset", 719 GPIOD_OUT_LOW | 720 GPIOD_FLAGS_BIT_NONEXCLUSIVE); 721 if (IS_ERR(pcm3168a->gpio_rst)) { 722 ret = PTR_ERR(pcm3168a->gpio_rst); 723 if (ret != -EPROBE_DEFER ) 724 dev_err(dev, "failed to acquire RST gpio: %d\n", ret); 725 726 return ret; 727 } 728 729 pcm3168a->scki = devm_clk_get(dev, "scki"); 730 if (IS_ERR(pcm3168a->scki)) { 731 ret = PTR_ERR(pcm3168a->scki); 732 if (ret != -EPROBE_DEFER) 733 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 734 return ret; 735 } 736 737 ret = clk_prepare_enable(pcm3168a->scki); 738 if (ret) { 739 dev_err(dev, "Failed to enable mclk: %d\n", ret); 740 return ret; 741 } 742 743 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 744 745 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 746 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 747 748 ret = devm_regulator_bulk_get(dev, 749 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 750 if (ret) { 751 if (ret != -EPROBE_DEFER) 752 dev_err(dev, "failed to request supplies: %d\n", ret); 753 goto err_clk; 754 } 755 756 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 757 pcm3168a->supplies); 758 if (ret) { 759 dev_err(dev, "failed to enable supplies: %d\n", ret); 760 goto err_clk; 761 } 762 763 pcm3168a->regmap = regmap; 764 if (IS_ERR(pcm3168a->regmap)) { 765 ret = PTR_ERR(pcm3168a->regmap); 766 dev_err(dev, "failed to allocate regmap: %d\n", ret); 767 goto err_regulator; 768 } 769 770 if (pcm3168a->gpio_rst) { 771 /* 772 * The device is taken out from reset via GPIO line, wait for 773 * 3846 SCKI clock cycles for the internal reset de-assertion 774 */ 775 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 776 } else { 777 ret = pcm3168a_reset(pcm3168a); 778 if (ret) { 779 dev_err(dev, "Failed to reset device: %d\n", ret); 780 goto err_regulator; 781 } 782 } 783 784 pm_runtime_set_active(dev); 785 pm_runtime_enable(dev); 786 pm_runtime_idle(dev); 787 788 memcpy(pcm3168a->dai_drv, pcm3168a_dais, sizeof(pcm3168a->dai_drv)); 789 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, 790 pcm3168a->dai_drv, 791 ARRAY_SIZE(pcm3168a->dai_drv)); 792 if (ret) { 793 dev_err(dev, "failed to register component: %d\n", ret); 794 goto err_regulator; 795 } 796 797 return 0; 798 799 err_regulator: 800 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 801 pcm3168a->supplies); 802 err_clk: 803 clk_disable_unprepare(pcm3168a->scki); 804 805 return ret; 806 } 807 EXPORT_SYMBOL_GPL(pcm3168a_probe); 808 809 static void pcm3168a_disable(struct device *dev) 810 { 811 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 812 813 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 814 pcm3168a->supplies); 815 clk_disable_unprepare(pcm3168a->scki); 816 } 817 818 void pcm3168a_remove(struct device *dev) 819 { 820 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 821 822 /* 823 * The RST is low active, we want the GPIO line to be low when the 824 * driver is removed, so set level to 1 which in practice means 825 * ASSERTED: 826 * The asserted level of GPIO_ACTIVE_LOW is LOW. 827 */ 828 gpiod_set_value_cansleep(pcm3168a->gpio_rst, 1); 829 pm_runtime_disable(dev); 830 #ifndef CONFIG_PM 831 pcm3168a_disable(dev); 832 #endif 833 } 834 EXPORT_SYMBOL_GPL(pcm3168a_remove); 835 836 #ifdef CONFIG_PM 837 static int pcm3168a_rt_resume(struct device *dev) 838 { 839 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 840 int ret; 841 842 ret = clk_prepare_enable(pcm3168a->scki); 843 if (ret) { 844 dev_err(dev, "Failed to enable mclk: %d\n", ret); 845 return ret; 846 } 847 848 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 849 pcm3168a->supplies); 850 if (ret) { 851 dev_err(dev, "Failed to enable supplies: %d\n", ret); 852 goto err_clk; 853 } 854 855 ret = pcm3168a_reset(pcm3168a); 856 if (ret) { 857 dev_err(dev, "Failed to reset device: %d\n", ret); 858 goto err_regulator; 859 } 860 861 regcache_cache_only(pcm3168a->regmap, false); 862 863 regcache_mark_dirty(pcm3168a->regmap); 864 865 ret = regcache_sync(pcm3168a->regmap); 866 if (ret) { 867 dev_err(dev, "Failed to sync regmap: %d\n", ret); 868 goto err_regulator; 869 } 870 871 return 0; 872 873 err_regulator: 874 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 875 pcm3168a->supplies); 876 err_clk: 877 clk_disable_unprepare(pcm3168a->scki); 878 879 return ret; 880 } 881 882 static int pcm3168a_rt_suspend(struct device *dev) 883 { 884 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 885 886 regcache_cache_only(pcm3168a->regmap, true); 887 888 pcm3168a_disable(dev); 889 890 return 0; 891 } 892 #endif 893 894 const struct dev_pm_ops pcm3168a_pm_ops = { 895 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 896 }; 897 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 898 899 MODULE_DESCRIPTION("PCM3168A codec driver"); 900 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 901 MODULE_LICENSE("GPL v2"); 902