1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCM3168A codec driver 4 * 5 * Copyright (C) 2015 Imagination Technologies Ltd. 6 * 7 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "pcm3168a.h" 21 22 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 23 SNDRV_PCM_FMTBIT_S24_3LE | \ 24 SNDRV_PCM_FMTBIT_S24_LE | \ 25 SNDRV_PCM_FMTBIT_S32_LE) 26 27 #define PCM3168A_FMT_I2S 0x0 28 #define PCM3168A_FMT_LEFT_J 0x1 29 #define PCM3168A_FMT_RIGHT_J 0x2 30 #define PCM3168A_FMT_RIGHT_J_16 0x3 31 #define PCM3168A_FMT_DSP_A 0x4 32 #define PCM3168A_FMT_DSP_B 0x5 33 #define PCM3168A_FMT_I2S_TDM 0x6 34 #define PCM3168A_FMT_LEFT_J_TDM 0x7 35 #define PCM3168A_FMT_DSP_MASK 0x4 36 37 #define PCM3168A_NUM_SUPPLIES 6 38 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 39 "VDD1", 40 "VDD2", 41 "VCCAD1", 42 "VCCAD2", 43 "VCCDA1", 44 "VCCDA2" 45 }; 46 47 #define PCM3168A_DAI_DAC 0 48 #define PCM3168A_DAI_ADC 1 49 50 /* ADC/DAC side parameters */ 51 struct pcm3168a_io_params { 52 bool master_mode; 53 unsigned int fmt; 54 int tdm_slots; 55 u32 tdm_mask; 56 int slot_width; 57 }; 58 59 struct pcm3168a_priv { 60 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 61 struct regmap *regmap; 62 struct clk *scki; 63 unsigned long sysclk; 64 65 struct pcm3168a_io_params io_params[2]; 66 }; 67 68 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 69 70 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 71 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 72 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 73 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 74 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 75 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 76 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 77 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 78 79 static const char *const pcm3168a_volume_type[] = { 80 "Individual", "Master + Individual" }; 81 82 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 83 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 84 85 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 86 87 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 88 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 89 90 static const char *const pcm3168a_demp[] = { 91 "Disabled", "48khz", "44.1khz", "32khz" }; 92 93 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 94 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 95 96 static const char *const pcm3168a_zf_func[] = { 97 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 98 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 99 100 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 101 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 102 103 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 104 105 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 106 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 107 108 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 109 110 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 111 0, 1, pcm3168a_con); 112 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 113 2, 3, pcm3168a_con); 114 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 115 4, 5, pcm3168a_con); 116 117 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 118 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 119 120 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 121 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 122 123 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 124 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 125 126 /* -100db to 0db, register values 0-54 cause mute */ 127 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 128 129 /* -100db to 20db, register values 0-14 cause mute */ 130 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 131 132 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 133 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 134 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 135 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 136 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 137 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 138 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 139 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 140 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 141 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 142 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 143 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 144 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 145 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 146 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 147 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 148 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 149 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 150 pcm3168a_dac_tlv), 151 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 152 PCM3168A_DAC_VOL_CHAN_START, 153 PCM3168A_DAC_VOL_CHAN_START + 1, 154 0, 54, 255, 0, pcm3168a_dac_tlv), 155 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 156 PCM3168A_DAC_VOL_CHAN_START + 2, 157 PCM3168A_DAC_VOL_CHAN_START + 3, 158 0, 54, 255, 0, pcm3168a_dac_tlv), 159 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 160 PCM3168A_DAC_VOL_CHAN_START + 4, 161 PCM3168A_DAC_VOL_CHAN_START + 5, 162 0, 54, 255, 0, pcm3168a_dac_tlv), 163 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 164 PCM3168A_DAC_VOL_CHAN_START + 6, 165 PCM3168A_DAC_VOL_CHAN_START + 7, 166 0, 54, 255, 0, pcm3168a_dac_tlv), 167 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 168 PCM3168A_ADC_BYP_SHIFT, 1, 1), 169 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 170 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 171 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 172 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 173 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 174 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 175 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 176 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 177 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 178 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 179 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 180 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 181 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 182 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 183 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 184 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 185 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 186 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 187 pcm3168a_adc_tlv), 188 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 189 PCM3168A_ADC_VOL_CHAN_START, 190 PCM3168A_ADC_VOL_CHAN_START + 1, 191 0, 14, 255, 0, pcm3168a_adc_tlv), 192 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 193 PCM3168A_ADC_VOL_CHAN_START + 2, 194 PCM3168A_ADC_VOL_CHAN_START + 3, 195 0, 14, 255, 0, pcm3168a_adc_tlv), 196 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 197 PCM3168A_ADC_VOL_CHAN_START + 4, 198 PCM3168A_ADC_VOL_CHAN_START + 5, 199 0, 14, 255, 0, pcm3168a_adc_tlv) 200 }; 201 202 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 203 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 204 PCM3168A_DAC_OPEDA_SHIFT, 1), 205 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 206 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 207 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 208 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 209 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 210 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 211 212 SND_SOC_DAPM_OUTPUT("AOUT1L"), 213 SND_SOC_DAPM_OUTPUT("AOUT1R"), 214 SND_SOC_DAPM_OUTPUT("AOUT2L"), 215 SND_SOC_DAPM_OUTPUT("AOUT2R"), 216 SND_SOC_DAPM_OUTPUT("AOUT3L"), 217 SND_SOC_DAPM_OUTPUT("AOUT3R"), 218 SND_SOC_DAPM_OUTPUT("AOUT4L"), 219 SND_SOC_DAPM_OUTPUT("AOUT4R"), 220 221 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 222 PCM3168A_ADC_PSVAD_SHIFT, 1), 223 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 224 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 225 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 226 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 227 228 SND_SOC_DAPM_INPUT("AIN1L"), 229 SND_SOC_DAPM_INPUT("AIN1R"), 230 SND_SOC_DAPM_INPUT("AIN2L"), 231 SND_SOC_DAPM_INPUT("AIN2R"), 232 SND_SOC_DAPM_INPUT("AIN3L"), 233 SND_SOC_DAPM_INPUT("AIN3R") 234 }; 235 236 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 237 /* Playback */ 238 { "AOUT1L", NULL, "DAC1" }, 239 { "AOUT1R", NULL, "DAC1" }, 240 241 { "AOUT2L", NULL, "DAC2" }, 242 { "AOUT2R", NULL, "DAC2" }, 243 244 { "AOUT3L", NULL, "DAC3" }, 245 { "AOUT3R", NULL, "DAC3" }, 246 247 { "AOUT4L", NULL, "DAC4" }, 248 { "AOUT4R", NULL, "DAC4" }, 249 250 /* Capture */ 251 { "ADC1", NULL, "AIN1L" }, 252 { "ADC1", NULL, "AIN1R" }, 253 254 { "ADC2", NULL, "AIN2L" }, 255 { "ADC2", NULL, "AIN2R" }, 256 257 { "ADC3", NULL, "AIN3L" }, 258 { "ADC3", NULL, "AIN3R" } 259 }; 260 261 static unsigned int pcm3168a_scki_ratios[] = { 262 768, 263 512, 264 384, 265 256, 266 192, 267 128 268 }; 269 270 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 271 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 272 273 #define PCM3168A_MAX_SYSCLK 36864000 274 275 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 276 { 277 int ret; 278 279 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 280 if (ret) 281 return ret; 282 283 /* Internal reset is de-asserted after 3846 SCKI cycles */ 284 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 285 286 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 287 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 288 } 289 290 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) 291 { 292 struct snd_soc_component *component = dai->component; 293 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 294 295 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 296 297 return 0; 298 } 299 300 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 301 int clk_id, unsigned int freq, int dir) 302 { 303 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 304 int ret; 305 306 if (freq > PCM3168A_MAX_SYSCLK) 307 return -EINVAL; 308 309 ret = clk_set_rate(pcm3168a->scki, freq); 310 if (ret) 311 return ret; 312 313 pcm3168a->sysclk = freq; 314 315 return 0; 316 } 317 318 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format) 319 { 320 struct snd_soc_component *component = dai->component; 321 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 322 u32 fmt, reg, mask, shift; 323 bool master_mode; 324 325 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 326 case SND_SOC_DAIFMT_LEFT_J: 327 fmt = PCM3168A_FMT_LEFT_J; 328 break; 329 case SND_SOC_DAIFMT_I2S: 330 fmt = PCM3168A_FMT_I2S; 331 break; 332 case SND_SOC_DAIFMT_RIGHT_J: 333 fmt = PCM3168A_FMT_RIGHT_J; 334 break; 335 case SND_SOC_DAIFMT_DSP_A: 336 fmt = PCM3168A_FMT_DSP_A; 337 break; 338 case SND_SOC_DAIFMT_DSP_B: 339 fmt = PCM3168A_FMT_DSP_B; 340 break; 341 default: 342 dev_err(component->dev, "unsupported dai format\n"); 343 return -EINVAL; 344 } 345 346 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 347 case SND_SOC_DAIFMT_CBS_CFS: 348 master_mode = false; 349 break; 350 case SND_SOC_DAIFMT_CBM_CFM: 351 master_mode = true; 352 break; 353 default: 354 dev_err(component->dev, "unsupported master/slave mode\n"); 355 return -EINVAL; 356 } 357 358 switch (format & SND_SOC_DAIFMT_INV_MASK) { 359 case SND_SOC_DAIFMT_NB_NF: 360 break; 361 default: 362 return -EINVAL; 363 } 364 365 if (dai->id == PCM3168A_DAI_DAC) { 366 reg = PCM3168A_DAC_PWR_MST_FMT; 367 mask = PCM3168A_DAC_FMT_MASK; 368 shift = PCM3168A_DAC_FMT_SHIFT; 369 } else { 370 reg = PCM3168A_ADC_MST_FMT; 371 mask = PCM3168A_ADC_FMTAD_MASK; 372 shift = PCM3168A_ADC_FMTAD_SHIFT; 373 } 374 375 pcm3168a->io_params[dai->id].master_mode = master_mode; 376 pcm3168a->io_params[dai->id].fmt = fmt; 377 378 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 379 380 return 0; 381 } 382 383 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 384 unsigned int rx_mask, int slots, 385 int slot_width) 386 { 387 struct snd_soc_component *component = dai->component; 388 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 389 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 390 391 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 392 dev_err(component->dev, 393 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 394 tx_mask, rx_mask, slots); 395 return -EINVAL; 396 } 397 398 if (slot_width && 399 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) { 400 dev_err(component->dev, "Unsupported slot_width %d\n", 401 slot_width); 402 return -EINVAL; 403 } 404 405 io_params->tdm_slots = slots; 406 io_params->slot_width = slot_width; 407 /* Ignore the not relevant mask for the DAI/direction */ 408 if (dai->id == PCM3168A_DAI_DAC) 409 io_params->tdm_mask = tx_mask; 410 else 411 io_params->tdm_mask = rx_mask; 412 413 return 0; 414 } 415 416 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 417 struct snd_pcm_hw_params *params, 418 struct snd_soc_dai *dai) 419 { 420 struct snd_soc_component *component = dai->component; 421 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 422 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 423 bool master_mode; 424 u32 val, mask, shift, reg; 425 unsigned int rate, fmt, ratio, max_ratio; 426 unsigned int tdm_slots; 427 int i, slot_width; 428 429 rate = params_rate(params); 430 431 ratio = pcm3168a->sysclk / rate; 432 433 if (dai->id == PCM3168A_DAI_DAC) { 434 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 435 reg = PCM3168A_DAC_PWR_MST_FMT; 436 mask = PCM3168A_DAC_MSDA_MASK; 437 shift = PCM3168A_DAC_MSDA_SHIFT; 438 } else { 439 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 440 reg = PCM3168A_ADC_MST_FMT; 441 mask = PCM3168A_ADC_MSAD_MASK; 442 shift = PCM3168A_ADC_MSAD_SHIFT; 443 } 444 445 master_mode = io_params->master_mode; 446 fmt = io_params->fmt; 447 448 for (i = 0; i < max_ratio; i++) { 449 if (pcm3168a_scki_ratios[i] == ratio) 450 break; 451 } 452 453 if (i == max_ratio) { 454 dev_err(component->dev, "unsupported sysclk ratio\n"); 455 return -EINVAL; 456 } 457 458 if (io_params->slot_width) 459 slot_width = io_params->slot_width; 460 else 461 slot_width = params_width(params); 462 463 switch (slot_width) { 464 case 16: 465 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 466 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n"); 467 return -EINVAL; 468 } 469 fmt = PCM3168A_FMT_RIGHT_J_16; 470 break; 471 case 24: 472 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 473 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n"); 474 return -EINVAL; 475 } 476 break; 477 case 32: 478 break; 479 default: 480 dev_err(component->dev, "unsupported frame size: %d\n", slot_width); 481 return -EINVAL; 482 } 483 484 if (io_params->tdm_slots) 485 tdm_slots = io_params->tdm_slots; 486 else 487 tdm_slots = params_channels(params); 488 489 /* 490 * Switch the codec to TDM mode when more than 2 TDM slots are needed 491 * for the stream. 492 * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually) 493 * then DIN1/DOUT1 is used in TDM mode. 494 * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is 495 * used in normal mode, no need to switch to TDM modes. 496 */ 497 if (tdm_slots > 2) { 498 switch (fmt) { 499 case PCM3168A_FMT_I2S: 500 case PCM3168A_FMT_DSP_A: 501 fmt = PCM3168A_FMT_I2S_TDM; 502 break; 503 case PCM3168A_FMT_LEFT_J: 504 case PCM3168A_FMT_DSP_B: 505 fmt = PCM3168A_FMT_LEFT_J_TDM; 506 break; 507 default: 508 dev_err(component->dev, 509 "TDM is supported under DSP/I2S/Left_J only\n"); 510 return -EINVAL; 511 } 512 } 513 514 if (master_mode) 515 val = ((i + 1) << shift); 516 else 517 val = 0; 518 519 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 520 521 if (dai->id == PCM3168A_DAI_DAC) { 522 mask = PCM3168A_DAC_FMT_MASK; 523 shift = PCM3168A_DAC_FMT_SHIFT; 524 } else { 525 mask = PCM3168A_ADC_FMTAD_MASK; 526 shift = PCM3168A_ADC_FMTAD_SHIFT; 527 } 528 529 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 530 531 return 0; 532 } 533 534 static int pcm3168a_startup(struct snd_pcm_substream *substream, 535 struct snd_soc_dai *dai) 536 { 537 struct snd_soc_component *component = dai->component; 538 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 539 unsigned int sample_min; 540 unsigned int channel_max; 541 unsigned int channel_maxs[] = { 542 8, /* DAC */ 543 6 /* ADC */ 544 }; 545 546 /* 547 * Available Data Bits 548 * 549 * RIGHT_J : 24 / 16 550 * LEFT_J : 24 551 * I2S : 24 552 * 553 * TDM available 554 * 555 * I2S 556 * LEFT_J 557 */ 558 switch (pcm3168a->io_params[dai->id].fmt) { 559 case PCM3168A_FMT_RIGHT_J: 560 sample_min = 16; 561 channel_max = 2; 562 break; 563 case PCM3168A_FMT_LEFT_J: 564 case PCM3168A_FMT_I2S: 565 case PCM3168A_FMT_DSP_A: 566 case PCM3168A_FMT_DSP_B: 567 sample_min = 24; 568 channel_max = channel_maxs[dai->id]; 569 break; 570 default: 571 sample_min = 24; 572 channel_max = 2; 573 } 574 575 snd_pcm_hw_constraint_minmax(substream->runtime, 576 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 577 sample_min, 32); 578 579 /* Allow all channels in multi DIN/DOUT mode */ 580 if (pcm3168a->io_params[dai->id].tdm_slots == 2) 581 channel_max = channel_maxs[dai->id]; 582 583 snd_pcm_hw_constraint_minmax(substream->runtime, 584 SNDRV_PCM_HW_PARAM_CHANNELS, 585 2, channel_max); 586 587 return 0; 588 } 589 static const struct snd_soc_dai_ops pcm3168a_dai_ops = { 590 .startup = pcm3168a_startup, 591 .set_fmt = pcm3168a_set_dai_fmt, 592 .set_sysclk = pcm3168a_set_dai_sysclk, 593 .hw_params = pcm3168a_hw_params, 594 .digital_mute = pcm3168a_digital_mute, 595 .set_tdm_slot = pcm3168a_set_tdm_slot, 596 }; 597 598 static struct snd_soc_dai_driver pcm3168a_dais[] = { 599 { 600 .name = "pcm3168a-dac", 601 .id = PCM3168A_DAI_DAC, 602 .playback = { 603 .stream_name = "Playback", 604 .channels_min = 1, 605 .channels_max = 8, 606 .rates = SNDRV_PCM_RATE_8000_192000, 607 .formats = PCM3168A_FORMATS 608 }, 609 .ops = &pcm3168a_dai_ops 610 }, 611 { 612 .name = "pcm3168a-adc", 613 .id = PCM3168A_DAI_ADC, 614 .capture = { 615 .stream_name = "Capture", 616 .channels_min = 1, 617 .channels_max = 6, 618 .rates = SNDRV_PCM_RATE_8000_96000, 619 .formats = PCM3168A_FORMATS 620 }, 621 .ops = &pcm3168a_dai_ops 622 }, 623 }; 624 625 static const struct reg_default pcm3168a_reg_default[] = { 626 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 627 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 628 { PCM3168A_DAC_OP_FLT, 0x00 }, 629 { PCM3168A_DAC_INV, 0x00 }, 630 { PCM3168A_DAC_MUTE, 0x00 }, 631 { PCM3168A_DAC_ZERO, 0x00 }, 632 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 633 { PCM3168A_DAC_VOL_MASTER, 0xff }, 634 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 635 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 636 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 637 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 638 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 639 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 640 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 641 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 642 { PCM3168A_ADC_SMODE, 0x00 }, 643 { PCM3168A_ADC_MST_FMT, 0x00 }, 644 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 645 { PCM3168A_ADC_SEAD, 0x00 }, 646 { PCM3168A_ADC_INV, 0x00 }, 647 { PCM3168A_ADC_MUTE, 0x00 }, 648 { PCM3168A_ADC_OV, 0x00 }, 649 { PCM3168A_ADC_ATT_OVF, 0x00 }, 650 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 651 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 652 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 653 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 654 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 655 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 656 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 657 }; 658 659 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 660 { 661 if (reg >= PCM3168A_RST_SMODE) 662 return true; 663 else 664 return false; 665 } 666 667 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 668 { 669 switch (reg) { 670 case PCM3168A_DAC_ZERO: 671 case PCM3168A_ADC_OV: 672 return true; 673 default: 674 return false; 675 } 676 } 677 678 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 679 { 680 if (reg < PCM3168A_RST_SMODE) 681 return false; 682 683 switch (reg) { 684 case PCM3168A_DAC_ZERO: 685 case PCM3168A_ADC_OV: 686 return false; 687 default: 688 return true; 689 } 690 } 691 692 const struct regmap_config pcm3168a_regmap = { 693 .reg_bits = 8, 694 .val_bits = 8, 695 696 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 697 .reg_defaults = pcm3168a_reg_default, 698 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 699 .readable_reg = pcm3168a_readable_register, 700 .volatile_reg = pcm3168a_volatile_register, 701 .writeable_reg = pcm3168a_writeable_register, 702 .cache_type = REGCACHE_FLAT 703 }; 704 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 705 706 static const struct snd_soc_component_driver pcm3168a_driver = { 707 .controls = pcm3168a_snd_controls, 708 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 709 .dapm_widgets = pcm3168a_dapm_widgets, 710 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 711 .dapm_routes = pcm3168a_dapm_routes, 712 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 713 .use_pmdown_time = 1, 714 .endianness = 1, 715 .non_legacy_dai_naming = 1, 716 }; 717 718 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 719 { 720 struct pcm3168a_priv *pcm3168a; 721 int ret, i; 722 723 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 724 if (pcm3168a == NULL) 725 return -ENOMEM; 726 727 dev_set_drvdata(dev, pcm3168a); 728 729 pcm3168a->scki = devm_clk_get(dev, "scki"); 730 if (IS_ERR(pcm3168a->scki)) { 731 ret = PTR_ERR(pcm3168a->scki); 732 if (ret != -EPROBE_DEFER) 733 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 734 return ret; 735 } 736 737 ret = clk_prepare_enable(pcm3168a->scki); 738 if (ret) { 739 dev_err(dev, "Failed to enable mclk: %d\n", ret); 740 return ret; 741 } 742 743 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 744 745 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 746 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 747 748 ret = devm_regulator_bulk_get(dev, 749 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 750 if (ret) { 751 if (ret != -EPROBE_DEFER) 752 dev_err(dev, "failed to request supplies: %d\n", ret); 753 goto err_clk; 754 } 755 756 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 757 pcm3168a->supplies); 758 if (ret) { 759 dev_err(dev, "failed to enable supplies: %d\n", ret); 760 goto err_clk; 761 } 762 763 pcm3168a->regmap = regmap; 764 if (IS_ERR(pcm3168a->regmap)) { 765 ret = PTR_ERR(pcm3168a->regmap); 766 dev_err(dev, "failed to allocate regmap: %d\n", ret); 767 goto err_regulator; 768 } 769 770 ret = pcm3168a_reset(pcm3168a); 771 if (ret) { 772 dev_err(dev, "Failed to reset device: %d\n", ret); 773 goto err_regulator; 774 } 775 776 pm_runtime_set_active(dev); 777 pm_runtime_enable(dev); 778 pm_runtime_idle(dev); 779 780 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais, 781 ARRAY_SIZE(pcm3168a_dais)); 782 if (ret) { 783 dev_err(dev, "failed to register component: %d\n", ret); 784 goto err_regulator; 785 } 786 787 return 0; 788 789 err_regulator: 790 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 791 pcm3168a->supplies); 792 err_clk: 793 clk_disable_unprepare(pcm3168a->scki); 794 795 return ret; 796 } 797 EXPORT_SYMBOL_GPL(pcm3168a_probe); 798 799 static void pcm3168a_disable(struct device *dev) 800 { 801 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 802 803 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 804 pcm3168a->supplies); 805 clk_disable_unprepare(pcm3168a->scki); 806 } 807 808 void pcm3168a_remove(struct device *dev) 809 { 810 pm_runtime_disable(dev); 811 #ifndef CONFIG_PM 812 pcm3168a_disable(dev); 813 #endif 814 } 815 EXPORT_SYMBOL_GPL(pcm3168a_remove); 816 817 #ifdef CONFIG_PM 818 static int pcm3168a_rt_resume(struct device *dev) 819 { 820 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 821 int ret; 822 823 ret = clk_prepare_enable(pcm3168a->scki); 824 if (ret) { 825 dev_err(dev, "Failed to enable mclk: %d\n", ret); 826 return ret; 827 } 828 829 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 830 pcm3168a->supplies); 831 if (ret) { 832 dev_err(dev, "Failed to enable supplies: %d\n", ret); 833 goto err_clk; 834 } 835 836 ret = pcm3168a_reset(pcm3168a); 837 if (ret) { 838 dev_err(dev, "Failed to reset device: %d\n", ret); 839 goto err_regulator; 840 } 841 842 regcache_cache_only(pcm3168a->regmap, false); 843 844 regcache_mark_dirty(pcm3168a->regmap); 845 846 ret = regcache_sync(pcm3168a->regmap); 847 if (ret) { 848 dev_err(dev, "Failed to sync regmap: %d\n", ret); 849 goto err_regulator; 850 } 851 852 return 0; 853 854 err_regulator: 855 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 856 pcm3168a->supplies); 857 err_clk: 858 clk_disable_unprepare(pcm3168a->scki); 859 860 return ret; 861 } 862 863 static int pcm3168a_rt_suspend(struct device *dev) 864 { 865 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 866 867 regcache_cache_only(pcm3168a->regmap, true); 868 869 pcm3168a_disable(dev); 870 871 return 0; 872 } 873 #endif 874 875 const struct dev_pm_ops pcm3168a_pm_ops = { 876 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 877 }; 878 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 879 880 MODULE_DESCRIPTION("PCM3168A codec driver"); 881 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 882 MODULE_LICENSE("GPL v2"); 883