1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCM3168A codec driver 4 * 5 * Copyright (C) 2015 Imagination Technologies Ltd. 6 * 7 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "pcm3168a.h" 21 22 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 23 SNDRV_PCM_FMTBIT_S24_3LE | \ 24 SNDRV_PCM_FMTBIT_S24_LE) 25 26 #define PCM3168A_FMT_I2S 0x0 27 #define PCM3168A_FMT_LEFT_J 0x1 28 #define PCM3168A_FMT_RIGHT_J 0x2 29 #define PCM3168A_FMT_RIGHT_J_16 0x3 30 #define PCM3168A_FMT_DSP_A 0x4 31 #define PCM3168A_FMT_DSP_B 0x5 32 #define PCM3168A_FMT_I2S_TDM 0x6 33 #define PCM3168A_FMT_LEFT_J_TDM 0x7 34 #define PCM3168A_FMT_DSP_MASK 0x4 35 36 #define PCM3168A_NUM_SUPPLIES 6 37 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 38 "VDD1", 39 "VDD2", 40 "VCCAD1", 41 "VCCAD2", 42 "VCCDA1", 43 "VCCDA2" 44 }; 45 46 #define PCM3168A_DAI_DAC 0 47 #define PCM3168A_DAI_ADC 1 48 49 /* ADC/DAC side parameters */ 50 struct pcm3168a_io_params { 51 bool master_mode; 52 unsigned int fmt; 53 int tdm_slots; 54 u32 tdm_mask; 55 int slot_width; 56 }; 57 58 struct pcm3168a_priv { 59 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 60 struct regmap *regmap; 61 struct clk *scki; 62 unsigned long sysclk; 63 64 struct pcm3168a_io_params io_params[2]; 65 }; 66 67 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 68 69 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 70 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 71 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 72 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 73 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 74 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 75 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 76 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 77 78 static const char *const pcm3168a_volume_type[] = { 79 "Individual", "Master + Individual" }; 80 81 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 82 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 83 84 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 85 86 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 87 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 88 89 static const char *const pcm3168a_demp[] = { 90 "Disabled", "48khz", "44.1khz", "32khz" }; 91 92 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 93 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 94 95 static const char *const pcm3168a_zf_func[] = { 96 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 97 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 98 99 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 100 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 101 102 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 103 104 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 105 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 106 107 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 108 109 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 110 0, 1, pcm3168a_con); 111 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 112 2, 3, pcm3168a_con); 113 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 114 4, 5, pcm3168a_con); 115 116 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 117 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 118 119 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 120 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 121 122 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 123 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 124 125 /* -100db to 0db, register values 0-54 cause mute */ 126 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 127 128 /* -100db to 20db, register values 0-14 cause mute */ 129 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 130 131 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 132 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 133 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 134 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 135 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 136 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 137 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 138 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 139 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 140 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 141 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 142 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 143 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 144 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 145 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 146 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 147 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 148 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 149 pcm3168a_dac_tlv), 150 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 151 PCM3168A_DAC_VOL_CHAN_START, 152 PCM3168A_DAC_VOL_CHAN_START + 1, 153 0, 54, 255, 0, pcm3168a_dac_tlv), 154 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 155 PCM3168A_DAC_VOL_CHAN_START + 2, 156 PCM3168A_DAC_VOL_CHAN_START + 3, 157 0, 54, 255, 0, pcm3168a_dac_tlv), 158 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 159 PCM3168A_DAC_VOL_CHAN_START + 4, 160 PCM3168A_DAC_VOL_CHAN_START + 5, 161 0, 54, 255, 0, pcm3168a_dac_tlv), 162 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 163 PCM3168A_DAC_VOL_CHAN_START + 6, 164 PCM3168A_DAC_VOL_CHAN_START + 7, 165 0, 54, 255, 0, pcm3168a_dac_tlv), 166 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 167 PCM3168A_ADC_BYP_SHIFT, 1, 1), 168 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 169 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 170 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 171 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 172 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 173 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 174 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 175 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 176 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 177 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 178 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 179 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 180 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 181 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 182 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 183 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 184 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 185 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 186 pcm3168a_adc_tlv), 187 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 188 PCM3168A_ADC_VOL_CHAN_START, 189 PCM3168A_ADC_VOL_CHAN_START + 1, 190 0, 14, 255, 0, pcm3168a_adc_tlv), 191 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 192 PCM3168A_ADC_VOL_CHAN_START + 2, 193 PCM3168A_ADC_VOL_CHAN_START + 3, 194 0, 14, 255, 0, pcm3168a_adc_tlv), 195 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 196 PCM3168A_ADC_VOL_CHAN_START + 4, 197 PCM3168A_ADC_VOL_CHAN_START + 5, 198 0, 14, 255, 0, pcm3168a_adc_tlv) 199 }; 200 201 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 202 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 203 PCM3168A_DAC_OPEDA_SHIFT, 1), 204 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 205 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 206 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 207 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 208 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 209 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 210 211 SND_SOC_DAPM_OUTPUT("AOUT1L"), 212 SND_SOC_DAPM_OUTPUT("AOUT1R"), 213 SND_SOC_DAPM_OUTPUT("AOUT2L"), 214 SND_SOC_DAPM_OUTPUT("AOUT2R"), 215 SND_SOC_DAPM_OUTPUT("AOUT3L"), 216 SND_SOC_DAPM_OUTPUT("AOUT3R"), 217 SND_SOC_DAPM_OUTPUT("AOUT4L"), 218 SND_SOC_DAPM_OUTPUT("AOUT4R"), 219 220 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 221 PCM3168A_ADC_PSVAD_SHIFT, 1), 222 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 223 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 224 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 225 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 226 227 SND_SOC_DAPM_INPUT("AIN1L"), 228 SND_SOC_DAPM_INPUT("AIN1R"), 229 SND_SOC_DAPM_INPUT("AIN2L"), 230 SND_SOC_DAPM_INPUT("AIN2R"), 231 SND_SOC_DAPM_INPUT("AIN3L"), 232 SND_SOC_DAPM_INPUT("AIN3R") 233 }; 234 235 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 236 /* Playback */ 237 { "AOUT1L", NULL, "DAC1" }, 238 { "AOUT1R", NULL, "DAC1" }, 239 240 { "AOUT2L", NULL, "DAC2" }, 241 { "AOUT2R", NULL, "DAC2" }, 242 243 { "AOUT3L", NULL, "DAC3" }, 244 { "AOUT3R", NULL, "DAC3" }, 245 246 { "AOUT4L", NULL, "DAC4" }, 247 { "AOUT4R", NULL, "DAC4" }, 248 249 /* Capture */ 250 { "ADC1", NULL, "AIN1L" }, 251 { "ADC1", NULL, "AIN1R" }, 252 253 { "ADC2", NULL, "AIN2L" }, 254 { "ADC2", NULL, "AIN2R" }, 255 256 { "ADC3", NULL, "AIN3L" }, 257 { "ADC3", NULL, "AIN3R" } 258 }; 259 260 static unsigned int pcm3168a_scki_ratios[] = { 261 768, 262 512, 263 384, 264 256, 265 192, 266 128 267 }; 268 269 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 270 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 271 272 #define PCM3168A_MAX_SYSCLK 36864000 273 274 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 275 { 276 int ret; 277 278 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 279 if (ret) 280 return ret; 281 282 /* Internal reset is de-asserted after 3846 SCKI cycles */ 283 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 284 285 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 286 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 287 } 288 289 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) 290 { 291 struct snd_soc_component *component = dai->component; 292 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 293 294 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 295 296 return 0; 297 } 298 299 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 300 int clk_id, unsigned int freq, int dir) 301 { 302 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 303 int ret; 304 305 if (freq > PCM3168A_MAX_SYSCLK) 306 return -EINVAL; 307 308 ret = clk_set_rate(pcm3168a->scki, freq); 309 if (ret) 310 return ret; 311 312 pcm3168a->sysclk = freq; 313 314 return 0; 315 } 316 317 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format) 318 { 319 struct snd_soc_component *component = dai->component; 320 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 321 u32 fmt, reg, mask, shift; 322 bool master_mode; 323 324 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 325 case SND_SOC_DAIFMT_LEFT_J: 326 fmt = PCM3168A_FMT_LEFT_J; 327 break; 328 case SND_SOC_DAIFMT_I2S: 329 fmt = PCM3168A_FMT_I2S; 330 break; 331 case SND_SOC_DAIFMT_RIGHT_J: 332 fmt = PCM3168A_FMT_RIGHT_J; 333 break; 334 case SND_SOC_DAIFMT_DSP_A: 335 fmt = PCM3168A_FMT_DSP_A; 336 break; 337 case SND_SOC_DAIFMT_DSP_B: 338 fmt = PCM3168A_FMT_DSP_B; 339 break; 340 default: 341 dev_err(component->dev, "unsupported dai format\n"); 342 return -EINVAL; 343 } 344 345 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 346 case SND_SOC_DAIFMT_CBS_CFS: 347 master_mode = false; 348 break; 349 case SND_SOC_DAIFMT_CBM_CFM: 350 master_mode = true; 351 break; 352 default: 353 dev_err(component->dev, "unsupported master/slave mode\n"); 354 return -EINVAL; 355 } 356 357 switch (format & SND_SOC_DAIFMT_INV_MASK) { 358 case SND_SOC_DAIFMT_NB_NF: 359 break; 360 default: 361 return -EINVAL; 362 } 363 364 if (dai->id == PCM3168A_DAI_DAC) { 365 reg = PCM3168A_DAC_PWR_MST_FMT; 366 mask = PCM3168A_DAC_FMT_MASK; 367 shift = PCM3168A_DAC_FMT_SHIFT; 368 } else { 369 reg = PCM3168A_ADC_MST_FMT; 370 mask = PCM3168A_ADC_FMTAD_MASK; 371 shift = PCM3168A_ADC_FMTAD_SHIFT; 372 } 373 374 pcm3168a->io_params[dai->id].master_mode = master_mode; 375 pcm3168a->io_params[dai->id].fmt = fmt; 376 377 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 378 379 return 0; 380 } 381 382 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 383 unsigned int rx_mask, int slots, 384 int slot_width) 385 { 386 struct snd_soc_component *component = dai->component; 387 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 388 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 389 390 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 391 dev_err(component->dev, 392 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 393 tx_mask, rx_mask, slots); 394 return -EINVAL; 395 } 396 397 if (slot_width && 398 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) { 399 dev_err(component->dev, "Unsupported slot_width %d\n", 400 slot_width); 401 return -EINVAL; 402 } 403 404 io_params->tdm_slots = slots; 405 io_params->slot_width = slot_width; 406 /* Ignore the not relevant mask for the DAI/direction */ 407 if (dai->id == PCM3168A_DAI_DAC) 408 io_params->tdm_mask = tx_mask; 409 else 410 io_params->tdm_mask = rx_mask; 411 412 return 0; 413 } 414 415 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 416 struct snd_pcm_hw_params *params, 417 struct snd_soc_dai *dai) 418 { 419 struct snd_soc_component *component = dai->component; 420 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 421 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id]; 422 bool master_mode; 423 u32 val, mask, shift, reg; 424 unsigned int rate, fmt, ratio, max_ratio; 425 unsigned int tdm_slots; 426 int i, slot_width; 427 428 rate = params_rate(params); 429 430 ratio = pcm3168a->sysclk / rate; 431 432 if (dai->id == PCM3168A_DAI_DAC) { 433 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 434 reg = PCM3168A_DAC_PWR_MST_FMT; 435 mask = PCM3168A_DAC_MSDA_MASK; 436 shift = PCM3168A_DAC_MSDA_SHIFT; 437 } else { 438 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 439 reg = PCM3168A_ADC_MST_FMT; 440 mask = PCM3168A_ADC_MSAD_MASK; 441 shift = PCM3168A_ADC_MSAD_SHIFT; 442 } 443 444 master_mode = io_params->master_mode; 445 fmt = io_params->fmt; 446 447 for (i = 0; i < max_ratio; i++) { 448 if (pcm3168a_scki_ratios[i] == ratio) 449 break; 450 } 451 452 if (i == max_ratio) { 453 dev_err(component->dev, "unsupported sysclk ratio\n"); 454 return -EINVAL; 455 } 456 457 if (io_params->slot_width) 458 slot_width = io_params->slot_width; 459 else 460 slot_width = params_width(params); 461 462 switch (slot_width) { 463 case 16: 464 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 465 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n"); 466 return -EINVAL; 467 } 468 fmt = PCM3168A_FMT_RIGHT_J_16; 469 break; 470 case 24: 471 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 472 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n"); 473 return -EINVAL; 474 } 475 break; 476 case 32: 477 break; 478 default: 479 dev_err(component->dev, "unsupported frame size: %d\n", slot_width); 480 return -EINVAL; 481 } 482 483 if (io_params->tdm_slots) 484 tdm_slots = io_params->tdm_slots; 485 else 486 tdm_slots = params_channels(params); 487 488 /* 489 * Switch the codec to TDM mode when more than 2 TDM slots are needed 490 * for the stream. 491 * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually) 492 * then DIN1/DOUT1 is used in TDM mode. 493 * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is 494 * used in normal mode, no need to switch to TDM modes. 495 */ 496 if (tdm_slots > 2) { 497 switch (fmt) { 498 case PCM3168A_FMT_I2S: 499 case PCM3168A_FMT_DSP_A: 500 fmt = PCM3168A_FMT_I2S_TDM; 501 break; 502 case PCM3168A_FMT_LEFT_J: 503 case PCM3168A_FMT_DSP_B: 504 fmt = PCM3168A_FMT_LEFT_J_TDM; 505 break; 506 default: 507 dev_err(component->dev, 508 "TDM is supported under DSP/I2S/Left_J only\n"); 509 return -EINVAL; 510 } 511 } 512 513 if (master_mode) 514 val = ((i + 1) << shift); 515 else 516 val = 0; 517 518 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 519 520 if (dai->id == PCM3168A_DAI_DAC) { 521 mask = PCM3168A_DAC_FMT_MASK; 522 shift = PCM3168A_DAC_FMT_SHIFT; 523 } else { 524 mask = PCM3168A_ADC_FMTAD_MASK; 525 shift = PCM3168A_ADC_FMTAD_SHIFT; 526 } 527 528 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 529 530 return 0; 531 } 532 533 static int pcm3168a_startup(struct snd_pcm_substream *substream, 534 struct snd_soc_dai *dai) 535 { 536 struct snd_soc_component *component = dai->component; 537 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 538 unsigned int sample_min; 539 unsigned int channel_max; 540 unsigned int channel_maxs[] = { 541 8, /* DAC */ 542 6 /* ADC */ 543 }; 544 545 /* 546 * Available Data Bits 547 * 548 * RIGHT_J : 24 / 16 549 * LEFT_J : 24 550 * I2S : 24 551 * 552 * TDM available 553 * 554 * I2S 555 * LEFT_J 556 */ 557 switch (pcm3168a->io_params[dai->id].fmt) { 558 case PCM3168A_FMT_RIGHT_J: 559 sample_min = 16; 560 channel_max = 2; 561 break; 562 case PCM3168A_FMT_LEFT_J: 563 case PCM3168A_FMT_I2S: 564 case PCM3168A_FMT_DSP_A: 565 case PCM3168A_FMT_DSP_B: 566 sample_min = 24; 567 channel_max = channel_maxs[dai->id]; 568 break; 569 default: 570 sample_min = 24; 571 channel_max = 2; 572 } 573 574 snd_pcm_hw_constraint_minmax(substream->runtime, 575 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 576 sample_min, 32); 577 578 /* Allow all channels in multi DIN/DOUT mode */ 579 if (pcm3168a->io_params[dai->id].tdm_slots == 2) 580 channel_max = channel_maxs[dai->id]; 581 582 snd_pcm_hw_constraint_minmax(substream->runtime, 583 SNDRV_PCM_HW_PARAM_CHANNELS, 584 2, channel_max); 585 586 return 0; 587 } 588 static const struct snd_soc_dai_ops pcm3168a_dai_ops = { 589 .startup = pcm3168a_startup, 590 .set_fmt = pcm3168a_set_dai_fmt, 591 .set_sysclk = pcm3168a_set_dai_sysclk, 592 .hw_params = pcm3168a_hw_params, 593 .digital_mute = pcm3168a_digital_mute, 594 .set_tdm_slot = pcm3168a_set_tdm_slot, 595 }; 596 597 static struct snd_soc_dai_driver pcm3168a_dais[] = { 598 { 599 .name = "pcm3168a-dac", 600 .id = PCM3168A_DAI_DAC, 601 .playback = { 602 .stream_name = "Playback", 603 .channels_min = 1, 604 .channels_max = 8, 605 .rates = SNDRV_PCM_RATE_8000_192000, 606 .formats = PCM3168A_FORMATS 607 }, 608 .ops = &pcm3168a_dai_ops 609 }, 610 { 611 .name = "pcm3168a-adc", 612 .id = PCM3168A_DAI_ADC, 613 .capture = { 614 .stream_name = "Capture", 615 .channels_min = 1, 616 .channels_max = 6, 617 .rates = SNDRV_PCM_RATE_8000_96000, 618 .formats = PCM3168A_FORMATS 619 }, 620 .ops = &pcm3168a_dai_ops 621 }, 622 }; 623 624 static const struct reg_default pcm3168a_reg_default[] = { 625 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 626 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 627 { PCM3168A_DAC_OP_FLT, 0x00 }, 628 { PCM3168A_DAC_INV, 0x00 }, 629 { PCM3168A_DAC_MUTE, 0x00 }, 630 { PCM3168A_DAC_ZERO, 0x00 }, 631 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 632 { PCM3168A_DAC_VOL_MASTER, 0xff }, 633 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 634 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 635 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 636 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 637 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 638 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 639 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 640 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 641 { PCM3168A_ADC_SMODE, 0x00 }, 642 { PCM3168A_ADC_MST_FMT, 0x00 }, 643 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 644 { PCM3168A_ADC_SEAD, 0x00 }, 645 { PCM3168A_ADC_INV, 0x00 }, 646 { PCM3168A_ADC_MUTE, 0x00 }, 647 { PCM3168A_ADC_OV, 0x00 }, 648 { PCM3168A_ADC_ATT_OVF, 0x00 }, 649 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 650 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 651 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 652 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 653 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 654 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 655 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 656 }; 657 658 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 659 { 660 if (reg >= PCM3168A_RST_SMODE) 661 return true; 662 else 663 return false; 664 } 665 666 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 667 { 668 switch (reg) { 669 case PCM3168A_DAC_ZERO: 670 case PCM3168A_ADC_OV: 671 return true; 672 default: 673 return false; 674 } 675 } 676 677 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 678 { 679 if (reg < PCM3168A_RST_SMODE) 680 return false; 681 682 switch (reg) { 683 case PCM3168A_DAC_ZERO: 684 case PCM3168A_ADC_OV: 685 return false; 686 default: 687 return true; 688 } 689 } 690 691 const struct regmap_config pcm3168a_regmap = { 692 .reg_bits = 8, 693 .val_bits = 8, 694 695 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 696 .reg_defaults = pcm3168a_reg_default, 697 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 698 .readable_reg = pcm3168a_readable_register, 699 .volatile_reg = pcm3168a_volatile_register, 700 .writeable_reg = pcm3168a_writeable_register, 701 .cache_type = REGCACHE_FLAT 702 }; 703 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 704 705 static const struct snd_soc_component_driver pcm3168a_driver = { 706 .controls = pcm3168a_snd_controls, 707 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 708 .dapm_widgets = pcm3168a_dapm_widgets, 709 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 710 .dapm_routes = pcm3168a_dapm_routes, 711 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 712 .use_pmdown_time = 1, 713 .endianness = 1, 714 .non_legacy_dai_naming = 1, 715 }; 716 717 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 718 { 719 struct pcm3168a_priv *pcm3168a; 720 int ret, i; 721 722 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 723 if (pcm3168a == NULL) 724 return -ENOMEM; 725 726 dev_set_drvdata(dev, pcm3168a); 727 728 pcm3168a->scki = devm_clk_get(dev, "scki"); 729 if (IS_ERR(pcm3168a->scki)) { 730 ret = PTR_ERR(pcm3168a->scki); 731 if (ret != -EPROBE_DEFER) 732 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 733 return ret; 734 } 735 736 ret = clk_prepare_enable(pcm3168a->scki); 737 if (ret) { 738 dev_err(dev, "Failed to enable mclk: %d\n", ret); 739 return ret; 740 } 741 742 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 743 744 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 745 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 746 747 ret = devm_regulator_bulk_get(dev, 748 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 749 if (ret) { 750 if (ret != -EPROBE_DEFER) 751 dev_err(dev, "failed to request supplies: %d\n", ret); 752 goto err_clk; 753 } 754 755 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 756 pcm3168a->supplies); 757 if (ret) { 758 dev_err(dev, "failed to enable supplies: %d\n", ret); 759 goto err_clk; 760 } 761 762 pcm3168a->regmap = regmap; 763 if (IS_ERR(pcm3168a->regmap)) { 764 ret = PTR_ERR(pcm3168a->regmap); 765 dev_err(dev, "failed to allocate regmap: %d\n", ret); 766 goto err_regulator; 767 } 768 769 ret = pcm3168a_reset(pcm3168a); 770 if (ret) { 771 dev_err(dev, "Failed to reset device: %d\n", ret); 772 goto err_regulator; 773 } 774 775 pm_runtime_set_active(dev); 776 pm_runtime_enable(dev); 777 pm_runtime_idle(dev); 778 779 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais, 780 ARRAY_SIZE(pcm3168a_dais)); 781 if (ret) { 782 dev_err(dev, "failed to register component: %d\n", ret); 783 goto err_regulator; 784 } 785 786 return 0; 787 788 err_regulator: 789 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 790 pcm3168a->supplies); 791 err_clk: 792 clk_disable_unprepare(pcm3168a->scki); 793 794 return ret; 795 } 796 EXPORT_SYMBOL_GPL(pcm3168a_probe); 797 798 static void pcm3168a_disable(struct device *dev) 799 { 800 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 801 802 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 803 pcm3168a->supplies); 804 clk_disable_unprepare(pcm3168a->scki); 805 } 806 807 void pcm3168a_remove(struct device *dev) 808 { 809 pm_runtime_disable(dev); 810 #ifndef CONFIG_PM 811 pcm3168a_disable(dev); 812 #endif 813 } 814 EXPORT_SYMBOL_GPL(pcm3168a_remove); 815 816 #ifdef CONFIG_PM 817 static int pcm3168a_rt_resume(struct device *dev) 818 { 819 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 820 int ret; 821 822 ret = clk_prepare_enable(pcm3168a->scki); 823 if (ret) { 824 dev_err(dev, "Failed to enable mclk: %d\n", ret); 825 return ret; 826 } 827 828 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 829 pcm3168a->supplies); 830 if (ret) { 831 dev_err(dev, "Failed to enable supplies: %d\n", ret); 832 goto err_clk; 833 } 834 835 ret = pcm3168a_reset(pcm3168a); 836 if (ret) { 837 dev_err(dev, "Failed to reset device: %d\n", ret); 838 goto err_regulator; 839 } 840 841 regcache_cache_only(pcm3168a->regmap, false); 842 843 regcache_mark_dirty(pcm3168a->regmap); 844 845 ret = regcache_sync(pcm3168a->regmap); 846 if (ret) { 847 dev_err(dev, "Failed to sync regmap: %d\n", ret); 848 goto err_regulator; 849 } 850 851 return 0; 852 853 err_regulator: 854 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 855 pcm3168a->supplies); 856 err_clk: 857 clk_disable_unprepare(pcm3168a->scki); 858 859 return ret; 860 } 861 862 static int pcm3168a_rt_suspend(struct device *dev) 863 { 864 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 865 866 regcache_cache_only(pcm3168a->regmap, true); 867 868 pcm3168a_disable(dev); 869 870 return 0; 871 } 872 #endif 873 874 const struct dev_pm_ops pcm3168a_pm_ops = { 875 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 876 }; 877 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 878 879 MODULE_DESCRIPTION("PCM3168A codec driver"); 880 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 881 MODULE_LICENSE("GPL v2"); 882