1 /* 2 * NAU8825 ALSA SoC audio driver 3 * 4 * Copyright 2015 Google Inc. 5 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __NAU8825_H__ 13 #define __NAU8825_H__ 14 15 #define NAU8825_REG_RESET 0x00 16 #define NAU8825_REG_ENA_CTRL 0x01 17 #define NAU8825_REG_CLK_DIVIDER 0x03 18 #define NAU8825_REG_FLL1 0x04 19 #define NAU8825_REG_FLL2 0x05 20 #define NAU8825_REG_FLL3 0x06 21 #define NAU8825_REG_FLL4 0x07 22 #define NAU8825_REG_FLL5 0x08 23 #define NAU8825_REG_FLL6 0x09 24 #define NAU8825_REG_FLL_VCO_RSV 0x0a 25 #define NAU8825_REG_HSD_CTRL 0x0c 26 #define NAU8825_REG_JACK_DET_CTRL 0x0d 27 #define NAU8825_REG_INTERRUPT_MASK 0x0f 28 #define NAU8825_REG_IRQ_STATUS 0x10 29 #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 30 #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 31 #define NAU8825_REG_SAR_CTRL 0x13 32 #define NAU8825_REG_KEYDET_CTRL 0x14 33 #define NAU8825_REG_VDET_THRESHOLD_1 0x15 34 #define NAU8825_REG_VDET_THRESHOLD_2 0x16 35 #define NAU8825_REG_VDET_THRESHOLD_3 0x17 36 #define NAU8825_REG_VDET_THRESHOLD_4 0x18 37 #define NAU8825_REG_GPIO34_CTRL 0x19 38 #define NAU8825_REG_GPIO12_CTRL 0x1a 39 #define NAU8825_REG_TDM_CTRL 0x1b 40 #define NAU8825_REG_I2S_PCM_CTRL1 0x1c 41 #define NAU8825_REG_I2S_PCM_CTRL2 0x1d 42 #define NAU8825_REG_LEFT_TIME_SLOT 0x1e 43 #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f 44 #define NAU8825_REG_BIQ_CTRL 0x20 45 #define NAU8825_REG_BIQ_COF1 0x21 46 #define NAU8825_REG_BIQ_COF2 0x22 47 #define NAU8825_REG_BIQ_COF3 0x23 48 #define NAU8825_REG_BIQ_COF4 0x24 49 #define NAU8825_REG_BIQ_COF5 0x25 50 #define NAU8825_REG_BIQ_COF6 0x26 51 #define NAU8825_REG_BIQ_COF7 0x27 52 #define NAU8825_REG_BIQ_COF8 0x28 53 #define NAU8825_REG_BIQ_COF9 0x29 54 #define NAU8825_REG_BIQ_COF10 0x2a 55 #define NAU8825_REG_ADC_RATE 0x2b 56 #define NAU8825_REG_DAC_CTRL1 0x2c 57 #define NAU8825_REG_DAC_CTRL2 0x2d 58 #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f 59 #define NAU8825_REG_ADC_DGAIN_CTRL 0x30 60 #define NAU8825_REG_MUTE_CTRL 0x31 61 #define NAU8825_REG_HSVOL_CTRL 0x32 62 #define NAU8825_REG_DACL_CTRL 0x33 63 #define NAU8825_REG_DACR_CTRL 0x34 64 #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 65 #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 66 #define NAU8825_REG_ADC_DRC_SLOPES 0x3a 67 #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b 68 #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 69 #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 70 #define NAU8825_REG_DAC_DRC_SLOPES 0x47 71 #define NAU8825_REG_DAC_DRC_ATKDCY 0x48 72 #define NAU8825_REG_IMM_MODE_CTRL 0x4c 73 #define NAU8825_REG_IMM_RMS_L 0x4d 74 #define NAU8825_REG_IMM_RMS_R 0x4e 75 #define NAU8825_REG_CLASSG_CTRL 0x50 76 #define NAU8825_REG_OPT_EFUSE_CTRL 0x51 77 #define NAU8825_REG_MISC_CTRL 0x55 78 #define NAU8825_REG_I2C_DEVICE_ID 0x58 79 #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 80 #define NAU8825_REG_BIAS_ADJ 0x66 81 #define NAU8825_REG_TRIM_SETTINGS 0x68 82 #define NAU8825_REG_ANALOG_CONTROL_1 0x69 83 #define NAU8825_REG_ANALOG_CONTROL_2 0x6a 84 #define NAU8825_REG_ANALOG_ADC_1 0x71 85 #define NAU8825_REG_ANALOG_ADC_2 0x72 86 #define NAU8825_REG_RDAC 0x73 87 #define NAU8825_REG_MIC_BIAS 0x74 88 #define NAU8825_REG_BOOST 0x76 89 #define NAU8825_REG_FEPGA 0x77 90 #define NAU8825_REG_POWER_UP_CONTROL 0x7f 91 #define NAU8825_REG_CHARGE_PUMP 0x80 92 #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 93 #define NAU8825_REG_GENERAL_STATUS 0x82 94 #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS 95 96 /* ENA_CTRL (0x1) */ 97 #define NAU8825_ENABLE_DACR_SFT 10 98 #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT) 99 #define NAU8825_ENABLE_DACL_SFT 9 100 #define NAU8825_ENABLE_ADC_SFT 8 101 #define NAU8825_ENABLE_SAR_SFT 1 102 103 /* CLK_DIVIDER (0x3) */ 104 #define NAU8825_CLK_SRC_SFT 15 105 #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) 106 #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) 107 #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) 108 #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) 109 110 /* FLL1 (0x04) */ 111 #define NAU8825_FLL_RATIO_MASK (0x7f << 0) 112 113 /* FLL3 (0x06) */ 114 #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) 115 116 /* FLL4 (0x07) */ 117 #define NAU8825_FLL_REF_DIV_MASK (0x3 << 10) 118 119 /* FLL5 (0x08) */ 120 #define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14) 121 122 /* FLL6 (0x9) */ 123 #define NAU8825_DCO_EN_MASK (0x1 << 15) 124 #define NAU8825_DCO_EN (0x1 << 15) 125 #define NAU8825_DCO_DIS (0x0 << 15) 126 #define NAU8825_SDM_EN_MASK (0x1 << 14) 127 #define NAU8825_SDM_EN (0x1 << 14) 128 #define NAU8825_SDM_DIS (0x0 << 14) 129 130 /* HSD_CTRL (0xc) */ 131 #define NAU8825_HSD_AUTO_MODE (1 << 6) 132 /* 0 - short to GND, 1 - open */ 133 #define NAU8825_SPKR_DWN1R (1 << 1) 134 #define NAU8825_SPKR_DWN1L (1 << 0) 135 136 /* JACK_DET_CTRL (0xd) */ 137 #define NAU8825_JACK_DET_RESTART (1 << 9) 138 #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5 139 #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT) 140 #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2 141 #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT) 142 #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */ 143 144 /* INTERRUPT_MASK (0xf) */ 145 #define NAU8825_IRQ_OUTPUT_EN (1 << 11) 146 #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10) 147 #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7) 148 #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5) 149 #define NAU8825_IRQ_EJECT_EN (1 << 2) 150 151 /* IRQ_STATUS (0x10) */ 152 #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) 153 #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) 154 #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) 155 #define NAU8825_KEY_IRQ_MASK (0x7 << 5) 156 #define NAU8825_KEY_RELEASE_IRQ (1 << 7) 157 #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) 158 #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) 159 #define NAU8825_MIC_DETECTION_IRQ (1 << 4) 160 #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) 161 #define NAU8825_JACK_EJECTION_DETECTED (1 << 2) 162 #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) 163 #define NAU8825_JACK_INSERTION_DETECTED (1 << 0) 164 165 /* INTERRUPT_DIS_CTRL (0x12) */ 166 #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10) 167 #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7) 168 #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5) 169 #define NAU8825_IRQ_EJECT_DIS (1 << 2) 170 171 /* SAR_CTRL (0x13) */ 172 #define NAU8825_SAR_ADC_EN_SFT 12 173 #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) 174 #define NAU8825_SAR_INPUT_MASK (1 << 11) 175 #define NAU8825_SAR_INPUT_JKSLV (1 << 11) 176 #define NAU8825_SAR_INPUT_JKR2 (0 << 11) 177 #define NAU8825_SAR_TRACKING_GAIN_SFT 8 178 #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) 179 #define NAU8825_SAR_COMPARE_TIME_SFT 2 180 #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) 181 #define NAU8825_SAR_SAMPLING_TIME_SFT 0 182 #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0) 183 184 /* KEYDET_CTRL (0x14) */ 185 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12 186 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) 187 #define NAU8825_KEYDET_LEVELS_NR_SFT 8 188 #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) 189 #define NAU8825_KEYDET_HYSTERESIS_SFT 0 190 #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf 191 192 /* GPIO12_CTRL (0x1a) */ 193 #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */ 194 #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */ 195 #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */ 196 197 /* I2S_PCM_CTRL1 (0x1c) */ 198 #define NAU8825_I2S_BP_SFT 7 199 #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) 200 #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) 201 #define NAU8825_I2S_PCMB_SFT 6 202 #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) 203 #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) 204 #define NAU8825_I2S_DL_SFT 2 205 #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) 206 #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) 207 #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) 208 #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) 209 #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) 210 #define NAU8825_I2S_DF_SFT 0 211 #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) 212 #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) 213 #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) 214 #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) 215 #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) 216 217 /* I2S_PCM_CTRL2 (0x1d) */ 218 #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */ 219 #define NAU8825_I2S_MS_SFT 3 220 #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) 221 #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) 222 #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) 223 224 /* ADC_RATE (0x2b) */ 225 #define NAU8825_ADC_SYNC_DOWN_SFT 0 226 #define NAU8825_ADC_SYNC_DOWN_MASK 0x3 227 #define NAU8825_ADC_SYNC_DOWN_32 0 228 #define NAU8825_ADC_SYNC_DOWN_64 1 229 #define NAU8825_ADC_SYNC_DOWN_128 2 230 #define NAU8825_ADC_SYNC_DOWN_256 3 231 232 /* DAC_CTRL1 (0x2c) */ 233 #define NAU8825_DAC_CLIP_OFF (1 << 7) 234 #define NAU8825_DAC_OVERSAMPLE_SFT 0 235 #define NAU8825_DAC_OVERSAMPLE_MASK 0x7 236 #define NAU8825_DAC_OVERSAMPLE_64 0 237 #define NAU8825_DAC_OVERSAMPLE_256 1 238 #define NAU8825_DAC_OVERSAMPLE_128 2 239 #define NAU8825_DAC_OVERSAMPLE_32 4 240 241 /* MUTE_CTRL (0x31) */ 242 #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) 243 #define NAU8825_DAC_SOFT_MUTE (1 << 9) 244 245 /* HSVOL_CTRL (0x32) */ 246 #define NAU8825_HP_MUTE (1 << 15) 247 248 /* DACL_CTRL (0x33) */ 249 #define NAU8825_DACL_CH_SEL_SFT 9 250 251 /* DACR_CTRL (0x34) */ 252 #define NAU8825_DACR_CH_SEL_SFT 9 253 254 /* I2C_DEVICE_ID (0x58) */ 255 #define NAU8825_GPIO2JD1 (1 << 7) 256 #define NAU8825_SOFTWARE_ID_MASK 0x3 257 #define NAU8825_SOFTWARE_ID_NAU8825 0x0 258 259 /* BIAS_ADJ (0x66) */ 260 #define NAU8825_BIAS_VMID (1 << 6) 261 #define NAU8825_BIAS_VMID_SEL_SFT 4 262 #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) 263 264 /* ANALOG_CONTROL_2 (0x6a) */ 265 #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) 266 #define NAU8825_DAC_CAPACITOR_MSB (1 << 1) 267 #define NAU8825_DAC_CAPACITOR_LSB (1 << 0) 268 269 /* ANALOG_ADC_2 (0x72) */ 270 #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) 271 #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) 272 #define NAU8825_ADC_VREFSEL_VMID (1 << 8) 273 #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) 274 #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) 275 #define NAU8825_POWERUP_ADCL (1 << 6) 276 277 /* MIC_BIAS (0x74) */ 278 #define NAU8825_MICBIAS_JKSLV (1 << 14) 279 #define NAU8825_MICBIAS_JKR2 (1 << 12) 280 #define NAU8825_MICBIAS_POWERUP_SFT 8 281 #define NAU8825_MICBIAS_VOLTAGE_SFT 0 282 #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 283 284 /* BOOST (0x76) */ 285 #define NAU8825_PRECHARGE_DIS (1 << 13) 286 #define NAU8825_GLOBAL_BIAS_EN (1 << 12) 287 #define NAU8825_HP_BOOST_G_DIS (1 << 8) 288 #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) 289 290 /* POWER_UP_CONTROL (0x7f) */ 291 #define NAU8825_POWERUP_INTEGR_R (1 << 5) 292 #define NAU8825_POWERUP_INTEGR_L (1 << 4) 293 #define NAU8825_POWERUP_DRV_IN_R (1 << 3) 294 #define NAU8825_POWERUP_DRV_IN_L (1 << 2) 295 #define NAU8825_POWERUP_HP_DRV_R (1 << 1) 296 #define NAU8825_POWERUP_HP_DRV_L (1 << 0) 297 298 /* CHARGE_PUMP (0x80) */ 299 #define NAU8825_JAMNODCLOW (1 << 10) 300 #define NAU8825_POWER_DOWN_DACR (1 << 9) 301 #define NAU8825_POWER_DOWN_DACL (1 << 8) 302 #define NAU8825_CHANRGE_PUMP_EN (1 << 5) 303 304 305 /* System Clock Source */ 306 enum { 307 NAU8825_CLK_MCLK = 0, 308 NAU8825_CLK_INTERNAL, 309 }; 310 311 struct nau8825 { 312 struct device *dev; 313 struct regmap *regmap; 314 struct snd_soc_dapm_context *dapm; 315 struct snd_soc_jack *jack; 316 struct clk *mclk; 317 int irq; 318 int mclk_freq; /* 0 - mclk is disabled */ 319 int button_pressed; 320 int micbias_voltage; 321 int vref_impedance; 322 bool jkdet_enable; 323 bool jkdet_pull_enable; 324 bool jkdet_pull_up; 325 int jkdet_polarity; 326 int sar_threshold_num; 327 int sar_threshold[8]; 328 int sar_hysteresis; 329 int sar_voltage; 330 int sar_compare_time; 331 int sar_sampling_time; 332 int key_debounce; 333 int jack_insert_debounce; 334 int jack_eject_debounce; 335 }; 336 337 int nau8825_enable_jack_detect(struct snd_soc_codec *codec, 338 struct snd_soc_jack *jack); 339 340 341 #endif /* __NAU8825_H__ */ 342