1 /* 2 * NAU8825 ALSA SoC audio driver 3 * 4 * Copyright 2015 Google Inc. 5 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __NAU8825_H__ 13 #define __NAU8825_H__ 14 15 #define NAU8825_REG_RESET 0x00 16 #define NAU8825_REG_ENA_CTRL 0x01 17 #define NAU8825_REG_IIC_ADDR_SET 0x02 18 #define NAU8825_REG_CLK_DIVIDER 0x03 19 #define NAU8825_REG_FLL1 0x04 20 #define NAU8825_REG_FLL2 0x05 21 #define NAU8825_REG_FLL3 0x06 22 #define NAU8825_REG_FLL4 0x07 23 #define NAU8825_REG_FLL5 0x08 24 #define NAU8825_REG_FLL6 0x09 25 #define NAU8825_REG_FLL_VCO_RSV 0x0a 26 #define NAU8825_REG_HSD_CTRL 0x0c 27 #define NAU8825_REG_JACK_DET_CTRL 0x0d 28 #define NAU8825_REG_INTERRUPT_MASK 0x0f 29 #define NAU8825_REG_IRQ_STATUS 0x10 30 #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 31 #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 32 #define NAU8825_REG_SAR_CTRL 0x13 33 #define NAU8825_REG_KEYDET_CTRL 0x14 34 #define NAU8825_REG_VDET_THRESHOLD_1 0x15 35 #define NAU8825_REG_VDET_THRESHOLD_2 0x16 36 #define NAU8825_REG_VDET_THRESHOLD_3 0x17 37 #define NAU8825_REG_VDET_THRESHOLD_4 0x18 38 #define NAU8825_REG_GPIO34_CTRL 0x19 39 #define NAU8825_REG_GPIO12_CTRL 0x1a 40 #define NAU8825_REG_TDM_CTRL 0x1b 41 #define NAU8825_REG_I2S_PCM_CTRL1 0x1c 42 #define NAU8825_REG_I2S_PCM_CTRL2 0x1d 43 #define NAU8825_REG_LEFT_TIME_SLOT 0x1e 44 #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f 45 #define NAU8825_REG_BIQ_CTRL 0x20 46 #define NAU8825_REG_BIQ_COF1 0x21 47 #define NAU8825_REG_BIQ_COF2 0x22 48 #define NAU8825_REG_BIQ_COF3 0x23 49 #define NAU8825_REG_BIQ_COF4 0x24 50 #define NAU8825_REG_BIQ_COF5 0x25 51 #define NAU8825_REG_BIQ_COF6 0x26 52 #define NAU8825_REG_BIQ_COF7 0x27 53 #define NAU8825_REG_BIQ_COF8 0x28 54 #define NAU8825_REG_BIQ_COF9 0x29 55 #define NAU8825_REG_BIQ_COF10 0x2a 56 #define NAU8825_REG_ADC_RATE 0x2b 57 #define NAU8825_REG_DAC_CTRL1 0x2c 58 #define NAU8825_REG_DAC_CTRL2 0x2d 59 #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f 60 #define NAU8825_REG_ADC_DGAIN_CTRL 0x30 61 #define NAU8825_REG_MUTE_CTRL 0x31 62 #define NAU8825_REG_HSVOL_CTRL 0x32 63 #define NAU8825_REG_DACL_CTRL 0x33 64 #define NAU8825_REG_DACR_CTRL 0x34 65 #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 66 #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 67 #define NAU8825_REG_ADC_DRC_SLOPES 0x3a 68 #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b 69 #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 70 #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 71 #define NAU8825_REG_DAC_DRC_SLOPES 0x47 72 #define NAU8825_REG_DAC_DRC_ATKDCY 0x48 73 #define NAU8825_REG_IMM_MODE_CTRL 0x4c 74 #define NAU8825_REG_IMM_RMS_L 0x4d 75 #define NAU8825_REG_IMM_RMS_R 0x4e 76 #define NAU8825_REG_CLASSG_CTRL 0x50 77 #define NAU8825_REG_OPT_EFUSE_CTRL 0x51 78 #define NAU8825_REG_MISC_CTRL 0x55 79 #define NAU8825_REG_I2C_DEVICE_ID 0x58 80 #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 81 #define NAU8825_REG_BIAS_ADJ 0x66 82 #define NAU8825_REG_TRIM_SETTINGS 0x68 83 #define NAU8825_REG_ANALOG_CONTROL_1 0x69 84 #define NAU8825_REG_ANALOG_CONTROL_2 0x6a 85 #define NAU8825_REG_ANALOG_ADC_1 0x71 86 #define NAU8825_REG_ANALOG_ADC_2 0x72 87 #define NAU8825_REG_RDAC 0x73 88 #define NAU8825_REG_MIC_BIAS 0x74 89 #define NAU8825_REG_BOOST 0x76 90 #define NAU8825_REG_FEPGA 0x77 91 #define NAU8825_REG_POWER_UP_CONTROL 0x7f 92 #define NAU8825_REG_CHARGE_PUMP 0x80 93 #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 94 #define NAU8825_REG_GENERAL_STATUS 0x82 95 #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS 96 97 /* ENA_CTRL (0x1) */ 98 #define NAU8825_ENABLE_DACR_SFT 10 99 #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT) 100 #define NAU8825_ENABLE_DACL_SFT 9 101 #define NAU8825_ENABLE_ADC_SFT 8 102 #define NAU8825_ENABLE_SAR_SFT 1 103 104 /* CLK_DIVIDER (0x3) */ 105 #define NAU8825_CLK_SRC_SFT 15 106 #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) 107 #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) 108 #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) 109 #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) 110 111 /* FLL1 (0x04) */ 112 #define NAU8825_FLL_RATIO_MASK (0x7f << 0) 113 114 /* FLL3 (0x06) */ 115 #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) 116 117 /* FLL4 (0x07) */ 118 #define NAU8825_FLL_REF_DIV_MASK (0x3 << 10) 119 120 /* FLL5 (0x08) */ 121 #define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14) 122 123 /* FLL6 (0x9) */ 124 #define NAU8825_DCO_EN_MASK (0x1 << 15) 125 #define NAU8825_DCO_EN (0x1 << 15) 126 #define NAU8825_DCO_DIS (0x0 << 15) 127 #define NAU8825_SDM_EN_MASK (0x1 << 14) 128 #define NAU8825_SDM_EN (0x1 << 14) 129 #define NAU8825_SDM_DIS (0x0 << 14) 130 131 /* HSD_CTRL (0xc) */ 132 #define NAU8825_HSD_AUTO_MODE (1 << 6) 133 /* 0 - open, 1 - short to GND */ 134 #define NAU8825_SPKR_DWN1R (1 << 1) 135 #define NAU8825_SPKR_DWN1L (1 << 0) 136 137 /* JACK_DET_CTRL (0xd) */ 138 #define NAU8825_JACK_DET_RESTART (1 << 9) 139 #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5 140 #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT) 141 #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2 142 #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT) 143 #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */ 144 145 /* INTERRUPT_MASK (0xf) */ 146 #define NAU8825_IRQ_OUTPUT_EN (1 << 11) 147 #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10) 148 #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7) 149 #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5) 150 #define NAU8825_IRQ_EJECT_EN (1 << 2) 151 152 /* IRQ_STATUS (0x10) */ 153 #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) 154 #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) 155 #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) 156 #define NAU8825_KEY_IRQ_MASK (0x7 << 5) 157 #define NAU8825_KEY_RELEASE_IRQ (1 << 7) 158 #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) 159 #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) 160 #define NAU8825_MIC_DETECTION_IRQ (1 << 4) 161 #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) 162 #define NAU8825_JACK_EJECTION_DETECTED (1 << 2) 163 #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) 164 #define NAU8825_JACK_INSERTION_DETECTED (1 << 0) 165 166 /* INTERRUPT_DIS_CTRL (0x12) */ 167 #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10) 168 #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7) 169 #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5) 170 #define NAU8825_IRQ_EJECT_DIS (1 << 2) 171 172 /* SAR_CTRL (0x13) */ 173 #define NAU8825_SAR_ADC_EN_SFT 12 174 #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) 175 #define NAU8825_SAR_INPUT_MASK (1 << 11) 176 #define NAU8825_SAR_INPUT_JKSLV (1 << 11) 177 #define NAU8825_SAR_INPUT_JKR2 (0 << 11) 178 #define NAU8825_SAR_TRACKING_GAIN_SFT 8 179 #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) 180 #define NAU8825_SAR_COMPARE_TIME_SFT 2 181 #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) 182 #define NAU8825_SAR_SAMPLING_TIME_SFT 0 183 #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0) 184 185 /* KEYDET_CTRL (0x14) */ 186 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12 187 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) 188 #define NAU8825_KEYDET_LEVELS_NR_SFT 8 189 #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) 190 #define NAU8825_KEYDET_HYSTERESIS_SFT 0 191 #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf 192 193 /* GPIO12_CTRL (0x1a) */ 194 #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */ 195 #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */ 196 #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */ 197 198 /* I2S_PCM_CTRL1 (0x1c) */ 199 #define NAU8825_I2S_BP_SFT 7 200 #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) 201 #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) 202 #define NAU8825_I2S_PCMB_SFT 6 203 #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) 204 #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) 205 #define NAU8825_I2S_DL_SFT 2 206 #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) 207 #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) 208 #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) 209 #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) 210 #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) 211 #define NAU8825_I2S_DF_SFT 0 212 #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) 213 #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) 214 #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) 215 #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) 216 #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) 217 218 /* I2S_PCM_CTRL2 (0x1d) */ 219 #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */ 220 #define NAU8825_I2S_MS_SFT 3 221 #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) 222 #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) 223 #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) 224 225 /* ADC_RATE (0x2b) */ 226 #define NAU8825_ADC_SYNC_DOWN_SFT 0 227 #define NAU8825_ADC_SYNC_DOWN_MASK 0x3 228 #define NAU8825_ADC_SYNC_DOWN_32 0 229 #define NAU8825_ADC_SYNC_DOWN_64 1 230 #define NAU8825_ADC_SYNC_DOWN_128 2 231 #define NAU8825_ADC_SYNC_DOWN_256 3 232 233 /* DAC_CTRL1 (0x2c) */ 234 #define NAU8825_DAC_CLIP_OFF (1 << 7) 235 #define NAU8825_DAC_OVERSAMPLE_SFT 0 236 #define NAU8825_DAC_OVERSAMPLE_MASK 0x7 237 #define NAU8825_DAC_OVERSAMPLE_64 0 238 #define NAU8825_DAC_OVERSAMPLE_256 1 239 #define NAU8825_DAC_OVERSAMPLE_128 2 240 #define NAU8825_DAC_OVERSAMPLE_32 4 241 242 /* MUTE_CTRL (0x31) */ 243 #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) 244 #define NAU8825_DAC_SOFT_MUTE (1 << 9) 245 246 /* HSVOL_CTRL (0x32) */ 247 #define NAU8825_HP_MUTE (1 << 15) 248 249 /* DACL_CTRL (0x33) */ 250 #define NAU8825_DACL_CH_SEL_SFT 9 251 252 /* DACR_CTRL (0x34) */ 253 #define NAU8825_DACR_CH_SEL_SFT 9 254 255 /* CLASSG_CTRL (0x50) */ 256 #define NAU8825_CLASSG_TIMER_SFT 8 257 #define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT) 258 #define NAU8825_CLASSG_EN (1 << 0) 259 260 /* I2C_DEVICE_ID (0x58) */ 261 #define NAU8825_GPIO2JD1 (1 << 7) 262 #define NAU8825_SOFTWARE_ID_MASK 0x3 263 #define NAU8825_SOFTWARE_ID_NAU8825 0x0 264 265 /* BIAS_ADJ (0x66) */ 266 #define NAU8825_BIAS_TESTDAC_EN (0x3 << 8) 267 #define NAU8825_BIAS_VMID (1 << 6) 268 #define NAU8825_BIAS_VMID_SEL_SFT 4 269 #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) 270 271 /* ANALOG_CONTROL_2 (0x6a) */ 272 #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) 273 #define NAU8825_DAC_CAPACITOR_MSB (1 << 1) 274 #define NAU8825_DAC_CAPACITOR_LSB (1 << 0) 275 276 /* ANALOG_ADC_2 (0x72) */ 277 #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) 278 #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) 279 #define NAU8825_ADC_VREFSEL_VMID (1 << 8) 280 #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) 281 #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) 282 #define NAU8825_POWERUP_ADCL (1 << 6) 283 284 /* RDAC (0x73) */ 285 #define NAU8825_RDAC_CLK_DELAY_SFT 4 286 #define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT) 287 #define NAU8825_RDAC_VREF_SFT 2 288 #define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT) 289 290 /* MIC_BIAS (0x74) */ 291 #define NAU8825_MICBIAS_JKSLV (1 << 14) 292 #define NAU8825_MICBIAS_JKR2 (1 << 12) 293 #define NAU8825_MICBIAS_POWERUP_SFT 8 294 #define NAU8825_MICBIAS_VOLTAGE_SFT 0 295 #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 296 297 /* BOOST (0x76) */ 298 #define NAU8825_PRECHARGE_DIS (1 << 13) 299 #define NAU8825_GLOBAL_BIAS_EN (1 << 12) 300 #define NAU8825_HP_BOOST_DIS (1 << 9) 301 #define NAU8825_HP_BOOST_G_DIS (1 << 8) 302 #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) 303 304 /* POWER_UP_CONTROL (0x7f) */ 305 #define NAU8825_POWERUP_INTEGR_R (1 << 5) 306 #define NAU8825_POWERUP_INTEGR_L (1 << 4) 307 #define NAU8825_POWERUP_DRV_IN_R (1 << 3) 308 #define NAU8825_POWERUP_DRV_IN_L (1 << 2) 309 #define NAU8825_POWERUP_HP_DRV_R (1 << 1) 310 #define NAU8825_POWERUP_HP_DRV_L (1 << 0) 311 312 /* CHARGE_PUMP (0x80) */ 313 #define NAU8825_JAMNODCLOW (1 << 10) 314 #define NAU8825_POWER_DOWN_DACR (1 << 9) 315 #define NAU8825_POWER_DOWN_DACL (1 << 8) 316 #define NAU8825_CHANRGE_PUMP_EN (1 << 5) 317 318 319 /* System Clock Source */ 320 enum { 321 NAU8825_CLK_MCLK = 0, 322 NAU8825_CLK_INTERNAL, 323 }; 324 325 struct nau8825 { 326 struct device *dev; 327 struct regmap *regmap; 328 struct snd_soc_dapm_context *dapm; 329 struct snd_soc_jack *jack; 330 struct clk *mclk; 331 int irq; 332 int mclk_freq; /* 0 - mclk is disabled */ 333 int button_pressed; 334 int micbias_voltage; 335 int vref_impedance; 336 bool jkdet_enable; 337 bool jkdet_pull_enable; 338 bool jkdet_pull_up; 339 int jkdet_polarity; 340 int sar_threshold_num; 341 int sar_threshold[8]; 342 int sar_hysteresis; 343 int sar_voltage; 344 int sar_compare_time; 345 int sar_sampling_time; 346 int key_debounce; 347 int jack_insert_debounce; 348 int jack_eject_debounce; 349 }; 350 351 int nau8825_enable_jack_detect(struct snd_soc_codec *codec, 352 struct snd_soc_jack *jack); 353 354 355 #endif /* __NAU8825_H__ */ 356