1 /* 2 * Nuvoton NAU8825 audio codec driver 3 * 4 * Copyright 2015 Google Chromium project. 5 * Author: Anatol Pomozov <anatol@chromium.org> 6 * Copyright 2015 Nuvoton Technology Corp. 7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com> 8 * 9 * Licensed under the GPL-2. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/clk.h> 19 #include <linux/acpi.h> 20 #include <linux/math64.h> 21 #include <linux/semaphore.h> 22 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 31 32 #include "nau8825.h" 33 34 35 #define NUVOTON_CODEC_DAI "nau8825-hifi" 36 37 #define NAU_FREF_MAX 13500000 38 #define NAU_FVCO_MAX 124000000 39 #define NAU_FVCO_MIN 90000000 40 41 /* cross talk suppression detection */ 42 #define LOG10_MAGIC 646456993 43 #define GAIN_AUGMENT 22500 44 #define SIDETONE_BASE 207000 45 46 /* the maximum frequency of CLK_ADC and CLK_DAC */ 47 #define CLK_DA_AD_MAX 6144000 48 49 static int nau8825_configure_sysclk(struct nau8825 *nau8825, 50 int clk_id, unsigned int freq); 51 52 struct nau8825_fll { 53 int mclk_src; 54 int ratio; 55 int fll_frac; 56 int fll_int; 57 int clk_ref_div; 58 }; 59 60 struct nau8825_fll_attr { 61 unsigned int param; 62 unsigned int val; 63 }; 64 65 /* scaling for mclk from sysclk_src output */ 66 static const struct nau8825_fll_attr mclk_src_scaling[] = { 67 { 1, 0x0 }, 68 { 2, 0x2 }, 69 { 4, 0x3 }, 70 { 8, 0x4 }, 71 { 16, 0x5 }, 72 { 32, 0x6 }, 73 { 3, 0x7 }, 74 { 6, 0xa }, 75 { 12, 0xb }, 76 { 24, 0xc }, 77 { 48, 0xd }, 78 { 96, 0xe }, 79 { 5, 0xf }, 80 }; 81 82 /* ratio for input clk freq */ 83 static const struct nau8825_fll_attr fll_ratio[] = { 84 { 512000, 0x01 }, 85 { 256000, 0x02 }, 86 { 128000, 0x04 }, 87 { 64000, 0x08 }, 88 { 32000, 0x10 }, 89 { 8000, 0x20 }, 90 { 4000, 0x40 }, 91 }; 92 93 static const struct nau8825_fll_attr fll_pre_scalar[] = { 94 { 1, 0x0 }, 95 { 2, 0x1 }, 96 { 4, 0x2 }, 97 { 8, 0x3 }, 98 }; 99 100 /* over sampling rate */ 101 struct nau8825_osr_attr { 102 unsigned int osr; 103 unsigned int clk_src; 104 }; 105 106 static const struct nau8825_osr_attr osr_dac_sel[] = { 107 { 64, 2 }, /* OSR 64, SRC 1/4 */ 108 { 256, 0 }, /* OSR 256, SRC 1 */ 109 { 128, 1 }, /* OSR 128, SRC 1/2 */ 110 { 0, 0 }, 111 { 32, 3 }, /* OSR 32, SRC 1/8 */ 112 }; 113 114 static const struct nau8825_osr_attr osr_adc_sel[] = { 115 { 32, 3 }, /* OSR 32, SRC 1/8 */ 116 { 64, 2 }, /* OSR 64, SRC 1/4 */ 117 { 128, 1 }, /* OSR 128, SRC 1/2 */ 118 { 256, 0 }, /* OSR 256, SRC 1 */ 119 }; 120 121 static const struct reg_default nau8825_reg_defaults[] = { 122 { NAU8825_REG_ENA_CTRL, 0x00ff }, 123 { NAU8825_REG_IIC_ADDR_SET, 0x0 }, 124 { NAU8825_REG_CLK_DIVIDER, 0x0050 }, 125 { NAU8825_REG_FLL1, 0x0 }, 126 { NAU8825_REG_FLL2, 0x3126 }, 127 { NAU8825_REG_FLL3, 0x0008 }, 128 { NAU8825_REG_FLL4, 0x0010 }, 129 { NAU8825_REG_FLL5, 0x0 }, 130 { NAU8825_REG_FLL6, 0x6000 }, 131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, 132 { NAU8825_REG_HSD_CTRL, 0x000c }, 133 { NAU8825_REG_JACK_DET_CTRL, 0x0 }, 134 { NAU8825_REG_INTERRUPT_MASK, 0x0 }, 135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, 136 { NAU8825_REG_SAR_CTRL, 0x0015 }, 137 { NAU8825_REG_KEYDET_CTRL, 0x0110 }, 138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, 139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, 140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, 141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, 142 { NAU8825_REG_GPIO34_CTRL, 0x0 }, 143 { NAU8825_REG_GPIO12_CTRL, 0x0 }, 144 { NAU8825_REG_TDM_CTRL, 0x0 }, 145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, 146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, 147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, 148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, 149 { NAU8825_REG_BIQ_CTRL, 0x0 }, 150 { NAU8825_REG_BIQ_COF1, 0x0 }, 151 { NAU8825_REG_BIQ_COF2, 0x0 }, 152 { NAU8825_REG_BIQ_COF3, 0x0 }, 153 { NAU8825_REG_BIQ_COF4, 0x0 }, 154 { NAU8825_REG_BIQ_COF5, 0x0 }, 155 { NAU8825_REG_BIQ_COF6, 0x0 }, 156 { NAU8825_REG_BIQ_COF7, 0x0 }, 157 { NAU8825_REG_BIQ_COF8, 0x0 }, 158 { NAU8825_REG_BIQ_COF9, 0x0 }, 159 { NAU8825_REG_BIQ_COF10, 0x0 }, 160 { NAU8825_REG_ADC_RATE, 0x0010 }, 161 { NAU8825_REG_DAC_CTRL1, 0x0001 }, 162 { NAU8825_REG_DAC_CTRL2, 0x0 }, 163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, 164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 165 { NAU8825_REG_MUTE_CTRL, 0x0 }, 166 { NAU8825_REG_HSVOL_CTRL, 0x0 }, 167 { NAU8825_REG_DACL_CTRL, 0x02cf }, 168 { NAU8825_REG_DACR_CTRL, 0x00cf }, 169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, 170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, 171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, 172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, 173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, 174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, 175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, 176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, 177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, 178 { NAU8825_REG_CLASSG_CTRL, 0x0 }, 179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, 180 { NAU8825_REG_MISC_CTRL, 0x0 }, 181 { NAU8825_REG_BIAS_ADJ, 0x0 }, 182 { NAU8825_REG_TRIM_SETTINGS, 0x0 }, 183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, 184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, 185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, 186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, 187 { NAU8825_REG_RDAC, 0x0008 }, 188 { NAU8825_REG_MIC_BIAS, 0x0006 }, 189 { NAU8825_REG_BOOST, 0x0 }, 190 { NAU8825_REG_FEPGA, 0x0 }, 191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, 192 { NAU8825_REG_CHARGE_PUMP, 0x0 }, 193 }; 194 195 /* register backup table when cross talk detection */ 196 static struct reg_default nau8825_xtalk_baktab[] = { 197 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 198 { NAU8825_REG_HSVOL_CTRL, 0 }, 199 { NAU8825_REG_DACL_CTRL, 0x00cf }, 200 { NAU8825_REG_DACR_CTRL, 0x02cf }, 201 }; 202 203 static const unsigned short logtable[256] = { 204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, 205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, 206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, 207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, 208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, 209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, 210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, 211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, 212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, 213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, 214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, 215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, 216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, 217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, 218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, 219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, 220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, 221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, 222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, 223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, 224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, 225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, 226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, 227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, 228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, 229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, 230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, 231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, 232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, 233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, 234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, 235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 236 }; 237 238 /** 239 * nau8825_sema_acquire - acquire the semaphore of nau88l25 240 * @nau8825: component to register the codec private data with 241 * @timeout: how long in jiffies to wait before failure or zero to wait 242 * until release 243 * 244 * Attempts to acquire the semaphore with number of jiffies. If no more 245 * tasks are allowed to acquire the semaphore, calling this function will 246 * put the task to sleep. If the semaphore is not released within the 247 * specified number of jiffies, this function returns. 248 * If the semaphore is not released within the specified number of jiffies, 249 * this function returns -ETIME. If the sleep is interrupted by a signal, 250 * this function will return -EINTR. It returns 0 if the semaphore was 251 * acquired successfully. 252 * 253 * Acquires the semaphore without jiffies. Try to acquire the semaphore 254 * atomically. Returns 0 if the semaphore has been acquired successfully 255 * or 1 if it it cannot be acquired. 256 */ 257 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout) 258 { 259 int ret; 260 261 if (timeout) { 262 ret = down_timeout(&nau8825->xtalk_sem, timeout); 263 if (ret < 0) 264 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); 265 } else { 266 ret = down_trylock(&nau8825->xtalk_sem); 267 if (ret) 268 dev_warn(nau8825->dev, "Acquire semaphore fail\n"); 269 } 270 271 return ret; 272 } 273 274 /** 275 * nau8825_sema_release - release the semaphore of nau88l25 276 * @nau8825: component to register the codec private data with 277 * 278 * Release the semaphore which may be called from any context and 279 * even by tasks which have never called down(). 280 */ 281 static inline void nau8825_sema_release(struct nau8825 *nau8825) 282 { 283 up(&nau8825->xtalk_sem); 284 } 285 286 /** 287 * nau8825_sema_reset - reset the semaphore for nau88l25 288 * @nau8825: component to register the codec private data with 289 * 290 * Reset the counter of the semaphore. Call this function to restart 291 * a new round task management. 292 */ 293 static inline void nau8825_sema_reset(struct nau8825 *nau8825) 294 { 295 nau8825->xtalk_sem.count = 1; 296 } 297 298 /** 299 * Ramp up the headphone volume change gradually to target level. 300 * 301 * @nau8825: component to register the codec private data with 302 * @vol_from: the volume to start up 303 * @vol_to: the target volume 304 * @step: the volume span to move on 305 * 306 * The headphone volume is from 0dB to minimum -54dB and -1dB per step. 307 * If the volume changes sharp, there is a pop noise heard in headphone. We 308 * provide the function to ramp up the volume up or down by delaying 10ms 309 * per step. 310 */ 311 static void nau8825_hpvol_ramp(struct nau8825 *nau8825, 312 unsigned int vol_from, unsigned int vol_to, unsigned int step) 313 { 314 unsigned int value, volume, ramp_up, from, to; 315 316 if (vol_from == vol_to || step == 0) { 317 return; 318 } else if (vol_from < vol_to) { 319 ramp_up = true; 320 from = vol_from; 321 to = vol_to; 322 } else { 323 ramp_up = false; 324 from = vol_to; 325 to = vol_from; 326 } 327 /* only handle volume from 0dB to minimum -54dB */ 328 if (to > NAU8825_HP_VOL_MIN) 329 to = NAU8825_HP_VOL_MIN; 330 331 for (volume = from; volume < to; volume += step) { 332 if (ramp_up) 333 value = volume; 334 else 335 value = to - volume + from; 336 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 337 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 338 (value << NAU8825_HPL_VOL_SFT) | value); 339 usleep_range(10000, 10500); 340 } 341 if (ramp_up) 342 value = to; 343 else 344 value = from; 345 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 346 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 347 (value << NAU8825_HPL_VOL_SFT) | value); 348 } 349 350 /** 351 * Computes log10 of a value; the result is round off to 3 decimal. This func- 352 * tion takes reference to dvb-math. The source code locates as the following. 353 * Linux/drivers/media/dvb-core/dvb_math.c 354 * @value: input for log10 355 * 356 * return log10(value) * 1000 357 */ 358 static u32 nau8825_intlog10_dec3(u32 value) 359 { 360 u32 msb, logentry, significand, interpolation, log10val; 361 u64 log2val; 362 363 /* first detect the msb (count begins at 0) */ 364 msb = fls(value) - 1; 365 /** 366 * now we use a logtable after the following method: 367 * 368 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 369 * where x = msb and therefore 1 <= y < 2 370 * first y is determined by shifting the value left 371 * so that msb is bit 31 372 * 0x00231f56 -> 0x8C7D5800 373 * the result is y * 2^31 -> "significand" 374 * then the highest 9 bits are used for a table lookup 375 * the highest bit is discarded because it's always set 376 * the highest nine bits in our example are 100011000 377 * so we would use the entry 0x18 378 */ 379 significand = value << (31 - msb); 380 logentry = (significand >> 23) & 0xff; 381 /** 382 * last step we do is interpolation because of the 383 * limitations of the log table the error is that part of 384 * the significand which isn't used for lookup then we 385 * compute the ratio between the error and the next table entry 386 * and interpolate it between the log table entry used and the 387 * next one the biggest error possible is 0x7fffff 388 * (in our example it's 0x7D5800) 389 * needed value for next table entry is 0x800000 390 * so the interpolation is 391 * (error / 0x800000) * (logtable_next - logtable_current) 392 * in the implementation the division is moved to the end for 393 * better accuracy there is also an overflow correction if 394 * logtable_next is 256 395 */ 396 interpolation = ((significand & 0x7fffff) * 397 ((logtable[(logentry + 1) & 0xff] - 398 logtable[logentry]) & 0xffff)) >> 15; 399 400 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation); 401 /** 402 * log10(x) = log2(x) * log10(2) 403 */ 404 log10val = (log2val * LOG10_MAGIC) >> 31; 405 /** 406 * the result is round off to 3 decimal 407 */ 408 return log10val / ((1 << 24) / 1000); 409 } 410 411 /** 412 * computes cross talk suppression sidetone gain. 413 * 414 * @sig_org: orignal signal level 415 * @sig_cros: cross talk signal level 416 * 417 * The orignal and cross talk signal vlues need to be characterized. 418 * Once these values have been characterized, this sidetone value 419 * can be converted to decibel with the equation below. 420 * sidetone = 20 * log (original signal level / crosstalk signal level) 421 * 422 * return cross talk sidetone gain 423 */ 424 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros) 425 { 426 u32 gain, sidetone; 427 428 if (WARN_ON(sig_org == 0 || sig_cros == 0)) 429 return 0; 430 431 sig_org = nau8825_intlog10_dec3(sig_org); 432 sig_cros = nau8825_intlog10_dec3(sig_cros); 433 if (sig_org >= sig_cros) 434 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT; 435 else 436 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT; 437 sidetone = SIDETONE_BASE - gain * 2; 438 sidetone /= 1000; 439 440 return sidetone; 441 } 442 443 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) 444 { 445 int index; 446 447 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++) 448 if (nau8825_xtalk_baktab[index].reg == reg) 449 return index; 450 return -EINVAL; 451 } 452 453 static void nau8825_xtalk_backup(struct nau8825 *nau8825) 454 { 455 int i; 456 457 if (nau8825->xtalk_baktab_initialized) 458 return; 459 460 /* Backup some register values to backup table */ 461 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) 462 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 463 &nau8825_xtalk_baktab[i].def); 464 465 nau8825->xtalk_baktab_initialized = true; 466 } 467 468 static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel) 469 { 470 int i, volume; 471 472 if (!nau8825->xtalk_baktab_initialized) 473 return; 474 475 /* Restore register values from backup table; When the driver restores 476 * the headphone volume in XTALK_DONE state, it needs recover to 477 * original level gradually with 3dB per step for less pop noise. 478 * Otherwise, the restore should do ASAP. 479 */ 480 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) { 481 if (!cause_cancel && nau8825_xtalk_baktab[i].reg == 482 NAU8825_REG_HSVOL_CTRL) { 483 /* Ramping up the volume change to reduce pop noise */ 484 volume = nau8825_xtalk_baktab[i].def & 485 NAU8825_HPR_VOL_MASK; 486 nau8825_hpvol_ramp(nau8825, 0, volume, 3); 487 continue; 488 } 489 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 490 nau8825_xtalk_baktab[i].def); 491 } 492 493 nau8825->xtalk_baktab_initialized = false; 494 } 495 496 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825) 497 { 498 /* Enable power of DAC path */ 499 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 500 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 501 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK | 502 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR | 503 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC | 504 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK); 505 /* Prevent startup click by letting charge pump to ramp up and 506 * change bump enable 507 */ 508 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 509 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 510 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN); 511 /* Enable clock sync of DAC and DAC clock */ 512 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 513 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN | 514 NAU8825_RDAC_FS_BCLK_ENB, 515 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN); 516 /* Power up output driver with 2 stage */ 517 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 518 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 519 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 520 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 521 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L); 522 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 523 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 524 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L); 525 /* HP outputs not shouted to ground */ 526 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 527 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0); 528 /* Enable HP boost driver */ 529 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 530 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS); 531 /* Enable class G compare path to supply 1.8V or 0.9V. */ 532 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL, 533 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN, 534 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN); 535 } 536 537 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825) 538 { 539 /* Power up left ADC and raise 5dB than Vmid for Vref */ 540 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 541 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 542 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB); 543 } 544 545 static void nau8825_xtalk_clock(struct nau8825 *nau8825) 546 { 547 /* Recover FLL default value */ 548 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0); 549 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126); 550 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008); 551 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010); 552 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0); 553 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000); 554 /* Enable internal VCO clock for detection signal generated */ 555 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 556 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 557 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 558 NAU8825_DCO_EN); 559 /* Given specific clock frequency of internal clock to 560 * generate signal. 561 */ 562 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 563 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 564 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 565 NAU8825_FLL_RATIO_MASK, 0x10); 566 } 567 568 static void nau8825_xtalk_prepare(struct nau8825 *nau8825) 569 { 570 int volume, index; 571 572 /* Backup those registers changed by cross talk detection */ 573 nau8825_xtalk_backup(nau8825); 574 /* Config IIS as master to output signal by codec */ 575 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 576 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 577 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER | 578 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1); 579 /* Ramp up headphone volume to 0dB to get better performance and 580 * avoid pop noise in headphone. 581 */ 582 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL); 583 if (index != -EINVAL) { 584 volume = nau8825_xtalk_baktab[index].def & 585 NAU8825_HPR_VOL_MASK; 586 nau8825_hpvol_ramp(nau8825, volume, 0, 3); 587 } 588 nau8825_xtalk_clock(nau8825); 589 nau8825_xtalk_prepare_dac(nau8825); 590 nau8825_xtalk_prepare_adc(nau8825); 591 /* Config channel path and digital gain */ 592 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 593 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK, 594 NAU8825_DACL_CH_SEL_L | 0xab); 595 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 596 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK, 597 NAU8825_DACR_CH_SEL_R | 0xab); 598 /* Config cross talk parameters and generate the 23Hz sine wave with 599 * 1/16 full scale of signal level for impedance measurement. 600 */ 601 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 602 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK | 603 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK, 604 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th | 605 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN); 606 /* RMS intrruption enable */ 607 regmap_update_bits(nau8825->regmap, 608 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0); 609 /* Power up left and right DAC */ 610 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 611 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 612 } 613 614 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825) 615 { 616 /* Disable HP boost driver */ 617 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 618 NAU8825_HP_BOOST_DIS, 0); 619 /* HP outputs shouted to ground */ 620 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 621 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 622 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 623 /* Power down left and right DAC */ 624 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 625 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 626 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 627 /* Enable the TESTDAC and disable L/R HP impedance */ 628 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 629 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP | 630 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 631 /* Power down output driver with 2 stage */ 632 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 633 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0); 634 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 635 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 636 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0); 637 /* Disable clock sync of DAC and DAC clock */ 638 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 639 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0); 640 /* Disable charge pump ramp up function and change bump */ 641 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 642 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0); 643 /* Disable power of DAC path */ 644 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 645 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 646 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0); 647 if (!nau8825->irq) 648 regmap_update_bits(nau8825->regmap, 649 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 650 } 651 652 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825) 653 { 654 /* Power down left ADC and restore voltage to Vmid */ 655 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 656 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0); 657 } 658 659 static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel) 660 { 661 /* Enable internal VCO needed for interruptions */ 662 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 663 nau8825_xtalk_clean_dac(nau8825); 664 nau8825_xtalk_clean_adc(nau8825); 665 /* Clear cross talk parameters and disable */ 666 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0); 667 /* RMS intrruption disable */ 668 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK, 669 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN); 670 /* Recover default value for IIS */ 671 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 672 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 673 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE); 674 /* Restore value of specific register for cross talk */ 675 nau8825_xtalk_restore(nau8825, cause_cancel); 676 } 677 678 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol) 679 { 680 /* Apply ADC volume for better cross talk performance */ 681 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL, 682 NAU8825_ADC_DIG_VOL_MASK, vol); 683 /* Disables JKTIP(HPL) DAC channel for right to left measurement. 684 * Do it before sending signal in order to erase pop noise. 685 */ 686 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 687 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN, 688 NAU8825_BIAS_TESTDACL_EN); 689 switch (nau8825->xtalk_state) { 690 case NAU8825_XTALK_HPR_R2L: 691 /* Enable right headphone impedance */ 692 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 693 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 694 NAU8825_BIAS_HPR_IMP); 695 break; 696 case NAU8825_XTALK_HPL_R2L: 697 /* Enable left headphone impedance */ 698 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 699 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 700 NAU8825_BIAS_HPL_IMP); 701 break; 702 default: 703 break; 704 } 705 msleep(100); 706 /* Impedance measurement mode enable */ 707 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 708 NAU8825_IMM_EN, NAU8825_IMM_EN); 709 } 710 711 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825) 712 { 713 /* Impedance measurement mode disable */ 714 regmap_update_bits(nau8825->regmap, 715 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0); 716 } 717 718 /* The cross talk measurement function can reduce cross talk across the 719 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal 720 * level to determine what cross talk reduction gain is. This system works by 721 * sending a 23Hz -24dBV sine wave into the headset output DAC and through 722 * the PGA. The output of the PGA is then connected to an internal current 723 * sense which measures the attenuated 23Hz signal and passing the output to 724 * an ADC which converts the measurement to a binary code. With two separated 725 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data 726 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement. 727 * Thus, the measurement function has four states to complete whole sequence. 728 * 1. Prepare state : Prepare the resource for detection and transfer to HPR 729 * IMM stat to make JKR1(HPR) impedance measure. 730 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer 731 * to HPL IMM state to make JKTIP(HPL) impedance measure. 732 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and 733 * transfer to IMM state to determine suppression sidetone gain. 734 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal 735 * and cross talk signal level. Apply this gain and then restore codec 736 * configuration. Then transfer to Done state for ending. 737 */ 738 static void nau8825_xtalk_measure(struct nau8825 *nau8825) 739 { 740 u32 sidetone; 741 742 switch (nau8825->xtalk_state) { 743 case NAU8825_XTALK_PREPARE: 744 /* In prepare state, set up clock, intrruption, DAC path, ADC 745 * path and cross talk detection parameters for preparation. 746 */ 747 nau8825_xtalk_prepare(nau8825); 748 msleep(280); 749 /* Trigger right headphone impedance detection */ 750 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L; 751 nau8825_xtalk_imm_start(nau8825, 0x00d2); 752 break; 753 case NAU8825_XTALK_HPR_R2L: 754 /* In right headphone IMM state, read out right headphone 755 * impedance measure result, and then start up left side. 756 */ 757 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 758 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 759 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n", 760 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 761 /* Disable then re-enable IMM mode to update */ 762 nau8825_xtalk_imm_stop(nau8825); 763 /* Trigger left headphone impedance detection */ 764 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L; 765 nau8825_xtalk_imm_start(nau8825, 0x00ff); 766 break; 767 case NAU8825_XTALK_HPL_R2L: 768 /* In left headphone IMM state, read out left headphone 769 * impedance measure result, and delay some time to wait 770 * detection sine wave output finish. Then, we can calculate 771 * the cross talk suppresstion side tone according to the L/R 772 * headphone imedance. 773 */ 774 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 775 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 776 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n", 777 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 778 nau8825_xtalk_imm_stop(nau8825); 779 msleep(150); 780 nau8825->xtalk_state = NAU8825_XTALK_IMM; 781 break; 782 case NAU8825_XTALK_IMM: 783 /* In impedance measure state, the orignal and cross talk 784 * signal level vlues are ready. The side tone gain is deter- 785 * mined with these signal level. After all, restore codec 786 * configuration. 787 */ 788 sidetone = nau8825_xtalk_sidetone( 789 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L], 790 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 791 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone); 792 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL, 793 (sidetone << 8) | sidetone); 794 nau8825_xtalk_clean(nau8825, false); 795 nau8825->xtalk_state = NAU8825_XTALK_DONE; 796 break; 797 default: 798 break; 799 } 800 } 801 802 static void nau8825_xtalk_work(struct work_struct *work) 803 { 804 struct nau8825 *nau8825 = container_of( 805 work, struct nau8825, xtalk_work); 806 807 nau8825_xtalk_measure(nau8825); 808 /* To determine the cross talk side tone gain when reach 809 * the impedance measure state. 810 */ 811 if (nau8825->xtalk_state == NAU8825_XTALK_IMM) 812 nau8825_xtalk_measure(nau8825); 813 814 /* Delay jack report until cross talk detection process 815 * completed. It can avoid application to do playback 816 * preparation before cross talk detection is still working. 817 * Meanwhile, the protection of the cross talk detection 818 * is released. 819 */ 820 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) { 821 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event, 822 nau8825->xtalk_event_mask); 823 nau8825_sema_release(nau8825); 824 nau8825->xtalk_protect = false; 825 } 826 } 827 828 static void nau8825_xtalk_cancel(struct nau8825 *nau8825) 829 { 830 /* If the crosstalk is eanbled and the process is on going, 831 * the driver forces to cancel the crosstalk task and 832 * restores the configuration to original status. 833 */ 834 if (nau8825->xtalk_enable && nau8825->xtalk_state != 835 NAU8825_XTALK_DONE) { 836 cancel_work_sync(&nau8825->xtalk_work); 837 nau8825_xtalk_clean(nau8825, true); 838 } 839 /* Reset parameters for cross talk suppression function */ 840 nau8825_sema_reset(nau8825); 841 nau8825->xtalk_state = NAU8825_XTALK_DONE; 842 nau8825->xtalk_protect = false; 843 } 844 845 static bool nau8825_readable_reg(struct device *dev, unsigned int reg) 846 { 847 switch (reg) { 848 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV: 849 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 850 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: 851 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 852 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 853 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 854 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: 855 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 856 case NAU8825_REG_MISC_CTRL: 857 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS: 858 case NAU8825_REG_BIAS_ADJ: 859 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 860 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 861 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 862 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: 863 return true; 864 default: 865 return false; 866 } 867 868 } 869 870 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) 871 { 872 switch (reg) { 873 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV: 874 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 875 case NAU8825_REG_INTERRUPT_MASK: 876 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: 877 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 878 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 879 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 880 case NAU8825_REG_IMM_MODE_CTRL: 881 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 882 case NAU8825_REG_MISC_CTRL: 883 case NAU8825_REG_BIAS_ADJ: 884 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 885 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 886 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 887 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) 895 { 896 switch (reg) { 897 case NAU8825_REG_RESET: 898 case NAU8825_REG_IRQ_STATUS: 899 case NAU8825_REG_INT_CLR_KEY_STATUS: 900 case NAU8825_REG_IMM_RMS_L: 901 case NAU8825_REG_IMM_RMS_R: 902 case NAU8825_REG_I2C_DEVICE_ID: 903 case NAU8825_REG_SARDOUT_RAM_STATUS: 904 case NAU8825_REG_CHARGE_PUMP_INPUT_READ: 905 case NAU8825_REG_GENERAL_STATUS: 906 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10: 907 return true; 908 default: 909 return false; 910 } 911 } 912 913 static int nau8825_adc_event(struct snd_soc_dapm_widget *w, 914 struct snd_kcontrol *kcontrol, int event) 915 { 916 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 917 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 918 919 switch (event) { 920 case SND_SOC_DAPM_POST_PMU: 921 msleep(125); 922 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 923 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 924 break; 925 case SND_SOC_DAPM_POST_PMD: 926 if (!nau8825->irq) 927 regmap_update_bits(nau8825->regmap, 928 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 return 0; 935 } 936 937 static int nau8825_pump_event(struct snd_soc_dapm_widget *w, 938 struct snd_kcontrol *kcontrol, int event) 939 { 940 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 941 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 942 943 switch (event) { 944 case SND_SOC_DAPM_POST_PMU: 945 /* Prevent startup click by letting charge pump to ramp up */ 946 msleep(10); 947 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 948 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); 949 break; 950 case SND_SOC_DAPM_PRE_PMD: 951 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 952 NAU8825_JAMNODCLOW, 0); 953 break; 954 default: 955 return -EINVAL; 956 } 957 958 return 0; 959 } 960 961 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w, 962 struct snd_kcontrol *kcontrol, int event) 963 { 964 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 965 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 966 967 switch (event) { 968 case SND_SOC_DAPM_PRE_PMU: 969 /* Disables the TESTDAC to let DAC signal pass through. */ 970 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 971 NAU8825_BIAS_TESTDAC_EN, 0); 972 break; 973 case SND_SOC_DAPM_POST_PMD: 974 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 975 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 976 break; 977 default: 978 return -EINVAL; 979 } 980 981 return 0; 982 } 983 984 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol, 985 struct snd_ctl_elem_value *ucontrol) 986 { 987 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 988 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 989 990 if (!component->regmap) 991 return -EINVAL; 992 993 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1, 994 ucontrol->value.bytes.data, params->max); 995 return 0; 996 } 997 998 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol, 999 struct snd_ctl_elem_value *ucontrol) 1000 { 1001 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1002 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1003 void *data; 1004 1005 if (!component->regmap) 1006 return -EINVAL; 1007 1008 data = kmemdup(ucontrol->value.bytes.data, 1009 params->max, GFP_KERNEL | GFP_DMA); 1010 if (!data) 1011 return -ENOMEM; 1012 1013 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1014 NAU8825_BIQ_WRT_EN, 0); 1015 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1, 1016 data, params->max); 1017 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1018 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN); 1019 1020 kfree(data); 1021 return 0; 1022 } 1023 1024 static const char * const nau8825_biq_path[] = { 1025 "ADC", "DAC" 1026 }; 1027 1028 static const struct soc_enum nau8825_biq_path_enum = 1029 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT, 1030 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path); 1031 1032 static const char * const nau8825_adc_decimation[] = { 1033 "32", "64", "128", "256" 1034 }; 1035 1036 static const struct soc_enum nau8825_adc_decimation_enum = 1037 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT, 1038 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation); 1039 1040 static const char * const nau8825_dac_oversampl[] = { 1041 "64", "256", "128", "", "32" 1042 }; 1043 1044 static const struct soc_enum nau8825_dac_oversampl_enum = 1045 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT, 1046 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl); 1047 1048 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); 1049 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 1050 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); 1051 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 1052 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400); 1053 1054 static const struct snd_kcontrol_new nau8825_controls[] = { 1055 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1056 0, 0xff, 0, adc_vol_tlv), 1057 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1058 12, 8, 0x0f, 0, sidetone_vol_tlv), 1059 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL, 1060 6, 0, 0x3f, 1, dac_vol_tlv), 1061 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL, 1062 8, 37, 0, fepga_gain_tlv), 1063 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL, 1064 0, 8, 0xff, 0, crosstalk_vol_tlv), 1065 1066 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum), 1067 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum), 1068 /* programmable biquad filter */ 1069 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum), 1070 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 1071 nau8825_biq_coeff_get, nau8825_biq_coeff_put), 1072 }; 1073 1074 /* DAC Mux 0x33[9] and 0x34[9] */ 1075 static const char * const nau8825_dac_src[] = { 1076 "DACL", "DACR", 1077 }; 1078 1079 static SOC_ENUM_SINGLE_DECL( 1080 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, 1081 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); 1082 1083 static SOC_ENUM_SINGLE_DECL( 1084 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, 1085 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); 1086 1087 static const struct snd_kcontrol_new nau8825_dacl_mux = 1088 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); 1089 1090 static const struct snd_kcontrol_new nau8825_dacr_mux = 1091 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); 1092 1093 1094 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { 1095 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2, 1096 15, 1), 1097 1098 SND_SOC_DAPM_INPUT("MIC"), 1099 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), 1100 1101 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, 1102 NULL, 0), 1103 1104 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, 1105 nau8825_adc_event, SND_SOC_DAPM_POST_PMU | 1106 SND_SOC_DAPM_POST_PMD), 1107 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), 1108 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL, 1109 0), 1110 1111 /* ADC for button press detection. A dapm supply widget is used to 1112 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON 1113 * during suspend. 1114 */ 1115 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL, 1116 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0), 1117 1118 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0), 1119 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0), 1120 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0), 1121 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0), 1122 1123 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, 1124 NAU8825_ENABLE_DACR_SFT, 0), 1125 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, 1126 NAU8825_ENABLE_DACL_SFT, 0), 1127 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), 1128 1129 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux), 1130 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux), 1131 1132 SND_SOC_DAPM_PGA_S("HP amp L", 0, 1133 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), 1134 SND_SOC_DAPM_PGA_S("HP amp R", 0, 1135 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), 1136 1137 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0, 1138 nau8825_pump_event, SND_SOC_DAPM_POST_PMU | 1139 SND_SOC_DAPM_PRE_PMD), 1140 1141 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 1142 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0), 1143 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 1144 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0), 1145 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 1146 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 1147 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 1148 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 1149 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 1150 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 1151 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 1152 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 1153 1154 SND_SOC_DAPM_PGA_S("Output DACL", 7, 1155 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event, 1156 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1157 SND_SOC_DAPM_PGA_S("Output DACR", 7, 1158 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event, 1159 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1160 1161 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 1162 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 1163 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0), 1164 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 1165 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0), 1166 1167 /* High current HPOL/R boost driver */ 1168 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 1169 NAU8825_REG_BOOST, 9, 1, NULL, 0), 1170 1171 /* Class G operation control*/ 1172 SND_SOC_DAPM_PGA_S("Class G", 10, 1173 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0), 1174 1175 SND_SOC_DAPM_OUTPUT("HPOL"), 1176 SND_SOC_DAPM_OUTPUT("HPOR"), 1177 }; 1178 1179 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { 1180 {"Frontend PGA", NULL, "MIC"}, 1181 {"ADC", NULL, "Frontend PGA"}, 1182 {"ADC", NULL, "ADC Clock"}, 1183 {"ADC", NULL, "ADC Power"}, 1184 {"AIFTX", NULL, "ADC"}, 1185 1186 {"DDACL", NULL, "Playback"}, 1187 {"DDACR", NULL, "Playback"}, 1188 {"DDACL", NULL, "DDAC Clock"}, 1189 {"DDACR", NULL, "DDAC Clock"}, 1190 {"DACL Mux", "DACL", "DDACL"}, 1191 {"DACL Mux", "DACR", "DDACR"}, 1192 {"DACR Mux", "DACL", "DDACL"}, 1193 {"DACR Mux", "DACR", "DDACR"}, 1194 {"HP amp L", NULL, "DACL Mux"}, 1195 {"HP amp R", NULL, "DACR Mux"}, 1196 {"Charge Pump", NULL, "HP amp L"}, 1197 {"Charge Pump", NULL, "HP amp R"}, 1198 {"ADACL", NULL, "Charge Pump"}, 1199 {"ADACR", NULL, "Charge Pump"}, 1200 {"ADACL Clock", NULL, "ADACL"}, 1201 {"ADACR Clock", NULL, "ADACR"}, 1202 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 1203 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 1204 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 1205 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 1206 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 1207 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 1208 {"Output DACL", NULL, "Output Driver L Stage 3"}, 1209 {"Output DACR", NULL, "Output Driver R Stage 3"}, 1210 {"HPOL Pulldown", NULL, "Output DACL"}, 1211 {"HPOR Pulldown", NULL, "Output DACR"}, 1212 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 1213 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 1214 {"Class G", NULL, "HP Boost Driver"}, 1215 {"HPOL", NULL, "Class G"}, 1216 {"HPOR", NULL, "Class G"}, 1217 }; 1218 1219 static int nau8825_clock_check(struct nau8825 *nau8825, 1220 int stream, int rate, int osr) 1221 { 1222 int osrate; 1223 1224 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1225 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1226 return -EINVAL; 1227 osrate = osr_dac_sel[osr].osr; 1228 } else { 1229 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1230 return -EINVAL; 1231 osrate = osr_adc_sel[osr].osr; 1232 } 1233 1234 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 1235 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 1236 return -EINVAL; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int nau8825_hw_params(struct snd_pcm_substream *substream, 1243 struct snd_pcm_hw_params *params, 1244 struct snd_soc_dai *dai) 1245 { 1246 struct snd_soc_component *component = dai->component; 1247 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1248 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 1249 1250 nau8825_sema_acquire(nau8825, 3 * HZ); 1251 1252 /* CLK_DAC or CLK_ADC = OSR * FS 1253 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1254 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1255 * values must be selected such that the maximum frequency is less 1256 * than 6.144 MHz. 1257 */ 1258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1259 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr); 1260 osr &= NAU8825_DAC_OVERSAMPLE_MASK; 1261 if (nau8825_clock_check(nau8825, substream->stream, 1262 params_rate(params), osr)) { 1263 nau8825_sema_release(nau8825); 1264 return -EINVAL; 1265 } 1266 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1267 NAU8825_CLK_DAC_SRC_MASK, 1268 osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT); 1269 } else { 1270 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr); 1271 osr &= NAU8825_ADC_SYNC_DOWN_MASK; 1272 if (nau8825_clock_check(nau8825, substream->stream, 1273 params_rate(params), osr)) { 1274 nau8825_sema_release(nau8825); 1275 return -EINVAL; 1276 } 1277 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1278 NAU8825_CLK_ADC_SRC_MASK, 1279 osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT); 1280 } 1281 1282 /* make BCLK and LRC divde configuration if the codec as master. */ 1283 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val); 1284 if (ctrl_val & NAU8825_I2S_MS_MASTER) { 1285 /* get the bclk and fs ratio */ 1286 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 1287 if (bclk_fs <= 32) 1288 bclk_div = 2; 1289 else if (bclk_fs <= 64) 1290 bclk_div = 1; 1291 else if (bclk_fs <= 128) 1292 bclk_div = 0; 1293 else { 1294 nau8825_sema_release(nau8825); 1295 return -EINVAL; 1296 } 1297 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1298 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK, 1299 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div); 1300 } 1301 1302 switch (params_width(params)) { 1303 case 16: 1304 val_len |= NAU8825_I2S_DL_16; 1305 break; 1306 case 20: 1307 val_len |= NAU8825_I2S_DL_20; 1308 break; 1309 case 24: 1310 val_len |= NAU8825_I2S_DL_24; 1311 break; 1312 case 32: 1313 val_len |= NAU8825_I2S_DL_32; 1314 break; 1315 default: 1316 nau8825_sema_release(nau8825); 1317 return -EINVAL; 1318 } 1319 1320 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1321 NAU8825_I2S_DL_MASK, val_len); 1322 1323 /* Release the semaphore. */ 1324 nau8825_sema_release(nau8825); 1325 1326 return 0; 1327 } 1328 1329 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1330 { 1331 struct snd_soc_component *component = codec_dai->component; 1332 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1333 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1334 1335 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1336 case SND_SOC_DAIFMT_CBM_CFM: 1337 ctrl2_val |= NAU8825_I2S_MS_MASTER; 1338 break; 1339 case SND_SOC_DAIFMT_CBS_CFS: 1340 break; 1341 default: 1342 return -EINVAL; 1343 } 1344 1345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1346 case SND_SOC_DAIFMT_NB_NF: 1347 break; 1348 case SND_SOC_DAIFMT_IB_NF: 1349 ctrl1_val |= NAU8825_I2S_BP_INV; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1356 case SND_SOC_DAIFMT_I2S: 1357 ctrl1_val |= NAU8825_I2S_DF_I2S; 1358 break; 1359 case SND_SOC_DAIFMT_LEFT_J: 1360 ctrl1_val |= NAU8825_I2S_DF_LEFT; 1361 break; 1362 case SND_SOC_DAIFMT_RIGHT_J: 1363 ctrl1_val |= NAU8825_I2S_DF_RIGTH; 1364 break; 1365 case SND_SOC_DAIFMT_DSP_A: 1366 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1367 break; 1368 case SND_SOC_DAIFMT_DSP_B: 1369 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1370 ctrl1_val |= NAU8825_I2S_PCMB_EN; 1371 break; 1372 default: 1373 return -EINVAL; 1374 } 1375 1376 nau8825_sema_acquire(nau8825, 3 * HZ); 1377 1378 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1379 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | 1380 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, 1381 ctrl1_val); 1382 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1383 NAU8825_I2S_MS_MASK, ctrl2_val); 1384 1385 /* Release the semaphore. */ 1386 nau8825_sema_release(nau8825); 1387 1388 return 0; 1389 } 1390 1391 static const struct snd_soc_dai_ops nau8825_dai_ops = { 1392 .hw_params = nau8825_hw_params, 1393 .set_fmt = nau8825_set_dai_fmt, 1394 }; 1395 1396 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 1397 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1398 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1399 1400 static struct snd_soc_dai_driver nau8825_dai = { 1401 .name = "nau8825-hifi", 1402 .playback = { 1403 .stream_name = "Playback", 1404 .channels_min = 1, 1405 .channels_max = 2, 1406 .rates = NAU8825_RATES, 1407 .formats = NAU8825_FORMATS, 1408 }, 1409 .capture = { 1410 .stream_name = "Capture", 1411 .channels_min = 1, 1412 .channels_max = 1, 1413 .rates = NAU8825_RATES, 1414 .formats = NAU8825_FORMATS, 1415 }, 1416 .ops = &nau8825_dai_ops, 1417 }; 1418 1419 /** 1420 * nau8825_enable_jack_detect - Specify a jack for event reporting 1421 * 1422 * @component: component to register the jack with 1423 * @jack: jack to use to report headset and button events on 1424 * 1425 * After this function has been called the headset insert/remove and button 1426 * events will be routed to the given jack. Jack can be null to stop 1427 * reporting. 1428 */ 1429 int nau8825_enable_jack_detect(struct snd_soc_component *component, 1430 struct snd_soc_jack *jack) 1431 { 1432 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1433 struct regmap *regmap = nau8825->regmap; 1434 1435 nau8825->jack = jack; 1436 1437 /* Ground HP Outputs[1:0], needed for headset auto detection 1438 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6] 1439 */ 1440 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1441 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 1442 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1443 1444 return 0; 1445 } 1446 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); 1447 1448 1449 static bool nau8825_is_jack_inserted(struct regmap *regmap) 1450 { 1451 bool active_high, is_high; 1452 int status, jkdet; 1453 1454 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet); 1455 active_high = jkdet & NAU8825_JACK_POLARITY; 1456 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); 1457 is_high = status & NAU8825_GPIO2JD1; 1458 /* return jack connection status according to jack insertion logic 1459 * active high or active low. 1460 */ 1461 return active_high == is_high; 1462 } 1463 1464 static void nau8825_restart_jack_detection(struct regmap *regmap) 1465 { 1466 /* this will restart the entire jack detection process including MIC/GND 1467 * switching and create interrupts. We have to go from 0 to 1 and back 1468 * to 0 to restart. 1469 */ 1470 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1471 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); 1472 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1473 NAU8825_JACK_DET_RESTART, 0); 1474 } 1475 1476 static void nau8825_int_status_clear_all(struct regmap *regmap) 1477 { 1478 int active_irq, clear_irq, i; 1479 1480 /* Reset the intrruption status from rightmost bit if the corres- 1481 * ponding irq event occurs. 1482 */ 1483 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); 1484 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) { 1485 clear_irq = (0x1 << i); 1486 if (active_irq & clear_irq) 1487 regmap_write(regmap, 1488 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1489 } 1490 } 1491 1492 static void nau8825_eject_jack(struct nau8825 *nau8825) 1493 { 1494 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1495 struct regmap *regmap = nau8825->regmap; 1496 1497 /* Force to cancel the cross talk detection process */ 1498 nau8825_xtalk_cancel(nau8825); 1499 1500 snd_soc_dapm_disable_pin(dapm, "SAR"); 1501 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1502 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 1503 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1504 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1505 /* ground HPL/HPR, MICGRND1/2 */ 1506 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); 1507 1508 snd_soc_dapm_sync(dapm); 1509 1510 /* Clear all interruption status */ 1511 nau8825_int_status_clear_all(regmap); 1512 1513 /* Enable the insertion interruption, disable the ejection inter- 1514 * ruption, and then bypass de-bounce circuit. 1515 */ 1516 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 1517 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS, 1518 NAU8825_IRQ_EJECT_DIS); 1519 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1520 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1521 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN, 1522 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1523 NAU8825_IRQ_HEADSET_COMPLETE_EN); 1524 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1525 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 1526 1527 /* Disable ADC needed for interruptions at audo mode */ 1528 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1529 NAU8825_ENABLE_ADC, 0); 1530 1531 /* Close clock for jack type detection at manual mode */ 1532 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1533 } 1534 1535 /* Enable audo mode interruptions with internal clock. */ 1536 static void nau8825_setup_auto_irq(struct nau8825 *nau8825) 1537 { 1538 struct regmap *regmap = nau8825->regmap; 1539 1540 /* Enable headset jack type detection complete interruption and 1541 * jack ejection interruption. 1542 */ 1543 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1544 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0); 1545 1546 /* Enable internal VCO needed for interruptions */ 1547 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 1548 1549 /* Enable ADC needed for interruptions */ 1550 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1551 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 1552 1553 /* Chip needs one FSCLK cycle in order to generate interruptions, 1554 * as we cannot guarantee one will be provided by the system. Turning 1555 * master mode on then off enables us to generate that FSCLK cycle 1556 * with a minimum of contention on the clock bus. 1557 */ 1558 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1559 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER); 1560 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1561 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); 1562 1563 /* Not bypass de-bounce circuit */ 1564 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1565 NAU8825_JACK_DET_DB_BYPASS, 0); 1566 1567 /* Unmask all interruptions */ 1568 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0); 1569 1570 /* Restart the jack detection process at auto mode */ 1571 nau8825_restart_jack_detection(regmap); 1572 } 1573 1574 static int nau8825_button_decode(int value) 1575 { 1576 int buttons = 0; 1577 1578 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */ 1579 if (value & BIT(0)) 1580 buttons |= SND_JACK_BTN_0; 1581 if (value & BIT(1)) 1582 buttons |= SND_JACK_BTN_1; 1583 if (value & BIT(2)) 1584 buttons |= SND_JACK_BTN_2; 1585 if (value & BIT(3)) 1586 buttons |= SND_JACK_BTN_3; 1587 if (value & BIT(4)) 1588 buttons |= SND_JACK_BTN_4; 1589 if (value & BIT(5)) 1590 buttons |= SND_JACK_BTN_5; 1591 1592 return buttons; 1593 } 1594 1595 static int nau8825_jack_insert(struct nau8825 *nau8825) 1596 { 1597 struct regmap *regmap = nau8825->regmap; 1598 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1599 int jack_status_reg, mic_detected; 1600 int type = 0; 1601 1602 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); 1603 mic_detected = (jack_status_reg >> 10) & 3; 1604 /* The JKSLV and JKR2 all detected in high impedance headset */ 1605 if (mic_detected == 0x3) 1606 nau8825->high_imped = true; 1607 else 1608 nau8825->high_imped = false; 1609 1610 switch (mic_detected) { 1611 case 0: 1612 /* no mic */ 1613 type = SND_JACK_HEADPHONE; 1614 break; 1615 case 1: 1616 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1617 type = SND_JACK_HEADSET; 1618 1619 /* Unground MICGND1 */ 1620 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1621 1 << 2); 1622 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1623 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1624 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1625 NAU8825_MICBIAS_JKR2); 1626 /* Attach SARADC to MICGND1 */ 1627 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1628 NAU8825_SAR_INPUT_MASK, 1629 NAU8825_SAR_INPUT_JKR2); 1630 1631 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1632 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1633 snd_soc_dapm_sync(dapm); 1634 break; 1635 case 2: 1636 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1637 type = SND_JACK_HEADSET; 1638 1639 /* Unground MICGND2 */ 1640 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1641 2 << 2); 1642 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1643 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1644 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1645 NAU8825_MICBIAS_JKSLV); 1646 /* Attach SARADC to MICGND2 */ 1647 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1648 NAU8825_SAR_INPUT_MASK, 1649 NAU8825_SAR_INPUT_JKSLV); 1650 1651 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1652 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1653 snd_soc_dapm_sync(dapm); 1654 break; 1655 case 3: 1656 /* detect error case */ 1657 dev_err(nau8825->dev, "detection error; disable mic function\n"); 1658 type = SND_JACK_HEADPHONE; 1659 break; 1660 } 1661 1662 /* Leaving HPOL/R grounded after jack insert by default. They will be 1663 * ungrounded as part of the widget power up sequence at the beginning 1664 * of playback to reduce pop. 1665 */ 1666 return type; 1667 } 1668 1669 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 1670 SND_JACK_BTN_2 | SND_JACK_BTN_3) 1671 1672 static irqreturn_t nau8825_interrupt(int irq, void *data) 1673 { 1674 struct nau8825 *nau8825 = (struct nau8825 *)data; 1675 struct regmap *regmap = nau8825->regmap; 1676 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1677 1678 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) { 1679 dev_err(nau8825->dev, "failed to read irq status\n"); 1680 return IRQ_NONE; 1681 } 1682 1683 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == 1684 NAU8825_JACK_EJECTION_DETECTED) { 1685 1686 nau8825_eject_jack(nau8825); 1687 event_mask |= SND_JACK_HEADSET; 1688 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; 1689 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { 1690 int key_status; 1691 1692 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, 1693 &key_status); 1694 1695 /* upper 8 bits of the register are for short pressed keys, 1696 * lower 8 bits - for long pressed buttons 1697 */ 1698 nau8825->button_pressed = nau8825_button_decode( 1699 key_status >> 8); 1700 1701 event |= nau8825->button_pressed; 1702 event_mask |= NAU8825_BUTTONS; 1703 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; 1704 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { 1705 event_mask = NAU8825_BUTTONS; 1706 clear_irq = NAU8825_KEY_RELEASE_IRQ; 1707 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { 1708 if (nau8825_is_jack_inserted(regmap)) { 1709 event |= nau8825_jack_insert(nau8825); 1710 if (nau8825->xtalk_enable && !nau8825->high_imped) { 1711 /* Apply the cross talk suppression in the 1712 * headset without high impedance. 1713 */ 1714 if (!nau8825->xtalk_protect) { 1715 /* Raise protection for cross talk de- 1716 * tection if no protection before. 1717 * The driver has to cancel the pro- 1718 * cess and restore changes if process 1719 * is ongoing when ejection. 1720 */ 1721 int ret; 1722 nau8825->xtalk_protect = true; 1723 ret = nau8825_sema_acquire(nau8825, 0); 1724 if (ret) 1725 nau8825->xtalk_protect = false; 1726 } 1727 /* Startup cross talk detection process */ 1728 if (nau8825->xtalk_protect) { 1729 nau8825->xtalk_state = 1730 NAU8825_XTALK_PREPARE; 1731 schedule_work(&nau8825->xtalk_work); 1732 } 1733 } else { 1734 /* The cross talk suppression shouldn't apply 1735 * in the headset with high impedance. Thus, 1736 * relieve the protection raised before. 1737 */ 1738 if (nau8825->xtalk_protect) { 1739 nau8825_sema_release(nau8825); 1740 nau8825->xtalk_protect = false; 1741 } 1742 } 1743 } else { 1744 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); 1745 nau8825_eject_jack(nau8825); 1746 } 1747 1748 event_mask |= SND_JACK_HEADSET; 1749 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; 1750 /* Record the interruption report event for driver to report 1751 * the event later. The jack report will delay until cross 1752 * talk detection process is done. 1753 */ 1754 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) { 1755 nau8825->xtalk_event = event; 1756 nau8825->xtalk_event_mask = event_mask; 1757 } 1758 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) { 1759 /* crosstalk detection enable and process on going */ 1760 if (nau8825->xtalk_enable && nau8825->xtalk_protect) 1761 schedule_work(&nau8825->xtalk_work); 1762 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ; 1763 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) == 1764 NAU8825_JACK_INSERTION_DETECTED) { 1765 /* One more step to check GPIO status directly. Thus, the 1766 * driver can confirm the real insertion interruption because 1767 * the intrruption at manual mode has bypassed debounce 1768 * circuit which can get rid of unstable status. 1769 */ 1770 if (nau8825_is_jack_inserted(regmap)) { 1771 /* Turn off insertion interruption at manual mode */ 1772 regmap_update_bits(regmap, 1773 NAU8825_REG_INTERRUPT_DIS_CTRL, 1774 NAU8825_IRQ_INSERT_DIS, 1775 NAU8825_IRQ_INSERT_DIS); 1776 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1777 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN); 1778 /* Enable interruption for jack type detection at audo 1779 * mode which can detect microphone and jack type. 1780 */ 1781 nau8825_setup_auto_irq(nau8825); 1782 } 1783 } 1784 1785 if (!clear_irq) 1786 clear_irq = active_irq; 1787 /* clears the rightmost interruption */ 1788 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1789 1790 /* Delay jack report until cross talk detection is done. It can avoid 1791 * application to do playback preparation when cross talk detection 1792 * process is still working. Otherwise, the resource like clock and 1793 * power will be issued by them at the same time and conflict happens. 1794 */ 1795 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE) 1796 snd_soc_jack_report(nau8825->jack, event, event_mask); 1797 1798 return IRQ_HANDLED; 1799 } 1800 1801 static void nau8825_setup_buttons(struct nau8825 *nau8825) 1802 { 1803 struct regmap *regmap = nau8825->regmap; 1804 1805 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1806 NAU8825_SAR_TRACKING_GAIN_MASK, 1807 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 1808 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1809 NAU8825_SAR_COMPARE_TIME_MASK, 1810 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT); 1811 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1812 NAU8825_SAR_SAMPLING_TIME_MASK, 1813 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT); 1814 1815 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1816 NAU8825_KEYDET_LEVELS_NR_MASK, 1817 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT); 1818 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1819 NAU8825_KEYDET_HYSTERESIS_MASK, 1820 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT); 1821 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1822 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK, 1823 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT); 1824 1825 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, 1826 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]); 1827 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, 1828 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]); 1829 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3, 1830 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]); 1831 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4, 1832 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]); 1833 1834 /* Enable short press and release interruptions */ 1835 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1836 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN, 1837 0); 1838 } 1839 1840 static void nau8825_init_regs(struct nau8825 *nau8825) 1841 { 1842 struct regmap *regmap = nau8825->regmap; 1843 1844 /* Latch IIC LSB value */ 1845 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001); 1846 /* Enable Bias/Vmid */ 1847 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1848 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID); 1849 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 1850 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN); 1851 1852 /* VMID Tieoff */ 1853 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ, 1854 NAU8825_BIAS_VMID_SEL_MASK, 1855 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT); 1856 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1857 regmap_update_bits(regmap, NAU8825_REG_BOOST, 1858 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 1859 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN, 1860 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 1861 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN); 1862 1863 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1864 NAU8825_JKDET_OUTPUT_EN, 1865 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN); 1866 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1867 NAU8825_JKDET_PULL_EN, 1868 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN); 1869 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1870 NAU8825_JKDET_PULL_UP, 1871 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0); 1872 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1873 NAU8825_JACK_POLARITY, 1874 /* jkdet_polarity - 1 is for active-low */ 1875 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY); 1876 1877 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1878 NAU8825_JACK_INSERT_DEBOUNCE_MASK, 1879 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT); 1880 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1881 NAU8825_JACK_EJECT_DEBOUNCE_MASK, 1882 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT); 1883 1884 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1885 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff); 1886 1887 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1888 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 1889 1890 if (nau8825->sar_threshold_num) 1891 nau8825_setup_buttons(nau8825); 1892 1893 /* Default oversampling/decimations settings are unusable 1894 * (audible hiss). Set it to something better. 1895 */ 1896 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, 1897 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, 1898 NAU8825_ADC_SYNC_DOWN_64); 1899 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 1900 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); 1901 /* Disable DACR/L power */ 1902 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 1903 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 1904 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 1905 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1906 * signal to avoid any glitches due to power up transients in both 1907 * the analog and digital DAC circuit. 1908 */ 1909 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1910 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 1911 /* CICCLP off */ 1912 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 1913 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF); 1914 1915 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1916 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2, 1917 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 1918 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB, 1919 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 1920 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB); 1921 /* Class G timer 64ms */ 1922 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL, 1923 NAU8825_CLASSG_TIMER_MASK, 1924 0x20 << NAU8825_CLASSG_TIMER_SFT); 1925 /* DAC clock delay 2ns, VREF */ 1926 regmap_update_bits(regmap, NAU8825_REG_RDAC, 1927 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, 1928 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | 1929 (0x3 << NAU8825_RDAC_VREF_SFT)); 1930 /* Config L/R channel */ 1931 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 1932 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); 1933 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 1934 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); 1935 /* Disable short Frame Sync detection logic */ 1936 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, 1937 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); 1938 } 1939 1940 static const struct regmap_config nau8825_regmap_config = { 1941 .val_bits = NAU8825_REG_DATA_LEN, 1942 .reg_bits = NAU8825_REG_ADDR_LEN, 1943 1944 .max_register = NAU8825_REG_MAX, 1945 .readable_reg = nau8825_readable_reg, 1946 .writeable_reg = nau8825_writeable_reg, 1947 .volatile_reg = nau8825_volatile_reg, 1948 1949 .cache_type = REGCACHE_RBTREE, 1950 .reg_defaults = nau8825_reg_defaults, 1951 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), 1952 }; 1953 1954 static int nau8825_component_probe(struct snd_soc_component *component) 1955 { 1956 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1957 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1958 1959 nau8825->dapm = dapm; 1960 1961 return 0; 1962 } 1963 1964 static void nau8825_component_remove(struct snd_soc_component *component) 1965 { 1966 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1967 1968 /* Cancel and reset cross tak suppresstion detection funciton */ 1969 nau8825_xtalk_cancel(nau8825); 1970 } 1971 1972 /** 1973 * nau8825_calc_fll_param - Calculate FLL parameters. 1974 * @fll_in: external clock provided to codec. 1975 * @fs: sampling rate. 1976 * @fll_param: Pointer to structure of FLL parameters. 1977 * 1978 * Calculate FLL parameters to configure codec. 1979 * 1980 * Returns 0 for success or negative error code. 1981 */ 1982 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs, 1983 struct nau8825_fll *fll_param) 1984 { 1985 u64 fvco, fvco_max; 1986 unsigned int fref, i, fvco_sel; 1987 1988 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1989 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1990 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK 1991 */ 1992 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1993 fref = fll_in / fll_pre_scalar[i].param; 1994 if (fref <= NAU_FREF_MAX) 1995 break; 1996 } 1997 if (i == ARRAY_SIZE(fll_pre_scalar)) 1998 return -EINVAL; 1999 fll_param->clk_ref_div = fll_pre_scalar[i].val; 2000 2001 /* Choose the FLL ratio based on FREF */ 2002 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 2003 if (fref >= fll_ratio[i].param) 2004 break; 2005 } 2006 if (i == ARRAY_SIZE(fll_ratio)) 2007 return -EINVAL; 2008 fll_param->ratio = fll_ratio[i].val; 2009 2010 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 2011 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 2012 * guaranteed across the full range of operation. 2013 * FDCO = freq_out * 2 * mclk_src_scaling 2014 */ 2015 fvco_max = 0; 2016 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 2017 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 2018 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 2019 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 2020 fvco_max < fvco) { 2021 fvco_max = fvco; 2022 fvco_sel = i; 2023 } 2024 } 2025 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 2026 return -EINVAL; 2027 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 2028 2029 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 2030 * input based on FDCO, FREF and FLL ratio. 2031 */ 2032 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 2033 fll_param->fll_int = (fvco >> 16) & 0x3FF; 2034 fll_param->fll_frac = fvco & 0xFFFF; 2035 return 0; 2036 } 2037 2038 static void nau8825_fll_apply(struct nau8825 *nau8825, 2039 struct nau8825_fll *fll_param) 2040 { 2041 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2042 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, 2043 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); 2044 /* Make DSP operate at high speed for better performance. */ 2045 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 2046 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, 2047 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); 2048 /* FLL 16-bit fractional input */ 2049 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac); 2050 /* FLL 10-bit integer input */ 2051 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3, 2052 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int); 2053 /* FLL pre-scaler */ 2054 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4, 2055 NAU8825_FLL_REF_DIV_MASK, 2056 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT); 2057 /* select divided VCO input */ 2058 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2059 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF); 2060 /* Disable free-running mode */ 2061 regmap_update_bits(nau8825->regmap, 2062 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); 2063 if (fll_param->fll_frac) { 2064 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 2065 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2066 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2067 NAU8825_FLL_FTR_SW_MASK, 2068 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2069 NAU8825_FLL_FTR_SW_FILTER); 2070 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2071 NAU8825_SDM_EN | NAU8825_CUTOFF500, 2072 NAU8825_SDM_EN | NAU8825_CUTOFF500); 2073 } else { 2074 /* disable FLL loop filter and cutoff frequency */ 2075 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2076 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2077 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); 2078 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2079 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); 2080 } 2081 } 2082 2083 /* freq_out must be 256*Fs in order to achieve the best performance */ 2084 static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source, 2085 unsigned int freq_in, unsigned int freq_out) 2086 { 2087 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2088 struct nau8825_fll fll_param; 2089 int ret, fs; 2090 2091 fs = freq_out / 256; 2092 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param); 2093 if (ret < 0) { 2094 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2095 return ret; 2096 } 2097 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 2098 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 2099 fll_param.fll_int, fll_param.clk_ref_div); 2100 2101 nau8825_fll_apply(nau8825, &fll_param); 2102 mdelay(2); 2103 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2104 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2105 return 0; 2106 } 2107 2108 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq) 2109 { 2110 int ret = 0; 2111 2112 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk"); 2113 if (IS_ERR(nau8825->mclk)) { 2114 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2115 return 0; 2116 } 2117 2118 if (!nau8825->mclk_freq) { 2119 ret = clk_prepare_enable(nau8825->mclk); 2120 if (ret) { 2121 dev_err(nau8825->dev, "Unable to prepare codec mclk\n"); 2122 return ret; 2123 } 2124 } 2125 2126 if (nau8825->mclk_freq != freq) { 2127 freq = clk_round_rate(nau8825->mclk, freq); 2128 ret = clk_set_rate(nau8825->mclk, freq); 2129 if (ret) { 2130 dev_err(nau8825->dev, "Unable to set mclk rate\n"); 2131 return ret; 2132 } 2133 nau8825->mclk_freq = freq; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) 2140 { 2141 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2142 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); 2143 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2144 NAU8825_DCO_EN, 0); 2145 /* Make DSP operate as default setting for power saving. */ 2146 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2147 NAU8825_ICTRL_LATCH_MASK, 0); 2148 } 2149 2150 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, 2151 unsigned int freq) 2152 { 2153 struct regmap *regmap = nau8825->regmap; 2154 int ret; 2155 2156 switch (clk_id) { 2157 case NAU8825_CLK_DIS: 2158 /* Clock provided externally and disable internal VCO clock */ 2159 nau8825_configure_mclk_as_sysclk(regmap); 2160 if (nau8825->mclk_freq) { 2161 clk_disable_unprepare(nau8825->mclk); 2162 nau8825->mclk_freq = 0; 2163 } 2164 2165 break; 2166 case NAU8825_CLK_MCLK: 2167 /* Acquire the semaphore to synchronize the playback and 2168 * interrupt handler. In order to avoid the playback inter- 2169 * fered by cross talk process, the driver make the playback 2170 * preparation halted until cross talk process finish. 2171 */ 2172 nau8825_sema_acquire(nau8825, 3 * HZ); 2173 nau8825_configure_mclk_as_sysclk(regmap); 2174 /* MCLK not changed by clock tree */ 2175 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2176 NAU8825_CLK_MCLK_SRC_MASK, 0); 2177 /* Release the semaphore. */ 2178 nau8825_sema_release(nau8825); 2179 2180 ret = nau8825_mclk_prepare(nau8825, freq); 2181 if (ret) 2182 return ret; 2183 2184 break; 2185 case NAU8825_CLK_INTERNAL: 2186 if (nau8825_is_jack_inserted(nau8825->regmap)) { 2187 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2188 NAU8825_DCO_EN, NAU8825_DCO_EN); 2189 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2190 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2191 /* Decrease the VCO frequency and make DSP operate 2192 * as default setting for power saving. 2193 */ 2194 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2195 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2196 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2197 NAU8825_ICTRL_LATCH_MASK | 2198 NAU8825_FLL_RATIO_MASK, 0x10); 2199 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2200 NAU8825_SDM_EN, NAU8825_SDM_EN); 2201 } else { 2202 /* The clock turns off intentionally for power saving 2203 * when no headset connected. 2204 */ 2205 nau8825_configure_mclk_as_sysclk(regmap); 2206 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n"); 2207 } 2208 if (nau8825->mclk_freq) { 2209 clk_disable_unprepare(nau8825->mclk); 2210 nau8825->mclk_freq = 0; 2211 } 2212 2213 break; 2214 case NAU8825_CLK_FLL_MCLK: 2215 /* Acquire the semaphore to synchronize the playback and 2216 * interrupt handler. In order to avoid the playback inter- 2217 * fered by cross talk process, the driver make the playback 2218 * preparation halted until cross talk process finish. 2219 */ 2220 nau8825_sema_acquire(nau8825, 3 * HZ); 2221 /* Higher FLL reference input frequency can only set lower 2222 * gain error, such as 0000 for input reference from MCLK 2223 * 12.288Mhz. 2224 */ 2225 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2226 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2227 NAU8825_FLL_CLK_SRC_MCLK | 0); 2228 /* Release the semaphore. */ 2229 nau8825_sema_release(nau8825); 2230 2231 ret = nau8825_mclk_prepare(nau8825, freq); 2232 if (ret) 2233 return ret; 2234 2235 break; 2236 case NAU8825_CLK_FLL_BLK: 2237 /* Acquire the semaphore to synchronize the playback and 2238 * interrupt handler. In order to avoid the playback inter- 2239 * fered by cross talk process, the driver make the playback 2240 * preparation halted until cross talk process finish. 2241 */ 2242 nau8825_sema_acquire(nau8825, 3 * HZ); 2243 /* If FLL reference input is from low frequency source, 2244 * higher error gain can apply such as 0xf which has 2245 * the most sensitive gain error correction threshold, 2246 * Therefore, FLL has the most accurate DCO to 2247 * target frequency. 2248 */ 2249 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2250 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2251 NAU8825_FLL_CLK_SRC_BLK | 2252 (0xf << NAU8825_GAIN_ERR_SFT)); 2253 /* Release the semaphore. */ 2254 nau8825_sema_release(nau8825); 2255 2256 if (nau8825->mclk_freq) { 2257 clk_disable_unprepare(nau8825->mclk); 2258 nau8825->mclk_freq = 0; 2259 } 2260 2261 break; 2262 case NAU8825_CLK_FLL_FS: 2263 /* Acquire the semaphore to synchronize the playback and 2264 * interrupt handler. In order to avoid the playback inter- 2265 * fered by cross talk process, the driver make the playback 2266 * preparation halted until cross talk process finish. 2267 */ 2268 nau8825_sema_acquire(nau8825, 3 * HZ); 2269 /* If FLL reference input is from low frequency source, 2270 * higher error gain can apply such as 0xf which has 2271 * the most sensitive gain error correction threshold, 2272 * Therefore, FLL has the most accurate DCO to 2273 * target frequency. 2274 */ 2275 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2276 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2277 NAU8825_FLL_CLK_SRC_FS | 2278 (0xf << NAU8825_GAIN_ERR_SFT)); 2279 /* Release the semaphore. */ 2280 nau8825_sema_release(nau8825); 2281 2282 if (nau8825->mclk_freq) { 2283 clk_disable_unprepare(nau8825->mclk); 2284 nau8825->mclk_freq = 0; 2285 } 2286 2287 break; 2288 default: 2289 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id); 2290 return -EINVAL; 2291 } 2292 2293 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq, 2294 clk_id); 2295 return 0; 2296 } 2297 2298 static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id, 2299 int source, unsigned int freq, int dir) 2300 { 2301 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2302 2303 return nau8825_configure_sysclk(nau8825, clk_id, freq); 2304 } 2305 2306 static int nau8825_resume_setup(struct nau8825 *nau8825) 2307 { 2308 struct regmap *regmap = nau8825->regmap; 2309 2310 /* Close clock when jack type detection at manual mode */ 2311 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 2312 2313 /* Clear all interruption status */ 2314 nau8825_int_status_clear_all(regmap); 2315 2316 /* Enable both insertion and ejection interruptions, and then 2317 * bypass de-bounce circuit. 2318 */ 2319 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2320 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN | 2321 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN, 2322 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN); 2323 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2324 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 2325 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 2326 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0); 2327 2328 return 0; 2329 } 2330 2331 static int nau8825_set_bias_level(struct snd_soc_component *component, 2332 enum snd_soc_bias_level level) 2333 { 2334 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2335 int ret; 2336 2337 switch (level) { 2338 case SND_SOC_BIAS_ON: 2339 break; 2340 2341 case SND_SOC_BIAS_PREPARE: 2342 break; 2343 2344 case SND_SOC_BIAS_STANDBY: 2345 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2346 if (nau8825->mclk_freq) { 2347 ret = clk_prepare_enable(nau8825->mclk); 2348 if (ret) { 2349 dev_err(nau8825->dev, "Unable to prepare component mclk\n"); 2350 return ret; 2351 } 2352 } 2353 /* Setup codec configuration after resume */ 2354 nau8825_resume_setup(nau8825); 2355 } 2356 break; 2357 2358 case SND_SOC_BIAS_OFF: 2359 /* Reset the configuration of jack type for detection */ 2360 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 2361 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS, 2362 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 2363 /* ground HPL/HPR, MICGRND1/2 */ 2364 regmap_update_bits(nau8825->regmap, 2365 NAU8825_REG_HSD_CTRL, 0xf, 0xf); 2366 /* Cancel and reset cross talk detection funciton */ 2367 nau8825_xtalk_cancel(nau8825); 2368 /* Turn off all interruptions before system shutdown. Keep the 2369 * interruption quiet before resume setup completes. 2370 */ 2371 regmap_write(nau8825->regmap, 2372 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff); 2373 /* Disable ADC needed for interruptions at audo mode */ 2374 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 2375 NAU8825_ENABLE_ADC, 0); 2376 if (nau8825->mclk_freq) 2377 clk_disable_unprepare(nau8825->mclk); 2378 break; 2379 } 2380 return 0; 2381 } 2382 2383 static int __maybe_unused nau8825_suspend(struct snd_soc_component *component) 2384 { 2385 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2386 2387 disable_irq(nau8825->irq); 2388 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 2389 /* Power down codec power; don't suppoet button wakeup */ 2390 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR"); 2391 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS"); 2392 snd_soc_dapm_sync(nau8825->dapm); 2393 regcache_cache_only(nau8825->regmap, true); 2394 regcache_mark_dirty(nau8825->regmap); 2395 2396 return 0; 2397 } 2398 2399 static int __maybe_unused nau8825_resume(struct snd_soc_component *component) 2400 { 2401 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2402 int ret; 2403 2404 regcache_cache_only(nau8825->regmap, false); 2405 regcache_sync(nau8825->regmap); 2406 nau8825->xtalk_protect = true; 2407 ret = nau8825_sema_acquire(nau8825, 0); 2408 if (ret) 2409 nau8825->xtalk_protect = false; 2410 enable_irq(nau8825->irq); 2411 2412 return 0; 2413 } 2414 2415 static const struct snd_soc_component_driver nau8825_component_driver = { 2416 .probe = nau8825_component_probe, 2417 .remove = nau8825_component_remove, 2418 .set_sysclk = nau8825_set_sysclk, 2419 .set_pll = nau8825_set_pll, 2420 .set_bias_level = nau8825_set_bias_level, 2421 .suspend = nau8825_suspend, 2422 .resume = nau8825_resume, 2423 .controls = nau8825_controls, 2424 .num_controls = ARRAY_SIZE(nau8825_controls), 2425 .dapm_widgets = nau8825_dapm_widgets, 2426 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), 2427 .dapm_routes = nau8825_dapm_routes, 2428 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), 2429 .suspend_bias_off = 1, 2430 .idle_bias_on = 1, 2431 .use_pmdown_time = 1, 2432 .endianness = 1, 2433 .non_legacy_dai_naming = 1, 2434 }; 2435 2436 static void nau8825_reset_chip(struct regmap *regmap) 2437 { 2438 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2439 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2440 } 2441 2442 static void nau8825_print_device_properties(struct nau8825 *nau8825) 2443 { 2444 int i; 2445 struct device *dev = nau8825->dev; 2446 2447 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable); 2448 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable); 2449 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up); 2450 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity); 2451 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage); 2452 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance); 2453 2454 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num); 2455 for (i = 0; i < nau8825->sar_threshold_num; i++) 2456 dev_dbg(dev, "sar-threshold[%d]=%d\n", i, 2457 nau8825->sar_threshold[i]); 2458 2459 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis); 2460 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage); 2461 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time); 2462 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time); 2463 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce); 2464 dev_dbg(dev, "jack-insert-debounce: %d\n", 2465 nau8825->jack_insert_debounce); 2466 dev_dbg(dev, "jack-eject-debounce: %d\n", 2467 nau8825->jack_eject_debounce); 2468 dev_dbg(dev, "crosstalk-enable: %d\n", 2469 nau8825->xtalk_enable); 2470 } 2471 2472 static int nau8825_read_device_properties(struct device *dev, 2473 struct nau8825 *nau8825) { 2474 int ret; 2475 2476 nau8825->jkdet_enable = device_property_read_bool(dev, 2477 "nuvoton,jkdet-enable"); 2478 nau8825->jkdet_pull_enable = device_property_read_bool(dev, 2479 "nuvoton,jkdet-pull-enable"); 2480 nau8825->jkdet_pull_up = device_property_read_bool(dev, 2481 "nuvoton,jkdet-pull-up"); 2482 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 2483 &nau8825->jkdet_polarity); 2484 if (ret) 2485 nau8825->jkdet_polarity = 1; 2486 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 2487 &nau8825->micbias_voltage); 2488 if (ret) 2489 nau8825->micbias_voltage = 6; 2490 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 2491 &nau8825->vref_impedance); 2492 if (ret) 2493 nau8825->vref_impedance = 2; 2494 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 2495 &nau8825->sar_threshold_num); 2496 if (ret) 2497 nau8825->sar_threshold_num = 4; 2498 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 2499 nau8825->sar_threshold, nau8825->sar_threshold_num); 2500 if (ret) { 2501 nau8825->sar_threshold[0] = 0x08; 2502 nau8825->sar_threshold[1] = 0x12; 2503 nau8825->sar_threshold[2] = 0x26; 2504 nau8825->sar_threshold[3] = 0x73; 2505 } 2506 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 2507 &nau8825->sar_hysteresis); 2508 if (ret) 2509 nau8825->sar_hysteresis = 0; 2510 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 2511 &nau8825->sar_voltage); 2512 if (ret) 2513 nau8825->sar_voltage = 6; 2514 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 2515 &nau8825->sar_compare_time); 2516 if (ret) 2517 nau8825->sar_compare_time = 1; 2518 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 2519 &nau8825->sar_sampling_time); 2520 if (ret) 2521 nau8825->sar_sampling_time = 1; 2522 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 2523 &nau8825->key_debounce); 2524 if (ret) 2525 nau8825->key_debounce = 3; 2526 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 2527 &nau8825->jack_insert_debounce); 2528 if (ret) 2529 nau8825->jack_insert_debounce = 7; 2530 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 2531 &nau8825->jack_eject_debounce); 2532 if (ret) 2533 nau8825->jack_eject_debounce = 0; 2534 nau8825->xtalk_enable = device_property_read_bool(dev, 2535 "nuvoton,crosstalk-enable"); 2536 2537 nau8825->mclk = devm_clk_get(dev, "mclk"); 2538 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) { 2539 return -EPROBE_DEFER; 2540 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) { 2541 /* The MCLK is managed externally or not used at all */ 2542 nau8825->mclk = NULL; 2543 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2544 } else if (IS_ERR(nau8825->mclk)) { 2545 return -EINVAL; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int nau8825_setup_irq(struct nau8825 *nau8825) 2552 { 2553 int ret; 2554 2555 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL, 2556 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 2557 "nau8825", nau8825); 2558 2559 if (ret) { 2560 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n", 2561 nau8825->irq, ret); 2562 return ret; 2563 } 2564 2565 return 0; 2566 } 2567 2568 static int nau8825_i2c_probe(struct i2c_client *i2c, 2569 const struct i2c_device_id *id) 2570 { 2571 struct device *dev = &i2c->dev; 2572 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev); 2573 int ret, value; 2574 2575 if (!nau8825) { 2576 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); 2577 if (!nau8825) 2578 return -ENOMEM; 2579 ret = nau8825_read_device_properties(dev, nau8825); 2580 if (ret) 2581 return ret; 2582 } 2583 2584 i2c_set_clientdata(i2c, nau8825); 2585 2586 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); 2587 if (IS_ERR(nau8825->regmap)) 2588 return PTR_ERR(nau8825->regmap); 2589 nau8825->dev = dev; 2590 nau8825->irq = i2c->irq; 2591 /* Initiate parameters, semaphore and work queue which are needed in 2592 * cross talk suppression measurment function. 2593 */ 2594 nau8825->xtalk_state = NAU8825_XTALK_DONE; 2595 nau8825->xtalk_protect = false; 2596 nau8825->xtalk_baktab_initialized = false; 2597 sema_init(&nau8825->xtalk_sem, 1); 2598 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work); 2599 2600 nau8825_print_device_properties(nau8825); 2601 2602 nau8825_reset_chip(nau8825->regmap); 2603 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); 2604 if (ret < 0) { 2605 dev_err(dev, "Failed to read device id from the NAU8825: %d\n", 2606 ret); 2607 return ret; 2608 } 2609 if ((value & NAU8825_SOFTWARE_ID_MASK) != 2610 NAU8825_SOFTWARE_ID_NAU8825) { 2611 dev_err(dev, "Not a NAU8825 chip\n"); 2612 return -ENODEV; 2613 } 2614 2615 nau8825_init_regs(nau8825); 2616 2617 if (i2c->irq) 2618 nau8825_setup_irq(nau8825); 2619 2620 return devm_snd_soc_register_component(&i2c->dev, 2621 &nau8825_component_driver, 2622 &nau8825_dai, 1); 2623 } 2624 2625 static int nau8825_i2c_remove(struct i2c_client *client) 2626 { 2627 return 0; 2628 } 2629 2630 static const struct i2c_device_id nau8825_i2c_ids[] = { 2631 { "nau8825", 0 }, 2632 { } 2633 }; 2634 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); 2635 2636 #ifdef CONFIG_OF 2637 static const struct of_device_id nau8825_of_ids[] = { 2638 { .compatible = "nuvoton,nau8825", }, 2639 {} 2640 }; 2641 MODULE_DEVICE_TABLE(of, nau8825_of_ids); 2642 #endif 2643 2644 #ifdef CONFIG_ACPI 2645 static const struct acpi_device_id nau8825_acpi_match[] = { 2646 { "10508825", 0 }, 2647 {}, 2648 }; 2649 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); 2650 #endif 2651 2652 static struct i2c_driver nau8825_driver = { 2653 .driver = { 2654 .name = "nau8825", 2655 .of_match_table = of_match_ptr(nau8825_of_ids), 2656 .acpi_match_table = ACPI_PTR(nau8825_acpi_match), 2657 }, 2658 .probe = nau8825_i2c_probe, 2659 .remove = nau8825_i2c_remove, 2660 .id_table = nau8825_i2c_ids, 2661 }; 2662 module_i2c_driver(nau8825_driver); 2663 2664 MODULE_DESCRIPTION("ASoC nau8825 driver"); 2665 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>"); 2666 MODULE_LICENSE("GPL"); 2667