1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Nuvoton NAU8825 audio codec driver 4 * 5 * Copyright 2015 Google Chromium project. 6 * Author: Anatol Pomozov <anatol@chromium.org> 7 * Copyright 2015 Nuvoton Technology Corp. 8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/clk.h> 18 #include <linux/acpi.h> 19 #include <linux/math64.h> 20 #include <linux/semaphore.h> 21 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/jack.h> 29 30 31 #include "nau8825.h" 32 33 34 #define NUVOTON_CODEC_DAI "nau8825-hifi" 35 36 #define NAU_FREF_MAX 13500000 37 #define NAU_FVCO_MAX 124000000 38 #define NAU_FVCO_MIN 90000000 39 40 /* cross talk suppression detection */ 41 #define LOG10_MAGIC 646456993 42 #define GAIN_AUGMENT 22500 43 #define SIDETONE_BASE 207000 44 45 /* the maximum frequency of CLK_ADC and CLK_DAC */ 46 #define CLK_DA_AD_MAX 6144000 47 48 static int nau8825_configure_sysclk(struct nau8825 *nau8825, 49 int clk_id, unsigned int freq); 50 static bool nau8825_is_jack_inserted(struct regmap *regmap); 51 52 struct nau8825_fll { 53 int mclk_src; 54 int ratio; 55 int fll_frac; 56 int fll_int; 57 int clk_ref_div; 58 }; 59 60 struct nau8825_fll_attr { 61 unsigned int param; 62 unsigned int val; 63 }; 64 65 /* scaling for mclk from sysclk_src output */ 66 static const struct nau8825_fll_attr mclk_src_scaling[] = { 67 { 1, 0x0 }, 68 { 2, 0x2 }, 69 { 4, 0x3 }, 70 { 8, 0x4 }, 71 { 16, 0x5 }, 72 { 32, 0x6 }, 73 { 3, 0x7 }, 74 { 6, 0xa }, 75 { 12, 0xb }, 76 { 24, 0xc }, 77 { 48, 0xd }, 78 { 96, 0xe }, 79 { 5, 0xf }, 80 }; 81 82 /* ratio for input clk freq */ 83 static const struct nau8825_fll_attr fll_ratio[] = { 84 { 512000, 0x01 }, 85 { 256000, 0x02 }, 86 { 128000, 0x04 }, 87 { 64000, 0x08 }, 88 { 32000, 0x10 }, 89 { 8000, 0x20 }, 90 { 4000, 0x40 }, 91 }; 92 93 static const struct nau8825_fll_attr fll_pre_scalar[] = { 94 { 1, 0x0 }, 95 { 2, 0x1 }, 96 { 4, 0x2 }, 97 { 8, 0x3 }, 98 }; 99 100 /* over sampling rate */ 101 struct nau8825_osr_attr { 102 unsigned int osr; 103 unsigned int clk_src; 104 }; 105 106 static const struct nau8825_osr_attr osr_dac_sel[] = { 107 { 64, 2 }, /* OSR 64, SRC 1/4 */ 108 { 256, 0 }, /* OSR 256, SRC 1 */ 109 { 128, 1 }, /* OSR 128, SRC 1/2 */ 110 { 0, 0 }, 111 { 32, 3 }, /* OSR 32, SRC 1/8 */ 112 }; 113 114 static const struct nau8825_osr_attr osr_adc_sel[] = { 115 { 32, 3 }, /* OSR 32, SRC 1/8 */ 116 { 64, 2 }, /* OSR 64, SRC 1/4 */ 117 { 128, 1 }, /* OSR 128, SRC 1/2 */ 118 { 256, 0 }, /* OSR 256, SRC 1 */ 119 }; 120 121 static const struct reg_default nau8825_reg_defaults[] = { 122 { NAU8825_REG_ENA_CTRL, 0x00ff }, 123 { NAU8825_REG_IIC_ADDR_SET, 0x0 }, 124 { NAU8825_REG_CLK_DIVIDER, 0x0050 }, 125 { NAU8825_REG_FLL1, 0x0 }, 126 { NAU8825_REG_FLL2, 0x3126 }, 127 { NAU8825_REG_FLL3, 0x0008 }, 128 { NAU8825_REG_FLL4, 0x0010 }, 129 { NAU8825_REG_FLL5, 0x0 }, 130 { NAU8825_REG_FLL6, 0x6000 }, 131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, 132 { NAU8825_REG_HSD_CTRL, 0x000c }, 133 { NAU8825_REG_JACK_DET_CTRL, 0x0 }, 134 { NAU8825_REG_INTERRUPT_MASK, 0x0 }, 135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, 136 { NAU8825_REG_SAR_CTRL, 0x0015 }, 137 { NAU8825_REG_KEYDET_CTRL, 0x0110 }, 138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, 139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, 140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, 141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, 142 { NAU8825_REG_GPIO34_CTRL, 0x0 }, 143 { NAU8825_REG_GPIO12_CTRL, 0x0 }, 144 { NAU8825_REG_TDM_CTRL, 0x0 }, 145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, 146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, 147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, 148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, 149 { NAU8825_REG_BIQ_CTRL, 0x0 }, 150 { NAU8825_REG_BIQ_COF1, 0x0 }, 151 { NAU8825_REG_BIQ_COF2, 0x0 }, 152 { NAU8825_REG_BIQ_COF3, 0x0 }, 153 { NAU8825_REG_BIQ_COF4, 0x0 }, 154 { NAU8825_REG_BIQ_COF5, 0x0 }, 155 { NAU8825_REG_BIQ_COF6, 0x0 }, 156 { NAU8825_REG_BIQ_COF7, 0x0 }, 157 { NAU8825_REG_BIQ_COF8, 0x0 }, 158 { NAU8825_REG_BIQ_COF9, 0x0 }, 159 { NAU8825_REG_BIQ_COF10, 0x0 }, 160 { NAU8825_REG_ADC_RATE, 0x0010 }, 161 { NAU8825_REG_DAC_CTRL1, 0x0001 }, 162 { NAU8825_REG_DAC_CTRL2, 0x0 }, 163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, 164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 165 { NAU8825_REG_MUTE_CTRL, 0x0 }, 166 { NAU8825_REG_HSVOL_CTRL, 0x0 }, 167 { NAU8825_REG_DACL_CTRL, 0x02cf }, 168 { NAU8825_REG_DACR_CTRL, 0x00cf }, 169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, 170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, 171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, 172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, 173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, 174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, 175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, 176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, 177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, 178 { NAU8825_REG_CLASSG_CTRL, 0x0 }, 179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, 180 { NAU8825_REG_MISC_CTRL, 0x0 }, 181 { NAU8825_REG_BIAS_ADJ, 0x0 }, 182 { NAU8825_REG_TRIM_SETTINGS, 0x0 }, 183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, 184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, 185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, 186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, 187 { NAU8825_REG_RDAC, 0x0008 }, 188 { NAU8825_REG_MIC_BIAS, 0x0006 }, 189 { NAU8825_REG_BOOST, 0x0 }, 190 { NAU8825_REG_FEPGA, 0x0 }, 191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, 192 { NAU8825_REG_CHARGE_PUMP, 0x0 }, 193 }; 194 195 /* register backup table when cross talk detection */ 196 static struct reg_default nau8825_xtalk_baktab[] = { 197 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 198 { NAU8825_REG_HSVOL_CTRL, 0 }, 199 { NAU8825_REG_DACL_CTRL, 0x00cf }, 200 { NAU8825_REG_DACR_CTRL, 0x02cf }, 201 }; 202 203 static const unsigned short logtable[256] = { 204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, 205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, 206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, 207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, 208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, 209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, 210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, 211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, 212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, 213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, 214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, 215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, 216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, 217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, 218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, 219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, 220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, 221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, 222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, 223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, 224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, 225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, 226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, 227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, 228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, 229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, 230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, 231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, 232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, 233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, 234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, 235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 236 }; 237 238 /** 239 * nau8825_sema_acquire - acquire the semaphore of nau88l25 240 * @nau8825: component to register the codec private data with 241 * @timeout: how long in jiffies to wait before failure or zero to wait 242 * until release 243 * 244 * Attempts to acquire the semaphore with number of jiffies. If no more 245 * tasks are allowed to acquire the semaphore, calling this function will 246 * put the task to sleep. If the semaphore is not released within the 247 * specified number of jiffies, this function returns. 248 * If the semaphore is not released within the specified number of jiffies, 249 * this function returns -ETIME. If the sleep is interrupted by a signal, 250 * this function will return -EINTR. It returns 0 if the semaphore was 251 * acquired successfully. 252 * 253 * Acquires the semaphore without jiffies. Try to acquire the semaphore 254 * atomically. Returns 0 if the semaphore has been acquired successfully 255 * or 1 if it cannot be acquired. 256 */ 257 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout) 258 { 259 int ret; 260 261 if (timeout) { 262 ret = down_timeout(&nau8825->xtalk_sem, timeout); 263 if (ret < 0) 264 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); 265 } else { 266 ret = down_trylock(&nau8825->xtalk_sem); 267 if (ret) 268 dev_warn(nau8825->dev, "Acquire semaphore fail\n"); 269 } 270 271 return ret; 272 } 273 274 /** 275 * nau8825_sema_release - release the semaphore of nau88l25 276 * @nau8825: component to register the codec private data with 277 * 278 * Release the semaphore which may be called from any context and 279 * even by tasks which have never called down(). 280 */ 281 static inline void nau8825_sema_release(struct nau8825 *nau8825) 282 { 283 up(&nau8825->xtalk_sem); 284 } 285 286 /** 287 * nau8825_sema_reset - reset the semaphore for nau88l25 288 * @nau8825: component to register the codec private data with 289 * 290 * Reset the counter of the semaphore. Call this function to restart 291 * a new round task management. 292 */ 293 static inline void nau8825_sema_reset(struct nau8825 *nau8825) 294 { 295 nau8825->xtalk_sem.count = 1; 296 } 297 298 /** 299 * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level. 300 * 301 * @nau8825: component to register the codec private data with 302 * @vol_from: the volume to start up 303 * @vol_to: the target volume 304 * @step: the volume span to move on 305 * 306 * The headphone volume is from 0dB to minimum -54dB and -1dB per step. 307 * If the volume changes sharp, there is a pop noise heard in headphone. We 308 * provide the function to ramp up the volume up or down by delaying 10ms 309 * per step. 310 */ 311 static void nau8825_hpvol_ramp(struct nau8825 *nau8825, 312 unsigned int vol_from, unsigned int vol_to, unsigned int step) 313 { 314 unsigned int value, volume, ramp_up, from, to; 315 316 if (vol_from == vol_to || step == 0) { 317 return; 318 } else if (vol_from < vol_to) { 319 ramp_up = true; 320 from = vol_from; 321 to = vol_to; 322 } else { 323 ramp_up = false; 324 from = vol_to; 325 to = vol_from; 326 } 327 /* only handle volume from 0dB to minimum -54dB */ 328 if (to > NAU8825_HP_VOL_MIN) 329 to = NAU8825_HP_VOL_MIN; 330 331 for (volume = from; volume < to; volume += step) { 332 if (ramp_up) 333 value = volume; 334 else 335 value = to - volume + from; 336 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 337 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 338 (value << NAU8825_HPL_VOL_SFT) | value); 339 usleep_range(10000, 10500); 340 } 341 if (ramp_up) 342 value = to; 343 else 344 value = from; 345 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 346 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 347 (value << NAU8825_HPL_VOL_SFT) | value); 348 } 349 350 /** 351 * nau8825_intlog10_dec3 - Computes log10 of a value 352 * the result is round off to 3 decimal. This function takes reference to 353 * dvb-math. The source code locates as the following. 354 * Linux/drivers/media/dvb-core/dvb_math.c 355 * @value: input for log10 356 * 357 * return log10(value) * 1000 358 */ 359 static u32 nau8825_intlog10_dec3(u32 value) 360 { 361 u32 msb, logentry, significand, interpolation, log10val; 362 u64 log2val; 363 364 /* first detect the msb (count begins at 0) */ 365 msb = fls(value) - 1; 366 /** 367 * now we use a logtable after the following method: 368 * 369 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 370 * where x = msb and therefore 1 <= y < 2 371 * first y is determined by shifting the value left 372 * so that msb is bit 31 373 * 0x00231f56 -> 0x8C7D5800 374 * the result is y * 2^31 -> "significand" 375 * then the highest 9 bits are used for a table lookup 376 * the highest bit is discarded because it's always set 377 * the highest nine bits in our example are 100011000 378 * so we would use the entry 0x18 379 */ 380 significand = value << (31 - msb); 381 logentry = (significand >> 23) & 0xff; 382 /** 383 * last step we do is interpolation because of the 384 * limitations of the log table the error is that part of 385 * the significand which isn't used for lookup then we 386 * compute the ratio between the error and the next table entry 387 * and interpolate it between the log table entry used and the 388 * next one the biggest error possible is 0x7fffff 389 * (in our example it's 0x7D5800) 390 * needed value for next table entry is 0x800000 391 * so the interpolation is 392 * (error / 0x800000) * (logtable_next - logtable_current) 393 * in the implementation the division is moved to the end for 394 * better accuracy there is also an overflow correction if 395 * logtable_next is 256 396 */ 397 interpolation = ((significand & 0x7fffff) * 398 ((logtable[(logentry + 1) & 0xff] - 399 logtable[logentry]) & 0xffff)) >> 15; 400 401 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation); 402 /** 403 * log10(x) = log2(x) * log10(2) 404 */ 405 log10val = (log2val * LOG10_MAGIC) >> 31; 406 /** 407 * the result is round off to 3 decimal 408 */ 409 return log10val / ((1 << 24) / 1000); 410 } 411 412 /** 413 * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain. 414 * 415 * @sig_org: orignal signal level 416 * @sig_cros: cross talk signal level 417 * 418 * The orignal and cross talk signal vlues need to be characterized. 419 * Once these values have been characterized, this sidetone value 420 * can be converted to decibel with the equation below. 421 * sidetone = 20 * log (original signal level / crosstalk signal level) 422 * 423 * return cross talk sidetone gain 424 */ 425 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros) 426 { 427 u32 gain, sidetone; 428 429 if (WARN_ON(sig_org == 0 || sig_cros == 0)) 430 return 0; 431 432 sig_org = nau8825_intlog10_dec3(sig_org); 433 sig_cros = nau8825_intlog10_dec3(sig_cros); 434 if (sig_org >= sig_cros) 435 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT; 436 else 437 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT; 438 sidetone = SIDETONE_BASE - gain * 2; 439 sidetone /= 1000; 440 441 return sidetone; 442 } 443 444 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) 445 { 446 int index; 447 448 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++) 449 if (nau8825_xtalk_baktab[index].reg == reg) 450 return index; 451 return -EINVAL; 452 } 453 454 static void nau8825_xtalk_backup(struct nau8825 *nau8825) 455 { 456 int i; 457 458 if (nau8825->xtalk_baktab_initialized) 459 return; 460 461 /* Backup some register values to backup table */ 462 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) 463 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 464 &nau8825_xtalk_baktab[i].def); 465 466 nau8825->xtalk_baktab_initialized = true; 467 } 468 469 static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel) 470 { 471 int i, volume; 472 473 if (!nau8825->xtalk_baktab_initialized) 474 return; 475 476 /* Restore register values from backup table; When the driver restores 477 * the headphone volume in XTALK_DONE state, it needs recover to 478 * original level gradually with 3dB per step for less pop noise. 479 * Otherwise, the restore should do ASAP. 480 */ 481 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) { 482 if (!cause_cancel && nau8825_xtalk_baktab[i].reg == 483 NAU8825_REG_HSVOL_CTRL) { 484 /* Ramping up the volume change to reduce pop noise */ 485 volume = nau8825_xtalk_baktab[i].def & 486 NAU8825_HPR_VOL_MASK; 487 nau8825_hpvol_ramp(nau8825, 0, volume, 3); 488 continue; 489 } 490 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 491 nau8825_xtalk_baktab[i].def); 492 } 493 494 nau8825->xtalk_baktab_initialized = false; 495 } 496 497 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825) 498 { 499 /* Enable power of DAC path */ 500 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 501 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 502 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK | 503 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR | 504 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC | 505 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK); 506 /* Prevent startup click by letting charge pump to ramp up and 507 * change bump enable 508 */ 509 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 510 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 511 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN); 512 /* Enable clock sync of DAC and DAC clock */ 513 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 514 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN | 515 NAU8825_RDAC_FS_BCLK_ENB, 516 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN); 517 /* Power up output driver with 2 stage */ 518 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 519 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 520 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 521 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 522 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L); 523 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 524 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 525 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L); 526 /* HP outputs not shouted to ground */ 527 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 528 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0); 529 /* Enable HP boost driver */ 530 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 531 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS); 532 /* Enable class G compare path to supply 1.8V or 0.9V. */ 533 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL, 534 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN, 535 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN); 536 } 537 538 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825) 539 { 540 /* Power up left ADC and raise 5dB than Vmid for Vref */ 541 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 542 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 543 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB); 544 } 545 546 static void nau8825_xtalk_clock(struct nau8825 *nau8825) 547 { 548 /* Recover FLL default value */ 549 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0); 550 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126); 551 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008); 552 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010); 553 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0); 554 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000); 555 /* Enable internal VCO clock for detection signal generated */ 556 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 557 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 558 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 559 NAU8825_DCO_EN); 560 /* Given specific clock frequency of internal clock to 561 * generate signal. 562 */ 563 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 564 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 565 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 566 NAU8825_FLL_RATIO_MASK, 0x10); 567 } 568 569 static void nau8825_xtalk_prepare(struct nau8825 *nau8825) 570 { 571 int volume, index; 572 573 /* Backup those registers changed by cross talk detection */ 574 nau8825_xtalk_backup(nau8825); 575 /* Config IIS as master to output signal by codec */ 576 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 577 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 578 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER | 579 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1); 580 /* Ramp up headphone volume to 0dB to get better performance and 581 * avoid pop noise in headphone. 582 */ 583 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL); 584 if (index != -EINVAL) { 585 volume = nau8825_xtalk_baktab[index].def & 586 NAU8825_HPR_VOL_MASK; 587 nau8825_hpvol_ramp(nau8825, volume, 0, 3); 588 } 589 nau8825_xtalk_clock(nau8825); 590 nau8825_xtalk_prepare_dac(nau8825); 591 nau8825_xtalk_prepare_adc(nau8825); 592 /* Config channel path and digital gain */ 593 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 594 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK, 595 NAU8825_DACL_CH_SEL_L | 0xab); 596 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 597 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK, 598 NAU8825_DACR_CH_SEL_R | 0xab); 599 /* Config cross talk parameters and generate the 23Hz sine wave with 600 * 1/16 full scale of signal level for impedance measurement. 601 */ 602 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 603 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK | 604 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK, 605 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th | 606 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN); 607 /* RMS intrruption enable */ 608 regmap_update_bits(nau8825->regmap, 609 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0); 610 /* Power up left and right DAC */ 611 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 612 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 613 } 614 615 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825) 616 { 617 /* Disable HP boost driver */ 618 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 619 NAU8825_HP_BOOST_DIS, 0); 620 /* HP outputs shouted to ground */ 621 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 622 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 623 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 624 /* Power down left and right DAC */ 625 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 626 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 627 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 628 /* Enable the TESTDAC and disable L/R HP impedance */ 629 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 630 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP | 631 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 632 /* Power down output driver with 2 stage */ 633 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 634 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0); 635 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 636 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 637 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0); 638 /* Disable clock sync of DAC and DAC clock */ 639 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 640 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0); 641 /* Disable charge pump ramp up function and change bump */ 642 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 643 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0); 644 /* Disable power of DAC path */ 645 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 646 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 647 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0); 648 if (!nau8825->irq) 649 regmap_update_bits(nau8825->regmap, 650 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 651 } 652 653 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825) 654 { 655 /* Power down left ADC and restore voltage to Vmid */ 656 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 657 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0); 658 } 659 660 static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel) 661 { 662 /* Enable internal VCO needed for interruptions */ 663 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 664 nau8825_xtalk_clean_dac(nau8825); 665 nau8825_xtalk_clean_adc(nau8825); 666 /* Clear cross talk parameters and disable */ 667 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0); 668 /* RMS intrruption disable */ 669 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK, 670 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN); 671 /* Recover default value for IIS */ 672 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 673 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 674 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE); 675 /* Restore value of specific register for cross talk */ 676 nau8825_xtalk_restore(nau8825, cause_cancel); 677 } 678 679 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol) 680 { 681 /* Apply ADC volume for better cross talk performance */ 682 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL, 683 NAU8825_ADC_DIG_VOL_MASK, vol); 684 /* Disables JKTIP(HPL) DAC channel for right to left measurement. 685 * Do it before sending signal in order to erase pop noise. 686 */ 687 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 688 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN, 689 NAU8825_BIAS_TESTDACL_EN); 690 switch (nau8825->xtalk_state) { 691 case NAU8825_XTALK_HPR_R2L: 692 /* Enable right headphone impedance */ 693 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 694 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 695 NAU8825_BIAS_HPR_IMP); 696 break; 697 case NAU8825_XTALK_HPL_R2L: 698 /* Enable left headphone impedance */ 699 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 700 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 701 NAU8825_BIAS_HPL_IMP); 702 break; 703 default: 704 break; 705 } 706 msleep(100); 707 /* Impedance measurement mode enable */ 708 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 709 NAU8825_IMM_EN, NAU8825_IMM_EN); 710 } 711 712 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825) 713 { 714 /* Impedance measurement mode disable */ 715 regmap_update_bits(nau8825->regmap, 716 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0); 717 } 718 719 /* The cross talk measurement function can reduce cross talk across the 720 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal 721 * level to determine what cross talk reduction gain is. This system works by 722 * sending a 23Hz -24dBV sine wave into the headset output DAC and through 723 * the PGA. The output of the PGA is then connected to an internal current 724 * sense which measures the attenuated 23Hz signal and passing the output to 725 * an ADC which converts the measurement to a binary code. With two separated 726 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data 727 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement. 728 * Thus, the measurement function has four states to complete whole sequence. 729 * 1. Prepare state : Prepare the resource for detection and transfer to HPR 730 * IMM stat to make JKR1(HPR) impedance measure. 731 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer 732 * to HPL IMM state to make JKTIP(HPL) impedance measure. 733 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and 734 * transfer to IMM state to determine suppression sidetone gain. 735 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal 736 * and cross talk signal level. Apply this gain and then restore codec 737 * configuration. Then transfer to Done state for ending. 738 */ 739 static void nau8825_xtalk_measure(struct nau8825 *nau8825) 740 { 741 u32 sidetone; 742 743 switch (nau8825->xtalk_state) { 744 case NAU8825_XTALK_PREPARE: 745 /* In prepare state, set up clock, intrruption, DAC path, ADC 746 * path and cross talk detection parameters for preparation. 747 */ 748 nau8825_xtalk_prepare(nau8825); 749 msleep(280); 750 /* Trigger right headphone impedance detection */ 751 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L; 752 nau8825_xtalk_imm_start(nau8825, 0x00d2); 753 break; 754 case NAU8825_XTALK_HPR_R2L: 755 /* In right headphone IMM state, read out right headphone 756 * impedance measure result, and then start up left side. 757 */ 758 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 759 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 760 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n", 761 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 762 /* Disable then re-enable IMM mode to update */ 763 nau8825_xtalk_imm_stop(nau8825); 764 /* Trigger left headphone impedance detection */ 765 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L; 766 nau8825_xtalk_imm_start(nau8825, 0x00ff); 767 break; 768 case NAU8825_XTALK_HPL_R2L: 769 /* In left headphone IMM state, read out left headphone 770 * impedance measure result, and delay some time to wait 771 * detection sine wave output finish. Then, we can calculate 772 * the cross talk suppresstion side tone according to the L/R 773 * headphone imedance. 774 */ 775 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 776 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 777 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n", 778 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 779 nau8825_xtalk_imm_stop(nau8825); 780 msleep(150); 781 nau8825->xtalk_state = NAU8825_XTALK_IMM; 782 break; 783 case NAU8825_XTALK_IMM: 784 /* In impedance measure state, the orignal and cross talk 785 * signal level vlues are ready. The side tone gain is deter- 786 * mined with these signal level. After all, restore codec 787 * configuration. 788 */ 789 sidetone = nau8825_xtalk_sidetone( 790 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L], 791 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 792 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone); 793 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL, 794 (sidetone << 8) | sidetone); 795 nau8825_xtalk_clean(nau8825, false); 796 nau8825->xtalk_state = NAU8825_XTALK_DONE; 797 break; 798 default: 799 break; 800 } 801 } 802 803 static void nau8825_xtalk_work(struct work_struct *work) 804 { 805 struct nau8825 *nau8825 = container_of( 806 work, struct nau8825, xtalk_work); 807 808 nau8825_xtalk_measure(nau8825); 809 /* To determine the cross talk side tone gain when reach 810 * the impedance measure state. 811 */ 812 if (nau8825->xtalk_state == NAU8825_XTALK_IMM) 813 nau8825_xtalk_measure(nau8825); 814 815 /* Delay jack report until cross talk detection process 816 * completed. It can avoid application to do playback 817 * preparation before cross talk detection is still working. 818 * Meanwhile, the protection of the cross talk detection 819 * is released. 820 */ 821 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) { 822 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event, 823 nau8825->xtalk_event_mask); 824 nau8825_sema_release(nau8825); 825 nau8825->xtalk_protect = false; 826 } 827 } 828 829 static void nau8825_xtalk_cancel(struct nau8825 *nau8825) 830 { 831 /* If the crosstalk is eanbled and the process is on going, 832 * the driver forces to cancel the crosstalk task and 833 * restores the configuration to original status. 834 */ 835 if (nau8825->xtalk_enable && nau8825->xtalk_state != 836 NAU8825_XTALK_DONE) { 837 cancel_work_sync(&nau8825->xtalk_work); 838 nau8825_xtalk_clean(nau8825, true); 839 } 840 /* Reset parameters for cross talk suppression function */ 841 nau8825_sema_reset(nau8825); 842 nau8825->xtalk_state = NAU8825_XTALK_DONE; 843 nau8825->xtalk_protect = false; 844 } 845 846 static bool nau8825_readable_reg(struct device *dev, unsigned int reg) 847 { 848 switch (reg) { 849 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV: 850 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 851 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: 852 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 853 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 854 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 855 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: 856 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 857 case NAU8825_REG_MISC_CTRL: 858 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS: 859 case NAU8825_REG_BIAS_ADJ: 860 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 861 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 862 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 863 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: 864 return true; 865 default: 866 return false; 867 } 868 869 } 870 871 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) 872 { 873 switch (reg) { 874 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV: 875 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 876 case NAU8825_REG_INTERRUPT_MASK: 877 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: 878 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 879 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 880 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 881 case NAU8825_REG_IMM_MODE_CTRL: 882 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 883 case NAU8825_REG_MISC_CTRL: 884 case NAU8825_REG_BIAS_ADJ: 885 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 886 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 887 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 888 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: 889 return true; 890 default: 891 return false; 892 } 893 } 894 895 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) 896 { 897 switch (reg) { 898 case NAU8825_REG_RESET: 899 case NAU8825_REG_IRQ_STATUS: 900 case NAU8825_REG_INT_CLR_KEY_STATUS: 901 case NAU8825_REG_IMM_RMS_L: 902 case NAU8825_REG_IMM_RMS_R: 903 case NAU8825_REG_I2C_DEVICE_ID: 904 case NAU8825_REG_SARDOUT_RAM_STATUS: 905 case NAU8825_REG_CHARGE_PUMP_INPUT_READ: 906 case NAU8825_REG_GENERAL_STATUS: 907 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10: 908 return true; 909 default: 910 return false; 911 } 912 } 913 914 static int nau8825_adc_event(struct snd_soc_dapm_widget *w, 915 struct snd_kcontrol *kcontrol, int event) 916 { 917 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 918 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 919 920 switch (event) { 921 case SND_SOC_DAPM_POST_PMU: 922 msleep(125); 923 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 924 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 925 break; 926 case SND_SOC_DAPM_POST_PMD: 927 if (!nau8825->irq) 928 regmap_update_bits(nau8825->regmap, 929 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 930 break; 931 default: 932 return -EINVAL; 933 } 934 935 return 0; 936 } 937 938 static int nau8825_pump_event(struct snd_soc_dapm_widget *w, 939 struct snd_kcontrol *kcontrol, int event) 940 { 941 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 942 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 943 944 switch (event) { 945 case SND_SOC_DAPM_POST_PMU: 946 /* Prevent startup click by letting charge pump to ramp up */ 947 msleep(10); 948 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 949 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); 950 break; 951 case SND_SOC_DAPM_PRE_PMD: 952 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 953 NAU8825_JAMNODCLOW, 0); 954 break; 955 default: 956 return -EINVAL; 957 } 958 959 return 0; 960 } 961 962 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w, 963 struct snd_kcontrol *kcontrol, int event) 964 { 965 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 966 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 967 968 switch (event) { 969 case SND_SOC_DAPM_PRE_PMU: 970 /* Disables the TESTDAC to let DAC signal pass through. */ 971 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 972 NAU8825_BIAS_TESTDAC_EN, 0); 973 break; 974 case SND_SOC_DAPM_POST_PMD: 975 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 976 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 977 break; 978 default: 979 return -EINVAL; 980 } 981 982 return 0; 983 } 984 985 static int system_clock_control(struct snd_soc_dapm_widget *w, 986 struct snd_kcontrol *k, int event) 987 { 988 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 989 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 990 struct regmap *regmap = nau8825->regmap; 991 992 if (SND_SOC_DAPM_EVENT_OFF(event)) { 993 dev_dbg(nau8825->dev, "system clock control : POWER OFF\n"); 994 /* Set clock source to disable or internal clock before the 995 * playback or capture end. Codec needs clock for Jack 996 * detection and button press if jack inserted; otherwise, 997 * the clock should be closed. 998 */ 999 if (nau8825_is_jack_inserted(regmap)) { 1000 nau8825_configure_sysclk(nau8825, 1001 NAU8825_CLK_INTERNAL, 0); 1002 } else { 1003 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1004 } 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol, 1011 struct snd_ctl_elem_value *ucontrol) 1012 { 1013 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1014 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1015 1016 if (!component->regmap) 1017 return -EINVAL; 1018 1019 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1, 1020 ucontrol->value.bytes.data, params->max); 1021 return 0; 1022 } 1023 1024 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol, 1025 struct snd_ctl_elem_value *ucontrol) 1026 { 1027 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1028 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1029 void *data; 1030 1031 if (!component->regmap) 1032 return -EINVAL; 1033 1034 data = kmemdup(ucontrol->value.bytes.data, 1035 params->max, GFP_KERNEL | GFP_DMA); 1036 if (!data) 1037 return -ENOMEM; 1038 1039 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1040 NAU8825_BIQ_WRT_EN, 0); 1041 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1, 1042 data, params->max); 1043 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1044 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN); 1045 1046 kfree(data); 1047 return 0; 1048 } 1049 1050 static const char * const nau8825_biq_path[] = { 1051 "ADC", "DAC" 1052 }; 1053 1054 static const struct soc_enum nau8825_biq_path_enum = 1055 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT, 1056 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path); 1057 1058 static const char * const nau8825_adc_decimation[] = { 1059 "32", "64", "128", "256" 1060 }; 1061 1062 static const struct soc_enum nau8825_adc_decimation_enum = 1063 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT, 1064 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation); 1065 1066 static const char * const nau8825_dac_oversampl[] = { 1067 "64", "256", "128", "", "32" 1068 }; 1069 1070 static const struct soc_enum nau8825_dac_oversampl_enum = 1071 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT, 1072 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl); 1073 1074 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); 1075 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 1076 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); 1077 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 1078 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400); 1079 1080 static const struct snd_kcontrol_new nau8825_controls[] = { 1081 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1082 0, 0xff, 0, adc_vol_tlv), 1083 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1084 12, 8, 0x0f, 0, sidetone_vol_tlv), 1085 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL, 1086 6, 0, 0x3f, 1, dac_vol_tlv), 1087 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL, 1088 8, 37, 0, fepga_gain_tlv), 1089 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL, 1090 0, 8, 0xff, 0, crosstalk_vol_tlv), 1091 1092 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum), 1093 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum), 1094 /* programmable biquad filter */ 1095 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum), 1096 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 1097 nau8825_biq_coeff_get, nau8825_biq_coeff_put), 1098 }; 1099 1100 /* DAC Mux 0x33[9] and 0x34[9] */ 1101 static const char * const nau8825_dac_src[] = { 1102 "DACL", "DACR", 1103 }; 1104 1105 static SOC_ENUM_SINGLE_DECL( 1106 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, 1107 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); 1108 1109 static SOC_ENUM_SINGLE_DECL( 1110 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, 1111 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); 1112 1113 static const struct snd_kcontrol_new nau8825_dacl_mux = 1114 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); 1115 1116 static const struct snd_kcontrol_new nau8825_dacr_mux = 1117 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); 1118 1119 1120 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { 1121 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2, 1122 15, 1), 1123 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 1124 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 1125 system_clock_control, SND_SOC_DAPM_POST_PMD), 1126 1127 SND_SOC_DAPM_INPUT("MIC"), 1128 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), 1129 1130 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, 1131 NULL, 0), 1132 1133 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, 1134 nau8825_adc_event, SND_SOC_DAPM_POST_PMU | 1135 SND_SOC_DAPM_POST_PMD), 1136 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), 1137 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL, 1138 0), 1139 1140 /* ADC for button press detection. A dapm supply widget is used to 1141 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON 1142 * during suspend. 1143 */ 1144 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL, 1145 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0), 1146 1147 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0), 1148 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0), 1149 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0), 1150 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0), 1151 1152 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, 1153 NAU8825_ENABLE_DACR_SFT, 0), 1154 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, 1155 NAU8825_ENABLE_DACL_SFT, 0), 1156 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), 1157 1158 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux), 1159 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux), 1160 1161 SND_SOC_DAPM_PGA_S("HP amp L", 0, 1162 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), 1163 SND_SOC_DAPM_PGA_S("HP amp R", 0, 1164 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), 1165 1166 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0, 1167 nau8825_pump_event, SND_SOC_DAPM_POST_PMU | 1168 SND_SOC_DAPM_PRE_PMD), 1169 1170 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 1171 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0), 1172 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 1173 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0), 1174 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 1175 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 1176 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 1177 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 1178 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 1179 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 1180 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 1181 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 1182 1183 SND_SOC_DAPM_PGA_S("Output DACL", 7, 1184 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event, 1185 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1186 SND_SOC_DAPM_PGA_S("Output DACR", 7, 1187 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event, 1188 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1189 1190 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 1191 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 1192 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0), 1193 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 1194 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0), 1195 1196 /* High current HPOL/R boost driver */ 1197 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 1198 NAU8825_REG_BOOST, 9, 1, NULL, 0), 1199 1200 /* Class G operation control*/ 1201 SND_SOC_DAPM_PGA_S("Class G", 10, 1202 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0), 1203 1204 SND_SOC_DAPM_OUTPUT("HPOL"), 1205 SND_SOC_DAPM_OUTPUT("HPOR"), 1206 }; 1207 1208 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { 1209 {"Frontend PGA", NULL, "MIC"}, 1210 {"ADC", NULL, "Frontend PGA"}, 1211 {"ADC", NULL, "ADC Clock"}, 1212 {"ADC", NULL, "ADC Power"}, 1213 {"AIFTX", NULL, "ADC"}, 1214 {"AIFTX", NULL, "System Clock"}, 1215 1216 {"AIFRX", NULL, "System Clock"}, 1217 {"DDACL", NULL, "AIFRX"}, 1218 {"DDACR", NULL, "AIFRX"}, 1219 {"DDACL", NULL, "DDAC Clock"}, 1220 {"DDACR", NULL, "DDAC Clock"}, 1221 {"DACL Mux", "DACL", "DDACL"}, 1222 {"DACL Mux", "DACR", "DDACR"}, 1223 {"DACR Mux", "DACL", "DDACL"}, 1224 {"DACR Mux", "DACR", "DDACR"}, 1225 {"HP amp L", NULL, "DACL Mux"}, 1226 {"HP amp R", NULL, "DACR Mux"}, 1227 {"Charge Pump", NULL, "HP amp L"}, 1228 {"Charge Pump", NULL, "HP amp R"}, 1229 {"ADACL", NULL, "Charge Pump"}, 1230 {"ADACR", NULL, "Charge Pump"}, 1231 {"ADACL Clock", NULL, "ADACL"}, 1232 {"ADACR Clock", NULL, "ADACR"}, 1233 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 1234 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 1235 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 1236 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 1237 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 1238 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 1239 {"Output DACL", NULL, "Output Driver L Stage 3"}, 1240 {"Output DACR", NULL, "Output Driver R Stage 3"}, 1241 {"HPOL Pulldown", NULL, "Output DACL"}, 1242 {"HPOR Pulldown", NULL, "Output DACR"}, 1243 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 1244 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 1245 {"Class G", NULL, "HP Boost Driver"}, 1246 {"HPOL", NULL, "Class G"}, 1247 {"HPOR", NULL, "Class G"}, 1248 }; 1249 1250 static const struct nau8825_osr_attr * 1251 nau8825_get_osr(struct nau8825 *nau8825, int stream) 1252 { 1253 unsigned int osr; 1254 1255 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1256 regmap_read(nau8825->regmap, 1257 NAU8825_REG_DAC_CTRL1, &osr); 1258 osr &= NAU8825_DAC_OVERSAMPLE_MASK; 1259 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1260 return NULL; 1261 return &osr_dac_sel[osr]; 1262 } else { 1263 regmap_read(nau8825->regmap, 1264 NAU8825_REG_ADC_RATE, &osr); 1265 osr &= NAU8825_ADC_SYNC_DOWN_MASK; 1266 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1267 return NULL; 1268 return &osr_adc_sel[osr]; 1269 } 1270 } 1271 1272 static int nau8825_dai_startup(struct snd_pcm_substream *substream, 1273 struct snd_soc_dai *dai) 1274 { 1275 struct snd_soc_component *component = dai->component; 1276 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1277 const struct nau8825_osr_attr *osr; 1278 1279 osr = nau8825_get_osr(nau8825, substream->stream); 1280 if (!osr || !osr->osr) 1281 return -EINVAL; 1282 1283 return snd_pcm_hw_constraint_minmax(substream->runtime, 1284 SNDRV_PCM_HW_PARAM_RATE, 1285 0, CLK_DA_AD_MAX / osr->osr); 1286 } 1287 1288 static int nau8825_hw_params(struct snd_pcm_substream *substream, 1289 struct snd_pcm_hw_params *params, 1290 struct snd_soc_dai *dai) 1291 { 1292 struct snd_soc_component *component = dai->component; 1293 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1294 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div; 1295 const struct nau8825_osr_attr *osr; 1296 int err = -EINVAL; 1297 1298 nau8825_sema_acquire(nau8825, 3 * HZ); 1299 1300 /* CLK_DAC or CLK_ADC = OSR * FS 1301 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1302 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1303 * values must be selected such that the maximum frequency is less 1304 * than 6.144 MHz. 1305 */ 1306 osr = nau8825_get_osr(nau8825, substream->stream); 1307 if (!osr || !osr->osr) 1308 goto error; 1309 if (params_rate(params) * osr->osr > CLK_DA_AD_MAX) 1310 goto error; 1311 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1312 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1313 NAU8825_CLK_DAC_SRC_MASK, 1314 osr->clk_src << NAU8825_CLK_DAC_SRC_SFT); 1315 else 1316 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1317 NAU8825_CLK_ADC_SRC_MASK, 1318 osr->clk_src << NAU8825_CLK_ADC_SRC_SFT); 1319 1320 /* make BCLK and LRC divde configuration if the codec as master. */ 1321 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val); 1322 if (ctrl_val & NAU8825_I2S_MS_MASTER) { 1323 /* get the bclk and fs ratio */ 1324 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 1325 if (bclk_fs <= 32) 1326 bclk_div = 2; 1327 else if (bclk_fs <= 64) 1328 bclk_div = 1; 1329 else if (bclk_fs <= 128) 1330 bclk_div = 0; 1331 else 1332 goto error; 1333 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1334 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK, 1335 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div); 1336 } 1337 1338 switch (params_width(params)) { 1339 case 16: 1340 val_len |= NAU8825_I2S_DL_16; 1341 break; 1342 case 20: 1343 val_len |= NAU8825_I2S_DL_20; 1344 break; 1345 case 24: 1346 val_len |= NAU8825_I2S_DL_24; 1347 break; 1348 case 32: 1349 val_len |= NAU8825_I2S_DL_32; 1350 break; 1351 default: 1352 goto error; 1353 } 1354 1355 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1356 NAU8825_I2S_DL_MASK, val_len); 1357 err = 0; 1358 1359 error: 1360 /* Release the semaphore. */ 1361 nau8825_sema_release(nau8825); 1362 1363 return err; 1364 } 1365 1366 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1367 { 1368 struct snd_soc_component *component = codec_dai->component; 1369 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1370 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1371 1372 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1373 case SND_SOC_DAIFMT_CBM_CFM: 1374 ctrl2_val |= NAU8825_I2S_MS_MASTER; 1375 break; 1376 case SND_SOC_DAIFMT_CBS_CFS: 1377 break; 1378 default: 1379 return -EINVAL; 1380 } 1381 1382 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1383 case SND_SOC_DAIFMT_NB_NF: 1384 break; 1385 case SND_SOC_DAIFMT_IB_NF: 1386 ctrl1_val |= NAU8825_I2S_BP_INV; 1387 break; 1388 default: 1389 return -EINVAL; 1390 } 1391 1392 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1393 case SND_SOC_DAIFMT_I2S: 1394 ctrl1_val |= NAU8825_I2S_DF_I2S; 1395 break; 1396 case SND_SOC_DAIFMT_LEFT_J: 1397 ctrl1_val |= NAU8825_I2S_DF_LEFT; 1398 break; 1399 case SND_SOC_DAIFMT_RIGHT_J: 1400 ctrl1_val |= NAU8825_I2S_DF_RIGTH; 1401 break; 1402 case SND_SOC_DAIFMT_DSP_A: 1403 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1404 break; 1405 case SND_SOC_DAIFMT_DSP_B: 1406 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1407 ctrl1_val |= NAU8825_I2S_PCMB_EN; 1408 break; 1409 default: 1410 return -EINVAL; 1411 } 1412 1413 nau8825_sema_acquire(nau8825, 3 * HZ); 1414 1415 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1416 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | 1417 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, 1418 ctrl1_val); 1419 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1420 NAU8825_I2S_MS_MASK, ctrl2_val); 1421 1422 /* Release the semaphore. */ 1423 nau8825_sema_release(nau8825); 1424 1425 return 0; 1426 } 1427 1428 static const struct snd_soc_dai_ops nau8825_dai_ops = { 1429 .startup = nau8825_dai_startup, 1430 .hw_params = nau8825_hw_params, 1431 .set_fmt = nau8825_set_dai_fmt, 1432 }; 1433 1434 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 1435 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1436 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1437 1438 static struct snd_soc_dai_driver nau8825_dai = { 1439 .name = "nau8825-hifi", 1440 .playback = { 1441 .stream_name = "Playback", 1442 .channels_min = 1, 1443 .channels_max = 2, 1444 .rates = NAU8825_RATES, 1445 .formats = NAU8825_FORMATS, 1446 }, 1447 .capture = { 1448 .stream_name = "Capture", 1449 .channels_min = 1, 1450 .channels_max = 2, /* Only 1 channel of data */ 1451 .rates = NAU8825_RATES, 1452 .formats = NAU8825_FORMATS, 1453 }, 1454 .ops = &nau8825_dai_ops, 1455 }; 1456 1457 /** 1458 * nau8825_enable_jack_detect - Specify a jack for event reporting 1459 * 1460 * @component: component to register the jack with 1461 * @jack: jack to use to report headset and button events on 1462 * 1463 * After this function has been called the headset insert/remove and button 1464 * events will be routed to the given jack. Jack can be null to stop 1465 * reporting. 1466 */ 1467 int nau8825_enable_jack_detect(struct snd_soc_component *component, 1468 struct snd_soc_jack *jack) 1469 { 1470 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1471 struct regmap *regmap = nau8825->regmap; 1472 1473 nau8825->jack = jack; 1474 1475 if (!nau8825->jack) { 1476 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1477 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | 1478 NAU8825_SPKR_DWN1L, 0); 1479 return 0; 1480 } 1481 /* Ground HP Outputs[1:0], needed for headset auto detection 1482 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6] 1483 */ 1484 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1485 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 1486 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1487 1488 return 0; 1489 } 1490 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); 1491 1492 1493 static bool nau8825_is_jack_inserted(struct regmap *regmap) 1494 { 1495 bool active_high, is_high; 1496 int status, jkdet; 1497 1498 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet); 1499 active_high = jkdet & NAU8825_JACK_POLARITY; 1500 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); 1501 is_high = status & NAU8825_GPIO2JD1; 1502 /* return jack connection status according to jack insertion logic 1503 * active high or active low. 1504 */ 1505 return active_high == is_high; 1506 } 1507 1508 static void nau8825_restart_jack_detection(struct regmap *regmap) 1509 { 1510 /* this will restart the entire jack detection process including MIC/GND 1511 * switching and create interrupts. We have to go from 0 to 1 and back 1512 * to 0 to restart. 1513 */ 1514 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1515 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); 1516 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1517 NAU8825_JACK_DET_RESTART, 0); 1518 } 1519 1520 static void nau8825_int_status_clear_all(struct regmap *regmap) 1521 { 1522 int active_irq, clear_irq, i; 1523 1524 /* Reset the intrruption status from rightmost bit if the corres- 1525 * ponding irq event occurs. 1526 */ 1527 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); 1528 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) { 1529 clear_irq = (0x1 << i); 1530 if (active_irq & clear_irq) 1531 regmap_write(regmap, 1532 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1533 } 1534 } 1535 1536 static void nau8825_eject_jack(struct nau8825 *nau8825) 1537 { 1538 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1539 struct regmap *regmap = nau8825->regmap; 1540 1541 /* Force to cancel the cross talk detection process */ 1542 nau8825_xtalk_cancel(nau8825); 1543 1544 snd_soc_dapm_disable_pin(dapm, "SAR"); 1545 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1546 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 1547 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1548 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1549 /* ground HPL/HPR, MICGRND1/2 */ 1550 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); 1551 1552 snd_soc_dapm_sync(dapm); 1553 1554 /* Clear all interruption status */ 1555 nau8825_int_status_clear_all(regmap); 1556 1557 /* Enable the insertion interruption, disable the ejection inter- 1558 * ruption, and then bypass de-bounce circuit. 1559 */ 1560 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 1561 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS, 1562 NAU8825_IRQ_EJECT_DIS); 1563 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1564 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1565 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN, 1566 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1567 NAU8825_IRQ_HEADSET_COMPLETE_EN); 1568 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1569 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 1570 1571 /* Disable ADC needed for interruptions at audo mode */ 1572 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1573 NAU8825_ENABLE_ADC, 0); 1574 1575 /* Close clock for jack type detection at manual mode */ 1576 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1577 } 1578 1579 /* Enable audo mode interruptions with internal clock. */ 1580 static void nau8825_setup_auto_irq(struct nau8825 *nau8825) 1581 { 1582 struct regmap *regmap = nau8825->regmap; 1583 1584 /* Enable headset jack type detection complete interruption and 1585 * jack ejection interruption. 1586 */ 1587 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1588 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0); 1589 1590 /* Enable internal VCO needed for interruptions */ 1591 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 1592 1593 /* Enable ADC needed for interruptions */ 1594 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1595 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 1596 1597 /* Chip needs one FSCLK cycle in order to generate interruptions, 1598 * as we cannot guarantee one will be provided by the system. Turning 1599 * master mode on then off enables us to generate that FSCLK cycle 1600 * with a minimum of contention on the clock bus. 1601 */ 1602 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1603 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER); 1604 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1605 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); 1606 1607 /* Not bypass de-bounce circuit */ 1608 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1609 NAU8825_JACK_DET_DB_BYPASS, 0); 1610 1611 /* Unmask all interruptions */ 1612 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0); 1613 1614 /* Restart the jack detection process at auto mode */ 1615 nau8825_restart_jack_detection(regmap); 1616 } 1617 1618 static int nau8825_button_decode(int value) 1619 { 1620 int buttons = 0; 1621 1622 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */ 1623 if (value & BIT(0)) 1624 buttons |= SND_JACK_BTN_0; 1625 if (value & BIT(1)) 1626 buttons |= SND_JACK_BTN_1; 1627 if (value & BIT(2)) 1628 buttons |= SND_JACK_BTN_2; 1629 if (value & BIT(3)) 1630 buttons |= SND_JACK_BTN_3; 1631 if (value & BIT(4)) 1632 buttons |= SND_JACK_BTN_4; 1633 if (value & BIT(5)) 1634 buttons |= SND_JACK_BTN_5; 1635 1636 return buttons; 1637 } 1638 1639 static int nau8825_jack_insert(struct nau8825 *nau8825) 1640 { 1641 struct regmap *regmap = nau8825->regmap; 1642 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1643 int jack_status_reg, mic_detected; 1644 int type = 0; 1645 1646 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); 1647 mic_detected = (jack_status_reg >> 10) & 3; 1648 /* The JKSLV and JKR2 all detected in high impedance headset */ 1649 if (mic_detected == 0x3) 1650 nau8825->high_imped = true; 1651 else 1652 nau8825->high_imped = false; 1653 1654 switch (mic_detected) { 1655 case 0: 1656 /* no mic */ 1657 type = SND_JACK_HEADPHONE; 1658 break; 1659 case 1: 1660 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1661 type = SND_JACK_HEADSET; 1662 1663 /* Unground MICGND1 */ 1664 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1665 1 << 2); 1666 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1667 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1668 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1669 NAU8825_MICBIAS_JKR2); 1670 /* Attach SARADC to MICGND1 */ 1671 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1672 NAU8825_SAR_INPUT_MASK, 1673 NAU8825_SAR_INPUT_JKR2); 1674 1675 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1676 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1677 snd_soc_dapm_sync(dapm); 1678 break; 1679 case 2: 1680 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1681 type = SND_JACK_HEADSET; 1682 1683 /* Unground MICGND2 */ 1684 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1685 2 << 2); 1686 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1687 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1688 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1689 NAU8825_MICBIAS_JKSLV); 1690 /* Attach SARADC to MICGND2 */ 1691 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1692 NAU8825_SAR_INPUT_MASK, 1693 NAU8825_SAR_INPUT_JKSLV); 1694 1695 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1696 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1697 snd_soc_dapm_sync(dapm); 1698 break; 1699 case 3: 1700 /* detect error case */ 1701 dev_err(nau8825->dev, "detection error; disable mic function\n"); 1702 type = SND_JACK_HEADPHONE; 1703 break; 1704 } 1705 1706 /* Leaving HPOL/R grounded after jack insert by default. They will be 1707 * ungrounded as part of the widget power up sequence at the beginning 1708 * of playback to reduce pop. 1709 */ 1710 return type; 1711 } 1712 1713 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 1714 SND_JACK_BTN_2 | SND_JACK_BTN_3) 1715 1716 static irqreturn_t nau8825_interrupt(int irq, void *data) 1717 { 1718 struct nau8825 *nau8825 = (struct nau8825 *)data; 1719 struct regmap *regmap = nau8825->regmap; 1720 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1721 1722 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) { 1723 dev_err(nau8825->dev, "failed to read irq status\n"); 1724 return IRQ_NONE; 1725 } 1726 1727 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == 1728 NAU8825_JACK_EJECTION_DETECTED) { 1729 1730 nau8825_eject_jack(nau8825); 1731 event_mask |= SND_JACK_HEADSET; 1732 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; 1733 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { 1734 int key_status; 1735 1736 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, 1737 &key_status); 1738 1739 /* upper 8 bits of the register are for short pressed keys, 1740 * lower 8 bits - for long pressed buttons 1741 */ 1742 nau8825->button_pressed = nau8825_button_decode( 1743 key_status >> 8); 1744 1745 event |= nau8825->button_pressed; 1746 event_mask |= NAU8825_BUTTONS; 1747 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; 1748 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { 1749 event_mask = NAU8825_BUTTONS; 1750 clear_irq = NAU8825_KEY_RELEASE_IRQ; 1751 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { 1752 if (nau8825_is_jack_inserted(regmap)) { 1753 event |= nau8825_jack_insert(nau8825); 1754 if (nau8825->xtalk_enable && !nau8825->high_imped) { 1755 /* Apply the cross talk suppression in the 1756 * headset without high impedance. 1757 */ 1758 if (!nau8825->xtalk_protect) { 1759 /* Raise protection for cross talk de- 1760 * tection if no protection before. 1761 * The driver has to cancel the pro- 1762 * cess and restore changes if process 1763 * is ongoing when ejection. 1764 */ 1765 int ret; 1766 nau8825->xtalk_protect = true; 1767 ret = nau8825_sema_acquire(nau8825, 0); 1768 if (ret) 1769 nau8825->xtalk_protect = false; 1770 } 1771 /* Startup cross talk detection process */ 1772 if (nau8825->xtalk_protect) { 1773 nau8825->xtalk_state = 1774 NAU8825_XTALK_PREPARE; 1775 schedule_work(&nau8825->xtalk_work); 1776 } 1777 } else { 1778 /* The cross talk suppression shouldn't apply 1779 * in the headset with high impedance. Thus, 1780 * relieve the protection raised before. 1781 */ 1782 if (nau8825->xtalk_protect) { 1783 nau8825_sema_release(nau8825); 1784 nau8825->xtalk_protect = false; 1785 } 1786 } 1787 } else { 1788 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); 1789 nau8825_eject_jack(nau8825); 1790 } 1791 1792 event_mask |= SND_JACK_HEADSET; 1793 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; 1794 /* Record the interruption report event for driver to report 1795 * the event later. The jack report will delay until cross 1796 * talk detection process is done. 1797 */ 1798 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) { 1799 nau8825->xtalk_event = event; 1800 nau8825->xtalk_event_mask = event_mask; 1801 } 1802 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) { 1803 /* crosstalk detection enable and process on going */ 1804 if (nau8825->xtalk_enable && nau8825->xtalk_protect) 1805 schedule_work(&nau8825->xtalk_work); 1806 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ; 1807 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) == 1808 NAU8825_JACK_INSERTION_DETECTED) { 1809 /* One more step to check GPIO status directly. Thus, the 1810 * driver can confirm the real insertion interruption because 1811 * the intrruption at manual mode has bypassed debounce 1812 * circuit which can get rid of unstable status. 1813 */ 1814 if (nau8825_is_jack_inserted(regmap)) { 1815 /* Turn off insertion interruption at manual mode */ 1816 regmap_update_bits(regmap, 1817 NAU8825_REG_INTERRUPT_DIS_CTRL, 1818 NAU8825_IRQ_INSERT_DIS, 1819 NAU8825_IRQ_INSERT_DIS); 1820 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1821 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN); 1822 /* Enable interruption for jack type detection at audo 1823 * mode which can detect microphone and jack type. 1824 */ 1825 nau8825_setup_auto_irq(nau8825); 1826 } 1827 } 1828 1829 if (!clear_irq) 1830 clear_irq = active_irq; 1831 /* clears the rightmost interruption */ 1832 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1833 1834 /* Delay jack report until cross talk detection is done. It can avoid 1835 * application to do playback preparation when cross talk detection 1836 * process is still working. Otherwise, the resource like clock and 1837 * power will be issued by them at the same time and conflict happens. 1838 */ 1839 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE) 1840 snd_soc_jack_report(nau8825->jack, event, event_mask); 1841 1842 return IRQ_HANDLED; 1843 } 1844 1845 static void nau8825_setup_buttons(struct nau8825 *nau8825) 1846 { 1847 struct regmap *regmap = nau8825->regmap; 1848 1849 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1850 NAU8825_SAR_TRACKING_GAIN_MASK, 1851 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 1852 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1853 NAU8825_SAR_COMPARE_TIME_MASK, 1854 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT); 1855 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1856 NAU8825_SAR_SAMPLING_TIME_MASK, 1857 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT); 1858 1859 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1860 NAU8825_KEYDET_LEVELS_NR_MASK, 1861 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT); 1862 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1863 NAU8825_KEYDET_HYSTERESIS_MASK, 1864 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT); 1865 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 1866 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK, 1867 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT); 1868 1869 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, 1870 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]); 1871 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, 1872 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]); 1873 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3, 1874 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]); 1875 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4, 1876 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]); 1877 1878 /* Enable short press and release interruptions */ 1879 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1880 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN, 1881 0); 1882 } 1883 1884 static void nau8825_init_regs(struct nau8825 *nau8825) 1885 { 1886 struct regmap *regmap = nau8825->regmap; 1887 1888 /* Latch IIC LSB value */ 1889 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001); 1890 /* Enable Bias/Vmid */ 1891 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1892 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID); 1893 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 1894 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN); 1895 1896 /* VMID Tieoff */ 1897 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ, 1898 NAU8825_BIAS_VMID_SEL_MASK, 1899 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT); 1900 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1901 regmap_update_bits(regmap, NAU8825_REG_BOOST, 1902 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 1903 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN, 1904 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 1905 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN); 1906 1907 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1908 NAU8825_JKDET_OUTPUT_EN, 1909 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN); 1910 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1911 NAU8825_JKDET_PULL_EN, 1912 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN); 1913 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 1914 NAU8825_JKDET_PULL_UP, 1915 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0); 1916 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1917 NAU8825_JACK_POLARITY, 1918 /* jkdet_polarity - 1 is for active-low */ 1919 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY); 1920 1921 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1922 NAU8825_JACK_INSERT_DEBOUNCE_MASK, 1923 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT); 1924 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1925 NAU8825_JACK_EJECT_DEBOUNCE_MASK, 1926 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT); 1927 1928 /* Pull up IRQ pin */ 1929 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1930 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN, 1931 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN); 1932 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1933 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff); 1934 1935 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1936 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 1937 1938 if (nau8825->sar_threshold_num) 1939 nau8825_setup_buttons(nau8825); 1940 1941 /* Default oversampling/decimations settings are unusable 1942 * (audible hiss). Set it to something better. 1943 */ 1944 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, 1945 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, 1946 NAU8825_ADC_SYNC_DOWN_64); 1947 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 1948 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); 1949 /* Disable DACR/L power */ 1950 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 1951 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 1952 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 1953 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1954 * signal to avoid any glitches due to power up transients in both 1955 * the analog and digital DAC circuit. 1956 */ 1957 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1958 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 1959 /* CICCLP off */ 1960 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 1961 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF); 1962 1963 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1964 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2, 1965 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 1966 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB, 1967 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 1968 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB); 1969 /* Class G timer 64ms */ 1970 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL, 1971 NAU8825_CLASSG_TIMER_MASK, 1972 0x20 << NAU8825_CLASSG_TIMER_SFT); 1973 /* DAC clock delay 2ns, VREF */ 1974 regmap_update_bits(regmap, NAU8825_REG_RDAC, 1975 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, 1976 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | 1977 (0x3 << NAU8825_RDAC_VREF_SFT)); 1978 /* Config L/R channel */ 1979 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 1980 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); 1981 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 1982 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); 1983 /* Disable short Frame Sync detection logic */ 1984 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, 1985 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); 1986 /* ADCDAT IO drive strength control */ 1987 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 1988 NAU8825_ADCOUT_DS_MASK, 1989 nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT); 1990 } 1991 1992 static const struct regmap_config nau8825_regmap_config = { 1993 .val_bits = NAU8825_REG_DATA_LEN, 1994 .reg_bits = NAU8825_REG_ADDR_LEN, 1995 1996 .max_register = NAU8825_REG_MAX, 1997 .readable_reg = nau8825_readable_reg, 1998 .writeable_reg = nau8825_writeable_reg, 1999 .volatile_reg = nau8825_volatile_reg, 2000 2001 .cache_type = REGCACHE_RBTREE, 2002 .reg_defaults = nau8825_reg_defaults, 2003 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), 2004 }; 2005 2006 static int nau8825_component_probe(struct snd_soc_component *component) 2007 { 2008 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2009 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2010 2011 nau8825->dapm = dapm; 2012 2013 return 0; 2014 } 2015 2016 static void nau8825_component_remove(struct snd_soc_component *component) 2017 { 2018 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2019 2020 /* Cancel and reset cross tak suppresstion detection funciton */ 2021 nau8825_xtalk_cancel(nau8825); 2022 } 2023 2024 /** 2025 * nau8825_calc_fll_param - Calculate FLL parameters. 2026 * @fll_in: external clock provided to codec. 2027 * @fs: sampling rate. 2028 * @fll_param: Pointer to structure of FLL parameters. 2029 * 2030 * Calculate FLL parameters to configure codec. 2031 * 2032 * Returns 0 for success or negative error code. 2033 */ 2034 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs, 2035 struct nau8825_fll *fll_param) 2036 { 2037 u64 fvco, fvco_max; 2038 unsigned int fref, i, fvco_sel; 2039 2040 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 2041 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 2042 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK 2043 */ 2044 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 2045 fref = fll_in / fll_pre_scalar[i].param; 2046 if (fref <= NAU_FREF_MAX) 2047 break; 2048 } 2049 if (i == ARRAY_SIZE(fll_pre_scalar)) 2050 return -EINVAL; 2051 fll_param->clk_ref_div = fll_pre_scalar[i].val; 2052 2053 /* Choose the FLL ratio based on FREF */ 2054 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 2055 if (fref >= fll_ratio[i].param) 2056 break; 2057 } 2058 if (i == ARRAY_SIZE(fll_ratio)) 2059 return -EINVAL; 2060 fll_param->ratio = fll_ratio[i].val; 2061 2062 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 2063 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 2064 * guaranteed across the full range of operation. 2065 * FDCO = freq_out * 2 * mclk_src_scaling 2066 */ 2067 fvco_max = 0; 2068 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 2069 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 2070 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 2071 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 2072 fvco_max < fvco) { 2073 fvco_max = fvco; 2074 fvco_sel = i; 2075 } 2076 } 2077 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 2078 return -EINVAL; 2079 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 2080 2081 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 2082 * input based on FDCO, FREF and FLL ratio. 2083 */ 2084 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 2085 fll_param->fll_int = (fvco >> 16) & 0x3FF; 2086 fll_param->fll_frac = fvco & 0xFFFF; 2087 return 0; 2088 } 2089 2090 static void nau8825_fll_apply(struct nau8825 *nau8825, 2091 struct nau8825_fll *fll_param) 2092 { 2093 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2094 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, 2095 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); 2096 /* Make DSP operate at high speed for better performance. */ 2097 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 2098 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, 2099 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); 2100 /* FLL 16-bit fractional input */ 2101 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac); 2102 /* FLL 10-bit integer input */ 2103 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3, 2104 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int); 2105 /* FLL pre-scaler */ 2106 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4, 2107 NAU8825_FLL_REF_DIV_MASK, 2108 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT); 2109 /* select divided VCO input */ 2110 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2111 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF); 2112 /* Disable free-running mode */ 2113 regmap_update_bits(nau8825->regmap, 2114 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); 2115 if (fll_param->fll_frac) { 2116 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 2117 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2118 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2119 NAU8825_FLL_FTR_SW_MASK, 2120 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2121 NAU8825_FLL_FTR_SW_FILTER); 2122 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2123 NAU8825_SDM_EN | NAU8825_CUTOFF500, 2124 NAU8825_SDM_EN | NAU8825_CUTOFF500); 2125 } else { 2126 /* disable FLL loop filter and cutoff frequency */ 2127 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2128 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2129 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); 2130 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2131 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); 2132 } 2133 } 2134 2135 /* freq_out must be 256*Fs in order to achieve the best performance */ 2136 static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source, 2137 unsigned int freq_in, unsigned int freq_out) 2138 { 2139 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2140 struct nau8825_fll fll_param; 2141 int ret, fs; 2142 2143 fs = freq_out / 256; 2144 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param); 2145 if (ret < 0) { 2146 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2147 return ret; 2148 } 2149 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 2150 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 2151 fll_param.fll_int, fll_param.clk_ref_div); 2152 2153 nau8825_fll_apply(nau8825, &fll_param); 2154 mdelay(2); 2155 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2156 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2157 return 0; 2158 } 2159 2160 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq) 2161 { 2162 int ret; 2163 2164 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk"); 2165 if (IS_ERR(nau8825->mclk)) { 2166 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2167 return 0; 2168 } 2169 2170 if (!nau8825->mclk_freq) { 2171 ret = clk_prepare_enable(nau8825->mclk); 2172 if (ret) { 2173 dev_err(nau8825->dev, "Unable to prepare codec mclk\n"); 2174 return ret; 2175 } 2176 } 2177 2178 if (nau8825->mclk_freq != freq) { 2179 freq = clk_round_rate(nau8825->mclk, freq); 2180 ret = clk_set_rate(nau8825->mclk, freq); 2181 if (ret) { 2182 dev_err(nau8825->dev, "Unable to set mclk rate\n"); 2183 return ret; 2184 } 2185 nau8825->mclk_freq = freq; 2186 } 2187 2188 return 0; 2189 } 2190 2191 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) 2192 { 2193 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2194 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); 2195 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2196 NAU8825_DCO_EN, 0); 2197 /* Make DSP operate as default setting for power saving. */ 2198 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2199 NAU8825_ICTRL_LATCH_MASK, 0); 2200 } 2201 2202 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, 2203 unsigned int freq) 2204 { 2205 struct regmap *regmap = nau8825->regmap; 2206 int ret; 2207 2208 switch (clk_id) { 2209 case NAU8825_CLK_DIS: 2210 /* Clock provided externally and disable internal VCO clock */ 2211 nau8825_configure_mclk_as_sysclk(regmap); 2212 if (nau8825->mclk_freq) { 2213 clk_disable_unprepare(nau8825->mclk); 2214 nau8825->mclk_freq = 0; 2215 } 2216 2217 break; 2218 case NAU8825_CLK_MCLK: 2219 /* Acquire the semaphore to synchronize the playback and 2220 * interrupt handler. In order to avoid the playback inter- 2221 * fered by cross talk process, the driver make the playback 2222 * preparation halted until cross talk process finish. 2223 */ 2224 nau8825_sema_acquire(nau8825, 3 * HZ); 2225 nau8825_configure_mclk_as_sysclk(regmap); 2226 /* MCLK not changed by clock tree */ 2227 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2228 NAU8825_CLK_MCLK_SRC_MASK, 0); 2229 /* Release the semaphore. */ 2230 nau8825_sema_release(nau8825); 2231 2232 ret = nau8825_mclk_prepare(nau8825, freq); 2233 if (ret) 2234 return ret; 2235 2236 break; 2237 case NAU8825_CLK_INTERNAL: 2238 if (nau8825_is_jack_inserted(nau8825->regmap)) { 2239 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2240 NAU8825_DCO_EN, NAU8825_DCO_EN); 2241 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2242 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2243 /* Decrease the VCO frequency and make DSP operate 2244 * as default setting for power saving. 2245 */ 2246 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2247 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2248 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2249 NAU8825_ICTRL_LATCH_MASK | 2250 NAU8825_FLL_RATIO_MASK, 0x10); 2251 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2252 NAU8825_SDM_EN, NAU8825_SDM_EN); 2253 } else { 2254 /* The clock turns off intentionally for power saving 2255 * when no headset connected. 2256 */ 2257 nau8825_configure_mclk_as_sysclk(regmap); 2258 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n"); 2259 } 2260 if (nau8825->mclk_freq) { 2261 clk_disable_unprepare(nau8825->mclk); 2262 nau8825->mclk_freq = 0; 2263 } 2264 2265 break; 2266 case NAU8825_CLK_FLL_MCLK: 2267 /* Acquire the semaphore to synchronize the playback and 2268 * interrupt handler. In order to avoid the playback inter- 2269 * fered by cross talk process, the driver make the playback 2270 * preparation halted until cross talk process finish. 2271 */ 2272 nau8825_sema_acquire(nau8825, 3 * HZ); 2273 /* Higher FLL reference input frequency can only set lower 2274 * gain error, such as 0000 for input reference from MCLK 2275 * 12.288Mhz. 2276 */ 2277 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2278 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2279 NAU8825_FLL_CLK_SRC_MCLK | 0); 2280 /* Release the semaphore. */ 2281 nau8825_sema_release(nau8825); 2282 2283 ret = nau8825_mclk_prepare(nau8825, freq); 2284 if (ret) 2285 return ret; 2286 2287 break; 2288 case NAU8825_CLK_FLL_BLK: 2289 /* Acquire the semaphore to synchronize the playback and 2290 * interrupt handler. In order to avoid the playback inter- 2291 * fered by cross talk process, the driver make the playback 2292 * preparation halted until cross talk process finish. 2293 */ 2294 nau8825_sema_acquire(nau8825, 3 * HZ); 2295 /* If FLL reference input is from low frequency source, 2296 * higher error gain can apply such as 0xf which has 2297 * the most sensitive gain error correction threshold, 2298 * Therefore, FLL has the most accurate DCO to 2299 * target frequency. 2300 */ 2301 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2302 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2303 NAU8825_FLL_CLK_SRC_BLK | 2304 (0xf << NAU8825_GAIN_ERR_SFT)); 2305 /* Release the semaphore. */ 2306 nau8825_sema_release(nau8825); 2307 2308 if (nau8825->mclk_freq) { 2309 clk_disable_unprepare(nau8825->mclk); 2310 nau8825->mclk_freq = 0; 2311 } 2312 2313 break; 2314 case NAU8825_CLK_FLL_FS: 2315 /* Acquire the semaphore to synchronize the playback and 2316 * interrupt handler. In order to avoid the playback inter- 2317 * fered by cross talk process, the driver make the playback 2318 * preparation halted until cross talk process finish. 2319 */ 2320 nau8825_sema_acquire(nau8825, 3 * HZ); 2321 /* If FLL reference input is from low frequency source, 2322 * higher error gain can apply such as 0xf which has 2323 * the most sensitive gain error correction threshold, 2324 * Therefore, FLL has the most accurate DCO to 2325 * target frequency. 2326 */ 2327 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2328 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2329 NAU8825_FLL_CLK_SRC_FS | 2330 (0xf << NAU8825_GAIN_ERR_SFT)); 2331 /* Release the semaphore. */ 2332 nau8825_sema_release(nau8825); 2333 2334 if (nau8825->mclk_freq) { 2335 clk_disable_unprepare(nau8825->mclk); 2336 nau8825->mclk_freq = 0; 2337 } 2338 2339 break; 2340 default: 2341 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id); 2342 return -EINVAL; 2343 } 2344 2345 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq, 2346 clk_id); 2347 return 0; 2348 } 2349 2350 static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id, 2351 int source, unsigned int freq, int dir) 2352 { 2353 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2354 2355 return nau8825_configure_sysclk(nau8825, clk_id, freq); 2356 } 2357 2358 static int nau8825_resume_setup(struct nau8825 *nau8825) 2359 { 2360 struct regmap *regmap = nau8825->regmap; 2361 2362 /* Close clock when jack type detection at manual mode */ 2363 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 2364 2365 /* Clear all interruption status */ 2366 nau8825_int_status_clear_all(regmap); 2367 2368 /* Enable both insertion and ejection interruptions, and then 2369 * bypass de-bounce circuit. 2370 */ 2371 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2372 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN | 2373 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN, 2374 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN); 2375 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2376 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 2377 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 2378 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0); 2379 2380 return 0; 2381 } 2382 2383 static int nau8825_set_bias_level(struct snd_soc_component *component, 2384 enum snd_soc_bias_level level) 2385 { 2386 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2387 int ret; 2388 2389 switch (level) { 2390 case SND_SOC_BIAS_ON: 2391 break; 2392 2393 case SND_SOC_BIAS_PREPARE: 2394 break; 2395 2396 case SND_SOC_BIAS_STANDBY: 2397 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2398 if (nau8825->mclk_freq) { 2399 ret = clk_prepare_enable(nau8825->mclk); 2400 if (ret) { 2401 dev_err(nau8825->dev, "Unable to prepare component mclk\n"); 2402 return ret; 2403 } 2404 } 2405 /* Setup codec configuration after resume */ 2406 nau8825_resume_setup(nau8825); 2407 } 2408 break; 2409 2410 case SND_SOC_BIAS_OFF: 2411 /* Reset the configuration of jack type for detection */ 2412 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 2413 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS, 2414 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 2415 /* ground HPL/HPR, MICGRND1/2 */ 2416 regmap_update_bits(nau8825->regmap, 2417 NAU8825_REG_HSD_CTRL, 0xf, 0xf); 2418 /* Cancel and reset cross talk detection funciton */ 2419 nau8825_xtalk_cancel(nau8825); 2420 /* Turn off all interruptions before system shutdown. Keep the 2421 * interruption quiet before resume setup completes. 2422 */ 2423 regmap_write(nau8825->regmap, 2424 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff); 2425 /* Disable ADC needed for interruptions at audo mode */ 2426 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 2427 NAU8825_ENABLE_ADC, 0); 2428 if (nau8825->mclk_freq) 2429 clk_disable_unprepare(nau8825->mclk); 2430 break; 2431 } 2432 return 0; 2433 } 2434 2435 static int __maybe_unused nau8825_suspend(struct snd_soc_component *component) 2436 { 2437 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2438 2439 disable_irq(nau8825->irq); 2440 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 2441 /* Power down codec power; don't suppoet button wakeup */ 2442 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR"); 2443 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS"); 2444 snd_soc_dapm_sync(nau8825->dapm); 2445 regcache_cache_only(nau8825->regmap, true); 2446 regcache_mark_dirty(nau8825->regmap); 2447 2448 return 0; 2449 } 2450 2451 static int __maybe_unused nau8825_resume(struct snd_soc_component *component) 2452 { 2453 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2454 int ret; 2455 2456 regcache_cache_only(nau8825->regmap, false); 2457 regcache_sync(nau8825->regmap); 2458 nau8825->xtalk_protect = true; 2459 ret = nau8825_sema_acquire(nau8825, 0); 2460 if (ret) 2461 nau8825->xtalk_protect = false; 2462 enable_irq(nau8825->irq); 2463 2464 return 0; 2465 } 2466 2467 static int nau8825_set_jack(struct snd_soc_component *component, 2468 struct snd_soc_jack *jack, void *data) 2469 { 2470 return nau8825_enable_jack_detect(component, jack); 2471 } 2472 2473 static const struct snd_soc_component_driver nau8825_component_driver = { 2474 .probe = nau8825_component_probe, 2475 .remove = nau8825_component_remove, 2476 .set_sysclk = nau8825_set_sysclk, 2477 .set_pll = nau8825_set_pll, 2478 .set_bias_level = nau8825_set_bias_level, 2479 .suspend = nau8825_suspend, 2480 .resume = nau8825_resume, 2481 .controls = nau8825_controls, 2482 .num_controls = ARRAY_SIZE(nau8825_controls), 2483 .dapm_widgets = nau8825_dapm_widgets, 2484 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), 2485 .dapm_routes = nau8825_dapm_routes, 2486 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), 2487 .set_jack = nau8825_set_jack, 2488 .suspend_bias_off = 1, 2489 .idle_bias_on = 1, 2490 .use_pmdown_time = 1, 2491 .endianness = 1, 2492 }; 2493 2494 static void nau8825_reset_chip(struct regmap *regmap) 2495 { 2496 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2497 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2498 } 2499 2500 static void nau8825_print_device_properties(struct nau8825 *nau8825) 2501 { 2502 int i; 2503 struct device *dev = nau8825->dev; 2504 2505 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable); 2506 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable); 2507 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up); 2508 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity); 2509 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage); 2510 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance); 2511 2512 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num); 2513 for (i = 0; i < nau8825->sar_threshold_num; i++) 2514 dev_dbg(dev, "sar-threshold[%d]=%d\n", i, 2515 nau8825->sar_threshold[i]); 2516 2517 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis); 2518 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage); 2519 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time); 2520 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time); 2521 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce); 2522 dev_dbg(dev, "jack-insert-debounce: %d\n", 2523 nau8825->jack_insert_debounce); 2524 dev_dbg(dev, "jack-eject-debounce: %d\n", 2525 nau8825->jack_eject_debounce); 2526 dev_dbg(dev, "crosstalk-enable: %d\n", 2527 nau8825->xtalk_enable); 2528 dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds); 2529 } 2530 2531 static int nau8825_read_device_properties(struct device *dev, 2532 struct nau8825 *nau8825) { 2533 int ret; 2534 2535 nau8825->jkdet_enable = device_property_read_bool(dev, 2536 "nuvoton,jkdet-enable"); 2537 nau8825->jkdet_pull_enable = device_property_read_bool(dev, 2538 "nuvoton,jkdet-pull-enable"); 2539 nau8825->jkdet_pull_up = device_property_read_bool(dev, 2540 "nuvoton,jkdet-pull-up"); 2541 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 2542 &nau8825->jkdet_polarity); 2543 if (ret) 2544 nau8825->jkdet_polarity = 1; 2545 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 2546 &nau8825->micbias_voltage); 2547 if (ret) 2548 nau8825->micbias_voltage = 6; 2549 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 2550 &nau8825->vref_impedance); 2551 if (ret) 2552 nau8825->vref_impedance = 2; 2553 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 2554 &nau8825->sar_threshold_num); 2555 if (ret) 2556 nau8825->sar_threshold_num = 4; 2557 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 2558 nau8825->sar_threshold, nau8825->sar_threshold_num); 2559 if (ret) { 2560 nau8825->sar_threshold[0] = 0x08; 2561 nau8825->sar_threshold[1] = 0x12; 2562 nau8825->sar_threshold[2] = 0x26; 2563 nau8825->sar_threshold[3] = 0x73; 2564 } 2565 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 2566 &nau8825->sar_hysteresis); 2567 if (ret) 2568 nau8825->sar_hysteresis = 0; 2569 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 2570 &nau8825->sar_voltage); 2571 if (ret) 2572 nau8825->sar_voltage = 6; 2573 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 2574 &nau8825->sar_compare_time); 2575 if (ret) 2576 nau8825->sar_compare_time = 1; 2577 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 2578 &nau8825->sar_sampling_time); 2579 if (ret) 2580 nau8825->sar_sampling_time = 1; 2581 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 2582 &nau8825->key_debounce); 2583 if (ret) 2584 nau8825->key_debounce = 3; 2585 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 2586 &nau8825->jack_insert_debounce); 2587 if (ret) 2588 nau8825->jack_insert_debounce = 7; 2589 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 2590 &nau8825->jack_eject_debounce); 2591 if (ret) 2592 nau8825->jack_eject_debounce = 0; 2593 nau8825->xtalk_enable = device_property_read_bool(dev, 2594 "nuvoton,crosstalk-enable"); 2595 nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong"); 2596 2597 nau8825->mclk = devm_clk_get(dev, "mclk"); 2598 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) { 2599 return -EPROBE_DEFER; 2600 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) { 2601 /* The MCLK is managed externally or not used at all */ 2602 nau8825->mclk = NULL; 2603 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2604 } else if (IS_ERR(nau8825->mclk)) { 2605 return -EINVAL; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int nau8825_setup_irq(struct nau8825 *nau8825) 2612 { 2613 int ret; 2614 2615 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL, 2616 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 2617 "nau8825", nau8825); 2618 2619 if (ret) { 2620 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n", 2621 nau8825->irq, ret); 2622 return ret; 2623 } 2624 2625 return 0; 2626 } 2627 2628 static int nau8825_i2c_probe(struct i2c_client *i2c) 2629 { 2630 struct device *dev = &i2c->dev; 2631 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev); 2632 int ret, value; 2633 2634 if (!nau8825) { 2635 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); 2636 if (!nau8825) 2637 return -ENOMEM; 2638 ret = nau8825_read_device_properties(dev, nau8825); 2639 if (ret) 2640 return ret; 2641 } 2642 2643 i2c_set_clientdata(i2c, nau8825); 2644 2645 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); 2646 if (IS_ERR(nau8825->regmap)) 2647 return PTR_ERR(nau8825->regmap); 2648 nau8825->dev = dev; 2649 nau8825->irq = i2c->irq; 2650 /* Initiate parameters, semaphore and work queue which are needed in 2651 * cross talk suppression measurment function. 2652 */ 2653 nau8825->xtalk_state = NAU8825_XTALK_DONE; 2654 nau8825->xtalk_protect = false; 2655 nau8825->xtalk_baktab_initialized = false; 2656 sema_init(&nau8825->xtalk_sem, 1); 2657 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work); 2658 2659 nau8825_print_device_properties(nau8825); 2660 2661 nau8825_reset_chip(nau8825->regmap); 2662 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); 2663 if (ret < 0) { 2664 dev_err(dev, "Failed to read device id from the NAU8825: %d\n", 2665 ret); 2666 return ret; 2667 } 2668 if ((value & NAU8825_SOFTWARE_ID_MASK) != 2669 NAU8825_SOFTWARE_ID_NAU8825) { 2670 dev_err(dev, "Not a NAU8825 chip\n"); 2671 return -ENODEV; 2672 } 2673 2674 nau8825_init_regs(nau8825); 2675 2676 if (i2c->irq) 2677 nau8825_setup_irq(nau8825); 2678 2679 return devm_snd_soc_register_component(&i2c->dev, 2680 &nau8825_component_driver, 2681 &nau8825_dai, 1); 2682 } 2683 2684 static int nau8825_i2c_remove(struct i2c_client *client) 2685 { 2686 return 0; 2687 } 2688 2689 static const struct i2c_device_id nau8825_i2c_ids[] = { 2690 { "nau8825", 0 }, 2691 { } 2692 }; 2693 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); 2694 2695 #ifdef CONFIG_OF 2696 static const struct of_device_id nau8825_of_ids[] = { 2697 { .compatible = "nuvoton,nau8825", }, 2698 {} 2699 }; 2700 MODULE_DEVICE_TABLE(of, nau8825_of_ids); 2701 #endif 2702 2703 #ifdef CONFIG_ACPI 2704 static const struct acpi_device_id nau8825_acpi_match[] = { 2705 { "10508825", 0 }, 2706 {}, 2707 }; 2708 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); 2709 #endif 2710 2711 static struct i2c_driver nau8825_driver = { 2712 .driver = { 2713 .name = "nau8825", 2714 .of_match_table = of_match_ptr(nau8825_of_ids), 2715 .acpi_match_table = ACPI_PTR(nau8825_acpi_match), 2716 }, 2717 .probe_new = nau8825_i2c_probe, 2718 .remove = nau8825_i2c_remove, 2719 .id_table = nau8825_i2c_ids, 2720 }; 2721 module_i2c_driver(nau8825_driver); 2722 2723 MODULE_DESCRIPTION("ASoC nau8825 driver"); 2724 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>"); 2725 MODULE_LICENSE("GPL"); 2726