1 /* 2 * NAU88L24 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/clk.h> 19 #include <linux/acpi.h> 20 #include <linux/math64.h> 21 #include <linux/semaphore.h> 22 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 31 #include "nau8824.h" 32 33 34 static int nau8824_config_sysclk(struct nau8824 *nau8824, 35 int clk_id, unsigned int freq); 36 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); 37 38 /* the ADC threshold of headset */ 39 #define DMIC_CLK 3072000 40 41 /* the ADC threshold of headset */ 42 #define HEADSET_SARADC_THD 0x80 43 44 /* the parameter threshold of FLL */ 45 #define NAU_FREF_MAX 13500000 46 #define NAU_FVCO_MAX 124000000 47 #define NAU_FVCO_MIN 90000000 48 49 /* scaling for mclk from sysclk_src output */ 50 static const struct nau8824_fll_attr mclk_src_scaling[] = { 51 { 1, 0x0 }, 52 { 2, 0x2 }, 53 { 4, 0x3 }, 54 { 8, 0x4 }, 55 { 16, 0x5 }, 56 { 32, 0x6 }, 57 { 3, 0x7 }, 58 { 6, 0xa }, 59 { 12, 0xb }, 60 { 24, 0xc }, 61 }; 62 63 /* ratio for input clk freq */ 64 static const struct nau8824_fll_attr fll_ratio[] = { 65 { 512000, 0x01 }, 66 { 256000, 0x02 }, 67 { 128000, 0x04 }, 68 { 64000, 0x08 }, 69 { 32000, 0x10 }, 70 { 8000, 0x20 }, 71 { 4000, 0x40 }, 72 }; 73 74 static const struct nau8824_fll_attr fll_pre_scalar[] = { 75 { 1, 0x0 }, 76 { 2, 0x1 }, 77 { 4, 0x2 }, 78 { 8, 0x3 }, 79 }; 80 81 /* the maximum frequency of CLK_ADC and CLK_DAC */ 82 #define CLK_DA_AD_MAX 6144000 83 84 /* over sampling rate */ 85 static const struct nau8824_osr_attr osr_dac_sel[] = { 86 { 64, 2 }, /* OSR 64, SRC 1/4 */ 87 { 256, 0 }, /* OSR 256, SRC 1 */ 88 { 128, 1 }, /* OSR 128, SRC 1/2 */ 89 { 0, 0 }, 90 { 32, 3 }, /* OSR 32, SRC 1/8 */ 91 }; 92 93 static const struct nau8824_osr_attr osr_adc_sel[] = { 94 { 32, 3 }, /* OSR 32, SRC 1/8 */ 95 { 64, 2 }, /* OSR 64, SRC 1/4 */ 96 { 128, 1 }, /* OSR 128, SRC 1/2 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 }; 99 100 static const struct reg_default nau8824_reg_defaults[] = { 101 { NAU8824_REG_ENA_CTRL, 0x0000 }, 102 { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, 103 { NAU8824_REG_CLK_DIVIDER, 0x0000 }, 104 { NAU8824_REG_FLL1, 0x0000 }, 105 { NAU8824_REG_FLL2, 0x3126 }, 106 { NAU8824_REG_FLL3, 0x0008 }, 107 { NAU8824_REG_FLL4, 0x0010 }, 108 { NAU8824_REG_FLL5, 0xC000 }, 109 { NAU8824_REG_FLL6, 0x6000 }, 110 { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, 111 { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, 112 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, 113 { NAU8824_REG_IRQ, 0x0000 }, 114 { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, 115 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, 116 { NAU8824_REG_SAR_ADC, 0x0015 }, 117 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, 118 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, 119 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, 120 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, 121 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, 122 { NAU8824_REG_GPIO_SEL, 0x0000 }, 123 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, 124 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, 125 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, 126 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, 127 { NAU8824_REG_TDM_CTRL, 0x0000 }, 128 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, 129 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, 130 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, 131 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, 132 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, 133 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, 134 { NAU8824_REG_EQ1_LOW, 0x112C }, 135 { NAU8824_REG_EQ2_EQ3, 0x2C2C }, 136 { NAU8824_REG_EQ4_EQ5, 0x2C2C }, 137 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, 138 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, 139 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, 140 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, 141 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, 142 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, 143 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, 144 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, 145 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, 146 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, 147 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, 148 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, 149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, 150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, 151 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, 152 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, 153 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, 154 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, 155 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, 156 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, 157 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, 158 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, 159 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, 160 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, 161 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, 162 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, 163 { NAU8824_REG_MODE, 0x0000 }, 164 { NAU8824_REG_MODE1, 0x0000 }, 165 { NAU8824_REG_MODE2, 0x0000 }, 166 { NAU8824_REG_CLASSG, 0x0000 }, 167 { NAU8824_REG_OTP_EFUSE, 0x0000 }, 168 { NAU8824_REG_OTPDOUT_1, 0x0000 }, 169 { NAU8824_REG_OTPDOUT_2, 0x0000 }, 170 { NAU8824_REG_MISC_CTRL, 0x0000 }, 171 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, 172 { NAU8824_REG_TEST_MODE, 0x0000 }, 173 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, 174 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, 175 { NAU8824_REG_BIAS_ADJ, 0x0000 }, 176 { NAU8824_REG_PGA_GAIN, 0x0000 }, 177 { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, 178 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, 179 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, 180 { NAU8824_REG_ENABLE_LO, 0x0000 }, 181 { NAU8824_REG_GAIN_LO, 0x0000 }, 182 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, 183 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, 184 { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, 185 { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, 186 { NAU8824_REG_RDAC, 0x0008 }, 187 { NAU8824_REG_MIC_BIAS, 0x0006 }, 188 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, 189 { NAU8824_REG_BOOST, 0x0000 }, 190 { NAU8824_REG_FEPGA, 0x0000 }, 191 { NAU8824_REG_FEPGA_II, 0x0000 }, 192 { NAU8824_REG_FEPGA_SE, 0x0000 }, 193 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, 194 { NAU8824_REG_ATT_PORT0, 0x0000 }, 195 { NAU8824_REG_ATT_PORT1, 0x0000 }, 196 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, 197 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, 198 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, 199 }; 200 201 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) 202 { 203 int ret; 204 205 if (timeout) { 206 ret = down_timeout(&nau8824->jd_sem, timeout); 207 if (ret < 0) 208 dev_warn(nau8824->dev, "Acquire semaphone timeout\n"); 209 } else { 210 ret = down_interruptible(&nau8824->jd_sem); 211 if (ret < 0) 212 dev_warn(nau8824->dev, "Acquire semaphone fail\n"); 213 } 214 215 return ret; 216 } 217 218 static inline void nau8824_sema_release(struct nau8824 *nau8824) 219 { 220 up(&nau8824->jd_sem); 221 } 222 223 static bool nau8824_readable_reg(struct device *dev, unsigned int reg) 224 { 225 switch (reg) { 226 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: 227 case NAU8824_REG_JACK_DET_CTRL: 228 case NAU8824_REG_INTERRUPT_SETTING_1: 229 case NAU8824_REG_IRQ: 230 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 231 case NAU8824_REG_GPIO_SEL: 232 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 233 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 234 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 235 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: 236 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: 237 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 238 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 239 case NAU8824_REG_I2C_TIMEOUT: 240 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 241 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 242 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 243 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: 244 return true; 245 default: 246 return false; 247 } 248 249 } 250 251 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: 255 case NAU8824_REG_JACK_DET_CTRL: 256 case NAU8824_REG_INTERRUPT_SETTING_1: 257 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 258 case NAU8824_REG_GPIO_SEL: 259 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 260 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 261 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 262 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: 263 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: 264 case NAU8824_REG_DRC_SLOPE_ADC_CH01: 265 case NAU8824_REG_DRC_ATKDCY_ADC_CH01: 266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: 267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: 268 case NAU8824_REG_DRC_SLOPE_ADC_CH23: 269 case NAU8824_REG_DRC_ATKDCY_ADC_CH23: 270 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: 271 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 272 case NAU8824_REG_I2C_TIMEOUT: 273 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 274 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 275 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case NAU8824_REG_RESET: 286 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: 287 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: 288 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: 289 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 290 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 291 case NAU8824_REG_CHARGE_PUMP_INPUT: 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static const char * const nau8824_companding[] = { 299 "Off", "NC", "u-law", "A-law" }; 300 301 static const struct soc_enum nau8824_companding_adc_enum = 302 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, 303 ARRAY_SIZE(nau8824_companding), nau8824_companding); 304 305 static const struct soc_enum nau8824_companding_dac_enum = 306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, 307 ARRAY_SIZE(nau8824_companding), nau8824_companding); 308 309 static const char * const nau8824_adc_decimation[] = { 310 "32", "64", "128", "256" }; 311 312 static const struct soc_enum nau8824_adc_decimation_enum = 313 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, 314 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); 315 316 static const char * const nau8824_dac_oversampl[] = { 317 "64", "256", "128", "", "32" }; 318 319 static const struct soc_enum nau8824_dac_oversampl_enum = 320 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, 321 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); 322 323 static const char * const nau8824_input_channel[] = { 324 "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; 325 326 static const struct soc_enum nau8824_adc_ch0_enum = 327 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, 328 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 329 330 static const struct soc_enum nau8824_adc_ch1_enum = 331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, 332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 333 334 static const struct soc_enum nau8824_adc_ch2_enum = 335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, 336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 337 338 static const struct soc_enum nau8824_adc_ch3_enum = 339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, 340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 341 342 static const char * const nau8824_tdm_slot[] = { 343 "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; 344 345 static const struct soc_enum nau8824_dac_left_sel_enum = 346 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, 347 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 348 349 static const struct soc_enum nau8824_dac_right_sel_enum = 350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, 351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 352 353 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); 354 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); 355 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); 356 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); 357 358 static const struct snd_kcontrol_new nau8824_snd_controls[] = { 359 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), 360 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), 361 362 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), 363 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), 364 365 SOC_SINGLE_TLV("Speaker Right DACR Volume", 366 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), 367 SOC_SINGLE_TLV("Speaker Left DACL Volume", 368 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), 369 SOC_SINGLE_TLV("Speaker Left DACR Volume", 370 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), 371 SOC_SINGLE_TLV("Speaker Right DACL Volume", 372 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), 373 374 SOC_SINGLE_TLV("Headphone Right DACR Volume", 375 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), 376 SOC_SINGLE_TLV("Headphone Left DACL Volume", 377 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), 378 SOC_SINGLE_TLV("Headphone Right DACL Volume", 379 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), 380 SOC_SINGLE_TLV("Headphone Left DACR Volume", 381 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), 382 383 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, 384 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), 385 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, 386 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), 387 388 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, 389 0, 0x164, 0, dmic_vol_tlv), 390 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, 391 0, 0x164, 0, dmic_vol_tlv), 392 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, 393 0, 0x164, 0, dmic_vol_tlv), 394 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, 395 0, 0x164, 0, dmic_vol_tlv), 396 397 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), 398 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), 399 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), 400 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), 401 402 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), 403 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), 404 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), 405 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), 406 407 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), 408 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), 409 410 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), 411 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), 412 }; 413 414 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, 415 struct snd_kcontrol *kcontrol, int event) 416 { 417 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 418 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 419 420 switch (event) { 421 case SND_SOC_DAPM_PRE_PMU: 422 /* Disables the TESTDAC to let DAC signal pass through. */ 423 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 424 NAU8824_TEST_DAC_EN, 0); 425 break; 426 case SND_SOC_DAPM_POST_PMD: 427 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 428 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int nau8824_spk_event(struct snd_soc_dapm_widget *w, 438 struct snd_kcontrol *kcontrol, int event) 439 { 440 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 441 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 442 443 switch (event) { 444 case SND_SOC_DAPM_PRE_PMU: 445 regmap_update_bits(nau8824->regmap, 446 NAU8824_REG_ANALOG_CONTROL_2, 447 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); 448 break; 449 case SND_SOC_DAPM_POST_PMD: 450 regmap_update_bits(nau8824->regmap, 451 NAU8824_REG_ANALOG_CONTROL_2, 452 NAU8824_CLASSD_CLAMP_DIS, 0); 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static int nau8824_pump_event(struct snd_soc_dapm_widget *w, 462 struct snd_kcontrol *kcontrol, int event) 463 { 464 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 465 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 466 467 switch (event) { 468 case SND_SOC_DAPM_POST_PMU: 469 /* Prevent startup click by letting charge pump to ramp up */ 470 msleep(10); 471 regmap_update_bits(nau8824->regmap, 472 NAU8824_REG_CHARGE_PUMP_CONTROL, 473 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); 474 break; 475 case SND_SOC_DAPM_PRE_PMD: 476 regmap_update_bits(nau8824->regmap, 477 NAU8824_REG_CHARGE_PUMP_CONTROL, 478 NAU8824_JAMNODCLOW, 0); 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static int system_clock_control(struct snd_soc_dapm_widget *w, 488 struct snd_kcontrol *k, int event) 489 { 490 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 491 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 492 493 if (SND_SOC_DAPM_EVENT_OFF(event)) { 494 /* Set clock source to disable or internal clock before the 495 * playback or capture end. Codec needs clock for Jack 496 * detection and button press if jack inserted; otherwise, 497 * the clock should be closed. 498 */ 499 if (nau8824_is_jack_inserted(nau8824)) { 500 nau8824_config_sysclk(nau8824, 501 NAU8824_CLK_INTERNAL, 0); 502 } else { 503 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 504 } 505 } 506 return 0; 507 } 508 509 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 510 struct snd_kcontrol *k, int event) 511 { 512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 513 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 514 int src; 515 516 /* The DMIC clock is gotten from system clock (256fs) divided by 517 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or 518 * less than 3.072 MHz. 519 */ 520 for (src = 0; src < 5; src++) { 521 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) 522 break; 523 } 524 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); 525 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 526 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); 527 528 return 0; 529 } 530 531 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = 532 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 533 NAU8824_ADC_CH0_DMIC_SFT, 1, 0); 534 535 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = 536 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 537 NAU8824_ADC_CH1_DMIC_SFT, 1, 0); 538 539 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = 540 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 541 NAU8824_ADC_CH2_DMIC_SFT, 1, 0); 542 543 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = 544 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 545 NAU8824_ADC_CH3_DMIC_SFT, 1, 0); 546 547 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { 548 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 549 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), 550 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 551 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), 552 }; 553 554 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { 555 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 556 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), 557 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 558 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), 559 }; 560 561 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { 562 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 563 NAU8824_DACR_HPL_EN_SFT, 1, 0), 564 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 565 NAU8824_DACL_HPL_EN_SFT, 1, 0), 566 }; 567 568 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { 569 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 570 NAU8824_DACL_HPR_EN_SFT, 1, 0), 571 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 572 NAU8824_DACR_HPR_EN_SFT, 1, 0), 573 }; 574 575 static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; 576 577 static SOC_ENUM_SINGLE_DECL( 578 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 579 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); 580 581 static SOC_ENUM_SINGLE_DECL( 582 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 583 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); 584 585 static const struct snd_kcontrol_new nau8824_dacl_mux = 586 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); 587 588 static const struct snd_kcontrol_new nau8824_dacr_mux = 589 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); 590 591 592 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { 593 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 594 system_clock_control, SND_SOC_DAPM_POST_PMD), 595 596 SND_SOC_DAPM_INPUT("HSMIC1"), 597 SND_SOC_DAPM_INPUT("HSMIC2"), 598 SND_SOC_DAPM_INPUT("MIC1"), 599 SND_SOC_DAPM_INPUT("MIC2"), 600 SND_SOC_DAPM_INPUT("DMIC1"), 601 SND_SOC_DAPM_INPUT("DMIC2"), 602 SND_SOC_DAPM_INPUT("DMIC3"), 603 SND_SOC_DAPM_INPUT("DMIC4"), 604 605 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, 606 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), 607 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, 608 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), 609 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, 610 NAU8824_DMIC1_EN_SFT, 0, NULL, 0), 611 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, 612 NAU8824_DMIC2_EN_SFT, 0, NULL, 0), 613 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 614 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 615 616 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, 617 0, 0, &nau8824_adc_ch0_dmic), 618 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, 619 0, 0, &nau8824_adc_ch1_dmic), 620 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, 621 0, 0, &nau8824_adc_ch2_dmic), 622 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, 623 0, 0, &nau8824_adc_ch3_dmic), 624 625 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, 626 12, 0, nau8824_adc_left_mixer, 627 ARRAY_SIZE(nau8824_adc_left_mixer)), 628 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, 629 13, 0, nau8824_adc_right_mixer, 630 ARRAY_SIZE(nau8824_adc_right_mixer)), 631 632 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, 633 NAU8824_ADCL_EN_SFT, 0), 634 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, 635 NAU8824_ADCR_EN_SFT, 0), 636 637 SND_SOC_DAPM_AIF_OUT("AIFTX", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 638 SND_SOC_DAPM_AIF_IN("AIFRX", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 639 640 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, 641 NAU8824_DACL_EN_SFT, 0), 642 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, 643 NAU8824_DACL_CLK_SFT, 0, NULL, 0), 644 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, 645 NAU8824_DACR_EN_SFT, 0), 646 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, 647 NAU8824_DACR_CLK_SFT, 0, NULL, 0), 648 649 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), 650 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), 651 652 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 653 8, 1, nau8824_output_dac_event, 654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 655 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 656 9, 1, nau8824_output_dac_event, 657 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 658 659 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, 660 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, 661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 662 663 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, 664 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, 665 ARRAY_SIZE(nau8824_hp_left_mixer)), 666 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, 667 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, 668 ARRAY_SIZE(nau8824_hp_right_mixer)), 669 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, 670 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, 671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 672 SND_SOC_DAPM_PGA("Output Driver L", 673 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 674 SND_SOC_DAPM_PGA("Output Driver R", 675 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 676 SND_SOC_DAPM_PGA("Main Driver L", 677 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 678 SND_SOC_DAPM_PGA("Main Driver R", 679 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 680 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, 681 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), 682 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, 683 NAU8824_CLASSG_EN_SFT, 0, NULL, 0), 684 685 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 686 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 687 SND_SOC_DAPM_OUTPUT("HPOL"), 688 SND_SOC_DAPM_OUTPUT("HPOR"), 689 }; 690 691 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { 692 {"DMIC1 Enable", "Switch", "DMIC1"}, 693 {"DMIC2 Enable", "Switch", "DMIC2"}, 694 {"DMIC3 Enable", "Switch", "DMIC3"}, 695 {"DMIC4 Enable", "Switch", "DMIC4"}, 696 697 {"DMIC1", NULL, "DMIC12 Power"}, 698 {"DMIC2", NULL, "DMIC12 Power"}, 699 {"DMIC3", NULL, "DMIC34 Power"}, 700 {"DMIC4", NULL, "DMIC34 Power"}, 701 {"DMIC12 Power", NULL, "DMIC Clock"}, 702 {"DMIC34 Power", NULL, "DMIC Clock"}, 703 704 {"Left ADC", "MIC Switch", "MIC1"}, 705 {"Left ADC", "HSMIC Switch", "HSMIC1"}, 706 {"Right ADC", "MIC Switch", "MIC2"}, 707 {"Right ADC", "HSMIC Switch", "HSMIC2"}, 708 709 {"ADCL", NULL, "Left ADC"}, 710 {"ADCR", NULL, "Right ADC"}, 711 712 {"AIFTX", NULL, "MICBIAS"}, 713 {"AIFTX", NULL, "ADCL"}, 714 {"AIFTX", NULL, "ADCR"}, 715 {"AIFTX", NULL, "DMIC1 Enable"}, 716 {"AIFTX", NULL, "DMIC2 Enable"}, 717 {"AIFTX", NULL, "DMIC3 Enable"}, 718 {"AIFTX", NULL, "DMIC4 Enable"}, 719 720 {"AIFTX", NULL, "System Clock"}, 721 {"AIFRX", NULL, "System Clock"}, 722 723 {"DACL", NULL, "AIFRX"}, 724 {"DACL", NULL, "DACL Clock"}, 725 {"DACR", NULL, "AIFRX"}, 726 {"DACR", NULL, "DACR Clock"}, 727 728 {"DACL Mux", "DACL", "DACL"}, 729 {"DACL Mux", "DACR", "DACR"}, 730 {"DACR Mux", "DACL", "DACL"}, 731 {"DACR Mux", "DACR", "DACR"}, 732 733 {"Output DACL", NULL, "DACL Mux"}, 734 {"Output DACR", NULL, "DACR Mux"}, 735 736 {"ClassD", NULL, "Output DACL"}, 737 {"ClassD", NULL, "Output DACR"}, 738 739 {"Left Headphone", "DAC Left Switch", "Output DACL"}, 740 {"Left Headphone", "DAC Right Switch", "Output DACR"}, 741 {"Right Headphone", "DAC Left Switch", "Output DACL"}, 742 {"Right Headphone", "DAC Right Switch", "Output DACR"}, 743 744 {"Charge Pump", NULL, "Left Headphone"}, 745 {"Charge Pump", NULL, "Right Headphone"}, 746 {"Output Driver L", NULL, "Charge Pump"}, 747 {"Output Driver R", NULL, "Charge Pump"}, 748 {"Main Driver L", NULL, "Output Driver L"}, 749 {"Main Driver R", NULL, "Output Driver R"}, 750 {"Class G", NULL, "Main Driver L"}, 751 {"Class G", NULL, "Main Driver R"}, 752 {"HP Boost Driver", NULL, "Class G"}, 753 754 {"SPKOUTL", NULL, "ClassD"}, 755 {"SPKOUTR", NULL, "ClassD"}, 756 {"HPOL", NULL, "HP Boost Driver"}, 757 {"HPOR", NULL, "HP Boost Driver"}, 758 }; 759 760 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) 761 { 762 struct snd_soc_jack *jack = nau8824->jack; 763 bool insert = FALSE; 764 765 if (nau8824->irq && jack) 766 insert = jack->status & SND_JACK_HEADPHONE; 767 768 return insert; 769 } 770 771 static void nau8824_int_status_clear_all(struct regmap *regmap) 772 { 773 int active_irq, clear_irq, i; 774 775 /* Reset the intrruption status from rightmost bit if the corres- 776 * ponding irq event occurs. 777 */ 778 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); 779 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { 780 clear_irq = (0x1 << i); 781 if (active_irq & clear_irq) 782 regmap_write(regmap, 783 NAU8824_REG_CLEAR_INT_REG, clear_irq); 784 } 785 } 786 787 static void nau8824_eject_jack(struct nau8824 *nau8824) 788 { 789 struct snd_soc_dapm_context *dapm = nau8824->dapm; 790 struct regmap *regmap = nau8824->regmap; 791 792 /* Clear all interruption status */ 793 nau8824_int_status_clear_all(regmap); 794 795 snd_soc_dapm_disable_pin(dapm, "SAR"); 796 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 797 snd_soc_dapm_sync(dapm); 798 799 /* Enable the insertion interruption, disable the ejection 800 * interruption, and then bypass de-bounce circuit. 801 */ 802 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 803 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 804 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 805 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 806 NAU8824_IRQ_EJECT_DIS); 807 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 808 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 809 NAU8824_IRQ_INSERT_EN); 810 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 811 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 812 813 /* Close clock for jack type detection at manual mode */ 814 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 815 } 816 817 static void nau8824_jdet_work(struct work_struct *work) 818 { 819 struct nau8824 *nau8824 = container_of( 820 work, struct nau8824, jdet_work); 821 struct snd_soc_dapm_context *dapm = nau8824->dapm; 822 struct regmap *regmap = nau8824->regmap; 823 int adc_value, event = 0, event_mask = 0; 824 825 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 826 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 827 snd_soc_dapm_sync(dapm); 828 829 msleep(100); 830 831 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); 832 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; 833 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); 834 if (adc_value < HEADSET_SARADC_THD) { 835 event |= SND_JACK_HEADPHONE; 836 837 snd_soc_dapm_disable_pin(dapm, "SAR"); 838 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 839 snd_soc_dapm_sync(dapm); 840 } else { 841 event |= SND_JACK_HEADSET; 842 } 843 event_mask |= SND_JACK_HEADSET; 844 snd_soc_jack_report(nau8824->jack, event, event_mask); 845 846 nau8824_sema_release(nau8824); 847 } 848 849 static void nau8824_setup_auto_irq(struct nau8824 *nau8824) 850 { 851 struct regmap *regmap = nau8824->regmap; 852 853 /* Enable jack ejection, short key press and release interruption. */ 854 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 855 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 856 NAU8824_IRQ_EJECT_EN); 857 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 858 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_KEY_RELEASE_DIS | 859 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); 860 /* Enable internal VCO needed for interruptions */ 861 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); 862 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 863 NAU8824_JD_SLEEP_MODE, 0); 864 } 865 866 static int nau8824_button_decode(int value) 867 { 868 int buttons = 0; 869 870 /* The chip supports up to 8 buttons, but ALSA defines 871 * only 6 buttons. 872 */ 873 if (value & BIT(0)) 874 buttons |= SND_JACK_BTN_0; 875 if (value & BIT(1)) 876 buttons |= SND_JACK_BTN_1; 877 if (value & BIT(2)) 878 buttons |= SND_JACK_BTN_2; 879 if (value & BIT(3)) 880 buttons |= SND_JACK_BTN_3; 881 if (value & BIT(4)) 882 buttons |= SND_JACK_BTN_4; 883 if (value & BIT(5)) 884 buttons |= SND_JACK_BTN_5; 885 886 return buttons; 887 } 888 889 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 890 SND_JACK_BTN_2 | SND_JACK_BTN_3) 891 892 static irqreturn_t nau8824_interrupt(int irq, void *data) 893 { 894 struct nau8824 *nau8824 = (struct nau8824 *)data; 895 struct regmap *regmap = nau8824->regmap; 896 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 897 898 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { 899 dev_err(nau8824->dev, "failed to read irq status\n"); 900 return IRQ_NONE; 901 } 902 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); 903 904 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { 905 nau8824_eject_jack(nau8824); 906 event_mask |= SND_JACK_HEADSET; 907 clear_irq = NAU8824_JACK_EJECTION_DETECTED; 908 /* release semaphore held after resume, 909 * and cancel jack detection 910 */ 911 nau8824_sema_release(nau8824); 912 cancel_work_sync(&nau8824->jdet_work); 913 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { 914 int key_status, button_pressed; 915 916 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, 917 &key_status); 918 919 /* lower 8 bits of the register are for pressed keys */ 920 button_pressed = nau8824_button_decode(key_status); 921 922 event |= button_pressed; 923 dev_dbg(nau8824->dev, "button %x pressed\n", event); 924 event_mask |= NAU8824_BUTTONS; 925 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; 926 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { 927 event_mask = NAU8824_BUTTONS; 928 clear_irq = NAU8824_KEY_RELEASE_IRQ; 929 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { 930 /* Turn off insertion interruption at manual mode */ 931 regmap_update_bits(regmap, 932 NAU8824_REG_INTERRUPT_SETTING, 933 NAU8824_IRQ_INSERT_DIS, 934 NAU8824_IRQ_INSERT_DIS); 935 regmap_update_bits(regmap, 936 NAU8824_REG_INTERRUPT_SETTING_1, 937 NAU8824_IRQ_INSERT_EN, 0); 938 /* detect microphone and jack type */ 939 cancel_work_sync(&nau8824->jdet_work); 940 schedule_work(&nau8824->jdet_work); 941 942 /* Enable interruption for jack type detection at audo 943 * mode which can detect microphone and jack type. 944 */ 945 nau8824_setup_auto_irq(nau8824); 946 } 947 948 if (!clear_irq) 949 clear_irq = active_irq; 950 /* clears the rightmost interruption */ 951 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); 952 953 if (event_mask) 954 snd_soc_jack_report(nau8824->jack, event, event_mask); 955 956 return IRQ_HANDLED; 957 } 958 959 static int nau8824_clock_check(struct nau8824 *nau8824, 960 int stream, int rate, int osr) 961 { 962 int osrate; 963 964 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 965 if (osr >= ARRAY_SIZE(osr_dac_sel)) 966 return -EINVAL; 967 osrate = osr_dac_sel[osr].osr; 968 } else { 969 if (osr >= ARRAY_SIZE(osr_adc_sel)) 970 return -EINVAL; 971 osrate = osr_adc_sel[osr].osr; 972 } 973 974 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 975 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 976 return -EINVAL; 977 } 978 979 return 0; 980 } 981 982 static int nau8824_hw_params(struct snd_pcm_substream *substream, 983 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 984 { 985 struct snd_soc_codec *codec = dai->codec; 986 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 987 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 988 989 nau8824_sema_acquire(nau8824, HZ); 990 991 /* CLK_DAC or CLK_ADC = OSR * FS 992 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 993 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 994 * values must be selected such that the maximum frequency is less 995 * than 6.144 MHz. 996 */ 997 nau8824->fs = params_rate(params); 998 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 999 regmap_read(nau8824->regmap, 1000 NAU8824_REG_DAC_FILTER_CTRL_1, &osr); 1001 osr &= NAU8824_DAC_OVERSAMPLE_MASK; 1002 if (nau8824_clock_check(nau8824, substream->stream, 1003 nau8824->fs, osr)) 1004 return -EINVAL; 1005 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1006 NAU8824_CLK_DAC_SRC_MASK, 1007 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); 1008 } else { 1009 regmap_read(nau8824->regmap, 1010 NAU8824_REG_ADC_FILTER_CTRL, &osr); 1011 osr &= NAU8824_ADC_SYNC_DOWN_MASK; 1012 if (nau8824_clock_check(nau8824, substream->stream, 1013 nau8824->fs, osr)) 1014 return -EINVAL; 1015 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1016 NAU8824_CLK_ADC_SRC_MASK, 1017 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); 1018 } 1019 1020 /* make BCLK and LRC divde configuration if the codec as master. */ 1021 regmap_read(nau8824->regmap, 1022 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); 1023 if (ctrl_val & NAU8824_I2S_MS_MASTER) { 1024 /* get the bclk and fs ratio */ 1025 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; 1026 if (bclk_fs <= 32) 1027 bclk_div = 0x3; 1028 else if (bclk_fs <= 64) 1029 bclk_div = 0x2; 1030 else if (bclk_fs <= 128) 1031 bclk_div = 0x1; 1032 else if (bclk_fs <= 256) 1033 bclk_div = 0; 1034 else 1035 return -EINVAL; 1036 regmap_update_bits(nau8824->regmap, 1037 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1038 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, 1039 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); 1040 } 1041 1042 switch (params_width(params)) { 1043 case 16: 1044 val_len |= NAU8824_I2S_DL_16; 1045 break; 1046 case 20: 1047 val_len |= NAU8824_I2S_DL_20; 1048 break; 1049 case 24: 1050 val_len |= NAU8824_I2S_DL_24; 1051 break; 1052 case 32: 1053 val_len |= NAU8824_I2S_DL_32; 1054 break; 1055 default: 1056 return -EINVAL; 1057 } 1058 1059 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1060 NAU8824_I2S_DL_MASK, val_len); 1061 1062 nau8824_sema_release(nau8824); 1063 1064 return 0; 1065 } 1066 1067 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1068 { 1069 struct snd_soc_codec *codec = dai->codec; 1070 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1071 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1072 1073 nau8824_sema_acquire(nau8824, HZ); 1074 1075 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1076 case SND_SOC_DAIFMT_CBM_CFM: 1077 ctrl2_val |= NAU8824_I2S_MS_MASTER; 1078 break; 1079 case SND_SOC_DAIFMT_CBS_CFS: 1080 break; 1081 default: 1082 return -EINVAL; 1083 } 1084 1085 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1086 case SND_SOC_DAIFMT_NB_NF: 1087 break; 1088 case SND_SOC_DAIFMT_IB_NF: 1089 ctrl1_val |= NAU8824_I2S_BP_INV; 1090 break; 1091 default: 1092 return -EINVAL; 1093 } 1094 1095 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1096 case SND_SOC_DAIFMT_I2S: 1097 ctrl1_val |= NAU8824_I2S_DF_I2S; 1098 break; 1099 case SND_SOC_DAIFMT_LEFT_J: 1100 ctrl1_val |= NAU8824_I2S_DF_LEFT; 1101 break; 1102 case SND_SOC_DAIFMT_RIGHT_J: 1103 ctrl1_val |= NAU8824_I2S_DF_RIGTH; 1104 break; 1105 case SND_SOC_DAIFMT_DSP_A: 1106 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1107 break; 1108 case SND_SOC_DAIFMT_DSP_B: 1109 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1110 ctrl1_val |= NAU8824_I2S_PCMB_EN; 1111 break; 1112 default: 1113 return -EINVAL; 1114 } 1115 1116 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1117 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | 1118 NAU8824_I2S_PCMB_EN, ctrl1_val); 1119 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1120 NAU8824_I2S_MS_MASK, ctrl2_val); 1121 1122 nau8824_sema_release(nau8824); 1123 1124 return 0; 1125 } 1126 1127 /** 1128 * nau8824_set_tdm_slot - configure DAI TDM. 1129 * @dai: DAI 1130 * @tx_mask: Bitmask representing active TX slots. Ex. 1131 * 0xf for normal 4 channel TDM. 1132 * 0xf0 for shifted 4 channel TDM 1133 * @rx_mask: Bitmask [0:1] representing active DACR RX slots. 1134 * Bitmask [2:3] representing active DACL RX slots. 1135 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. 1136 * 0xf for DACL/R selecting TDM CH3. 1137 * 0xf0 for DACL/R selecting shifted TDM CH3. 1138 * @slots: Number of slots in use. 1139 * @slot_width: Width in bits for each slot. 1140 * 1141 * Configures a DAI for TDM operation. Only support 4 slots TDM. 1142 */ 1143 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, 1144 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1145 { 1146 struct snd_soc_codec *codec = dai->codec; 1147 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1148 unsigned int tslot_l = 0, ctrl_val = 0; 1149 1150 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || 1151 ((rx_mask & 0xf0) && (rx_mask & 0xf)) || 1152 ((rx_mask & 0xf0) && (tx_mask & 0xf)) || 1153 ((rx_mask & 0xf) && (tx_mask & 0xf0))) 1154 return -EINVAL; 1155 1156 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); 1157 if (tx_mask & 0xf0) { 1158 tslot_l = 4 * slot_width; 1159 ctrl_val |= (tx_mask >> 4); 1160 } else { 1161 ctrl_val |= tx_mask; 1162 } 1163 if (rx_mask & 0xf0) 1164 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); 1165 else 1166 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); 1167 1168 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, 1169 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | 1170 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | 1171 NAU8824_TDM_TX_MASK, ctrl_val); 1172 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, 1173 NAU8824_TSLOT_L_MASK, tslot_l); 1174 1175 return 0; 1176 } 1177 1178 /** 1179 * nau8824_calc_fll_param - Calculate FLL parameters. 1180 * @fll_in: external clock provided to codec. 1181 * @fs: sampling rate. 1182 * @fll_param: Pointer to structure of FLL parameters. 1183 * 1184 * Calculate FLL parameters to configure codec. 1185 * 1186 * Returns 0 for success or negative error code. 1187 */ 1188 static int nau8824_calc_fll_param(unsigned int fll_in, 1189 unsigned int fs, struct nau8824_fll *fll_param) 1190 { 1191 u64 fvco, fvco_max; 1192 unsigned int fref, i, fvco_sel; 1193 1194 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1195 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1196 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK 1197 */ 1198 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1199 fref = fll_in / fll_pre_scalar[i].param; 1200 if (fref <= NAU_FREF_MAX) 1201 break; 1202 } 1203 if (i == ARRAY_SIZE(fll_pre_scalar)) 1204 return -EINVAL; 1205 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1206 1207 /* Choose the FLL ratio based on FREF */ 1208 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1209 if (fref >= fll_ratio[i].param) 1210 break; 1211 } 1212 if (i == ARRAY_SIZE(fll_ratio)) 1213 return -EINVAL; 1214 fll_param->ratio = fll_ratio[i].val; 1215 1216 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1217 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 1218 * guaranteed across the full range of operation. 1219 * FDCO = freq_out * 2 * mclk_src_scaling 1220 */ 1221 fvco_max = 0; 1222 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1223 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1224 fvco = 256 * fs * 2 * mclk_src_scaling[i].param; 1225 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1226 fvco_max < fvco) { 1227 fvco_max = fvco; 1228 fvco_sel = i; 1229 } 1230 } 1231 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1232 return -EINVAL; 1233 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1234 1235 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 1236 * input based on FDCO, FREF and FLL ratio. 1237 */ 1238 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 1239 fll_param->fll_int = (fvco >> 16) & 0x3FF; 1240 fll_param->fll_frac = fvco & 0xFFFF; 1241 return 0; 1242 } 1243 1244 static void nau8824_fll_apply(struct regmap *regmap, 1245 struct nau8824_fll *fll_param) 1246 { 1247 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1248 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, 1249 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); 1250 regmap_update_bits(regmap, NAU8824_REG_FLL1, 1251 NAU8824_FLL_RATIO_MASK, fll_param->ratio); 1252 /* FLL 16-bit fractional input */ 1253 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); 1254 /* FLL 10-bit integer input */ 1255 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1256 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); 1257 /* FLL pre-scaler */ 1258 regmap_update_bits(regmap, NAU8824_REG_FLL4, 1259 NAU8824_FLL_REF_DIV_MASK, 1260 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); 1261 /* select divided VCO input */ 1262 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1263 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); 1264 /* Disable free-running mode */ 1265 regmap_update_bits(regmap, 1266 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 1267 if (fll_param->fll_frac) { 1268 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1269 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1270 NAU8824_FLL_FTR_SW_MASK, 1271 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1272 NAU8824_FLL_FTR_SW_FILTER); 1273 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1274 NAU8824_SDM_EN, NAU8824_SDM_EN); 1275 } else { 1276 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1277 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1278 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); 1279 regmap_update_bits(regmap, 1280 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); 1281 } 1282 } 1283 1284 /* freq_out must be 256*Fs in order to achieve the best performance */ 1285 static int nau8824_set_pll(struct snd_soc_codec *codec, int pll_id, int source, 1286 unsigned int freq_in, unsigned int freq_out) 1287 { 1288 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1289 struct nau8824_fll fll_param; 1290 int ret, fs; 1291 1292 fs = freq_out / 256; 1293 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); 1294 if (ret < 0) { 1295 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); 1296 return ret; 1297 } 1298 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1299 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 1300 fll_param.fll_int, fll_param.clk_ref_div); 1301 1302 nau8824_fll_apply(nau8824->regmap, &fll_param); 1303 mdelay(2); 1304 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1305 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1306 1307 return 0; 1308 } 1309 1310 static int nau8824_config_sysclk(struct nau8824 *nau8824, 1311 int clk_id, unsigned int freq) 1312 { 1313 struct regmap *regmap = nau8824->regmap; 1314 1315 switch (clk_id) { 1316 case NAU8824_CLK_DIS: 1317 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1318 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1319 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1320 NAU8824_DCO_EN, 0); 1321 break; 1322 1323 case NAU8824_CLK_MCLK: 1324 nau8824_sema_acquire(nau8824, HZ); 1325 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1326 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1327 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1328 NAU8824_DCO_EN, 0); 1329 nau8824_sema_release(nau8824); 1330 break; 1331 1332 case NAU8824_CLK_INTERNAL: 1333 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1334 NAU8824_DCO_EN, NAU8824_DCO_EN); 1335 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1336 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1337 break; 1338 1339 case NAU8824_CLK_FLL_MCLK: 1340 nau8824_sema_acquire(nau8824, HZ); 1341 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1342 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); 1343 nau8824_sema_release(nau8824); 1344 break; 1345 1346 case NAU8824_CLK_FLL_BLK: 1347 nau8824_sema_acquire(nau8824, HZ); 1348 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1349 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); 1350 nau8824_sema_release(nau8824); 1351 break; 1352 1353 case NAU8824_CLK_FLL_FS: 1354 nau8824_sema_acquire(nau8824, HZ); 1355 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1356 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); 1357 nau8824_sema_release(nau8824); 1358 break; 1359 1360 default: 1361 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); 1362 return -EINVAL; 1363 } 1364 1365 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1366 clk_id); 1367 1368 return 0; 1369 } 1370 1371 static int nau8824_set_sysclk(struct snd_soc_codec *codec, 1372 int clk_id, int source, unsigned int freq, int dir) 1373 { 1374 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1375 1376 return nau8824_config_sysclk(nau8824, clk_id, freq); 1377 } 1378 1379 static void nau8824_resume_setup(struct nau8824 *nau8824) 1380 { 1381 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 1382 if (nau8824->irq) { 1383 /* Clear all interruption status */ 1384 nau8824_int_status_clear_all(nau8824->regmap); 1385 /* Enable jack detection at sleep mode, insertion detection, 1386 * and ejection detection. 1387 */ 1388 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1389 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1390 regmap_update_bits(nau8824->regmap, 1391 NAU8824_REG_INTERRUPT_SETTING_1, 1392 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 1393 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); 1394 regmap_update_bits(nau8824->regmap, 1395 NAU8824_REG_INTERRUPT_SETTING, 1396 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); 1397 } 1398 } 1399 1400 static int nau8824_set_bias_level(struct snd_soc_codec *codec, 1401 enum snd_soc_bias_level level) 1402 { 1403 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1404 1405 switch (level) { 1406 case SND_SOC_BIAS_ON: 1407 break; 1408 1409 case SND_SOC_BIAS_PREPARE: 1410 break; 1411 1412 case SND_SOC_BIAS_STANDBY: 1413 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 1414 /* Setup codec configuration after resume */ 1415 nau8824_resume_setup(nau8824); 1416 } 1417 break; 1418 1419 case SND_SOC_BIAS_OFF: 1420 regmap_update_bits(nau8824->regmap, 1421 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1422 regmap_update_bits(nau8824->regmap, 1423 NAU8824_REG_INTERRUPT_SETTING_1, 1424 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1425 break; 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int nau8824_codec_probe(struct snd_soc_codec *codec) 1432 { 1433 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1434 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1435 1436 nau8824->dapm = dapm; 1437 1438 return 0; 1439 } 1440 1441 static int __maybe_unused nau8824_suspend(struct snd_soc_codec *codec) 1442 { 1443 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1444 1445 if (nau8824->irq) { 1446 disable_irq(nau8824->irq); 1447 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1448 } 1449 regcache_cache_only(nau8824->regmap, true); 1450 regcache_mark_dirty(nau8824->regmap); 1451 1452 return 0; 1453 } 1454 1455 static int __maybe_unused nau8824_resume(struct snd_soc_codec *codec) 1456 { 1457 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1458 1459 regcache_cache_only(nau8824->regmap, false); 1460 regcache_sync(nau8824->regmap); 1461 if (nau8824->irq) { 1462 /* Hold semaphore to postpone playback happening 1463 * until jack detection done. 1464 */ 1465 nau8824_sema_acquire(nau8824, 0); 1466 enable_irq(nau8824->irq); 1467 } 1468 1469 return 0; 1470 } 1471 1472 static const struct snd_soc_codec_driver nau8824_codec_driver = { 1473 .probe = nau8824_codec_probe, 1474 .set_sysclk = nau8824_set_sysclk, 1475 .set_pll = nau8824_set_pll, 1476 .set_bias_level = nau8824_set_bias_level, 1477 .suspend = nau8824_suspend, 1478 .resume = nau8824_resume, 1479 .suspend_bias_off = true, 1480 1481 .component_driver = { 1482 .controls = nau8824_snd_controls, 1483 .num_controls = ARRAY_SIZE(nau8824_snd_controls), 1484 .dapm_widgets = nau8824_dapm_widgets, 1485 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), 1486 .dapm_routes = nau8824_dapm_routes, 1487 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), 1488 }, 1489 }; 1490 1491 static const struct snd_soc_dai_ops nau8824_dai_ops = { 1492 .hw_params = nau8824_hw_params, 1493 .set_fmt = nau8824_set_fmt, 1494 .set_tdm_slot = nau8824_set_tdm_slot, 1495 }; 1496 1497 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 1498 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1499 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1500 1501 static struct snd_soc_dai_driver nau8824_dai = { 1502 .name = NAU8824_CODEC_DAI, 1503 .playback = { 1504 .stream_name = "Playback", 1505 .channels_min = 1, 1506 .channels_max = 2, 1507 .rates = NAU8824_RATES, 1508 .formats = NAU8824_FORMATS, 1509 }, 1510 .capture = { 1511 .stream_name = "Capture", 1512 .channels_min = 1, 1513 .channels_max = 2, 1514 .rates = NAU8824_RATES, 1515 .formats = NAU8824_FORMATS, 1516 }, 1517 .ops = &nau8824_dai_ops, 1518 }; 1519 1520 static const struct regmap_config nau8824_regmap_config = { 1521 .val_bits = NAU8824_REG_ADDR_LEN, 1522 .reg_bits = NAU8824_REG_DATA_LEN, 1523 1524 .max_register = NAU8824_REG_MAX, 1525 .readable_reg = nau8824_readable_reg, 1526 .writeable_reg = nau8824_writeable_reg, 1527 .volatile_reg = nau8824_volatile_reg, 1528 1529 .cache_type = REGCACHE_RBTREE, 1530 .reg_defaults = nau8824_reg_defaults, 1531 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), 1532 }; 1533 1534 /** 1535 * nau8824_enable_jack_detect - Specify a jack for event reporting 1536 * 1537 * @component: component to register the jack with 1538 * @jack: jack to use to report headset and button events on 1539 * 1540 * After this function has been called the headset insert/remove and button 1541 * events will be routed to the given jack. Jack can be null to stop 1542 * reporting. 1543 */ 1544 int nau8824_enable_jack_detect(struct snd_soc_codec *codec, 1545 struct snd_soc_jack *jack) 1546 { 1547 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1548 int ret; 1549 1550 nau8824->jack = jack; 1551 /* Initiate jack detection work queue */ 1552 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); 1553 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, 1554 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1555 "nau8824", nau8824); 1556 if (ret) { 1557 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", 1558 nau8824->irq, ret); 1559 } 1560 1561 return ret; 1562 } 1563 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); 1564 1565 static void nau8824_reset_chip(struct regmap *regmap) 1566 { 1567 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1568 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1569 } 1570 1571 static void nau8824_setup_buttons(struct nau8824 *nau8824) 1572 { 1573 struct regmap *regmap = nau8824->regmap; 1574 1575 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1576 NAU8824_SAR_TRACKING_GAIN_MASK, 1577 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); 1578 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1579 NAU8824_SAR_COMPARE_TIME_MASK, 1580 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); 1581 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1582 NAU8824_SAR_SAMPLING_TIME_MASK, 1583 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); 1584 1585 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1586 NAU8824_LEVELS_NR_MASK, 1587 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); 1588 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1589 NAU8824_HYSTERESIS_MASK, 1590 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); 1591 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1592 NAU8824_SHORTKEY_DEBOUNCE_MASK, 1593 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); 1594 1595 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, 1596 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); 1597 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, 1598 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); 1599 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, 1600 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); 1601 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, 1602 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); 1603 } 1604 1605 static void nau8824_init_regs(struct nau8824 *nau8824) 1606 { 1607 struct regmap *regmap = nau8824->regmap; 1608 1609 /* Enable Bias/VMID/VMID Tieoff */ 1610 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, 1611 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | 1612 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); 1613 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1614 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); 1615 mdelay(2); 1616 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, 1617 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); 1618 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1619 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1620 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1621 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, 1622 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1623 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); 1624 /* Scaling for ADC and DAC clock */ 1625 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1626 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, 1627 (0x1 << NAU8824_CLK_ADC_SRC_SFT) | 1628 (0x1 << NAU8824_CLK_DAC_SRC_SFT)); 1629 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, 1630 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); 1631 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 1632 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1633 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1634 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, 1635 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1636 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1637 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); 1638 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, 1639 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1640 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1641 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1642 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, 1643 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1644 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1645 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1646 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); 1647 /* Class G timer 64ms */ 1648 regmap_update_bits(regmap, NAU8824_REG_CLASSG, 1649 NAU8824_CLASSG_TIMER_MASK, 1650 0x20 << NAU8824_CLASSG_TIMER_SFT); 1651 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, 1652 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); 1653 /* Disable DACR/L power */ 1654 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, 1655 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1656 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, 1657 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1658 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); 1659 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1660 * signal to avoid any glitches due to power up transients in both 1661 * the analog and digital DAC circuit. 1662 */ 1663 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1664 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 1665 /* Config L/R channel */ 1666 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 1667 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); 1668 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 1669 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); 1670 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1671 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, 1672 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); 1673 /* Default oversampling/decimations settings are unusable 1674 * (audible hiss). Set it to something better. 1675 */ 1676 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, 1677 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); 1678 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, 1679 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, 1680 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); 1681 /* DAC clock delay 2ns, VREF */ 1682 regmap_update_bits(regmap, NAU8824_REG_RDAC, 1683 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, 1684 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | 1685 (0x3 << NAU8824_RDAC_VREF_SFT)); 1686 /* PGA input mode selection */ 1687 regmap_update_bits(regmap, NAU8824_REG_FEPGA, 1688 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, 1689 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); 1690 /* Digital microphone control */ 1691 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, 1692 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, 1693 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); 1694 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, 1695 NAU8824_JACK_LOGIC, 1696 /* jkdet_polarity - 1 is for active-low */ 1697 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); 1698 regmap_update_bits(regmap, 1699 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, 1700 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); 1701 if (nau8824->sar_threshold_num) 1702 nau8824_setup_buttons(nau8824); 1703 } 1704 1705 static int nau8824_setup_irq(struct nau8824 *nau8824) 1706 { 1707 /* Disable interruption before codec initiation done */ 1708 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1709 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1710 regmap_update_bits(nau8824->regmap, 1711 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1712 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, 1713 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1714 1715 return 0; 1716 } 1717 1718 static void nau8824_print_device_properties(struct nau8824 *nau8824) 1719 { 1720 struct device *dev = nau8824->dev; 1721 int i; 1722 1723 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); 1724 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); 1725 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); 1726 1727 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); 1728 for (i = 0; i < nau8824->sar_threshold_num; i++) 1729 dev_dbg(dev, "sar-threshold[%d]=%x\n", i, 1730 nau8824->sar_threshold[i]); 1731 1732 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); 1733 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); 1734 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); 1735 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); 1736 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); 1737 dev_dbg(dev, "jack-eject-debounce: %d\n", 1738 nau8824->jack_eject_debounce); 1739 } 1740 1741 static int nau8824_read_device_properties(struct device *dev, 1742 struct nau8824 *nau8824) { 1743 int ret; 1744 1745 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1746 &nau8824->jkdet_polarity); 1747 if (ret) 1748 nau8824->jkdet_polarity = 1; 1749 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1750 &nau8824->micbias_voltage); 1751 if (ret) 1752 nau8824->micbias_voltage = 6; 1753 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1754 &nau8824->vref_impedance); 1755 if (ret) 1756 nau8824->vref_impedance = 2; 1757 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 1758 &nau8824->sar_threshold_num); 1759 if (ret) 1760 nau8824->sar_threshold_num = 4; 1761 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 1762 nau8824->sar_threshold, nau8824->sar_threshold_num); 1763 if (ret) { 1764 nau8824->sar_threshold[0] = 0x0a; 1765 nau8824->sar_threshold[1] = 0x14; 1766 nau8824->sar_threshold[2] = 0x26; 1767 nau8824->sar_threshold[3] = 0x73; 1768 } 1769 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 1770 &nau8824->sar_hysteresis); 1771 if (ret) 1772 nau8824->sar_hysteresis = 0; 1773 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 1774 &nau8824->sar_voltage); 1775 if (ret) 1776 nau8824->sar_voltage = 6; 1777 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 1778 &nau8824->sar_compare_time); 1779 if (ret) 1780 nau8824->sar_compare_time = 1; 1781 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 1782 &nau8824->sar_sampling_time); 1783 if (ret) 1784 nau8824->sar_sampling_time = 1; 1785 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 1786 &nau8824->key_debounce); 1787 if (ret) 1788 nau8824->key_debounce = 0; 1789 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1790 &nau8824->jack_eject_debounce); 1791 if (ret) 1792 nau8824->jack_eject_debounce = 1; 1793 1794 return 0; 1795 } 1796 1797 static int nau8824_i2c_probe(struct i2c_client *i2c, 1798 const struct i2c_device_id *id) 1799 { 1800 struct device *dev = &i2c->dev; 1801 struct nau8824 *nau8824 = dev_get_platdata(dev); 1802 int ret, value; 1803 1804 if (!nau8824) { 1805 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); 1806 if (!nau8824) 1807 return -ENOMEM; 1808 ret = nau8824_read_device_properties(dev, nau8824); 1809 if (ret) 1810 return ret; 1811 } 1812 i2c_set_clientdata(i2c, nau8824); 1813 1814 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); 1815 if (IS_ERR(nau8824->regmap)) 1816 return PTR_ERR(nau8824->regmap); 1817 nau8824->dev = dev; 1818 nau8824->irq = i2c->irq; 1819 sema_init(&nau8824->jd_sem, 1); 1820 1821 nau8824_print_device_properties(nau8824); 1822 1823 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); 1824 if (ret < 0) { 1825 dev_err(dev, "Failed to read device id from the NAU8824: %d\n", 1826 ret); 1827 return ret; 1828 } 1829 nau8824_reset_chip(nau8824->regmap); 1830 nau8824_init_regs(nau8824); 1831 1832 if (i2c->irq) 1833 nau8824_setup_irq(nau8824); 1834 1835 return snd_soc_register_codec(dev, 1836 &nau8824_codec_driver, &nau8824_dai, 1); 1837 } 1838 1839 1840 static int nau8824_i2c_remove(struct i2c_client *client) 1841 { 1842 snd_soc_unregister_codec(&client->dev); 1843 return 0; 1844 } 1845 1846 static const struct i2c_device_id nau8824_i2c_ids[] = { 1847 { "nau8824", 0 }, 1848 { } 1849 }; 1850 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); 1851 1852 #ifdef CONFIG_OF 1853 static const struct of_device_id nau8824_of_ids[] = { 1854 { .compatible = "nuvoton,nau8824", }, 1855 {} 1856 }; 1857 MODULE_DEVICE_TABLE(of, nau8824_of_ids); 1858 #endif 1859 1860 #ifdef CONFIG_ACPI 1861 static const struct acpi_device_id nau8824_acpi_match[] = { 1862 { "10508824", 0 }, 1863 {}, 1864 }; 1865 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); 1866 #endif 1867 1868 static struct i2c_driver nau8824_i2c_driver = { 1869 .driver = { 1870 .name = "nau8824", 1871 .of_match_table = of_match_ptr(nau8824_of_ids), 1872 .acpi_match_table = ACPI_PTR(nau8824_acpi_match), 1873 }, 1874 .probe = nau8824_i2c_probe, 1875 .remove = nau8824_i2c_remove, 1876 .id_table = nau8824_i2c_ids, 1877 }; 1878 module_i2c_driver(nau8824_i2c_driver); 1879 1880 1881 MODULE_DESCRIPTION("ASoC NAU88L24 driver"); 1882 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 1883 MODULE_LICENSE("GPL v2"); 1884