1 /* 2 * NAU88L24 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/clk.h> 19 #include <linux/acpi.h> 20 #include <linux/math64.h> 21 #include <linux/semaphore.h> 22 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 31 #include "nau8824.h" 32 33 34 static int nau8824_config_sysclk(struct nau8824 *nau8824, 35 int clk_id, unsigned int freq); 36 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); 37 38 /* the ADC threshold of headset */ 39 #define DMIC_CLK 3072000 40 41 /* the ADC threshold of headset */ 42 #define HEADSET_SARADC_THD 0x80 43 44 /* the parameter threshold of FLL */ 45 #define NAU_FREF_MAX 13500000 46 #define NAU_FVCO_MAX 100000000 47 #define NAU_FVCO_MIN 90000000 48 49 /* scaling for mclk from sysclk_src output */ 50 static const struct nau8824_fll_attr mclk_src_scaling[] = { 51 { 1, 0x0 }, 52 { 2, 0x2 }, 53 { 4, 0x3 }, 54 { 8, 0x4 }, 55 { 16, 0x5 }, 56 { 32, 0x6 }, 57 { 3, 0x7 }, 58 { 6, 0xa }, 59 { 12, 0xb }, 60 { 24, 0xc }, 61 }; 62 63 /* ratio for input clk freq */ 64 static const struct nau8824_fll_attr fll_ratio[] = { 65 { 512000, 0x01 }, 66 { 256000, 0x02 }, 67 { 128000, 0x04 }, 68 { 64000, 0x08 }, 69 { 32000, 0x10 }, 70 { 8000, 0x20 }, 71 { 4000, 0x40 }, 72 }; 73 74 static const struct nau8824_fll_attr fll_pre_scalar[] = { 75 { 1, 0x0 }, 76 { 2, 0x1 }, 77 { 4, 0x2 }, 78 { 8, 0x3 }, 79 }; 80 81 /* the maximum frequency of CLK_ADC and CLK_DAC */ 82 #define CLK_DA_AD_MAX 6144000 83 84 /* over sampling rate */ 85 static const struct nau8824_osr_attr osr_dac_sel[] = { 86 { 64, 2 }, /* OSR 64, SRC 1/4 */ 87 { 256, 0 }, /* OSR 256, SRC 1 */ 88 { 128, 1 }, /* OSR 128, SRC 1/2 */ 89 { 0, 0 }, 90 { 32, 3 }, /* OSR 32, SRC 1/8 */ 91 }; 92 93 static const struct nau8824_osr_attr osr_adc_sel[] = { 94 { 32, 3 }, /* OSR 32, SRC 1/8 */ 95 { 64, 2 }, /* OSR 64, SRC 1/4 */ 96 { 128, 1 }, /* OSR 128, SRC 1/2 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 }; 99 100 static const struct reg_default nau8824_reg_defaults[] = { 101 { NAU8824_REG_ENA_CTRL, 0x0000 }, 102 { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, 103 { NAU8824_REG_CLK_DIVIDER, 0x0000 }, 104 { NAU8824_REG_FLL1, 0x0000 }, 105 { NAU8824_REG_FLL2, 0x3126 }, 106 { NAU8824_REG_FLL3, 0x0008 }, 107 { NAU8824_REG_FLL4, 0x0010 }, 108 { NAU8824_REG_FLL5, 0xC000 }, 109 { NAU8824_REG_FLL6, 0x6000 }, 110 { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, 111 { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, 112 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, 113 { NAU8824_REG_IRQ, 0x0000 }, 114 { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, 115 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, 116 { NAU8824_REG_SAR_ADC, 0x0015 }, 117 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, 118 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, 119 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, 120 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, 121 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, 122 { NAU8824_REG_GPIO_SEL, 0x0000 }, 123 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, 124 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, 125 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, 126 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, 127 { NAU8824_REG_TDM_CTRL, 0x0000 }, 128 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, 129 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, 130 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, 131 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, 132 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, 133 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, 134 { NAU8824_REG_EQ1_LOW, 0x112C }, 135 { NAU8824_REG_EQ2_EQ3, 0x2C2C }, 136 { NAU8824_REG_EQ4_EQ5, 0x2C2C }, 137 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, 138 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, 139 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, 140 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, 141 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, 142 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, 143 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, 144 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, 145 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, 146 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, 147 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, 148 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, 149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, 150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, 151 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, 152 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, 153 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, 154 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, 155 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, 156 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, 157 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, 158 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, 159 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, 160 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, 161 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, 162 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, 163 { NAU8824_REG_MODE, 0x0000 }, 164 { NAU8824_REG_MODE1, 0x0000 }, 165 { NAU8824_REG_MODE2, 0x0000 }, 166 { NAU8824_REG_CLASSG, 0x0000 }, 167 { NAU8824_REG_OTP_EFUSE, 0x0000 }, 168 { NAU8824_REG_OTPDOUT_1, 0x0000 }, 169 { NAU8824_REG_OTPDOUT_2, 0x0000 }, 170 { NAU8824_REG_MISC_CTRL, 0x0000 }, 171 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, 172 { NAU8824_REG_TEST_MODE, 0x0000 }, 173 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, 174 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, 175 { NAU8824_REG_BIAS_ADJ, 0x0000 }, 176 { NAU8824_REG_PGA_GAIN, 0x0000 }, 177 { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, 178 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, 179 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, 180 { NAU8824_REG_ENABLE_LO, 0x0000 }, 181 { NAU8824_REG_GAIN_LO, 0x0000 }, 182 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, 183 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, 184 { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, 185 { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, 186 { NAU8824_REG_RDAC, 0x0008 }, 187 { NAU8824_REG_MIC_BIAS, 0x0006 }, 188 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, 189 { NAU8824_REG_BOOST, 0x0000 }, 190 { NAU8824_REG_FEPGA, 0x0000 }, 191 { NAU8824_REG_FEPGA_II, 0x0000 }, 192 { NAU8824_REG_FEPGA_SE, 0x0000 }, 193 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, 194 { NAU8824_REG_ATT_PORT0, 0x0000 }, 195 { NAU8824_REG_ATT_PORT1, 0x0000 }, 196 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, 197 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, 198 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, 199 }; 200 201 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) 202 { 203 int ret; 204 205 if (timeout) { 206 ret = down_timeout(&nau8824->jd_sem, timeout); 207 if (ret < 0) 208 dev_warn(nau8824->dev, "Acquire semaphone timeout\n"); 209 } else { 210 ret = down_interruptible(&nau8824->jd_sem); 211 if (ret < 0) 212 dev_warn(nau8824->dev, "Acquire semaphone fail\n"); 213 } 214 215 return ret; 216 } 217 218 static inline void nau8824_sema_release(struct nau8824 *nau8824) 219 { 220 up(&nau8824->jd_sem); 221 } 222 223 static bool nau8824_readable_reg(struct device *dev, unsigned int reg) 224 { 225 switch (reg) { 226 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: 227 case NAU8824_REG_JACK_DET_CTRL: 228 case NAU8824_REG_INTERRUPT_SETTING_1: 229 case NAU8824_REG_IRQ: 230 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 231 case NAU8824_REG_GPIO_SEL: 232 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 233 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 234 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 235 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: 236 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: 237 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 238 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 239 case NAU8824_REG_I2C_TIMEOUT: 240 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 241 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 242 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 243 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: 244 return true; 245 default: 246 return false; 247 } 248 249 } 250 251 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: 255 case NAU8824_REG_JACK_DET_CTRL: 256 case NAU8824_REG_INTERRUPT_SETTING_1: 257 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 258 case NAU8824_REG_GPIO_SEL: 259 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 260 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 261 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 262 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: 263 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: 264 case NAU8824_REG_DRC_SLOPE_ADC_CH01: 265 case NAU8824_REG_DRC_ATKDCY_ADC_CH01: 266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: 267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: 268 case NAU8824_REG_DRC_SLOPE_ADC_CH23: 269 case NAU8824_REG_DRC_ATKDCY_ADC_CH23: 270 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: 271 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 272 case NAU8824_REG_I2C_TIMEOUT: 273 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 274 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 275 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case NAU8824_REG_RESET: 286 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: 287 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: 288 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: 289 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 290 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 291 case NAU8824_REG_CHARGE_PUMP_INPUT: 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static const char * const nau8824_companding[] = { 299 "Off", "NC", "u-law", "A-law" }; 300 301 static const struct soc_enum nau8824_companding_adc_enum = 302 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, 303 ARRAY_SIZE(nau8824_companding), nau8824_companding); 304 305 static const struct soc_enum nau8824_companding_dac_enum = 306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, 307 ARRAY_SIZE(nau8824_companding), nau8824_companding); 308 309 static const char * const nau8824_adc_decimation[] = { 310 "32", "64", "128", "256" }; 311 312 static const struct soc_enum nau8824_adc_decimation_enum = 313 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, 314 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); 315 316 static const char * const nau8824_dac_oversampl[] = { 317 "64", "256", "128", "", "32" }; 318 319 static const struct soc_enum nau8824_dac_oversampl_enum = 320 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, 321 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); 322 323 static const char * const nau8824_input_channel[] = { 324 "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; 325 326 static const struct soc_enum nau8824_adc_ch0_enum = 327 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, 328 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 329 330 static const struct soc_enum nau8824_adc_ch1_enum = 331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, 332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 333 334 static const struct soc_enum nau8824_adc_ch2_enum = 335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, 336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 337 338 static const struct soc_enum nau8824_adc_ch3_enum = 339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, 340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 341 342 static const char * const nau8824_tdm_slot[] = { 343 "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; 344 345 static const struct soc_enum nau8824_dac_left_sel_enum = 346 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, 347 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 348 349 static const struct soc_enum nau8824_dac_right_sel_enum = 350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, 351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 352 353 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); 354 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); 355 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); 356 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); 357 358 static const struct snd_kcontrol_new nau8824_snd_controls[] = { 359 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), 360 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), 361 362 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), 363 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), 364 365 SOC_SINGLE_TLV("Speaker Right DACR Volume", 366 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), 367 SOC_SINGLE_TLV("Speaker Left DACL Volume", 368 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), 369 SOC_SINGLE_TLV("Speaker Left DACR Volume", 370 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), 371 SOC_SINGLE_TLV("Speaker Right DACL Volume", 372 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), 373 374 SOC_SINGLE_TLV("Headphone Right DACR Volume", 375 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), 376 SOC_SINGLE_TLV("Headphone Left DACL Volume", 377 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), 378 SOC_SINGLE_TLV("Headphone Right DACL Volume", 379 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), 380 SOC_SINGLE_TLV("Headphone Left DACR Volume", 381 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), 382 383 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, 384 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), 385 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, 386 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), 387 388 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, 389 0, 0x164, 0, dmic_vol_tlv), 390 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, 391 0, 0x164, 0, dmic_vol_tlv), 392 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, 393 0, 0x164, 0, dmic_vol_tlv), 394 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, 395 0, 0x164, 0, dmic_vol_tlv), 396 397 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), 398 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), 399 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), 400 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), 401 402 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), 403 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), 404 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), 405 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), 406 407 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), 408 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), 409 410 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), 411 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), 412 }; 413 414 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, 415 struct snd_kcontrol *kcontrol, int event) 416 { 417 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 418 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 419 420 switch (event) { 421 case SND_SOC_DAPM_PRE_PMU: 422 /* Disables the TESTDAC to let DAC signal pass through. */ 423 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 424 NAU8824_TEST_DAC_EN, 0); 425 break; 426 case SND_SOC_DAPM_POST_PMD: 427 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 428 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int nau8824_spk_event(struct snd_soc_dapm_widget *w, 438 struct snd_kcontrol *kcontrol, int event) 439 { 440 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 441 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 442 443 switch (event) { 444 case SND_SOC_DAPM_PRE_PMU: 445 regmap_update_bits(nau8824->regmap, 446 NAU8824_REG_ANALOG_CONTROL_2, 447 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); 448 break; 449 case SND_SOC_DAPM_POST_PMD: 450 regmap_update_bits(nau8824->regmap, 451 NAU8824_REG_ANALOG_CONTROL_2, 452 NAU8824_CLASSD_CLAMP_DIS, 0); 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static int nau8824_pump_event(struct snd_soc_dapm_widget *w, 462 struct snd_kcontrol *kcontrol, int event) 463 { 464 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 465 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 466 467 switch (event) { 468 case SND_SOC_DAPM_POST_PMU: 469 /* Prevent startup click by letting charge pump to ramp up */ 470 msleep(10); 471 regmap_update_bits(nau8824->regmap, 472 NAU8824_REG_CHARGE_PUMP_CONTROL, 473 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); 474 break; 475 case SND_SOC_DAPM_PRE_PMD: 476 regmap_update_bits(nau8824->regmap, 477 NAU8824_REG_CHARGE_PUMP_CONTROL, 478 NAU8824_JAMNODCLOW, 0); 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static int system_clock_control(struct snd_soc_dapm_widget *w, 488 struct snd_kcontrol *k, int event) 489 { 490 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 491 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 492 493 if (SND_SOC_DAPM_EVENT_OFF(event)) { 494 /* Set clock source to disable or internal clock before the 495 * playback or capture end. Codec needs clock for Jack 496 * detection and button press if jack inserted; otherwise, 497 * the clock should be closed. 498 */ 499 if (nau8824_is_jack_inserted(nau8824)) { 500 nau8824_config_sysclk(nau8824, 501 NAU8824_CLK_INTERNAL, 0); 502 } else { 503 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 504 } 505 } 506 return 0; 507 } 508 509 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 510 struct snd_kcontrol *k, int event) 511 { 512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 513 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 514 int src; 515 516 /* The DMIC clock is gotten from system clock (256fs) divided by 517 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or 518 * less than 3.072 MHz. 519 */ 520 for (src = 0; src < 5; src++) { 521 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) 522 break; 523 } 524 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); 525 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 526 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); 527 528 return 0; 529 } 530 531 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = 532 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 533 NAU8824_ADC_CH0_DMIC_SFT, 1, 0); 534 535 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = 536 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 537 NAU8824_ADC_CH1_DMIC_SFT, 1, 0); 538 539 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = 540 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 541 NAU8824_ADC_CH2_DMIC_SFT, 1, 0); 542 543 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = 544 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 545 NAU8824_ADC_CH3_DMIC_SFT, 1, 0); 546 547 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { 548 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 549 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), 550 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 551 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), 552 }; 553 554 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { 555 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 556 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), 557 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 558 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), 559 }; 560 561 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { 562 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 563 NAU8824_DACR_HPL_EN_SFT, 1, 0), 564 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 565 NAU8824_DACL_HPL_EN_SFT, 1, 0), 566 }; 567 568 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { 569 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 570 NAU8824_DACL_HPR_EN_SFT, 1, 0), 571 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 572 NAU8824_DACR_HPR_EN_SFT, 1, 0), 573 }; 574 575 static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; 576 577 static SOC_ENUM_SINGLE_DECL( 578 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 579 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); 580 581 static SOC_ENUM_SINGLE_DECL( 582 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 583 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); 584 585 static const struct snd_kcontrol_new nau8824_dacl_mux = 586 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); 587 588 static const struct snd_kcontrol_new nau8824_dacr_mux = 589 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); 590 591 592 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { 593 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 594 system_clock_control, SND_SOC_DAPM_POST_PMD), 595 596 SND_SOC_DAPM_INPUT("HSMIC1"), 597 SND_SOC_DAPM_INPUT("HSMIC2"), 598 SND_SOC_DAPM_INPUT("MIC1"), 599 SND_SOC_DAPM_INPUT("MIC2"), 600 SND_SOC_DAPM_INPUT("DMIC1"), 601 SND_SOC_DAPM_INPUT("DMIC2"), 602 SND_SOC_DAPM_INPUT("DMIC3"), 603 SND_SOC_DAPM_INPUT("DMIC4"), 604 605 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, 606 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), 607 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, 608 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), 609 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, 610 NAU8824_DMIC1_EN_SFT, 0, NULL, 0), 611 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, 612 NAU8824_DMIC2_EN_SFT, 0, NULL, 0), 613 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 614 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 615 616 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, 617 0, 0, &nau8824_adc_ch0_dmic), 618 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, 619 0, 0, &nau8824_adc_ch1_dmic), 620 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, 621 0, 0, &nau8824_adc_ch2_dmic), 622 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, 623 0, 0, &nau8824_adc_ch3_dmic), 624 625 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, 626 12, 0, nau8824_adc_left_mixer, 627 ARRAY_SIZE(nau8824_adc_left_mixer)), 628 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, 629 13, 0, nau8824_adc_right_mixer, 630 ARRAY_SIZE(nau8824_adc_right_mixer)), 631 632 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, 633 NAU8824_ADCL_EN_SFT, 0), 634 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, 635 NAU8824_ADCR_EN_SFT, 0), 636 637 SND_SOC_DAPM_AIF_OUT("AIFTX", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 638 SND_SOC_DAPM_AIF_IN("AIFRX", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 639 640 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, 641 NAU8824_DACL_EN_SFT, 0), 642 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, 643 NAU8824_DACL_CLK_SFT, 0, NULL, 0), 644 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, 645 NAU8824_DACR_EN_SFT, 0), 646 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, 647 NAU8824_DACR_CLK_SFT, 0, NULL, 0), 648 649 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), 650 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), 651 652 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 653 8, 1, nau8824_output_dac_event, 654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 655 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 656 9, 1, nau8824_output_dac_event, 657 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 658 659 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, 660 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, 661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 662 663 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, 664 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, 665 ARRAY_SIZE(nau8824_hp_left_mixer)), 666 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, 667 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, 668 ARRAY_SIZE(nau8824_hp_right_mixer)), 669 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, 670 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, 671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 672 SND_SOC_DAPM_PGA("Output Driver L", 673 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 674 SND_SOC_DAPM_PGA("Output Driver R", 675 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 676 SND_SOC_DAPM_PGA("Main Driver L", 677 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 678 SND_SOC_DAPM_PGA("Main Driver R", 679 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 680 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, 681 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), 682 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, 683 NAU8824_CLASSG_EN_SFT, 0, NULL, 0), 684 685 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 686 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 687 SND_SOC_DAPM_OUTPUT("HPOL"), 688 SND_SOC_DAPM_OUTPUT("HPOR"), 689 }; 690 691 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { 692 {"DMIC1 Enable", "Switch", "DMIC1"}, 693 {"DMIC2 Enable", "Switch", "DMIC2"}, 694 {"DMIC3 Enable", "Switch", "DMIC3"}, 695 {"DMIC4 Enable", "Switch", "DMIC4"}, 696 697 {"DMIC1", NULL, "DMIC12 Power"}, 698 {"DMIC2", NULL, "DMIC12 Power"}, 699 {"DMIC3", NULL, "DMIC34 Power"}, 700 {"DMIC4", NULL, "DMIC34 Power"}, 701 {"DMIC12 Power", NULL, "DMIC Clock"}, 702 {"DMIC34 Power", NULL, "DMIC Clock"}, 703 704 {"Left ADC", "MIC Switch", "MIC1"}, 705 {"Left ADC", "HSMIC Switch", "HSMIC1"}, 706 {"Right ADC", "MIC Switch", "MIC2"}, 707 {"Right ADC", "HSMIC Switch", "HSMIC2"}, 708 709 {"ADCL", NULL, "Left ADC"}, 710 {"ADCR", NULL, "Right ADC"}, 711 712 {"AIFTX", NULL, "MICBIAS"}, 713 {"AIFTX", NULL, "ADCL"}, 714 {"AIFTX", NULL, "ADCR"}, 715 {"AIFTX", NULL, "DMIC1 Enable"}, 716 {"AIFTX", NULL, "DMIC2 Enable"}, 717 {"AIFTX", NULL, "DMIC3 Enable"}, 718 {"AIFTX", NULL, "DMIC4 Enable"}, 719 720 {"AIFTX", NULL, "System Clock"}, 721 {"AIFRX", NULL, "System Clock"}, 722 723 {"DACL", NULL, "AIFRX"}, 724 {"DACL", NULL, "DACL Clock"}, 725 {"DACR", NULL, "AIFRX"}, 726 {"DACR", NULL, "DACR Clock"}, 727 728 {"DACL Mux", "DACL", "DACL"}, 729 {"DACL Mux", "DACR", "DACR"}, 730 {"DACR Mux", "DACL", "DACL"}, 731 {"DACR Mux", "DACR", "DACR"}, 732 733 {"Output DACL", NULL, "DACL Mux"}, 734 {"Output DACR", NULL, "DACR Mux"}, 735 736 {"ClassD", NULL, "Output DACL"}, 737 {"ClassD", NULL, "Output DACR"}, 738 739 {"Left Headphone", "DAC Left Switch", "Output DACL"}, 740 {"Left Headphone", "DAC Right Switch", "Output DACR"}, 741 {"Right Headphone", "DAC Left Switch", "Output DACL"}, 742 {"Right Headphone", "DAC Right Switch", "Output DACR"}, 743 744 {"Charge Pump", NULL, "Left Headphone"}, 745 {"Charge Pump", NULL, "Right Headphone"}, 746 {"Output Driver L", NULL, "Charge Pump"}, 747 {"Output Driver R", NULL, "Charge Pump"}, 748 {"Main Driver L", NULL, "Output Driver L"}, 749 {"Main Driver R", NULL, "Output Driver R"}, 750 {"Class G", NULL, "Main Driver L"}, 751 {"Class G", NULL, "Main Driver R"}, 752 {"HP Boost Driver", NULL, "Class G"}, 753 754 {"SPKOUTL", NULL, "ClassD"}, 755 {"SPKOUTR", NULL, "ClassD"}, 756 {"HPOL", NULL, "HP Boost Driver"}, 757 {"HPOR", NULL, "HP Boost Driver"}, 758 }; 759 760 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) 761 { 762 struct snd_soc_jack *jack = nau8824->jack; 763 bool insert = FALSE; 764 765 if (nau8824->irq && jack) 766 insert = jack->status & SND_JACK_HEADPHONE; 767 768 return insert; 769 } 770 771 static void nau8824_int_status_clear_all(struct regmap *regmap) 772 { 773 int active_irq, clear_irq, i; 774 775 /* Reset the intrruption status from rightmost bit if the corres- 776 * ponding irq event occurs. 777 */ 778 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); 779 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { 780 clear_irq = (0x1 << i); 781 if (active_irq & clear_irq) 782 regmap_write(regmap, 783 NAU8824_REG_CLEAR_INT_REG, clear_irq); 784 } 785 } 786 787 static void nau8824_eject_jack(struct nau8824 *nau8824) 788 { 789 struct snd_soc_dapm_context *dapm = nau8824->dapm; 790 struct regmap *regmap = nau8824->regmap; 791 792 /* Clear all interruption status */ 793 nau8824_int_status_clear_all(regmap); 794 795 snd_soc_dapm_disable_pin(dapm, "SAR"); 796 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 797 snd_soc_dapm_sync(dapm); 798 799 /* Enable the insertion interruption, disable the ejection 800 * interruption, and then bypass de-bounce circuit. 801 */ 802 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 803 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 804 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 805 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 806 NAU8824_IRQ_EJECT_DIS); 807 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 808 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 809 NAU8824_IRQ_INSERT_EN); 810 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 811 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 812 813 /* Close clock for jack type detection at manual mode */ 814 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 815 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 816 } 817 818 static void nau8824_jdet_work(struct work_struct *work) 819 { 820 struct nau8824 *nau8824 = container_of( 821 work, struct nau8824, jdet_work); 822 struct snd_soc_dapm_context *dapm = nau8824->dapm; 823 struct regmap *regmap = nau8824->regmap; 824 int adc_value, event = 0, event_mask = 0; 825 826 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 827 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 828 snd_soc_dapm_sync(dapm); 829 830 msleep(100); 831 832 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); 833 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; 834 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); 835 if (adc_value < HEADSET_SARADC_THD) { 836 event |= SND_JACK_HEADPHONE; 837 838 snd_soc_dapm_disable_pin(dapm, "SAR"); 839 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 840 snd_soc_dapm_sync(dapm); 841 } else { 842 event |= SND_JACK_HEADSET; 843 } 844 event_mask |= SND_JACK_HEADSET; 845 snd_soc_jack_report(nau8824->jack, event, event_mask); 846 847 /* Enable short key press and release interruption. */ 848 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 849 NAU8824_IRQ_KEY_RELEASE_DIS | 850 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); 851 852 nau8824_sema_release(nau8824); 853 } 854 855 static void nau8824_setup_auto_irq(struct nau8824 *nau8824) 856 { 857 struct regmap *regmap = nau8824->regmap; 858 859 /* Enable jack ejection interruption. */ 860 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 861 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 862 NAU8824_IRQ_EJECT_EN); 863 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 864 NAU8824_IRQ_EJECT_DIS, 0); 865 /* Enable internal VCO needed for interruptions */ 866 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE) 867 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); 868 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 869 NAU8824_JD_SLEEP_MODE, 0); 870 } 871 872 static int nau8824_button_decode(int value) 873 { 874 int buttons = 0; 875 876 /* The chip supports up to 8 buttons, but ALSA defines 877 * only 6 buttons. 878 */ 879 if (value & BIT(0)) 880 buttons |= SND_JACK_BTN_0; 881 if (value & BIT(1)) 882 buttons |= SND_JACK_BTN_1; 883 if (value & BIT(2)) 884 buttons |= SND_JACK_BTN_2; 885 if (value & BIT(3)) 886 buttons |= SND_JACK_BTN_3; 887 if (value & BIT(4)) 888 buttons |= SND_JACK_BTN_4; 889 if (value & BIT(5)) 890 buttons |= SND_JACK_BTN_5; 891 892 return buttons; 893 } 894 895 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 896 SND_JACK_BTN_2 | SND_JACK_BTN_3) 897 898 static irqreturn_t nau8824_interrupt(int irq, void *data) 899 { 900 struct nau8824 *nau8824 = (struct nau8824 *)data; 901 struct regmap *regmap = nau8824->regmap; 902 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 903 904 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { 905 dev_err(nau8824->dev, "failed to read irq status\n"); 906 return IRQ_NONE; 907 } 908 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); 909 910 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { 911 nau8824_eject_jack(nau8824); 912 event_mask |= SND_JACK_HEADSET; 913 clear_irq = NAU8824_JACK_EJECTION_DETECTED; 914 /* release semaphore held after resume, 915 * and cancel jack detection 916 */ 917 nau8824_sema_release(nau8824); 918 cancel_work_sync(&nau8824->jdet_work); 919 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { 920 int key_status, button_pressed; 921 922 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, 923 &key_status); 924 925 /* lower 8 bits of the register are for pressed keys */ 926 button_pressed = nau8824_button_decode(key_status); 927 928 event |= button_pressed; 929 dev_dbg(nau8824->dev, "button %x pressed\n", event); 930 event_mask |= NAU8824_BUTTONS; 931 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; 932 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { 933 event_mask = NAU8824_BUTTONS; 934 clear_irq = NAU8824_KEY_RELEASE_IRQ; 935 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { 936 /* Turn off insertion interruption at manual mode */ 937 regmap_update_bits(regmap, 938 NAU8824_REG_INTERRUPT_SETTING, 939 NAU8824_IRQ_INSERT_DIS, 940 NAU8824_IRQ_INSERT_DIS); 941 regmap_update_bits(regmap, 942 NAU8824_REG_INTERRUPT_SETTING_1, 943 NAU8824_IRQ_INSERT_EN, 0); 944 /* detect microphone and jack type */ 945 cancel_work_sync(&nau8824->jdet_work); 946 schedule_work(&nau8824->jdet_work); 947 948 /* Enable interruption for jack type detection at audo 949 * mode which can detect microphone and jack type. 950 */ 951 nau8824_setup_auto_irq(nau8824); 952 } 953 954 if (!clear_irq) 955 clear_irq = active_irq; 956 /* clears the rightmost interruption */ 957 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); 958 959 if (event_mask) 960 snd_soc_jack_report(nau8824->jack, event, event_mask); 961 962 return IRQ_HANDLED; 963 } 964 965 static int nau8824_clock_check(struct nau8824 *nau8824, 966 int stream, int rate, int osr) 967 { 968 int osrate; 969 970 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 971 if (osr >= ARRAY_SIZE(osr_dac_sel)) 972 return -EINVAL; 973 osrate = osr_dac_sel[osr].osr; 974 } else { 975 if (osr >= ARRAY_SIZE(osr_adc_sel)) 976 return -EINVAL; 977 osrate = osr_adc_sel[osr].osr; 978 } 979 980 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 981 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 982 return -EINVAL; 983 } 984 985 return 0; 986 } 987 988 static int nau8824_hw_params(struct snd_pcm_substream *substream, 989 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 990 { 991 struct snd_soc_codec *codec = dai->codec; 992 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 993 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 994 995 nau8824_sema_acquire(nau8824, HZ); 996 997 /* CLK_DAC or CLK_ADC = OSR * FS 998 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 999 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1000 * values must be selected such that the maximum frequency is less 1001 * than 6.144 MHz. 1002 */ 1003 nau8824->fs = params_rate(params); 1004 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1005 regmap_read(nau8824->regmap, 1006 NAU8824_REG_DAC_FILTER_CTRL_1, &osr); 1007 osr &= NAU8824_DAC_OVERSAMPLE_MASK; 1008 if (nau8824_clock_check(nau8824, substream->stream, 1009 nau8824->fs, osr)) 1010 return -EINVAL; 1011 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1012 NAU8824_CLK_DAC_SRC_MASK, 1013 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); 1014 } else { 1015 regmap_read(nau8824->regmap, 1016 NAU8824_REG_ADC_FILTER_CTRL, &osr); 1017 osr &= NAU8824_ADC_SYNC_DOWN_MASK; 1018 if (nau8824_clock_check(nau8824, substream->stream, 1019 nau8824->fs, osr)) 1020 return -EINVAL; 1021 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1022 NAU8824_CLK_ADC_SRC_MASK, 1023 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); 1024 } 1025 1026 /* make BCLK and LRC divde configuration if the codec as master. */ 1027 regmap_read(nau8824->regmap, 1028 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); 1029 if (ctrl_val & NAU8824_I2S_MS_MASTER) { 1030 /* get the bclk and fs ratio */ 1031 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; 1032 if (bclk_fs <= 32) 1033 bclk_div = 0x3; 1034 else if (bclk_fs <= 64) 1035 bclk_div = 0x2; 1036 else if (bclk_fs <= 128) 1037 bclk_div = 0x1; 1038 else if (bclk_fs <= 256) 1039 bclk_div = 0; 1040 else 1041 return -EINVAL; 1042 regmap_update_bits(nau8824->regmap, 1043 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1044 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, 1045 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); 1046 } 1047 1048 switch (params_width(params)) { 1049 case 16: 1050 val_len |= NAU8824_I2S_DL_16; 1051 break; 1052 case 20: 1053 val_len |= NAU8824_I2S_DL_20; 1054 break; 1055 case 24: 1056 val_len |= NAU8824_I2S_DL_24; 1057 break; 1058 case 32: 1059 val_len |= NAU8824_I2S_DL_32; 1060 break; 1061 default: 1062 return -EINVAL; 1063 } 1064 1065 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1066 NAU8824_I2S_DL_MASK, val_len); 1067 1068 nau8824_sema_release(nau8824); 1069 1070 return 0; 1071 } 1072 1073 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1074 { 1075 struct snd_soc_codec *codec = dai->codec; 1076 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1077 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1078 1079 nau8824_sema_acquire(nau8824, HZ); 1080 1081 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1082 case SND_SOC_DAIFMT_CBM_CFM: 1083 ctrl2_val |= NAU8824_I2S_MS_MASTER; 1084 break; 1085 case SND_SOC_DAIFMT_CBS_CFS: 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 1091 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1092 case SND_SOC_DAIFMT_NB_NF: 1093 break; 1094 case SND_SOC_DAIFMT_IB_NF: 1095 ctrl1_val |= NAU8824_I2S_BP_INV; 1096 break; 1097 default: 1098 return -EINVAL; 1099 } 1100 1101 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1102 case SND_SOC_DAIFMT_I2S: 1103 ctrl1_val |= NAU8824_I2S_DF_I2S; 1104 break; 1105 case SND_SOC_DAIFMT_LEFT_J: 1106 ctrl1_val |= NAU8824_I2S_DF_LEFT; 1107 break; 1108 case SND_SOC_DAIFMT_RIGHT_J: 1109 ctrl1_val |= NAU8824_I2S_DF_RIGTH; 1110 break; 1111 case SND_SOC_DAIFMT_DSP_A: 1112 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1113 break; 1114 case SND_SOC_DAIFMT_DSP_B: 1115 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1116 ctrl1_val |= NAU8824_I2S_PCMB_EN; 1117 break; 1118 default: 1119 return -EINVAL; 1120 } 1121 1122 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1123 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | 1124 NAU8824_I2S_PCMB_EN, ctrl1_val); 1125 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1126 NAU8824_I2S_MS_MASK, ctrl2_val); 1127 1128 nau8824_sema_release(nau8824); 1129 1130 return 0; 1131 } 1132 1133 /** 1134 * nau8824_set_tdm_slot - configure DAI TDM. 1135 * @dai: DAI 1136 * @tx_mask: Bitmask representing active TX slots. Ex. 1137 * 0xf for normal 4 channel TDM. 1138 * 0xf0 for shifted 4 channel TDM 1139 * @rx_mask: Bitmask [0:1] representing active DACR RX slots. 1140 * Bitmask [2:3] representing active DACL RX slots. 1141 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. 1142 * 0xf for DACL/R selecting TDM CH3. 1143 * 0xf0 for DACL/R selecting shifted TDM CH3. 1144 * @slots: Number of slots in use. 1145 * @slot_width: Width in bits for each slot. 1146 * 1147 * Configures a DAI for TDM operation. Only support 4 slots TDM. 1148 */ 1149 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, 1150 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1151 { 1152 struct snd_soc_codec *codec = dai->codec; 1153 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1154 unsigned int tslot_l = 0, ctrl_val = 0; 1155 1156 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || 1157 ((rx_mask & 0xf0) && (rx_mask & 0xf)) || 1158 ((rx_mask & 0xf0) && (tx_mask & 0xf)) || 1159 ((rx_mask & 0xf) && (tx_mask & 0xf0))) 1160 return -EINVAL; 1161 1162 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); 1163 if (tx_mask & 0xf0) { 1164 tslot_l = 4 * slot_width; 1165 ctrl_val |= (tx_mask >> 4); 1166 } else { 1167 ctrl_val |= tx_mask; 1168 } 1169 if (rx_mask & 0xf0) 1170 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); 1171 else 1172 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); 1173 1174 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, 1175 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | 1176 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | 1177 NAU8824_TDM_TX_MASK, ctrl_val); 1178 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, 1179 NAU8824_TSLOT_L_MASK, tslot_l); 1180 1181 return 0; 1182 } 1183 1184 /** 1185 * nau8824_calc_fll_param - Calculate FLL parameters. 1186 * @fll_in: external clock provided to codec. 1187 * @fs: sampling rate. 1188 * @fll_param: Pointer to structure of FLL parameters. 1189 * 1190 * Calculate FLL parameters to configure codec. 1191 * 1192 * Returns 0 for success or negative error code. 1193 */ 1194 static int nau8824_calc_fll_param(unsigned int fll_in, 1195 unsigned int fs, struct nau8824_fll *fll_param) 1196 { 1197 u64 fvco, fvco_max; 1198 unsigned int fref, i, fvco_sel; 1199 1200 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1201 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1202 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK 1203 */ 1204 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1205 fref = fll_in / fll_pre_scalar[i].param; 1206 if (fref <= NAU_FREF_MAX) 1207 break; 1208 } 1209 if (i == ARRAY_SIZE(fll_pre_scalar)) 1210 return -EINVAL; 1211 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1212 1213 /* Choose the FLL ratio based on FREF */ 1214 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1215 if (fref >= fll_ratio[i].param) 1216 break; 1217 } 1218 if (i == ARRAY_SIZE(fll_ratio)) 1219 return -EINVAL; 1220 fll_param->ratio = fll_ratio[i].val; 1221 1222 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1223 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 1224 * guaranteed across the full range of operation. 1225 * FDCO = freq_out * 2 * mclk_src_scaling 1226 */ 1227 fvco_max = 0; 1228 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1229 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1230 fvco = 256 * fs * 2 * mclk_src_scaling[i].param; 1231 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1232 fvco_max < fvco) { 1233 fvco_max = fvco; 1234 fvco_sel = i; 1235 } 1236 } 1237 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1238 return -EINVAL; 1239 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1240 1241 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 1242 * input based on FDCO, FREF and FLL ratio. 1243 */ 1244 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 1245 fll_param->fll_int = (fvco >> 16) & 0x3FF; 1246 fll_param->fll_frac = fvco & 0xFFFF; 1247 return 0; 1248 } 1249 1250 static void nau8824_fll_apply(struct regmap *regmap, 1251 struct nau8824_fll *fll_param) 1252 { 1253 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1254 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, 1255 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); 1256 regmap_update_bits(regmap, NAU8824_REG_FLL1, 1257 NAU8824_FLL_RATIO_MASK, fll_param->ratio); 1258 /* FLL 16-bit fractional input */ 1259 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); 1260 /* FLL 10-bit integer input */ 1261 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1262 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); 1263 /* FLL pre-scaler */ 1264 regmap_update_bits(regmap, NAU8824_REG_FLL4, 1265 NAU8824_FLL_REF_DIV_MASK, 1266 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); 1267 /* select divided VCO input */ 1268 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1269 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); 1270 /* Disable free-running mode */ 1271 regmap_update_bits(regmap, 1272 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 1273 if (fll_param->fll_frac) { 1274 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1275 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1276 NAU8824_FLL_FTR_SW_MASK, 1277 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1278 NAU8824_FLL_FTR_SW_FILTER); 1279 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1280 NAU8824_SDM_EN, NAU8824_SDM_EN); 1281 } else { 1282 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1283 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1284 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); 1285 regmap_update_bits(regmap, 1286 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); 1287 } 1288 } 1289 1290 /* freq_out must be 256*Fs in order to achieve the best performance */ 1291 static int nau8824_set_pll(struct snd_soc_codec *codec, int pll_id, int source, 1292 unsigned int freq_in, unsigned int freq_out) 1293 { 1294 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1295 struct nau8824_fll fll_param; 1296 int ret, fs; 1297 1298 fs = freq_out / 256; 1299 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); 1300 if (ret < 0) { 1301 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); 1302 return ret; 1303 } 1304 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1305 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 1306 fll_param.fll_int, fll_param.clk_ref_div); 1307 1308 nau8824_fll_apply(nau8824->regmap, &fll_param); 1309 mdelay(2); 1310 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1311 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1312 1313 return 0; 1314 } 1315 1316 static int nau8824_config_sysclk(struct nau8824 *nau8824, 1317 int clk_id, unsigned int freq) 1318 { 1319 struct regmap *regmap = nau8824->regmap; 1320 1321 switch (clk_id) { 1322 case NAU8824_CLK_DIS: 1323 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1324 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1325 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1326 NAU8824_DCO_EN, 0); 1327 break; 1328 1329 case NAU8824_CLK_MCLK: 1330 nau8824_sema_acquire(nau8824, HZ); 1331 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1332 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1333 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1334 NAU8824_DCO_EN, 0); 1335 nau8824_sema_release(nau8824); 1336 break; 1337 1338 case NAU8824_CLK_INTERNAL: 1339 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1340 NAU8824_DCO_EN, NAU8824_DCO_EN); 1341 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1342 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1343 break; 1344 1345 case NAU8824_CLK_FLL_MCLK: 1346 nau8824_sema_acquire(nau8824, HZ); 1347 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1348 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); 1349 nau8824_sema_release(nau8824); 1350 break; 1351 1352 case NAU8824_CLK_FLL_BLK: 1353 nau8824_sema_acquire(nau8824, HZ); 1354 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1355 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); 1356 nau8824_sema_release(nau8824); 1357 break; 1358 1359 case NAU8824_CLK_FLL_FS: 1360 nau8824_sema_acquire(nau8824, HZ); 1361 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1362 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); 1363 nau8824_sema_release(nau8824); 1364 break; 1365 1366 default: 1367 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); 1368 return -EINVAL; 1369 } 1370 1371 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1372 clk_id); 1373 1374 return 0; 1375 } 1376 1377 static int nau8824_set_sysclk(struct snd_soc_codec *codec, 1378 int clk_id, int source, unsigned int freq, int dir) 1379 { 1380 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1381 1382 return nau8824_config_sysclk(nau8824, clk_id, freq); 1383 } 1384 1385 static void nau8824_resume_setup(struct nau8824 *nau8824) 1386 { 1387 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 1388 if (nau8824->irq) { 1389 /* Clear all interruption status */ 1390 nau8824_int_status_clear_all(nau8824->regmap); 1391 /* Enable jack detection at sleep mode, insertion detection, 1392 * and ejection detection. 1393 */ 1394 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1395 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1396 regmap_update_bits(nau8824->regmap, 1397 NAU8824_REG_INTERRUPT_SETTING_1, 1398 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 1399 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); 1400 regmap_update_bits(nau8824->regmap, 1401 NAU8824_REG_INTERRUPT_SETTING, 1402 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); 1403 } 1404 } 1405 1406 static int nau8824_set_bias_level(struct snd_soc_codec *codec, 1407 enum snd_soc_bias_level level) 1408 { 1409 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1410 1411 switch (level) { 1412 case SND_SOC_BIAS_ON: 1413 break; 1414 1415 case SND_SOC_BIAS_PREPARE: 1416 break; 1417 1418 case SND_SOC_BIAS_STANDBY: 1419 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 1420 /* Setup codec configuration after resume */ 1421 nau8824_resume_setup(nau8824); 1422 } 1423 break; 1424 1425 case SND_SOC_BIAS_OFF: 1426 regmap_update_bits(nau8824->regmap, 1427 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1428 regmap_update_bits(nau8824->regmap, 1429 NAU8824_REG_INTERRUPT_SETTING_1, 1430 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1431 break; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int nau8824_codec_probe(struct snd_soc_codec *codec) 1438 { 1439 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1440 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1441 1442 nau8824->dapm = dapm; 1443 1444 return 0; 1445 } 1446 1447 static int __maybe_unused nau8824_suspend(struct snd_soc_codec *codec) 1448 { 1449 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1450 1451 if (nau8824->irq) { 1452 disable_irq(nau8824->irq); 1453 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1454 } 1455 regcache_cache_only(nau8824->regmap, true); 1456 regcache_mark_dirty(nau8824->regmap); 1457 1458 return 0; 1459 } 1460 1461 static int __maybe_unused nau8824_resume(struct snd_soc_codec *codec) 1462 { 1463 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1464 1465 regcache_cache_only(nau8824->regmap, false); 1466 regcache_sync(nau8824->regmap); 1467 if (nau8824->irq) { 1468 /* Hold semaphore to postpone playback happening 1469 * until jack detection done. 1470 */ 1471 nau8824_sema_acquire(nau8824, 0); 1472 enable_irq(nau8824->irq); 1473 } 1474 1475 return 0; 1476 } 1477 1478 static const struct snd_soc_codec_driver nau8824_codec_driver = { 1479 .probe = nau8824_codec_probe, 1480 .set_sysclk = nau8824_set_sysclk, 1481 .set_pll = nau8824_set_pll, 1482 .set_bias_level = nau8824_set_bias_level, 1483 .suspend = nau8824_suspend, 1484 .resume = nau8824_resume, 1485 .suspend_bias_off = true, 1486 1487 .component_driver = { 1488 .controls = nau8824_snd_controls, 1489 .num_controls = ARRAY_SIZE(nau8824_snd_controls), 1490 .dapm_widgets = nau8824_dapm_widgets, 1491 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), 1492 .dapm_routes = nau8824_dapm_routes, 1493 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), 1494 }, 1495 }; 1496 1497 static const struct snd_soc_dai_ops nau8824_dai_ops = { 1498 .hw_params = nau8824_hw_params, 1499 .set_fmt = nau8824_set_fmt, 1500 .set_tdm_slot = nau8824_set_tdm_slot, 1501 }; 1502 1503 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 1504 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1505 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1506 1507 static struct snd_soc_dai_driver nau8824_dai = { 1508 .name = NAU8824_CODEC_DAI, 1509 .playback = { 1510 .stream_name = "Playback", 1511 .channels_min = 1, 1512 .channels_max = 2, 1513 .rates = NAU8824_RATES, 1514 .formats = NAU8824_FORMATS, 1515 }, 1516 .capture = { 1517 .stream_name = "Capture", 1518 .channels_min = 1, 1519 .channels_max = 2, 1520 .rates = NAU8824_RATES, 1521 .formats = NAU8824_FORMATS, 1522 }, 1523 .ops = &nau8824_dai_ops, 1524 }; 1525 1526 static const struct regmap_config nau8824_regmap_config = { 1527 .val_bits = NAU8824_REG_ADDR_LEN, 1528 .reg_bits = NAU8824_REG_DATA_LEN, 1529 1530 .max_register = NAU8824_REG_MAX, 1531 .readable_reg = nau8824_readable_reg, 1532 .writeable_reg = nau8824_writeable_reg, 1533 .volatile_reg = nau8824_volatile_reg, 1534 1535 .cache_type = REGCACHE_RBTREE, 1536 .reg_defaults = nau8824_reg_defaults, 1537 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), 1538 }; 1539 1540 /** 1541 * nau8824_enable_jack_detect - Specify a jack for event reporting 1542 * 1543 * @component: component to register the jack with 1544 * @jack: jack to use to report headset and button events on 1545 * 1546 * After this function has been called the headset insert/remove and button 1547 * events will be routed to the given jack. Jack can be null to stop 1548 * reporting. 1549 */ 1550 int nau8824_enable_jack_detect(struct snd_soc_codec *codec, 1551 struct snd_soc_jack *jack) 1552 { 1553 struct nau8824 *nau8824 = snd_soc_codec_get_drvdata(codec); 1554 int ret; 1555 1556 nau8824->jack = jack; 1557 /* Initiate jack detection work queue */ 1558 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); 1559 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, 1560 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1561 "nau8824", nau8824); 1562 if (ret) { 1563 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", 1564 nau8824->irq, ret); 1565 } 1566 1567 return ret; 1568 } 1569 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); 1570 1571 static void nau8824_reset_chip(struct regmap *regmap) 1572 { 1573 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1574 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1575 } 1576 1577 static void nau8824_setup_buttons(struct nau8824 *nau8824) 1578 { 1579 struct regmap *regmap = nau8824->regmap; 1580 1581 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1582 NAU8824_SAR_TRACKING_GAIN_MASK, 1583 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); 1584 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1585 NAU8824_SAR_COMPARE_TIME_MASK, 1586 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); 1587 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1588 NAU8824_SAR_SAMPLING_TIME_MASK, 1589 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); 1590 1591 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1592 NAU8824_LEVELS_NR_MASK, 1593 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); 1594 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1595 NAU8824_HYSTERESIS_MASK, 1596 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); 1597 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1598 NAU8824_SHORTKEY_DEBOUNCE_MASK, 1599 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); 1600 1601 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, 1602 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); 1603 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, 1604 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); 1605 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, 1606 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); 1607 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, 1608 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); 1609 } 1610 1611 static void nau8824_init_regs(struct nau8824 *nau8824) 1612 { 1613 struct regmap *regmap = nau8824->regmap; 1614 1615 /* Enable Bias/VMID/VMID Tieoff */ 1616 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, 1617 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | 1618 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); 1619 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1620 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); 1621 mdelay(2); 1622 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, 1623 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); 1624 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1625 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1626 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1627 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, 1628 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1629 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); 1630 /* Scaling for ADC and DAC clock */ 1631 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1632 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, 1633 (0x1 << NAU8824_CLK_ADC_SRC_SFT) | 1634 (0x1 << NAU8824_CLK_DAC_SRC_SFT)); 1635 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, 1636 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); 1637 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 1638 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1639 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1640 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, 1641 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1642 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1643 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); 1644 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, 1645 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1646 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1647 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1648 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, 1649 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1650 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1651 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1652 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); 1653 /* Class G timer 64ms */ 1654 regmap_update_bits(regmap, NAU8824_REG_CLASSG, 1655 NAU8824_CLASSG_TIMER_MASK, 1656 0x20 << NAU8824_CLASSG_TIMER_SFT); 1657 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, 1658 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); 1659 /* Disable DACR/L power */ 1660 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, 1661 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1662 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, 1663 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1664 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); 1665 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1666 * signal to avoid any glitches due to power up transients in both 1667 * the analog and digital DAC circuit. 1668 */ 1669 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1670 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 1671 /* Config L/R channel */ 1672 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 1673 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); 1674 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 1675 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); 1676 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1677 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, 1678 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); 1679 /* Default oversampling/decimations settings are unusable 1680 * (audible hiss). Set it to something better. 1681 */ 1682 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, 1683 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); 1684 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, 1685 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, 1686 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); 1687 /* DAC clock delay 2ns, VREF */ 1688 regmap_update_bits(regmap, NAU8824_REG_RDAC, 1689 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, 1690 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | 1691 (0x3 << NAU8824_RDAC_VREF_SFT)); 1692 /* PGA input mode selection */ 1693 regmap_update_bits(regmap, NAU8824_REG_FEPGA, 1694 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, 1695 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); 1696 /* Digital microphone control */ 1697 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, 1698 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, 1699 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); 1700 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, 1701 NAU8824_JACK_LOGIC, 1702 /* jkdet_polarity - 1 is for active-low */ 1703 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); 1704 regmap_update_bits(regmap, 1705 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, 1706 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); 1707 if (nau8824->sar_threshold_num) 1708 nau8824_setup_buttons(nau8824); 1709 } 1710 1711 static int nau8824_setup_irq(struct nau8824 *nau8824) 1712 { 1713 /* Disable interruption before codec initiation done */ 1714 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1715 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1716 regmap_update_bits(nau8824->regmap, 1717 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1718 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, 1719 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1720 1721 return 0; 1722 } 1723 1724 static void nau8824_print_device_properties(struct nau8824 *nau8824) 1725 { 1726 struct device *dev = nau8824->dev; 1727 int i; 1728 1729 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); 1730 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); 1731 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); 1732 1733 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); 1734 for (i = 0; i < nau8824->sar_threshold_num; i++) 1735 dev_dbg(dev, "sar-threshold[%d]=%x\n", i, 1736 nau8824->sar_threshold[i]); 1737 1738 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); 1739 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); 1740 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); 1741 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); 1742 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); 1743 dev_dbg(dev, "jack-eject-debounce: %d\n", 1744 nau8824->jack_eject_debounce); 1745 } 1746 1747 static int nau8824_read_device_properties(struct device *dev, 1748 struct nau8824 *nau8824) { 1749 int ret; 1750 1751 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1752 &nau8824->jkdet_polarity); 1753 if (ret) 1754 nau8824->jkdet_polarity = 1; 1755 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1756 &nau8824->micbias_voltage); 1757 if (ret) 1758 nau8824->micbias_voltage = 6; 1759 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1760 &nau8824->vref_impedance); 1761 if (ret) 1762 nau8824->vref_impedance = 2; 1763 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 1764 &nau8824->sar_threshold_num); 1765 if (ret) 1766 nau8824->sar_threshold_num = 4; 1767 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 1768 nau8824->sar_threshold, nau8824->sar_threshold_num); 1769 if (ret) { 1770 nau8824->sar_threshold[0] = 0x0a; 1771 nau8824->sar_threshold[1] = 0x14; 1772 nau8824->sar_threshold[2] = 0x26; 1773 nau8824->sar_threshold[3] = 0x73; 1774 } 1775 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 1776 &nau8824->sar_hysteresis); 1777 if (ret) 1778 nau8824->sar_hysteresis = 0; 1779 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 1780 &nau8824->sar_voltage); 1781 if (ret) 1782 nau8824->sar_voltage = 6; 1783 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 1784 &nau8824->sar_compare_time); 1785 if (ret) 1786 nau8824->sar_compare_time = 1; 1787 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 1788 &nau8824->sar_sampling_time); 1789 if (ret) 1790 nau8824->sar_sampling_time = 1; 1791 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 1792 &nau8824->key_debounce); 1793 if (ret) 1794 nau8824->key_debounce = 0; 1795 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1796 &nau8824->jack_eject_debounce); 1797 if (ret) 1798 nau8824->jack_eject_debounce = 1; 1799 1800 return 0; 1801 } 1802 1803 static int nau8824_i2c_probe(struct i2c_client *i2c, 1804 const struct i2c_device_id *id) 1805 { 1806 struct device *dev = &i2c->dev; 1807 struct nau8824 *nau8824 = dev_get_platdata(dev); 1808 int ret, value; 1809 1810 if (!nau8824) { 1811 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); 1812 if (!nau8824) 1813 return -ENOMEM; 1814 ret = nau8824_read_device_properties(dev, nau8824); 1815 if (ret) 1816 return ret; 1817 } 1818 i2c_set_clientdata(i2c, nau8824); 1819 1820 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); 1821 if (IS_ERR(nau8824->regmap)) 1822 return PTR_ERR(nau8824->regmap); 1823 nau8824->dev = dev; 1824 nau8824->irq = i2c->irq; 1825 sema_init(&nau8824->jd_sem, 1); 1826 1827 nau8824_print_device_properties(nau8824); 1828 1829 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); 1830 if (ret < 0) { 1831 dev_err(dev, "Failed to read device id from the NAU8824: %d\n", 1832 ret); 1833 return ret; 1834 } 1835 nau8824_reset_chip(nau8824->regmap); 1836 nau8824_init_regs(nau8824); 1837 1838 if (i2c->irq) 1839 nau8824_setup_irq(nau8824); 1840 1841 return snd_soc_register_codec(dev, 1842 &nau8824_codec_driver, &nau8824_dai, 1); 1843 } 1844 1845 1846 static int nau8824_i2c_remove(struct i2c_client *client) 1847 { 1848 snd_soc_unregister_codec(&client->dev); 1849 return 0; 1850 } 1851 1852 static const struct i2c_device_id nau8824_i2c_ids[] = { 1853 { "nau8824", 0 }, 1854 { } 1855 }; 1856 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); 1857 1858 #ifdef CONFIG_OF 1859 static const struct of_device_id nau8824_of_ids[] = { 1860 { .compatible = "nuvoton,nau8824", }, 1861 {} 1862 }; 1863 MODULE_DEVICE_TABLE(of, nau8824_of_ids); 1864 #endif 1865 1866 #ifdef CONFIG_ACPI 1867 static const struct acpi_device_id nau8824_acpi_match[] = { 1868 { "10508824", 0 }, 1869 {}, 1870 }; 1871 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); 1872 #endif 1873 1874 static struct i2c_driver nau8824_i2c_driver = { 1875 .driver = { 1876 .name = "nau8824", 1877 .of_match_table = of_match_ptr(nau8824_of_ids), 1878 .acpi_match_table = ACPI_PTR(nau8824_acpi_match), 1879 }, 1880 .probe = nau8824_i2c_probe, 1881 .remove = nau8824_i2c_remove, 1882 .id_table = nau8824_i2c_ids, 1883 }; 1884 module_i2c_driver(nau8824_i2c_driver); 1885 1886 1887 MODULE_DESCRIPTION("ASoC NAU88L24 driver"); 1888 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 1889 MODULE_LICENSE("GPL v2"); 1890