1 /* 2 * NAU88L24 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/clk.h> 19 #include <linux/acpi.h> 20 #include <linux/math64.h> 21 #include <linux/semaphore.h> 22 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 31 #include "nau8824.h" 32 33 34 static int nau8824_config_sysclk(struct nau8824 *nau8824, 35 int clk_id, unsigned int freq); 36 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); 37 38 /* the ADC threshold of headset */ 39 #define DMIC_CLK 3072000 40 41 /* the ADC threshold of headset */ 42 #define HEADSET_SARADC_THD 0x80 43 44 /* the parameter threshold of FLL */ 45 #define NAU_FREF_MAX 13500000 46 #define NAU_FVCO_MAX 100000000 47 #define NAU_FVCO_MIN 90000000 48 49 /* scaling for mclk from sysclk_src output */ 50 static const struct nau8824_fll_attr mclk_src_scaling[] = { 51 { 1, 0x0 }, 52 { 2, 0x2 }, 53 { 4, 0x3 }, 54 { 8, 0x4 }, 55 { 16, 0x5 }, 56 { 32, 0x6 }, 57 { 3, 0x7 }, 58 { 6, 0xa }, 59 { 12, 0xb }, 60 { 24, 0xc }, 61 }; 62 63 /* ratio for input clk freq */ 64 static const struct nau8824_fll_attr fll_ratio[] = { 65 { 512000, 0x01 }, 66 { 256000, 0x02 }, 67 { 128000, 0x04 }, 68 { 64000, 0x08 }, 69 { 32000, 0x10 }, 70 { 8000, 0x20 }, 71 { 4000, 0x40 }, 72 }; 73 74 static const struct nau8824_fll_attr fll_pre_scalar[] = { 75 { 1, 0x0 }, 76 { 2, 0x1 }, 77 { 4, 0x2 }, 78 { 8, 0x3 }, 79 }; 80 81 /* the maximum frequency of CLK_ADC and CLK_DAC */ 82 #define CLK_DA_AD_MAX 6144000 83 84 /* over sampling rate */ 85 static const struct nau8824_osr_attr osr_dac_sel[] = { 86 { 64, 2 }, /* OSR 64, SRC 1/4 */ 87 { 256, 0 }, /* OSR 256, SRC 1 */ 88 { 128, 1 }, /* OSR 128, SRC 1/2 */ 89 { 0, 0 }, 90 { 32, 3 }, /* OSR 32, SRC 1/8 */ 91 }; 92 93 static const struct nau8824_osr_attr osr_adc_sel[] = { 94 { 32, 3 }, /* OSR 32, SRC 1/8 */ 95 { 64, 2 }, /* OSR 64, SRC 1/4 */ 96 { 128, 1 }, /* OSR 128, SRC 1/2 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 }; 99 100 static const struct reg_default nau8824_reg_defaults[] = { 101 { NAU8824_REG_ENA_CTRL, 0x0000 }, 102 { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, 103 { NAU8824_REG_CLK_DIVIDER, 0x0000 }, 104 { NAU8824_REG_FLL1, 0x0000 }, 105 { NAU8824_REG_FLL2, 0x3126 }, 106 { NAU8824_REG_FLL3, 0x0008 }, 107 { NAU8824_REG_FLL4, 0x0010 }, 108 { NAU8824_REG_FLL5, 0xC000 }, 109 { NAU8824_REG_FLL6, 0x6000 }, 110 { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, 111 { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, 112 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, 113 { NAU8824_REG_IRQ, 0x0000 }, 114 { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, 115 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, 116 { NAU8824_REG_SAR_ADC, 0x0015 }, 117 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, 118 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, 119 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, 120 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, 121 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, 122 { NAU8824_REG_GPIO_SEL, 0x0000 }, 123 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, 124 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, 125 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, 126 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, 127 { NAU8824_REG_TDM_CTRL, 0x0000 }, 128 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, 129 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, 130 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, 131 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, 132 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, 133 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, 134 { NAU8824_REG_EQ1_LOW, 0x112C }, 135 { NAU8824_REG_EQ2_EQ3, 0x2C2C }, 136 { NAU8824_REG_EQ4_EQ5, 0x2C2C }, 137 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, 138 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, 139 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, 140 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, 141 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, 142 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, 143 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, 144 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, 145 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, 146 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, 147 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, 148 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, 149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, 150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, 151 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, 152 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, 153 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, 154 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, 155 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, 156 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, 157 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, 158 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, 159 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, 160 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, 161 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, 162 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, 163 { NAU8824_REG_MODE, 0x0000 }, 164 { NAU8824_REG_MODE1, 0x0000 }, 165 { NAU8824_REG_MODE2, 0x0000 }, 166 { NAU8824_REG_CLASSG, 0x0000 }, 167 { NAU8824_REG_OTP_EFUSE, 0x0000 }, 168 { NAU8824_REG_OTPDOUT_1, 0x0000 }, 169 { NAU8824_REG_OTPDOUT_2, 0x0000 }, 170 { NAU8824_REG_MISC_CTRL, 0x0000 }, 171 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, 172 { NAU8824_REG_TEST_MODE, 0x0000 }, 173 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, 174 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, 175 { NAU8824_REG_BIAS_ADJ, 0x0000 }, 176 { NAU8824_REG_PGA_GAIN, 0x0000 }, 177 { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, 178 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, 179 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, 180 { NAU8824_REG_ENABLE_LO, 0x0000 }, 181 { NAU8824_REG_GAIN_LO, 0x0000 }, 182 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, 183 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, 184 { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, 185 { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, 186 { NAU8824_REG_RDAC, 0x0008 }, 187 { NAU8824_REG_MIC_BIAS, 0x0006 }, 188 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, 189 { NAU8824_REG_BOOST, 0x0000 }, 190 { NAU8824_REG_FEPGA, 0x0000 }, 191 { NAU8824_REG_FEPGA_II, 0x0000 }, 192 { NAU8824_REG_FEPGA_SE, 0x0000 }, 193 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, 194 { NAU8824_REG_ATT_PORT0, 0x0000 }, 195 { NAU8824_REG_ATT_PORT1, 0x0000 }, 196 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, 197 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, 198 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, 199 }; 200 201 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) 202 { 203 int ret; 204 205 if (timeout) { 206 ret = down_timeout(&nau8824->jd_sem, timeout); 207 if (ret < 0) 208 dev_warn(nau8824->dev, "Acquire semaphone timeout\n"); 209 } else { 210 ret = down_interruptible(&nau8824->jd_sem); 211 if (ret < 0) 212 dev_warn(nau8824->dev, "Acquire semaphone fail\n"); 213 } 214 215 return ret; 216 } 217 218 static inline void nau8824_sema_release(struct nau8824 *nau8824) 219 { 220 up(&nau8824->jd_sem); 221 } 222 223 static bool nau8824_readable_reg(struct device *dev, unsigned int reg) 224 { 225 switch (reg) { 226 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: 227 case NAU8824_REG_JACK_DET_CTRL: 228 case NAU8824_REG_INTERRUPT_SETTING_1: 229 case NAU8824_REG_IRQ: 230 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 231 case NAU8824_REG_GPIO_SEL: 232 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 233 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 234 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 235 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: 236 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: 237 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 238 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 239 case NAU8824_REG_I2C_TIMEOUT: 240 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 241 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 242 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 243 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: 244 return true; 245 default: 246 return false; 247 } 248 249 } 250 251 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: 255 case NAU8824_REG_JACK_DET_CTRL: 256 case NAU8824_REG_INTERRUPT_SETTING_1: 257 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 258 case NAU8824_REG_GPIO_SEL: 259 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 260 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 261 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 262 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: 263 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: 264 case NAU8824_REG_DRC_SLOPE_ADC_CH01: 265 case NAU8824_REG_DRC_ATKDCY_ADC_CH01: 266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: 267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: 268 case NAU8824_REG_DRC_SLOPE_ADC_CH23: 269 case NAU8824_REG_DRC_ATKDCY_ADC_CH23: 270 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: 271 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 272 case NAU8824_REG_I2C_TIMEOUT: 273 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 274 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 275 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case NAU8824_REG_RESET: 286 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: 287 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: 288 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: 289 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 290 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 291 case NAU8824_REG_CHARGE_PUMP_INPUT: 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static const char * const nau8824_companding[] = { 299 "Off", "NC", "u-law", "A-law" }; 300 301 static const struct soc_enum nau8824_companding_adc_enum = 302 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, 303 ARRAY_SIZE(nau8824_companding), nau8824_companding); 304 305 static const struct soc_enum nau8824_companding_dac_enum = 306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, 307 ARRAY_SIZE(nau8824_companding), nau8824_companding); 308 309 static const char * const nau8824_adc_decimation[] = { 310 "32", "64", "128", "256" }; 311 312 static const struct soc_enum nau8824_adc_decimation_enum = 313 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, 314 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); 315 316 static const char * const nau8824_dac_oversampl[] = { 317 "64", "256", "128", "", "32" }; 318 319 static const struct soc_enum nau8824_dac_oversampl_enum = 320 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, 321 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); 322 323 static const char * const nau8824_input_channel[] = { 324 "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; 325 326 static const struct soc_enum nau8824_adc_ch0_enum = 327 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, 328 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 329 330 static const struct soc_enum nau8824_adc_ch1_enum = 331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, 332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 333 334 static const struct soc_enum nau8824_adc_ch2_enum = 335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, 336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 337 338 static const struct soc_enum nau8824_adc_ch3_enum = 339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, 340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 341 342 static const char * const nau8824_tdm_slot[] = { 343 "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; 344 345 static const struct soc_enum nau8824_dac_left_sel_enum = 346 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, 347 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 348 349 static const struct soc_enum nau8824_dac_right_sel_enum = 350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, 351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 352 353 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); 354 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); 355 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); 356 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); 357 358 static const struct snd_kcontrol_new nau8824_snd_controls[] = { 359 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), 360 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), 361 362 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), 363 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), 364 365 SOC_SINGLE_TLV("Speaker Right DACR Volume", 366 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), 367 SOC_SINGLE_TLV("Speaker Left DACL Volume", 368 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), 369 SOC_SINGLE_TLV("Speaker Left DACR Volume", 370 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), 371 SOC_SINGLE_TLV("Speaker Right DACL Volume", 372 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), 373 374 SOC_SINGLE_TLV("Headphone Right DACR Volume", 375 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), 376 SOC_SINGLE_TLV("Headphone Left DACL Volume", 377 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), 378 SOC_SINGLE_TLV("Headphone Right DACL Volume", 379 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), 380 SOC_SINGLE_TLV("Headphone Left DACR Volume", 381 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), 382 383 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, 384 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), 385 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, 386 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), 387 388 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, 389 0, 0x164, 0, dmic_vol_tlv), 390 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, 391 0, 0x164, 0, dmic_vol_tlv), 392 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, 393 0, 0x164, 0, dmic_vol_tlv), 394 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, 395 0, 0x164, 0, dmic_vol_tlv), 396 397 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), 398 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), 399 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), 400 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), 401 402 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), 403 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), 404 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), 405 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), 406 407 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), 408 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), 409 410 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), 411 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), 412 }; 413 414 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, 415 struct snd_kcontrol *kcontrol, int event) 416 { 417 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 418 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 419 420 switch (event) { 421 case SND_SOC_DAPM_PRE_PMU: 422 /* Disables the TESTDAC to let DAC signal pass through. */ 423 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 424 NAU8824_TEST_DAC_EN, 0); 425 break; 426 case SND_SOC_DAPM_POST_PMD: 427 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 428 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int nau8824_spk_event(struct snd_soc_dapm_widget *w, 438 struct snd_kcontrol *kcontrol, int event) 439 { 440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 441 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 442 443 switch (event) { 444 case SND_SOC_DAPM_PRE_PMU: 445 regmap_update_bits(nau8824->regmap, 446 NAU8824_REG_ANALOG_CONTROL_2, 447 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); 448 break; 449 case SND_SOC_DAPM_POST_PMD: 450 regmap_update_bits(nau8824->regmap, 451 NAU8824_REG_ANALOG_CONTROL_2, 452 NAU8824_CLASSD_CLAMP_DIS, 0); 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static int nau8824_pump_event(struct snd_soc_dapm_widget *w, 462 struct snd_kcontrol *kcontrol, int event) 463 { 464 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 465 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 466 467 switch (event) { 468 case SND_SOC_DAPM_POST_PMU: 469 /* Prevent startup click by letting charge pump to ramp up */ 470 msleep(10); 471 regmap_update_bits(nau8824->regmap, 472 NAU8824_REG_CHARGE_PUMP_CONTROL, 473 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); 474 break; 475 case SND_SOC_DAPM_PRE_PMD: 476 regmap_update_bits(nau8824->regmap, 477 NAU8824_REG_CHARGE_PUMP_CONTROL, 478 NAU8824_JAMNODCLOW, 0); 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static int system_clock_control(struct snd_soc_dapm_widget *w, 488 struct snd_kcontrol *k, int event) 489 { 490 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 491 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 492 struct regmap *regmap = nau8824->regmap; 493 unsigned int value; 494 bool clk_fll, error; 495 496 if (SND_SOC_DAPM_EVENT_OFF(event)) { 497 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n"); 498 /* Set clock source to disable or internal clock before the 499 * playback or capture end. Codec needs clock for Jack 500 * detection and button press if jack inserted; otherwise, 501 * the clock should be closed. 502 */ 503 if (nau8824_is_jack_inserted(nau8824)) { 504 nau8824_config_sysclk(nau8824, 505 NAU8824_CLK_INTERNAL, 0); 506 } else { 507 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 508 } 509 } else { 510 dev_dbg(nau8824->dev, "system clock control : POWER ON\n"); 511 /* Check the clock source setting is proper or not 512 * no matter the source is from FLL or MCLK. 513 */ 514 regmap_read(regmap, NAU8824_REG_FLL1, &value); 515 clk_fll = value & NAU8824_FLL_RATIO_MASK; 516 /* It's error to use internal clock when playback */ 517 regmap_read(regmap, NAU8824_REG_FLL6, &value); 518 error = value & NAU8824_DCO_EN; 519 if (!error) { 520 /* Check error depending on source is FLL or MCLK. */ 521 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value); 522 if (clk_fll) 523 error = !(value & NAU8824_CLK_SRC_VCO); 524 else 525 error = value & NAU8824_CLK_SRC_VCO; 526 } 527 /* Recover the clock source setting if error. */ 528 if (error) { 529 if (clk_fll) { 530 regmap_update_bits(regmap, 531 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 532 regmap_update_bits(regmap, 533 NAU8824_REG_CLK_DIVIDER, 534 NAU8824_CLK_SRC_MASK, 535 NAU8824_CLK_SRC_VCO); 536 } else { 537 nau8824_config_sysclk(nau8824, 538 NAU8824_CLK_MCLK, 0); 539 } 540 } 541 } 542 543 return 0; 544 } 545 546 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 547 struct snd_kcontrol *k, int event) 548 { 549 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 550 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 551 int src; 552 553 /* The DMIC clock is gotten from system clock (256fs) divided by 554 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or 555 * less than 3.072 MHz. 556 */ 557 for (src = 0; src < 5; src++) { 558 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) 559 break; 560 } 561 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); 562 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 563 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); 564 565 return 0; 566 } 567 568 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = 569 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 570 NAU8824_ADC_CH0_DMIC_SFT, 1, 0); 571 572 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = 573 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 574 NAU8824_ADC_CH1_DMIC_SFT, 1, 0); 575 576 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = 577 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 578 NAU8824_ADC_CH2_DMIC_SFT, 1, 0); 579 580 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = 581 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 582 NAU8824_ADC_CH3_DMIC_SFT, 1, 0); 583 584 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { 585 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 586 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), 587 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 588 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), 589 }; 590 591 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { 592 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 593 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), 594 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 595 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), 596 }; 597 598 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { 599 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 600 NAU8824_DACR_HPL_EN_SFT, 1, 0), 601 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 602 NAU8824_DACL_HPL_EN_SFT, 1, 0), 603 }; 604 605 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { 606 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 607 NAU8824_DACL_HPR_EN_SFT, 1, 0), 608 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 609 NAU8824_DACR_HPR_EN_SFT, 1, 0), 610 }; 611 612 static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; 613 614 static SOC_ENUM_SINGLE_DECL( 615 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 616 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); 617 618 static SOC_ENUM_SINGLE_DECL( 619 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 620 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); 621 622 static const struct snd_kcontrol_new nau8824_dacl_mux = 623 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); 624 625 static const struct snd_kcontrol_new nau8824_dacr_mux = 626 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); 627 628 629 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { 630 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 631 system_clock_control, SND_SOC_DAPM_POST_PMD | 632 SND_SOC_DAPM_POST_PMU), 633 634 SND_SOC_DAPM_INPUT("HSMIC1"), 635 SND_SOC_DAPM_INPUT("HSMIC2"), 636 SND_SOC_DAPM_INPUT("MIC1"), 637 SND_SOC_DAPM_INPUT("MIC2"), 638 SND_SOC_DAPM_INPUT("DMIC1"), 639 SND_SOC_DAPM_INPUT("DMIC2"), 640 SND_SOC_DAPM_INPUT("DMIC3"), 641 SND_SOC_DAPM_INPUT("DMIC4"), 642 643 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, 644 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), 645 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, 646 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), 647 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, 648 NAU8824_DMIC1_EN_SFT, 0, NULL, 0), 649 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, 650 NAU8824_DMIC2_EN_SFT, 0, NULL, 0), 651 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 652 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 653 654 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, 655 0, 0, &nau8824_adc_ch0_dmic), 656 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, 657 0, 0, &nau8824_adc_ch1_dmic), 658 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, 659 0, 0, &nau8824_adc_ch2_dmic), 660 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, 661 0, 0, &nau8824_adc_ch3_dmic), 662 663 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, 664 12, 0, nau8824_adc_left_mixer, 665 ARRAY_SIZE(nau8824_adc_left_mixer)), 666 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, 667 13, 0, nau8824_adc_right_mixer, 668 ARRAY_SIZE(nau8824_adc_right_mixer)), 669 670 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, 671 NAU8824_ADCL_EN_SFT, 0), 672 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, 673 NAU8824_ADCR_EN_SFT, 0), 674 675 SND_SOC_DAPM_AIF_OUT("AIFTX", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 676 SND_SOC_DAPM_AIF_IN("AIFRX", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 677 678 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, 679 NAU8824_DACL_EN_SFT, 0), 680 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, 681 NAU8824_DACL_CLK_SFT, 0, NULL, 0), 682 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, 683 NAU8824_DACR_EN_SFT, 0), 684 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, 685 NAU8824_DACR_CLK_SFT, 0, NULL, 0), 686 687 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), 688 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), 689 690 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 691 8, 1, nau8824_output_dac_event, 692 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 693 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 694 9, 1, nau8824_output_dac_event, 695 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 696 697 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, 698 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, 699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 700 701 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, 702 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, 703 ARRAY_SIZE(nau8824_hp_left_mixer)), 704 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, 705 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, 706 ARRAY_SIZE(nau8824_hp_right_mixer)), 707 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, 708 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, 709 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 710 SND_SOC_DAPM_PGA("Output Driver L", 711 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 712 SND_SOC_DAPM_PGA("Output Driver R", 713 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 714 SND_SOC_DAPM_PGA("Main Driver L", 715 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 716 SND_SOC_DAPM_PGA("Main Driver R", 717 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 718 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, 719 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), 720 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, 721 NAU8824_CLASSG_EN_SFT, 0, NULL, 0), 722 723 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 724 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 725 SND_SOC_DAPM_OUTPUT("HPOL"), 726 SND_SOC_DAPM_OUTPUT("HPOR"), 727 }; 728 729 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { 730 {"DMIC1 Enable", "Switch", "DMIC1"}, 731 {"DMIC2 Enable", "Switch", "DMIC2"}, 732 {"DMIC3 Enable", "Switch", "DMIC3"}, 733 {"DMIC4 Enable", "Switch", "DMIC4"}, 734 735 {"DMIC1", NULL, "DMIC12 Power"}, 736 {"DMIC2", NULL, "DMIC12 Power"}, 737 {"DMIC3", NULL, "DMIC34 Power"}, 738 {"DMIC4", NULL, "DMIC34 Power"}, 739 {"DMIC12 Power", NULL, "DMIC Clock"}, 740 {"DMIC34 Power", NULL, "DMIC Clock"}, 741 742 {"Left ADC", "MIC Switch", "MIC1"}, 743 {"Left ADC", "HSMIC Switch", "HSMIC1"}, 744 {"Right ADC", "MIC Switch", "MIC2"}, 745 {"Right ADC", "HSMIC Switch", "HSMIC2"}, 746 747 {"ADCL", NULL, "Left ADC"}, 748 {"ADCR", NULL, "Right ADC"}, 749 750 {"AIFTX", NULL, "MICBIAS"}, 751 {"AIFTX", NULL, "ADCL"}, 752 {"AIFTX", NULL, "ADCR"}, 753 {"AIFTX", NULL, "DMIC1 Enable"}, 754 {"AIFTX", NULL, "DMIC2 Enable"}, 755 {"AIFTX", NULL, "DMIC3 Enable"}, 756 {"AIFTX", NULL, "DMIC4 Enable"}, 757 758 {"AIFTX", NULL, "System Clock"}, 759 {"AIFRX", NULL, "System Clock"}, 760 761 {"DACL", NULL, "AIFRX"}, 762 {"DACL", NULL, "DACL Clock"}, 763 {"DACR", NULL, "AIFRX"}, 764 {"DACR", NULL, "DACR Clock"}, 765 766 {"DACL Mux", "DACL", "DACL"}, 767 {"DACL Mux", "DACR", "DACR"}, 768 {"DACR Mux", "DACL", "DACL"}, 769 {"DACR Mux", "DACR", "DACR"}, 770 771 {"Output DACL", NULL, "DACL Mux"}, 772 {"Output DACR", NULL, "DACR Mux"}, 773 774 {"ClassD", NULL, "Output DACL"}, 775 {"ClassD", NULL, "Output DACR"}, 776 777 {"Left Headphone", "DAC Left Switch", "Output DACL"}, 778 {"Left Headphone", "DAC Right Switch", "Output DACR"}, 779 {"Right Headphone", "DAC Left Switch", "Output DACL"}, 780 {"Right Headphone", "DAC Right Switch", "Output DACR"}, 781 782 {"Charge Pump", NULL, "Left Headphone"}, 783 {"Charge Pump", NULL, "Right Headphone"}, 784 {"Output Driver L", NULL, "Charge Pump"}, 785 {"Output Driver R", NULL, "Charge Pump"}, 786 {"Main Driver L", NULL, "Output Driver L"}, 787 {"Main Driver R", NULL, "Output Driver R"}, 788 {"Class G", NULL, "Main Driver L"}, 789 {"Class G", NULL, "Main Driver R"}, 790 {"HP Boost Driver", NULL, "Class G"}, 791 792 {"SPKOUTL", NULL, "ClassD"}, 793 {"SPKOUTR", NULL, "ClassD"}, 794 {"HPOL", NULL, "HP Boost Driver"}, 795 {"HPOR", NULL, "HP Boost Driver"}, 796 }; 797 798 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) 799 { 800 struct snd_soc_jack *jack = nau8824->jack; 801 bool insert = FALSE; 802 803 if (nau8824->irq && jack) 804 insert = jack->status & SND_JACK_HEADPHONE; 805 806 return insert; 807 } 808 809 static void nau8824_int_status_clear_all(struct regmap *regmap) 810 { 811 int active_irq, clear_irq, i; 812 813 /* Reset the intrruption status from rightmost bit if the corres- 814 * ponding irq event occurs. 815 */ 816 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); 817 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { 818 clear_irq = (0x1 << i); 819 if (active_irq & clear_irq) 820 regmap_write(regmap, 821 NAU8824_REG_CLEAR_INT_REG, clear_irq); 822 } 823 } 824 825 static void nau8824_eject_jack(struct nau8824 *nau8824) 826 { 827 struct snd_soc_dapm_context *dapm = nau8824->dapm; 828 struct regmap *regmap = nau8824->regmap; 829 830 /* Clear all interruption status */ 831 nau8824_int_status_clear_all(regmap); 832 833 snd_soc_dapm_disable_pin(dapm, "SAR"); 834 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 835 snd_soc_dapm_sync(dapm); 836 837 /* Enable the insertion interruption, disable the ejection 838 * interruption, and then bypass de-bounce circuit. 839 */ 840 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 841 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 842 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 843 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 844 NAU8824_IRQ_EJECT_DIS); 845 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 846 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 847 NAU8824_IRQ_INSERT_EN); 848 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 849 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 850 851 /* Close clock for jack type detection at manual mode */ 852 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 853 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 854 } 855 856 static void nau8824_jdet_work(struct work_struct *work) 857 { 858 struct nau8824 *nau8824 = container_of( 859 work, struct nau8824, jdet_work); 860 struct snd_soc_dapm_context *dapm = nau8824->dapm; 861 struct regmap *regmap = nau8824->regmap; 862 int adc_value, event = 0, event_mask = 0; 863 864 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 865 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 866 snd_soc_dapm_sync(dapm); 867 868 msleep(100); 869 870 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); 871 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; 872 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); 873 if (adc_value < HEADSET_SARADC_THD) { 874 event |= SND_JACK_HEADPHONE; 875 876 snd_soc_dapm_disable_pin(dapm, "SAR"); 877 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 878 snd_soc_dapm_sync(dapm); 879 } else { 880 event |= SND_JACK_HEADSET; 881 } 882 event_mask |= SND_JACK_HEADSET; 883 snd_soc_jack_report(nau8824->jack, event, event_mask); 884 885 /* Enable short key press and release interruption. */ 886 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 887 NAU8824_IRQ_KEY_RELEASE_DIS | 888 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); 889 890 nau8824_sema_release(nau8824); 891 } 892 893 static void nau8824_setup_auto_irq(struct nau8824 *nau8824) 894 { 895 struct regmap *regmap = nau8824->regmap; 896 897 /* Enable jack ejection interruption. */ 898 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 899 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 900 NAU8824_IRQ_EJECT_EN); 901 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 902 NAU8824_IRQ_EJECT_DIS, 0); 903 /* Enable internal VCO needed for interruptions */ 904 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE) 905 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); 906 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 907 NAU8824_JD_SLEEP_MODE, 0); 908 } 909 910 static int nau8824_button_decode(int value) 911 { 912 int buttons = 0; 913 914 /* The chip supports up to 8 buttons, but ALSA defines 915 * only 6 buttons. 916 */ 917 if (value & BIT(0)) 918 buttons |= SND_JACK_BTN_0; 919 if (value & BIT(1)) 920 buttons |= SND_JACK_BTN_1; 921 if (value & BIT(2)) 922 buttons |= SND_JACK_BTN_2; 923 if (value & BIT(3)) 924 buttons |= SND_JACK_BTN_3; 925 if (value & BIT(4)) 926 buttons |= SND_JACK_BTN_4; 927 if (value & BIT(5)) 928 buttons |= SND_JACK_BTN_5; 929 930 return buttons; 931 } 932 933 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 934 SND_JACK_BTN_2 | SND_JACK_BTN_3) 935 936 static irqreturn_t nau8824_interrupt(int irq, void *data) 937 { 938 struct nau8824 *nau8824 = (struct nau8824 *)data; 939 struct regmap *regmap = nau8824->regmap; 940 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 941 942 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { 943 dev_err(nau8824->dev, "failed to read irq status\n"); 944 return IRQ_NONE; 945 } 946 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); 947 948 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { 949 nau8824_eject_jack(nau8824); 950 event_mask |= SND_JACK_HEADSET; 951 clear_irq = NAU8824_JACK_EJECTION_DETECTED; 952 /* release semaphore held after resume, 953 * and cancel jack detection 954 */ 955 nau8824_sema_release(nau8824); 956 cancel_work_sync(&nau8824->jdet_work); 957 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { 958 int key_status, button_pressed; 959 960 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, 961 &key_status); 962 963 /* lower 8 bits of the register are for pressed keys */ 964 button_pressed = nau8824_button_decode(key_status); 965 966 event |= button_pressed; 967 dev_dbg(nau8824->dev, "button %x pressed\n", event); 968 event_mask |= NAU8824_BUTTONS; 969 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; 970 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { 971 event_mask = NAU8824_BUTTONS; 972 clear_irq = NAU8824_KEY_RELEASE_IRQ; 973 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { 974 /* Turn off insertion interruption at manual mode */ 975 regmap_update_bits(regmap, 976 NAU8824_REG_INTERRUPT_SETTING, 977 NAU8824_IRQ_INSERT_DIS, 978 NAU8824_IRQ_INSERT_DIS); 979 regmap_update_bits(regmap, 980 NAU8824_REG_INTERRUPT_SETTING_1, 981 NAU8824_IRQ_INSERT_EN, 0); 982 /* detect microphone and jack type */ 983 cancel_work_sync(&nau8824->jdet_work); 984 schedule_work(&nau8824->jdet_work); 985 986 /* Enable interruption for jack type detection at audo 987 * mode which can detect microphone and jack type. 988 */ 989 nau8824_setup_auto_irq(nau8824); 990 } 991 992 if (!clear_irq) 993 clear_irq = active_irq; 994 /* clears the rightmost interruption */ 995 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); 996 997 if (event_mask) 998 snd_soc_jack_report(nau8824->jack, event, event_mask); 999 1000 return IRQ_HANDLED; 1001 } 1002 1003 static int nau8824_clock_check(struct nau8824 *nau8824, 1004 int stream, int rate, int osr) 1005 { 1006 int osrate; 1007 1008 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1009 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1010 return -EINVAL; 1011 osrate = osr_dac_sel[osr].osr; 1012 } else { 1013 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1014 return -EINVAL; 1015 osrate = osr_adc_sel[osr].osr; 1016 } 1017 1018 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 1019 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 1020 return -EINVAL; 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int nau8824_hw_params(struct snd_pcm_substream *substream, 1027 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1028 { 1029 struct snd_soc_component *component = dai->component; 1030 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1031 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 1032 1033 nau8824_sema_acquire(nau8824, HZ); 1034 1035 /* CLK_DAC or CLK_ADC = OSR * FS 1036 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1037 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1038 * values must be selected such that the maximum frequency is less 1039 * than 6.144 MHz. 1040 */ 1041 nau8824->fs = params_rate(params); 1042 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1043 regmap_read(nau8824->regmap, 1044 NAU8824_REG_DAC_FILTER_CTRL_1, &osr); 1045 osr &= NAU8824_DAC_OVERSAMPLE_MASK; 1046 if (nau8824_clock_check(nau8824, substream->stream, 1047 nau8824->fs, osr)) 1048 return -EINVAL; 1049 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1050 NAU8824_CLK_DAC_SRC_MASK, 1051 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); 1052 } else { 1053 regmap_read(nau8824->regmap, 1054 NAU8824_REG_ADC_FILTER_CTRL, &osr); 1055 osr &= NAU8824_ADC_SYNC_DOWN_MASK; 1056 if (nau8824_clock_check(nau8824, substream->stream, 1057 nau8824->fs, osr)) 1058 return -EINVAL; 1059 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1060 NAU8824_CLK_ADC_SRC_MASK, 1061 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); 1062 } 1063 1064 /* make BCLK and LRC divde configuration if the codec as master. */ 1065 regmap_read(nau8824->regmap, 1066 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); 1067 if (ctrl_val & NAU8824_I2S_MS_MASTER) { 1068 /* get the bclk and fs ratio */ 1069 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; 1070 if (bclk_fs <= 32) 1071 bclk_div = 0x3; 1072 else if (bclk_fs <= 64) 1073 bclk_div = 0x2; 1074 else if (bclk_fs <= 128) 1075 bclk_div = 0x1; 1076 else if (bclk_fs <= 256) 1077 bclk_div = 0; 1078 else 1079 return -EINVAL; 1080 regmap_update_bits(nau8824->regmap, 1081 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1082 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, 1083 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); 1084 } 1085 1086 switch (params_width(params)) { 1087 case 16: 1088 val_len |= NAU8824_I2S_DL_16; 1089 break; 1090 case 20: 1091 val_len |= NAU8824_I2S_DL_20; 1092 break; 1093 case 24: 1094 val_len |= NAU8824_I2S_DL_24; 1095 break; 1096 case 32: 1097 val_len |= NAU8824_I2S_DL_32; 1098 break; 1099 default: 1100 return -EINVAL; 1101 } 1102 1103 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1104 NAU8824_I2S_DL_MASK, val_len); 1105 1106 nau8824_sema_release(nau8824); 1107 1108 return 0; 1109 } 1110 1111 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1112 { 1113 struct snd_soc_component *component = dai->component; 1114 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1115 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1116 1117 nau8824_sema_acquire(nau8824, HZ); 1118 1119 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1120 case SND_SOC_DAIFMT_CBM_CFM: 1121 ctrl2_val |= NAU8824_I2S_MS_MASTER; 1122 break; 1123 case SND_SOC_DAIFMT_CBS_CFS: 1124 break; 1125 default: 1126 return -EINVAL; 1127 } 1128 1129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1130 case SND_SOC_DAIFMT_NB_NF: 1131 break; 1132 case SND_SOC_DAIFMT_IB_NF: 1133 ctrl1_val |= NAU8824_I2S_BP_INV; 1134 break; 1135 default: 1136 return -EINVAL; 1137 } 1138 1139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1140 case SND_SOC_DAIFMT_I2S: 1141 ctrl1_val |= NAU8824_I2S_DF_I2S; 1142 break; 1143 case SND_SOC_DAIFMT_LEFT_J: 1144 ctrl1_val |= NAU8824_I2S_DF_LEFT; 1145 break; 1146 case SND_SOC_DAIFMT_RIGHT_J: 1147 ctrl1_val |= NAU8824_I2S_DF_RIGTH; 1148 break; 1149 case SND_SOC_DAIFMT_DSP_A: 1150 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1151 break; 1152 case SND_SOC_DAIFMT_DSP_B: 1153 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1154 ctrl1_val |= NAU8824_I2S_PCMB_EN; 1155 break; 1156 default: 1157 return -EINVAL; 1158 } 1159 1160 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1161 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | 1162 NAU8824_I2S_PCMB_EN, ctrl1_val); 1163 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1164 NAU8824_I2S_MS_MASK, ctrl2_val); 1165 1166 nau8824_sema_release(nau8824); 1167 1168 return 0; 1169 } 1170 1171 /** 1172 * nau8824_set_tdm_slot - configure DAI TDM. 1173 * @dai: DAI 1174 * @tx_mask: Bitmask representing active TX slots. Ex. 1175 * 0xf for normal 4 channel TDM. 1176 * 0xf0 for shifted 4 channel TDM 1177 * @rx_mask: Bitmask [0:1] representing active DACR RX slots. 1178 * Bitmask [2:3] representing active DACL RX slots. 1179 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. 1180 * 0xf for DACL/R selecting TDM CH3. 1181 * 0xf0 for DACL/R selecting shifted TDM CH3. 1182 * @slots: Number of slots in use. 1183 * @slot_width: Width in bits for each slot. 1184 * 1185 * Configures a DAI for TDM operation. Only support 4 slots TDM. 1186 */ 1187 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, 1188 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1189 { 1190 struct snd_soc_component *component = dai->component; 1191 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1192 unsigned int tslot_l = 0, ctrl_val = 0; 1193 1194 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || 1195 ((rx_mask & 0xf0) && (rx_mask & 0xf)) || 1196 ((rx_mask & 0xf0) && (tx_mask & 0xf)) || 1197 ((rx_mask & 0xf) && (tx_mask & 0xf0))) 1198 return -EINVAL; 1199 1200 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); 1201 if (tx_mask & 0xf0) { 1202 tslot_l = 4 * slot_width; 1203 ctrl_val |= (tx_mask >> 4); 1204 } else { 1205 ctrl_val |= tx_mask; 1206 } 1207 if (rx_mask & 0xf0) 1208 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); 1209 else 1210 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); 1211 1212 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, 1213 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | 1214 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | 1215 NAU8824_TDM_TX_MASK, ctrl_val); 1216 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, 1217 NAU8824_TSLOT_L_MASK, tslot_l); 1218 1219 return 0; 1220 } 1221 1222 /** 1223 * nau8824_calc_fll_param - Calculate FLL parameters. 1224 * @fll_in: external clock provided to codec. 1225 * @fs: sampling rate. 1226 * @fll_param: Pointer to structure of FLL parameters. 1227 * 1228 * Calculate FLL parameters to configure codec. 1229 * 1230 * Returns 0 for success or negative error code. 1231 */ 1232 static int nau8824_calc_fll_param(unsigned int fll_in, 1233 unsigned int fs, struct nau8824_fll *fll_param) 1234 { 1235 u64 fvco, fvco_max; 1236 unsigned int fref, i, fvco_sel; 1237 1238 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1239 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1240 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK 1241 */ 1242 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1243 fref = fll_in / fll_pre_scalar[i].param; 1244 if (fref <= NAU_FREF_MAX) 1245 break; 1246 } 1247 if (i == ARRAY_SIZE(fll_pre_scalar)) 1248 return -EINVAL; 1249 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1250 1251 /* Choose the FLL ratio based on FREF */ 1252 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1253 if (fref >= fll_ratio[i].param) 1254 break; 1255 } 1256 if (i == ARRAY_SIZE(fll_ratio)) 1257 return -EINVAL; 1258 fll_param->ratio = fll_ratio[i].val; 1259 1260 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1261 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 1262 * guaranteed across the full range of operation. 1263 * FDCO = freq_out * 2 * mclk_src_scaling 1264 */ 1265 fvco_max = 0; 1266 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1267 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1268 fvco = 256 * fs * 2 * mclk_src_scaling[i].param; 1269 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1270 fvco_max < fvco) { 1271 fvco_max = fvco; 1272 fvco_sel = i; 1273 } 1274 } 1275 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1276 return -EINVAL; 1277 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1278 1279 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 1280 * input based on FDCO, FREF and FLL ratio. 1281 */ 1282 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 1283 fll_param->fll_int = (fvco >> 16) & 0x3FF; 1284 fll_param->fll_frac = fvco & 0xFFFF; 1285 return 0; 1286 } 1287 1288 static void nau8824_fll_apply(struct regmap *regmap, 1289 struct nau8824_fll *fll_param) 1290 { 1291 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1292 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, 1293 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); 1294 regmap_update_bits(regmap, NAU8824_REG_FLL1, 1295 NAU8824_FLL_RATIO_MASK, fll_param->ratio); 1296 /* FLL 16-bit fractional input */ 1297 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); 1298 /* FLL 10-bit integer input */ 1299 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1300 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); 1301 /* FLL pre-scaler */ 1302 regmap_update_bits(regmap, NAU8824_REG_FLL4, 1303 NAU8824_FLL_REF_DIV_MASK, 1304 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); 1305 /* select divided VCO input */ 1306 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1307 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); 1308 /* Disable free-running mode */ 1309 regmap_update_bits(regmap, 1310 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 1311 if (fll_param->fll_frac) { 1312 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1313 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1314 NAU8824_FLL_FTR_SW_MASK, 1315 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1316 NAU8824_FLL_FTR_SW_FILTER); 1317 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1318 NAU8824_SDM_EN, NAU8824_SDM_EN); 1319 } else { 1320 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1321 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1322 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); 1323 regmap_update_bits(regmap, 1324 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); 1325 } 1326 } 1327 1328 /* freq_out must be 256*Fs in order to achieve the best performance */ 1329 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source, 1330 unsigned int freq_in, unsigned int freq_out) 1331 { 1332 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1333 struct nau8824_fll fll_param; 1334 int ret, fs; 1335 1336 fs = freq_out / 256; 1337 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); 1338 if (ret < 0) { 1339 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); 1340 return ret; 1341 } 1342 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1343 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 1344 fll_param.fll_int, fll_param.clk_ref_div); 1345 1346 nau8824_fll_apply(nau8824->regmap, &fll_param); 1347 mdelay(2); 1348 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1349 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1350 1351 return 0; 1352 } 1353 1354 static int nau8824_config_sysclk(struct nau8824 *nau8824, 1355 int clk_id, unsigned int freq) 1356 { 1357 struct regmap *regmap = nau8824->regmap; 1358 1359 switch (clk_id) { 1360 case NAU8824_CLK_DIS: 1361 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1362 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1363 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1364 NAU8824_DCO_EN, 0); 1365 break; 1366 1367 case NAU8824_CLK_MCLK: 1368 nau8824_sema_acquire(nau8824, HZ); 1369 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1370 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1371 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1372 NAU8824_DCO_EN, 0); 1373 nau8824_sema_release(nau8824); 1374 break; 1375 1376 case NAU8824_CLK_INTERNAL: 1377 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1378 NAU8824_DCO_EN, NAU8824_DCO_EN); 1379 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1380 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1381 break; 1382 1383 case NAU8824_CLK_FLL_MCLK: 1384 nau8824_sema_acquire(nau8824, HZ); 1385 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1386 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); 1387 nau8824_sema_release(nau8824); 1388 break; 1389 1390 case NAU8824_CLK_FLL_BLK: 1391 nau8824_sema_acquire(nau8824, HZ); 1392 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1393 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); 1394 nau8824_sema_release(nau8824); 1395 break; 1396 1397 case NAU8824_CLK_FLL_FS: 1398 nau8824_sema_acquire(nau8824, HZ); 1399 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1400 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); 1401 nau8824_sema_release(nau8824); 1402 break; 1403 1404 default: 1405 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); 1406 return -EINVAL; 1407 } 1408 1409 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1410 clk_id); 1411 1412 return 0; 1413 } 1414 1415 static int nau8824_set_sysclk(struct snd_soc_component *component, 1416 int clk_id, int source, unsigned int freq, int dir) 1417 { 1418 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1419 1420 return nau8824_config_sysclk(nau8824, clk_id, freq); 1421 } 1422 1423 static void nau8824_resume_setup(struct nau8824 *nau8824) 1424 { 1425 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 1426 if (nau8824->irq) { 1427 /* Clear all interruption status */ 1428 nau8824_int_status_clear_all(nau8824->regmap); 1429 /* Enable jack detection at sleep mode, insertion detection, 1430 * and ejection detection. 1431 */ 1432 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1433 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1434 regmap_update_bits(nau8824->regmap, 1435 NAU8824_REG_INTERRUPT_SETTING_1, 1436 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 1437 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); 1438 regmap_update_bits(nau8824->regmap, 1439 NAU8824_REG_INTERRUPT_SETTING, 1440 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); 1441 } 1442 } 1443 1444 static int nau8824_set_bias_level(struct snd_soc_component *component, 1445 enum snd_soc_bias_level level) 1446 { 1447 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1448 1449 switch (level) { 1450 case SND_SOC_BIAS_ON: 1451 break; 1452 1453 case SND_SOC_BIAS_PREPARE: 1454 break; 1455 1456 case SND_SOC_BIAS_STANDBY: 1457 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1458 /* Setup codec configuration after resume */ 1459 nau8824_resume_setup(nau8824); 1460 } 1461 break; 1462 1463 case SND_SOC_BIAS_OFF: 1464 regmap_update_bits(nau8824->regmap, 1465 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1466 regmap_update_bits(nau8824->regmap, 1467 NAU8824_REG_INTERRUPT_SETTING_1, 1468 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1469 break; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int nau8824_component_probe(struct snd_soc_component *component) 1476 { 1477 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1478 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1479 1480 nau8824->dapm = dapm; 1481 1482 return 0; 1483 } 1484 1485 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component) 1486 { 1487 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1488 1489 if (nau8824->irq) { 1490 disable_irq(nau8824->irq); 1491 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1492 } 1493 regcache_cache_only(nau8824->regmap, true); 1494 regcache_mark_dirty(nau8824->regmap); 1495 1496 return 0; 1497 } 1498 1499 static int __maybe_unused nau8824_resume(struct snd_soc_component *component) 1500 { 1501 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1502 1503 regcache_cache_only(nau8824->regmap, false); 1504 regcache_sync(nau8824->regmap); 1505 if (nau8824->irq) { 1506 /* Hold semaphore to postpone playback happening 1507 * until jack detection done. 1508 */ 1509 nau8824_sema_acquire(nau8824, 0); 1510 enable_irq(nau8824->irq); 1511 } 1512 1513 return 0; 1514 } 1515 1516 static const struct snd_soc_component_driver nau8824_component_driver = { 1517 .probe = nau8824_component_probe, 1518 .set_sysclk = nau8824_set_sysclk, 1519 .set_pll = nau8824_set_pll, 1520 .set_bias_level = nau8824_set_bias_level, 1521 .suspend = nau8824_suspend, 1522 .resume = nau8824_resume, 1523 .controls = nau8824_snd_controls, 1524 .num_controls = ARRAY_SIZE(nau8824_snd_controls), 1525 .dapm_widgets = nau8824_dapm_widgets, 1526 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), 1527 .dapm_routes = nau8824_dapm_routes, 1528 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), 1529 .suspend_bias_off = 1, 1530 .idle_bias_on = 1, 1531 .use_pmdown_time = 1, 1532 .endianness = 1, 1533 .non_legacy_dai_naming = 1, 1534 }; 1535 1536 static const struct snd_soc_dai_ops nau8824_dai_ops = { 1537 .hw_params = nau8824_hw_params, 1538 .set_fmt = nau8824_set_fmt, 1539 .set_tdm_slot = nau8824_set_tdm_slot, 1540 }; 1541 1542 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 1543 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1544 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1545 1546 static struct snd_soc_dai_driver nau8824_dai = { 1547 .name = NAU8824_CODEC_DAI, 1548 .playback = { 1549 .stream_name = "Playback", 1550 .channels_min = 1, 1551 .channels_max = 2, 1552 .rates = NAU8824_RATES, 1553 .formats = NAU8824_FORMATS, 1554 }, 1555 .capture = { 1556 .stream_name = "Capture", 1557 .channels_min = 1, 1558 .channels_max = 2, 1559 .rates = NAU8824_RATES, 1560 .formats = NAU8824_FORMATS, 1561 }, 1562 .ops = &nau8824_dai_ops, 1563 }; 1564 1565 static const struct regmap_config nau8824_regmap_config = { 1566 .val_bits = NAU8824_REG_ADDR_LEN, 1567 .reg_bits = NAU8824_REG_DATA_LEN, 1568 1569 .max_register = NAU8824_REG_MAX, 1570 .readable_reg = nau8824_readable_reg, 1571 .writeable_reg = nau8824_writeable_reg, 1572 .volatile_reg = nau8824_volatile_reg, 1573 1574 .cache_type = REGCACHE_RBTREE, 1575 .reg_defaults = nau8824_reg_defaults, 1576 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), 1577 }; 1578 1579 /** 1580 * nau8824_enable_jack_detect - Specify a jack for event reporting 1581 * 1582 * @component: component to register the jack with 1583 * @jack: jack to use to report headset and button events on 1584 * 1585 * After this function has been called the headset insert/remove and button 1586 * events will be routed to the given jack. Jack can be null to stop 1587 * reporting. 1588 */ 1589 int nau8824_enable_jack_detect(struct snd_soc_component *component, 1590 struct snd_soc_jack *jack) 1591 { 1592 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1593 int ret; 1594 1595 nau8824->jack = jack; 1596 /* Initiate jack detection work queue */ 1597 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); 1598 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, 1599 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1600 "nau8824", nau8824); 1601 if (ret) { 1602 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", 1603 nau8824->irq, ret); 1604 } 1605 1606 return ret; 1607 } 1608 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); 1609 1610 static void nau8824_reset_chip(struct regmap *regmap) 1611 { 1612 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1613 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1614 } 1615 1616 static void nau8824_setup_buttons(struct nau8824 *nau8824) 1617 { 1618 struct regmap *regmap = nau8824->regmap; 1619 1620 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1621 NAU8824_SAR_TRACKING_GAIN_MASK, 1622 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); 1623 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1624 NAU8824_SAR_COMPARE_TIME_MASK, 1625 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); 1626 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1627 NAU8824_SAR_SAMPLING_TIME_MASK, 1628 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); 1629 1630 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1631 NAU8824_LEVELS_NR_MASK, 1632 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); 1633 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1634 NAU8824_HYSTERESIS_MASK, 1635 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); 1636 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1637 NAU8824_SHORTKEY_DEBOUNCE_MASK, 1638 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); 1639 1640 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, 1641 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); 1642 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, 1643 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); 1644 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, 1645 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); 1646 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, 1647 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); 1648 } 1649 1650 static void nau8824_init_regs(struct nau8824 *nau8824) 1651 { 1652 struct regmap *regmap = nau8824->regmap; 1653 1654 /* Enable Bias/VMID/VMID Tieoff */ 1655 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, 1656 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | 1657 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); 1658 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1659 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); 1660 mdelay(2); 1661 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, 1662 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); 1663 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1664 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1665 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1666 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, 1667 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1668 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); 1669 /* Scaling for ADC and DAC clock */ 1670 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1671 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, 1672 (0x1 << NAU8824_CLK_ADC_SRC_SFT) | 1673 (0x1 << NAU8824_CLK_DAC_SRC_SFT)); 1674 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, 1675 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); 1676 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 1677 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1678 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1679 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, 1680 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1681 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1682 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); 1683 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, 1684 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1685 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1686 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1687 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, 1688 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1689 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1690 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1691 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); 1692 /* Class G timer 64ms */ 1693 regmap_update_bits(regmap, NAU8824_REG_CLASSG, 1694 NAU8824_CLASSG_TIMER_MASK, 1695 0x20 << NAU8824_CLASSG_TIMER_SFT); 1696 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, 1697 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); 1698 /* Disable DACR/L power */ 1699 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, 1700 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1701 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, 1702 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1703 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); 1704 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1705 * signal to avoid any glitches due to power up transients in both 1706 * the analog and digital DAC circuit. 1707 */ 1708 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1709 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 1710 /* Config L/R channel */ 1711 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 1712 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); 1713 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 1714 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); 1715 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1716 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, 1717 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); 1718 /* Default oversampling/decimations settings are unusable 1719 * (audible hiss). Set it to something better. 1720 */ 1721 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, 1722 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); 1723 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, 1724 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, 1725 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); 1726 /* DAC clock delay 2ns, VREF */ 1727 regmap_update_bits(regmap, NAU8824_REG_RDAC, 1728 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, 1729 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | 1730 (0x3 << NAU8824_RDAC_VREF_SFT)); 1731 /* PGA input mode selection */ 1732 regmap_update_bits(regmap, NAU8824_REG_FEPGA, 1733 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, 1734 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); 1735 /* Digital microphone control */ 1736 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, 1737 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, 1738 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); 1739 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, 1740 NAU8824_JACK_LOGIC, 1741 /* jkdet_polarity - 1 is for active-low */ 1742 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); 1743 regmap_update_bits(regmap, 1744 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, 1745 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); 1746 if (nau8824->sar_threshold_num) 1747 nau8824_setup_buttons(nau8824); 1748 } 1749 1750 static int nau8824_setup_irq(struct nau8824 *nau8824) 1751 { 1752 /* Disable interruption before codec initiation done */ 1753 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1754 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1755 regmap_update_bits(nau8824->regmap, 1756 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1757 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, 1758 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1759 1760 return 0; 1761 } 1762 1763 static void nau8824_print_device_properties(struct nau8824 *nau8824) 1764 { 1765 struct device *dev = nau8824->dev; 1766 int i; 1767 1768 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); 1769 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); 1770 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); 1771 1772 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); 1773 for (i = 0; i < nau8824->sar_threshold_num; i++) 1774 dev_dbg(dev, "sar-threshold[%d]=%x\n", i, 1775 nau8824->sar_threshold[i]); 1776 1777 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); 1778 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); 1779 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); 1780 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); 1781 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); 1782 dev_dbg(dev, "jack-eject-debounce: %d\n", 1783 nau8824->jack_eject_debounce); 1784 } 1785 1786 static int nau8824_read_device_properties(struct device *dev, 1787 struct nau8824 *nau8824) { 1788 int ret; 1789 1790 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1791 &nau8824->jkdet_polarity); 1792 if (ret) 1793 nau8824->jkdet_polarity = 1; 1794 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1795 &nau8824->micbias_voltage); 1796 if (ret) 1797 nau8824->micbias_voltage = 6; 1798 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1799 &nau8824->vref_impedance); 1800 if (ret) 1801 nau8824->vref_impedance = 2; 1802 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 1803 &nau8824->sar_threshold_num); 1804 if (ret) 1805 nau8824->sar_threshold_num = 4; 1806 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 1807 nau8824->sar_threshold, nau8824->sar_threshold_num); 1808 if (ret) { 1809 nau8824->sar_threshold[0] = 0x0a; 1810 nau8824->sar_threshold[1] = 0x14; 1811 nau8824->sar_threshold[2] = 0x26; 1812 nau8824->sar_threshold[3] = 0x73; 1813 } 1814 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 1815 &nau8824->sar_hysteresis); 1816 if (ret) 1817 nau8824->sar_hysteresis = 0; 1818 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 1819 &nau8824->sar_voltage); 1820 if (ret) 1821 nau8824->sar_voltage = 6; 1822 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 1823 &nau8824->sar_compare_time); 1824 if (ret) 1825 nau8824->sar_compare_time = 1; 1826 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 1827 &nau8824->sar_sampling_time); 1828 if (ret) 1829 nau8824->sar_sampling_time = 1; 1830 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 1831 &nau8824->key_debounce); 1832 if (ret) 1833 nau8824->key_debounce = 0; 1834 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1835 &nau8824->jack_eject_debounce); 1836 if (ret) 1837 nau8824->jack_eject_debounce = 1; 1838 1839 return 0; 1840 } 1841 1842 static int nau8824_i2c_probe(struct i2c_client *i2c, 1843 const struct i2c_device_id *id) 1844 { 1845 struct device *dev = &i2c->dev; 1846 struct nau8824 *nau8824 = dev_get_platdata(dev); 1847 int ret, value; 1848 1849 if (!nau8824) { 1850 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); 1851 if (!nau8824) 1852 return -ENOMEM; 1853 ret = nau8824_read_device_properties(dev, nau8824); 1854 if (ret) 1855 return ret; 1856 } 1857 i2c_set_clientdata(i2c, nau8824); 1858 1859 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); 1860 if (IS_ERR(nau8824->regmap)) 1861 return PTR_ERR(nau8824->regmap); 1862 nau8824->dev = dev; 1863 nau8824->irq = i2c->irq; 1864 sema_init(&nau8824->jd_sem, 1); 1865 1866 nau8824_print_device_properties(nau8824); 1867 1868 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); 1869 if (ret < 0) { 1870 dev_err(dev, "Failed to read device id from the NAU8824: %d\n", 1871 ret); 1872 return ret; 1873 } 1874 nau8824_reset_chip(nau8824->regmap); 1875 nau8824_init_regs(nau8824); 1876 1877 if (i2c->irq) 1878 nau8824_setup_irq(nau8824); 1879 1880 return devm_snd_soc_register_component(dev, 1881 &nau8824_component_driver, &nau8824_dai, 1); 1882 } 1883 1884 static const struct i2c_device_id nau8824_i2c_ids[] = { 1885 { "nau8824", 0 }, 1886 { } 1887 }; 1888 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); 1889 1890 #ifdef CONFIG_OF 1891 static const struct of_device_id nau8824_of_ids[] = { 1892 { .compatible = "nuvoton,nau8824", }, 1893 {} 1894 }; 1895 MODULE_DEVICE_TABLE(of, nau8824_of_ids); 1896 #endif 1897 1898 #ifdef CONFIG_ACPI 1899 static const struct acpi_device_id nau8824_acpi_match[] = { 1900 { "10508824", 0 }, 1901 {}, 1902 }; 1903 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); 1904 #endif 1905 1906 static struct i2c_driver nau8824_i2c_driver = { 1907 .driver = { 1908 .name = "nau8824", 1909 .of_match_table = of_match_ptr(nau8824_of_ids), 1910 .acpi_match_table = ACPI_PTR(nau8824_acpi_match), 1911 }, 1912 .probe = nau8824_i2c_probe, 1913 .id_table = nau8824_i2c_ids, 1914 }; 1915 module_i2c_driver(nau8824_i2c_driver); 1916 1917 1918 MODULE_DESCRIPTION("ASoC NAU88L24 driver"); 1919 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 1920 MODULE_LICENSE("GPL v2"); 1921