1 /* 2 * NAU88L24 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/clk.h> 19 #include <linux/acpi.h> 20 #include <linux/math64.h> 21 #include <linux/semaphore.h> 22 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 31 #include "nau8824.h" 32 33 34 static int nau8824_config_sysclk(struct nau8824 *nau8824, 35 int clk_id, unsigned int freq); 36 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); 37 38 /* the ADC threshold of headset */ 39 #define DMIC_CLK 3072000 40 41 /* the ADC threshold of headset */ 42 #define HEADSET_SARADC_THD 0x80 43 44 /* the parameter threshold of FLL */ 45 #define NAU_FREF_MAX 13500000 46 #define NAU_FVCO_MAX 100000000 47 #define NAU_FVCO_MIN 90000000 48 49 /* scaling for mclk from sysclk_src output */ 50 static const struct nau8824_fll_attr mclk_src_scaling[] = { 51 { 1, 0x0 }, 52 { 2, 0x2 }, 53 { 4, 0x3 }, 54 { 8, 0x4 }, 55 { 16, 0x5 }, 56 { 32, 0x6 }, 57 { 3, 0x7 }, 58 { 6, 0xa }, 59 { 12, 0xb }, 60 { 24, 0xc }, 61 }; 62 63 /* ratio for input clk freq */ 64 static const struct nau8824_fll_attr fll_ratio[] = { 65 { 512000, 0x01 }, 66 { 256000, 0x02 }, 67 { 128000, 0x04 }, 68 { 64000, 0x08 }, 69 { 32000, 0x10 }, 70 { 8000, 0x20 }, 71 { 4000, 0x40 }, 72 }; 73 74 static const struct nau8824_fll_attr fll_pre_scalar[] = { 75 { 1, 0x0 }, 76 { 2, 0x1 }, 77 { 4, 0x2 }, 78 { 8, 0x3 }, 79 }; 80 81 /* the maximum frequency of CLK_ADC and CLK_DAC */ 82 #define CLK_DA_AD_MAX 6144000 83 84 /* over sampling rate */ 85 static const struct nau8824_osr_attr osr_dac_sel[] = { 86 { 64, 2 }, /* OSR 64, SRC 1/4 */ 87 { 256, 0 }, /* OSR 256, SRC 1 */ 88 { 128, 1 }, /* OSR 128, SRC 1/2 */ 89 { 0, 0 }, 90 { 32, 3 }, /* OSR 32, SRC 1/8 */ 91 }; 92 93 static const struct nau8824_osr_attr osr_adc_sel[] = { 94 { 32, 3 }, /* OSR 32, SRC 1/8 */ 95 { 64, 2 }, /* OSR 64, SRC 1/4 */ 96 { 128, 1 }, /* OSR 128, SRC 1/2 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 }; 99 100 static const struct reg_default nau8824_reg_defaults[] = { 101 { NAU8824_REG_ENA_CTRL, 0x0000 }, 102 { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, 103 { NAU8824_REG_CLK_DIVIDER, 0x0000 }, 104 { NAU8824_REG_FLL1, 0x0000 }, 105 { NAU8824_REG_FLL2, 0x3126 }, 106 { NAU8824_REG_FLL3, 0x0008 }, 107 { NAU8824_REG_FLL4, 0x0010 }, 108 { NAU8824_REG_FLL5, 0xC000 }, 109 { NAU8824_REG_FLL6, 0x6000 }, 110 { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, 111 { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, 112 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, 113 { NAU8824_REG_IRQ, 0x0000 }, 114 { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, 115 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, 116 { NAU8824_REG_SAR_ADC, 0x0015 }, 117 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, 118 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, 119 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, 120 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, 121 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, 122 { NAU8824_REG_GPIO_SEL, 0x0000 }, 123 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, 124 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, 125 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, 126 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, 127 { NAU8824_REG_TDM_CTRL, 0x0000 }, 128 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, 129 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, 130 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, 131 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, 132 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, 133 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, 134 { NAU8824_REG_EQ1_LOW, 0x112C }, 135 { NAU8824_REG_EQ2_EQ3, 0x2C2C }, 136 { NAU8824_REG_EQ4_EQ5, 0x2C2C }, 137 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, 138 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, 139 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, 140 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, 141 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, 142 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, 143 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, 144 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, 145 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, 146 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, 147 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, 148 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, 149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, 150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, 151 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, 152 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, 153 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, 154 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, 155 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, 156 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, 157 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, 158 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, 159 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, 160 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, 161 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, 162 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, 163 { NAU8824_REG_MODE, 0x0000 }, 164 { NAU8824_REG_MODE1, 0x0000 }, 165 { NAU8824_REG_MODE2, 0x0000 }, 166 { NAU8824_REG_CLASSG, 0x0000 }, 167 { NAU8824_REG_OTP_EFUSE, 0x0000 }, 168 { NAU8824_REG_OTPDOUT_1, 0x0000 }, 169 { NAU8824_REG_OTPDOUT_2, 0x0000 }, 170 { NAU8824_REG_MISC_CTRL, 0x0000 }, 171 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, 172 { NAU8824_REG_TEST_MODE, 0x0000 }, 173 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, 174 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, 175 { NAU8824_REG_BIAS_ADJ, 0x0000 }, 176 { NAU8824_REG_PGA_GAIN, 0x0000 }, 177 { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, 178 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, 179 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, 180 { NAU8824_REG_ENABLE_LO, 0x0000 }, 181 { NAU8824_REG_GAIN_LO, 0x0000 }, 182 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, 183 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, 184 { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, 185 { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, 186 { NAU8824_REG_RDAC, 0x0008 }, 187 { NAU8824_REG_MIC_BIAS, 0x0006 }, 188 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, 189 { NAU8824_REG_BOOST, 0x0000 }, 190 { NAU8824_REG_FEPGA, 0x0000 }, 191 { NAU8824_REG_FEPGA_II, 0x0000 }, 192 { NAU8824_REG_FEPGA_SE, 0x0000 }, 193 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, 194 { NAU8824_REG_ATT_PORT0, 0x0000 }, 195 { NAU8824_REG_ATT_PORT1, 0x0000 }, 196 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, 197 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, 198 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, 199 }; 200 201 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) 202 { 203 int ret; 204 205 if (timeout) { 206 ret = down_timeout(&nau8824->jd_sem, timeout); 207 if (ret < 0) 208 dev_warn(nau8824->dev, "Acquire semaphore timeout\n"); 209 } else { 210 ret = down_interruptible(&nau8824->jd_sem); 211 if (ret < 0) 212 dev_warn(nau8824->dev, "Acquire semaphore fail\n"); 213 } 214 215 return ret; 216 } 217 218 static inline void nau8824_sema_release(struct nau8824 *nau8824) 219 { 220 up(&nau8824->jd_sem); 221 } 222 223 static bool nau8824_readable_reg(struct device *dev, unsigned int reg) 224 { 225 switch (reg) { 226 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: 227 case NAU8824_REG_JACK_DET_CTRL: 228 case NAU8824_REG_INTERRUPT_SETTING_1: 229 case NAU8824_REG_IRQ: 230 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 231 case NAU8824_REG_GPIO_SEL: 232 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 233 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 234 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 235 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: 236 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: 237 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 238 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 239 case NAU8824_REG_I2C_TIMEOUT: 240 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 241 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 242 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 243 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: 244 return true; 245 default: 246 return false; 247 } 248 249 } 250 251 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: 255 case NAU8824_REG_JACK_DET_CTRL: 256 case NAU8824_REG_INTERRUPT_SETTING_1: 257 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 258 case NAU8824_REG_GPIO_SEL: 259 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 260 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 261 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 262 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: 263 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: 264 case NAU8824_REG_DRC_SLOPE_ADC_CH01: 265 case NAU8824_REG_DRC_ATKDCY_ADC_CH01: 266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: 267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: 268 case NAU8824_REG_DRC_SLOPE_ADC_CH23: 269 case NAU8824_REG_DRC_ATKDCY_ADC_CH23: 270 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: 271 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 272 case NAU8824_REG_I2C_TIMEOUT: 273 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 274 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 275 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case NAU8824_REG_RESET: 286 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: 287 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: 288 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: 289 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 290 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 291 case NAU8824_REG_CHARGE_PUMP_INPUT: 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static const char * const nau8824_companding[] = { 299 "Off", "NC", "u-law", "A-law" }; 300 301 static const struct soc_enum nau8824_companding_adc_enum = 302 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, 303 ARRAY_SIZE(nau8824_companding), nau8824_companding); 304 305 static const struct soc_enum nau8824_companding_dac_enum = 306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, 307 ARRAY_SIZE(nau8824_companding), nau8824_companding); 308 309 static const char * const nau8824_adc_decimation[] = { 310 "32", "64", "128", "256" }; 311 312 static const struct soc_enum nau8824_adc_decimation_enum = 313 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, 314 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); 315 316 static const char * const nau8824_dac_oversampl[] = { 317 "64", "256", "128", "", "32" }; 318 319 static const struct soc_enum nau8824_dac_oversampl_enum = 320 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, 321 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); 322 323 static const char * const nau8824_input_channel[] = { 324 "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; 325 326 static const struct soc_enum nau8824_adc_ch0_enum = 327 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, 328 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 329 330 static const struct soc_enum nau8824_adc_ch1_enum = 331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, 332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 333 334 static const struct soc_enum nau8824_adc_ch2_enum = 335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, 336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 337 338 static const struct soc_enum nau8824_adc_ch3_enum = 339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, 340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 341 342 static const char * const nau8824_tdm_slot[] = { 343 "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; 344 345 static const struct soc_enum nau8824_dac_left_sel_enum = 346 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, 347 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 348 349 static const struct soc_enum nau8824_dac_right_sel_enum = 350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, 351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 352 353 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); 354 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); 355 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); 356 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); 357 358 static const struct snd_kcontrol_new nau8824_snd_controls[] = { 359 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), 360 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), 361 362 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), 363 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), 364 365 SOC_SINGLE_TLV("Speaker Right DACR Volume", 366 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), 367 SOC_SINGLE_TLV("Speaker Left DACL Volume", 368 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), 369 SOC_SINGLE_TLV("Speaker Left DACR Volume", 370 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), 371 SOC_SINGLE_TLV("Speaker Right DACL Volume", 372 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), 373 374 SOC_SINGLE_TLV("Headphone Right DACR Volume", 375 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), 376 SOC_SINGLE_TLV("Headphone Left DACL Volume", 377 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), 378 SOC_SINGLE_TLV("Headphone Right DACL Volume", 379 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), 380 SOC_SINGLE_TLV("Headphone Left DACR Volume", 381 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), 382 383 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, 384 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), 385 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, 386 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), 387 388 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, 389 0, 0x164, 0, dmic_vol_tlv), 390 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, 391 0, 0x164, 0, dmic_vol_tlv), 392 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, 393 0, 0x164, 0, dmic_vol_tlv), 394 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, 395 0, 0x164, 0, dmic_vol_tlv), 396 397 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), 398 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), 399 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), 400 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), 401 402 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), 403 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), 404 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), 405 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), 406 407 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), 408 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), 409 410 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), 411 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), 412 413 SOC_SINGLE("THD for key media", 414 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0), 415 SOC_SINGLE("THD for key voice command", 416 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0), 417 SOC_SINGLE("THD for key volume up", 418 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0), 419 SOC_SINGLE("THD for key volume down", 420 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0), 421 }; 422 423 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, 424 struct snd_kcontrol *kcontrol, int event) 425 { 426 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 427 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 428 429 switch (event) { 430 case SND_SOC_DAPM_PRE_PMU: 431 /* Disables the TESTDAC to let DAC signal pass through. */ 432 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 433 NAU8824_TEST_DAC_EN, 0); 434 break; 435 case SND_SOC_DAPM_POST_PMD: 436 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 437 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int nau8824_spk_event(struct snd_soc_dapm_widget *w, 447 struct snd_kcontrol *kcontrol, int event) 448 { 449 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 450 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 451 452 switch (event) { 453 case SND_SOC_DAPM_PRE_PMU: 454 regmap_update_bits(nau8824->regmap, 455 NAU8824_REG_ANALOG_CONTROL_2, 456 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); 457 break; 458 case SND_SOC_DAPM_POST_PMD: 459 regmap_update_bits(nau8824->regmap, 460 NAU8824_REG_ANALOG_CONTROL_2, 461 NAU8824_CLASSD_CLAMP_DIS, 0); 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 return 0; 468 } 469 470 static int nau8824_pump_event(struct snd_soc_dapm_widget *w, 471 struct snd_kcontrol *kcontrol, int event) 472 { 473 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 474 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 475 476 switch (event) { 477 case SND_SOC_DAPM_POST_PMU: 478 /* Prevent startup click by letting charge pump to ramp up */ 479 msleep(10); 480 regmap_update_bits(nau8824->regmap, 481 NAU8824_REG_CHARGE_PUMP_CONTROL, 482 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); 483 break; 484 case SND_SOC_DAPM_PRE_PMD: 485 regmap_update_bits(nau8824->regmap, 486 NAU8824_REG_CHARGE_PUMP_CONTROL, 487 NAU8824_JAMNODCLOW, 0); 488 break; 489 default: 490 return -EINVAL; 491 } 492 493 return 0; 494 } 495 496 static int system_clock_control(struct snd_soc_dapm_widget *w, 497 struct snd_kcontrol *k, int event) 498 { 499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 500 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 501 struct regmap *regmap = nau8824->regmap; 502 unsigned int value; 503 bool clk_fll, error; 504 505 if (SND_SOC_DAPM_EVENT_OFF(event)) { 506 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n"); 507 /* Set clock source to disable or internal clock before the 508 * playback or capture end. Codec needs clock for Jack 509 * detection and button press if jack inserted; otherwise, 510 * the clock should be closed. 511 */ 512 if (nau8824_is_jack_inserted(nau8824)) { 513 nau8824_config_sysclk(nau8824, 514 NAU8824_CLK_INTERNAL, 0); 515 } else { 516 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 517 } 518 } else { 519 dev_dbg(nau8824->dev, "system clock control : POWER ON\n"); 520 /* Check the clock source setting is proper or not 521 * no matter the source is from FLL or MCLK. 522 */ 523 regmap_read(regmap, NAU8824_REG_FLL1, &value); 524 clk_fll = value & NAU8824_FLL_RATIO_MASK; 525 /* It's error to use internal clock when playback */ 526 regmap_read(regmap, NAU8824_REG_FLL6, &value); 527 error = value & NAU8824_DCO_EN; 528 if (!error) { 529 /* Check error depending on source is FLL or MCLK. */ 530 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value); 531 if (clk_fll) 532 error = !(value & NAU8824_CLK_SRC_VCO); 533 else 534 error = value & NAU8824_CLK_SRC_VCO; 535 } 536 /* Recover the clock source setting if error. */ 537 if (error) { 538 if (clk_fll) { 539 regmap_update_bits(regmap, 540 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 541 regmap_update_bits(regmap, 542 NAU8824_REG_CLK_DIVIDER, 543 NAU8824_CLK_SRC_MASK, 544 NAU8824_CLK_SRC_VCO); 545 } else { 546 nau8824_config_sysclk(nau8824, 547 NAU8824_CLK_MCLK, 0); 548 } 549 } 550 } 551 552 return 0; 553 } 554 555 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 556 struct snd_kcontrol *k, int event) 557 { 558 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 559 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 560 int src; 561 562 /* The DMIC clock is gotten from system clock (256fs) divided by 563 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or 564 * less than 3.072 MHz. 565 */ 566 for (src = 0; src < 5; src++) { 567 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) 568 break; 569 } 570 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); 571 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 572 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); 573 574 return 0; 575 } 576 577 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = 578 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 579 NAU8824_ADC_CH0_DMIC_SFT, 1, 0); 580 581 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = 582 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 583 NAU8824_ADC_CH1_DMIC_SFT, 1, 0); 584 585 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = 586 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 587 NAU8824_ADC_CH2_DMIC_SFT, 1, 0); 588 589 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = 590 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 591 NAU8824_ADC_CH3_DMIC_SFT, 1, 0); 592 593 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { 594 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 595 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), 596 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 597 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), 598 }; 599 600 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { 601 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 602 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), 603 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 604 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), 605 }; 606 607 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { 608 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 609 NAU8824_DACR_HPL_EN_SFT, 1, 0), 610 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 611 NAU8824_DACL_HPL_EN_SFT, 1, 0), 612 }; 613 614 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { 615 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 616 NAU8824_DACL_HPR_EN_SFT, 1, 0), 617 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 618 NAU8824_DACR_HPR_EN_SFT, 1, 0), 619 }; 620 621 static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; 622 623 static SOC_ENUM_SINGLE_DECL( 624 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 625 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); 626 627 static SOC_ENUM_SINGLE_DECL( 628 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 629 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); 630 631 static const struct snd_kcontrol_new nau8824_dacl_mux = 632 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); 633 634 static const struct snd_kcontrol_new nau8824_dacr_mux = 635 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); 636 637 638 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { 639 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 640 system_clock_control, SND_SOC_DAPM_POST_PMD | 641 SND_SOC_DAPM_POST_PMU), 642 643 SND_SOC_DAPM_INPUT("HSMIC1"), 644 SND_SOC_DAPM_INPUT("HSMIC2"), 645 SND_SOC_DAPM_INPUT("MIC1"), 646 SND_SOC_DAPM_INPUT("MIC2"), 647 SND_SOC_DAPM_INPUT("DMIC1"), 648 SND_SOC_DAPM_INPUT("DMIC2"), 649 SND_SOC_DAPM_INPUT("DMIC3"), 650 SND_SOC_DAPM_INPUT("DMIC4"), 651 652 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, 653 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), 654 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, 655 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), 656 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, 657 NAU8824_DMIC1_EN_SFT, 0, NULL, 0), 658 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, 659 NAU8824_DMIC2_EN_SFT, 0, NULL, 0), 660 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 661 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 662 663 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, 664 0, 0, &nau8824_adc_ch0_dmic), 665 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, 666 0, 0, &nau8824_adc_ch1_dmic), 667 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, 668 0, 0, &nau8824_adc_ch2_dmic), 669 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, 670 0, 0, &nau8824_adc_ch3_dmic), 671 672 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, 673 12, 0, nau8824_adc_left_mixer, 674 ARRAY_SIZE(nau8824_adc_left_mixer)), 675 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, 676 13, 0, nau8824_adc_right_mixer, 677 ARRAY_SIZE(nau8824_adc_right_mixer)), 678 679 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, 680 NAU8824_ADCL_EN_SFT, 0), 681 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, 682 NAU8824_ADCR_EN_SFT, 0), 683 684 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0), 685 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 686 687 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, 688 NAU8824_DACL_EN_SFT, 0), 689 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, 690 NAU8824_DACL_CLK_SFT, 0, NULL, 0), 691 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, 692 NAU8824_DACR_EN_SFT, 0), 693 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, 694 NAU8824_DACR_CLK_SFT, 0, NULL, 0), 695 696 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), 697 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), 698 699 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 700 8, 1, nau8824_output_dac_event, 701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 702 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 703 9, 1, nau8824_output_dac_event, 704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 705 706 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, 707 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, 708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 709 710 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, 711 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, 712 ARRAY_SIZE(nau8824_hp_left_mixer)), 713 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, 714 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, 715 ARRAY_SIZE(nau8824_hp_right_mixer)), 716 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, 717 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, 718 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 719 SND_SOC_DAPM_PGA("Output Driver L", 720 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 721 SND_SOC_DAPM_PGA("Output Driver R", 722 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 723 SND_SOC_DAPM_PGA("Main Driver L", 724 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 725 SND_SOC_DAPM_PGA("Main Driver R", 726 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 727 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, 728 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), 729 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, 730 NAU8824_CLASSG_EN_SFT, 0, NULL, 0), 731 732 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 733 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 734 SND_SOC_DAPM_OUTPUT("HPOL"), 735 SND_SOC_DAPM_OUTPUT("HPOR"), 736 }; 737 738 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { 739 {"DMIC1 Enable", "Switch", "DMIC1"}, 740 {"DMIC2 Enable", "Switch", "DMIC2"}, 741 {"DMIC3 Enable", "Switch", "DMIC3"}, 742 {"DMIC4 Enable", "Switch", "DMIC4"}, 743 744 {"DMIC1", NULL, "DMIC12 Power"}, 745 {"DMIC2", NULL, "DMIC12 Power"}, 746 {"DMIC3", NULL, "DMIC34 Power"}, 747 {"DMIC4", NULL, "DMIC34 Power"}, 748 {"DMIC12 Power", NULL, "DMIC Clock"}, 749 {"DMIC34 Power", NULL, "DMIC Clock"}, 750 751 {"Left ADC", "MIC Switch", "MIC1"}, 752 {"Left ADC", "HSMIC Switch", "HSMIC1"}, 753 {"Right ADC", "MIC Switch", "MIC2"}, 754 {"Right ADC", "HSMIC Switch", "HSMIC2"}, 755 756 {"ADCL", NULL, "Left ADC"}, 757 {"ADCR", NULL, "Right ADC"}, 758 759 {"AIFTX", NULL, "MICBIAS"}, 760 {"AIFTX", NULL, "ADCL"}, 761 {"AIFTX", NULL, "ADCR"}, 762 {"AIFTX", NULL, "DMIC1 Enable"}, 763 {"AIFTX", NULL, "DMIC2 Enable"}, 764 {"AIFTX", NULL, "DMIC3 Enable"}, 765 {"AIFTX", NULL, "DMIC4 Enable"}, 766 767 {"AIFTX", NULL, "System Clock"}, 768 {"AIFRX", NULL, "System Clock"}, 769 770 {"DACL", NULL, "AIFRX"}, 771 {"DACL", NULL, "DACL Clock"}, 772 {"DACR", NULL, "AIFRX"}, 773 {"DACR", NULL, "DACR Clock"}, 774 775 {"DACL Mux", "DACL", "DACL"}, 776 {"DACL Mux", "DACR", "DACR"}, 777 {"DACR Mux", "DACL", "DACL"}, 778 {"DACR Mux", "DACR", "DACR"}, 779 780 {"Output DACL", NULL, "DACL Mux"}, 781 {"Output DACR", NULL, "DACR Mux"}, 782 783 {"ClassD", NULL, "Output DACL"}, 784 {"ClassD", NULL, "Output DACR"}, 785 786 {"Left Headphone", "DAC Left Switch", "Output DACL"}, 787 {"Left Headphone", "DAC Right Switch", "Output DACR"}, 788 {"Right Headphone", "DAC Left Switch", "Output DACL"}, 789 {"Right Headphone", "DAC Right Switch", "Output DACR"}, 790 791 {"Charge Pump", NULL, "Left Headphone"}, 792 {"Charge Pump", NULL, "Right Headphone"}, 793 {"Output Driver L", NULL, "Charge Pump"}, 794 {"Output Driver R", NULL, "Charge Pump"}, 795 {"Main Driver L", NULL, "Output Driver L"}, 796 {"Main Driver R", NULL, "Output Driver R"}, 797 {"Class G", NULL, "Main Driver L"}, 798 {"Class G", NULL, "Main Driver R"}, 799 {"HP Boost Driver", NULL, "Class G"}, 800 801 {"SPKOUTL", NULL, "ClassD"}, 802 {"SPKOUTR", NULL, "ClassD"}, 803 {"HPOL", NULL, "HP Boost Driver"}, 804 {"HPOR", NULL, "HP Boost Driver"}, 805 }; 806 807 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) 808 { 809 struct snd_soc_jack *jack = nau8824->jack; 810 bool insert = false; 811 812 if (nau8824->irq && jack) 813 insert = jack->status & SND_JACK_HEADPHONE; 814 815 return insert; 816 } 817 818 static void nau8824_int_status_clear_all(struct regmap *regmap) 819 { 820 int active_irq, clear_irq, i; 821 822 /* Reset the intrruption status from rightmost bit if the corres- 823 * ponding irq event occurs. 824 */ 825 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); 826 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { 827 clear_irq = (0x1 << i); 828 if (active_irq & clear_irq) 829 regmap_write(regmap, 830 NAU8824_REG_CLEAR_INT_REG, clear_irq); 831 } 832 } 833 834 static void nau8824_dapm_disable_pin(struct nau8824 *nau8824, const char *pin) 835 { 836 struct snd_soc_dapm_context *dapm = nau8824->dapm; 837 const char *prefix = dapm->component->name_prefix; 838 char prefixed_pin[80]; 839 840 if (prefix) { 841 snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s", 842 prefix, pin); 843 snd_soc_dapm_disable_pin(dapm, prefixed_pin); 844 } else { 845 snd_soc_dapm_disable_pin(dapm, pin); 846 } 847 } 848 849 static void nau8824_dapm_enable_pin(struct nau8824 *nau8824, const char *pin) 850 { 851 struct snd_soc_dapm_context *dapm = nau8824->dapm; 852 const char *prefix = dapm->component->name_prefix; 853 char prefixed_pin[80]; 854 855 if (prefix) { 856 snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s", 857 prefix, pin); 858 snd_soc_dapm_force_enable_pin(dapm, prefixed_pin); 859 } else { 860 snd_soc_dapm_force_enable_pin(dapm, pin); 861 } 862 } 863 864 static void nau8824_eject_jack(struct nau8824 *nau8824) 865 { 866 struct snd_soc_dapm_context *dapm = nau8824->dapm; 867 struct regmap *regmap = nau8824->regmap; 868 869 /* Clear all interruption status */ 870 nau8824_int_status_clear_all(regmap); 871 872 nau8824_dapm_disable_pin(nau8824, "SAR"); 873 nau8824_dapm_disable_pin(nau8824, "MICBIAS"); 874 snd_soc_dapm_sync(dapm); 875 876 /* Enable the insertion interruption, disable the ejection 877 * interruption, and then bypass de-bounce circuit. 878 */ 879 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 880 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 881 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 882 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 883 NAU8824_IRQ_EJECT_DIS); 884 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 885 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 886 NAU8824_IRQ_INSERT_EN); 887 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 888 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 889 890 /* Close clock for jack type detection at manual mode */ 891 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 892 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 893 } 894 895 static void nau8824_jdet_work(struct work_struct *work) 896 { 897 struct nau8824 *nau8824 = container_of( 898 work, struct nau8824, jdet_work); 899 struct snd_soc_dapm_context *dapm = nau8824->dapm; 900 struct regmap *regmap = nau8824->regmap; 901 int adc_value, event = 0, event_mask = 0; 902 903 nau8824_dapm_enable_pin(nau8824, "MICBIAS"); 904 nau8824_dapm_enable_pin(nau8824, "SAR"); 905 snd_soc_dapm_sync(dapm); 906 907 msleep(100); 908 909 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); 910 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; 911 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); 912 if (adc_value < HEADSET_SARADC_THD) { 913 event |= SND_JACK_HEADPHONE; 914 915 nau8824_dapm_disable_pin(nau8824, "SAR"); 916 nau8824_dapm_disable_pin(nau8824, "MICBIAS"); 917 snd_soc_dapm_sync(dapm); 918 } else { 919 event |= SND_JACK_HEADSET; 920 } 921 event_mask |= SND_JACK_HEADSET; 922 snd_soc_jack_report(nau8824->jack, event, event_mask); 923 924 /* Enable short key press and release interruption. */ 925 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 926 NAU8824_IRQ_KEY_RELEASE_DIS | 927 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); 928 929 nau8824_sema_release(nau8824); 930 } 931 932 static void nau8824_setup_auto_irq(struct nau8824 *nau8824) 933 { 934 struct regmap *regmap = nau8824->regmap; 935 936 /* Enable jack ejection interruption. */ 937 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 938 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 939 NAU8824_IRQ_EJECT_EN); 940 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 941 NAU8824_IRQ_EJECT_DIS, 0); 942 /* Enable internal VCO needed for interruptions */ 943 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE) 944 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); 945 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 946 NAU8824_JD_SLEEP_MODE, 0); 947 } 948 949 static int nau8824_button_decode(int value) 950 { 951 int buttons = 0; 952 953 /* The chip supports up to 8 buttons, but ALSA defines 954 * only 6 buttons. 955 */ 956 if (value & BIT(0)) 957 buttons |= SND_JACK_BTN_0; 958 if (value & BIT(1)) 959 buttons |= SND_JACK_BTN_1; 960 if (value & BIT(2)) 961 buttons |= SND_JACK_BTN_2; 962 if (value & BIT(3)) 963 buttons |= SND_JACK_BTN_3; 964 if (value & BIT(4)) 965 buttons |= SND_JACK_BTN_4; 966 if (value & BIT(5)) 967 buttons |= SND_JACK_BTN_5; 968 969 return buttons; 970 } 971 972 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 973 SND_JACK_BTN_2 | SND_JACK_BTN_3) 974 975 static irqreturn_t nau8824_interrupt(int irq, void *data) 976 { 977 struct nau8824 *nau8824 = (struct nau8824 *)data; 978 struct regmap *regmap = nau8824->regmap; 979 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 980 981 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { 982 dev_err(nau8824->dev, "failed to read irq status\n"); 983 return IRQ_NONE; 984 } 985 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); 986 987 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { 988 nau8824_eject_jack(nau8824); 989 event_mask |= SND_JACK_HEADSET; 990 clear_irq = NAU8824_JACK_EJECTION_DETECTED; 991 /* release semaphore held after resume, 992 * and cancel jack detection 993 */ 994 nau8824_sema_release(nau8824); 995 cancel_work_sync(&nau8824->jdet_work); 996 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { 997 int key_status, button_pressed; 998 999 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, 1000 &key_status); 1001 1002 /* lower 8 bits of the register are for pressed keys */ 1003 button_pressed = nau8824_button_decode(key_status); 1004 1005 event |= button_pressed; 1006 dev_dbg(nau8824->dev, "button %x pressed\n", event); 1007 event_mask |= NAU8824_BUTTONS; 1008 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; 1009 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { 1010 event_mask = NAU8824_BUTTONS; 1011 clear_irq = NAU8824_KEY_RELEASE_IRQ; 1012 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { 1013 /* Turn off insertion interruption at manual mode */ 1014 regmap_update_bits(regmap, 1015 NAU8824_REG_INTERRUPT_SETTING, 1016 NAU8824_IRQ_INSERT_DIS, 1017 NAU8824_IRQ_INSERT_DIS); 1018 regmap_update_bits(regmap, 1019 NAU8824_REG_INTERRUPT_SETTING_1, 1020 NAU8824_IRQ_INSERT_EN, 0); 1021 /* detect microphone and jack type */ 1022 cancel_work_sync(&nau8824->jdet_work); 1023 schedule_work(&nau8824->jdet_work); 1024 1025 /* Enable interruption for jack type detection at audo 1026 * mode which can detect microphone and jack type. 1027 */ 1028 nau8824_setup_auto_irq(nau8824); 1029 } 1030 1031 if (!clear_irq) 1032 clear_irq = active_irq; 1033 /* clears the rightmost interruption */ 1034 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); 1035 1036 if (event_mask) 1037 snd_soc_jack_report(nau8824->jack, event, event_mask); 1038 1039 return IRQ_HANDLED; 1040 } 1041 1042 static int nau8824_clock_check(struct nau8824 *nau8824, 1043 int stream, int rate, int osr) 1044 { 1045 int osrate; 1046 1047 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1048 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1049 return -EINVAL; 1050 osrate = osr_dac_sel[osr].osr; 1051 } else { 1052 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1053 return -EINVAL; 1054 osrate = osr_adc_sel[osr].osr; 1055 } 1056 1057 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 1058 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 1059 return -EINVAL; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int nau8824_hw_params(struct snd_pcm_substream *substream, 1066 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1067 { 1068 struct snd_soc_component *component = dai->component; 1069 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1070 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 1071 1072 nau8824_sema_acquire(nau8824, HZ); 1073 1074 /* CLK_DAC or CLK_ADC = OSR * FS 1075 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1076 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1077 * values must be selected such that the maximum frequency is less 1078 * than 6.144 MHz. 1079 */ 1080 nau8824->fs = params_rate(params); 1081 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1082 regmap_read(nau8824->regmap, 1083 NAU8824_REG_DAC_FILTER_CTRL_1, &osr); 1084 osr &= NAU8824_DAC_OVERSAMPLE_MASK; 1085 if (nau8824_clock_check(nau8824, substream->stream, 1086 nau8824->fs, osr)) 1087 return -EINVAL; 1088 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1089 NAU8824_CLK_DAC_SRC_MASK, 1090 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); 1091 } else { 1092 regmap_read(nau8824->regmap, 1093 NAU8824_REG_ADC_FILTER_CTRL, &osr); 1094 osr &= NAU8824_ADC_SYNC_DOWN_MASK; 1095 if (nau8824_clock_check(nau8824, substream->stream, 1096 nau8824->fs, osr)) 1097 return -EINVAL; 1098 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1099 NAU8824_CLK_ADC_SRC_MASK, 1100 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); 1101 } 1102 1103 /* make BCLK and LRC divde configuration if the codec as master. */ 1104 regmap_read(nau8824->regmap, 1105 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); 1106 if (ctrl_val & NAU8824_I2S_MS_MASTER) { 1107 /* get the bclk and fs ratio */ 1108 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; 1109 if (bclk_fs <= 32) 1110 bclk_div = 0x3; 1111 else if (bclk_fs <= 64) 1112 bclk_div = 0x2; 1113 else if (bclk_fs <= 128) 1114 bclk_div = 0x1; 1115 else if (bclk_fs <= 256) 1116 bclk_div = 0; 1117 else 1118 return -EINVAL; 1119 regmap_update_bits(nau8824->regmap, 1120 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1121 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, 1122 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); 1123 } 1124 1125 switch (params_width(params)) { 1126 case 16: 1127 val_len |= NAU8824_I2S_DL_16; 1128 break; 1129 case 20: 1130 val_len |= NAU8824_I2S_DL_20; 1131 break; 1132 case 24: 1133 val_len |= NAU8824_I2S_DL_24; 1134 break; 1135 case 32: 1136 val_len |= NAU8824_I2S_DL_32; 1137 break; 1138 default: 1139 return -EINVAL; 1140 } 1141 1142 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1143 NAU8824_I2S_DL_MASK, val_len); 1144 1145 nau8824_sema_release(nau8824); 1146 1147 return 0; 1148 } 1149 1150 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1151 { 1152 struct snd_soc_component *component = dai->component; 1153 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1154 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1155 1156 nau8824_sema_acquire(nau8824, HZ); 1157 1158 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1159 case SND_SOC_DAIFMT_CBM_CFM: 1160 ctrl2_val |= NAU8824_I2S_MS_MASTER; 1161 break; 1162 case SND_SOC_DAIFMT_CBS_CFS: 1163 break; 1164 default: 1165 return -EINVAL; 1166 } 1167 1168 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1169 case SND_SOC_DAIFMT_NB_NF: 1170 break; 1171 case SND_SOC_DAIFMT_IB_NF: 1172 ctrl1_val |= NAU8824_I2S_BP_INV; 1173 break; 1174 default: 1175 return -EINVAL; 1176 } 1177 1178 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1179 case SND_SOC_DAIFMT_I2S: 1180 ctrl1_val |= NAU8824_I2S_DF_I2S; 1181 break; 1182 case SND_SOC_DAIFMT_LEFT_J: 1183 ctrl1_val |= NAU8824_I2S_DF_LEFT; 1184 break; 1185 case SND_SOC_DAIFMT_RIGHT_J: 1186 ctrl1_val |= NAU8824_I2S_DF_RIGTH; 1187 break; 1188 case SND_SOC_DAIFMT_DSP_A: 1189 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1190 break; 1191 case SND_SOC_DAIFMT_DSP_B: 1192 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1193 ctrl1_val |= NAU8824_I2S_PCMB_EN; 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1200 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | 1201 NAU8824_I2S_PCMB_EN, ctrl1_val); 1202 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1203 NAU8824_I2S_MS_MASK, ctrl2_val); 1204 1205 nau8824_sema_release(nau8824); 1206 1207 return 0; 1208 } 1209 1210 /** 1211 * nau8824_set_tdm_slot - configure DAI TDM. 1212 * @dai: DAI 1213 * @tx_mask: Bitmask representing active TX slots. Ex. 1214 * 0xf for normal 4 channel TDM. 1215 * 0xf0 for shifted 4 channel TDM 1216 * @rx_mask: Bitmask [0:1] representing active DACR RX slots. 1217 * Bitmask [2:3] representing active DACL RX slots. 1218 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. 1219 * 0xf for DACL/R selecting TDM CH3. 1220 * 0xf0 for DACL/R selecting shifted TDM CH3. 1221 * @slots: Number of slots in use. 1222 * @slot_width: Width in bits for each slot. 1223 * 1224 * Configures a DAI for TDM operation. Only support 4 slots TDM. 1225 */ 1226 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, 1227 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1228 { 1229 struct snd_soc_component *component = dai->component; 1230 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1231 unsigned int tslot_l = 0, ctrl_val = 0; 1232 1233 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || 1234 ((rx_mask & 0xf0) && (rx_mask & 0xf)) || 1235 ((rx_mask & 0xf0) && (tx_mask & 0xf)) || 1236 ((rx_mask & 0xf) && (tx_mask & 0xf0))) 1237 return -EINVAL; 1238 1239 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); 1240 if (tx_mask & 0xf0) { 1241 tslot_l = 4 * slot_width; 1242 ctrl_val |= (tx_mask >> 4); 1243 } else { 1244 ctrl_val |= tx_mask; 1245 } 1246 if (rx_mask & 0xf0) 1247 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); 1248 else 1249 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); 1250 1251 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, 1252 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | 1253 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | 1254 NAU8824_TDM_TX_MASK, ctrl_val); 1255 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, 1256 NAU8824_TSLOT_L_MASK, tslot_l); 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * nau8824_calc_fll_param - Calculate FLL parameters. 1263 * @fll_in: external clock provided to codec. 1264 * @fs: sampling rate. 1265 * @fll_param: Pointer to structure of FLL parameters. 1266 * 1267 * Calculate FLL parameters to configure codec. 1268 * 1269 * Returns 0 for success or negative error code. 1270 */ 1271 static int nau8824_calc_fll_param(unsigned int fll_in, 1272 unsigned int fs, struct nau8824_fll *fll_param) 1273 { 1274 u64 fvco, fvco_max; 1275 unsigned int fref, i, fvco_sel; 1276 1277 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1278 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1279 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK 1280 */ 1281 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1282 fref = fll_in / fll_pre_scalar[i].param; 1283 if (fref <= NAU_FREF_MAX) 1284 break; 1285 } 1286 if (i == ARRAY_SIZE(fll_pre_scalar)) 1287 return -EINVAL; 1288 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1289 1290 /* Choose the FLL ratio based on FREF */ 1291 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1292 if (fref >= fll_ratio[i].param) 1293 break; 1294 } 1295 if (i == ARRAY_SIZE(fll_ratio)) 1296 return -EINVAL; 1297 fll_param->ratio = fll_ratio[i].val; 1298 1299 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1300 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 1301 * guaranteed across the full range of operation. 1302 * FDCO = freq_out * 2 * mclk_src_scaling 1303 */ 1304 fvco_max = 0; 1305 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1306 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1307 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1308 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1309 fvco_max < fvco) { 1310 fvco_max = fvco; 1311 fvco_sel = i; 1312 } 1313 } 1314 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1315 return -EINVAL; 1316 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1317 1318 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 1319 * input based on FDCO, FREF and FLL ratio. 1320 */ 1321 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 1322 fll_param->fll_int = (fvco >> 16) & 0x3FF; 1323 fll_param->fll_frac = fvco & 0xFFFF; 1324 return 0; 1325 } 1326 1327 static void nau8824_fll_apply(struct regmap *regmap, 1328 struct nau8824_fll *fll_param) 1329 { 1330 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1331 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, 1332 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); 1333 regmap_update_bits(regmap, NAU8824_REG_FLL1, 1334 NAU8824_FLL_RATIO_MASK, fll_param->ratio); 1335 /* FLL 16-bit fractional input */ 1336 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); 1337 /* FLL 10-bit integer input */ 1338 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1339 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); 1340 /* FLL pre-scaler */ 1341 regmap_update_bits(regmap, NAU8824_REG_FLL4, 1342 NAU8824_FLL_REF_DIV_MASK, 1343 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); 1344 /* select divided VCO input */ 1345 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1346 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); 1347 /* Disable free-running mode */ 1348 regmap_update_bits(regmap, 1349 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 1350 if (fll_param->fll_frac) { 1351 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1352 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1353 NAU8824_FLL_FTR_SW_MASK, 1354 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1355 NAU8824_FLL_FTR_SW_FILTER); 1356 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1357 NAU8824_SDM_EN, NAU8824_SDM_EN); 1358 } else { 1359 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1360 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1361 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); 1362 regmap_update_bits(regmap, 1363 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); 1364 } 1365 } 1366 1367 /* freq_out must be 256*Fs in order to achieve the best performance */ 1368 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source, 1369 unsigned int freq_in, unsigned int freq_out) 1370 { 1371 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1372 struct nau8824_fll fll_param; 1373 int ret, fs; 1374 1375 fs = freq_out / 256; 1376 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); 1377 if (ret < 0) { 1378 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); 1379 return ret; 1380 } 1381 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1382 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 1383 fll_param.fll_int, fll_param.clk_ref_div); 1384 1385 nau8824_fll_apply(nau8824->regmap, &fll_param); 1386 mdelay(2); 1387 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1388 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1389 1390 return 0; 1391 } 1392 1393 static int nau8824_config_sysclk(struct nau8824 *nau8824, 1394 int clk_id, unsigned int freq) 1395 { 1396 struct regmap *regmap = nau8824->regmap; 1397 1398 switch (clk_id) { 1399 case NAU8824_CLK_DIS: 1400 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1401 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1402 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1403 NAU8824_DCO_EN, 0); 1404 break; 1405 1406 case NAU8824_CLK_MCLK: 1407 nau8824_sema_acquire(nau8824, HZ); 1408 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1409 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1410 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1411 NAU8824_DCO_EN, 0); 1412 nau8824_sema_release(nau8824); 1413 break; 1414 1415 case NAU8824_CLK_INTERNAL: 1416 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1417 NAU8824_DCO_EN, NAU8824_DCO_EN); 1418 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1419 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1420 break; 1421 1422 case NAU8824_CLK_FLL_MCLK: 1423 nau8824_sema_acquire(nau8824, HZ); 1424 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1425 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); 1426 nau8824_sema_release(nau8824); 1427 break; 1428 1429 case NAU8824_CLK_FLL_BLK: 1430 nau8824_sema_acquire(nau8824, HZ); 1431 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1432 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); 1433 nau8824_sema_release(nau8824); 1434 break; 1435 1436 case NAU8824_CLK_FLL_FS: 1437 nau8824_sema_acquire(nau8824, HZ); 1438 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1439 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); 1440 nau8824_sema_release(nau8824); 1441 break; 1442 1443 default: 1444 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); 1445 return -EINVAL; 1446 } 1447 1448 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1449 clk_id); 1450 1451 return 0; 1452 } 1453 1454 static int nau8824_set_sysclk(struct snd_soc_component *component, 1455 int clk_id, int source, unsigned int freq, int dir) 1456 { 1457 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1458 1459 return nau8824_config_sysclk(nau8824, clk_id, freq); 1460 } 1461 1462 static void nau8824_resume_setup(struct nau8824 *nau8824) 1463 { 1464 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 1465 if (nau8824->irq) { 1466 /* Clear all interruption status */ 1467 nau8824_int_status_clear_all(nau8824->regmap); 1468 /* Enable jack detection at sleep mode, insertion detection, 1469 * and ejection detection. 1470 */ 1471 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1472 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1473 regmap_update_bits(nau8824->regmap, 1474 NAU8824_REG_INTERRUPT_SETTING_1, 1475 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 1476 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); 1477 regmap_update_bits(nau8824->regmap, 1478 NAU8824_REG_INTERRUPT_SETTING, 1479 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); 1480 } 1481 } 1482 1483 static int nau8824_set_bias_level(struct snd_soc_component *component, 1484 enum snd_soc_bias_level level) 1485 { 1486 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1487 1488 switch (level) { 1489 case SND_SOC_BIAS_ON: 1490 break; 1491 1492 case SND_SOC_BIAS_PREPARE: 1493 break; 1494 1495 case SND_SOC_BIAS_STANDBY: 1496 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1497 /* Setup codec configuration after resume */ 1498 nau8824_resume_setup(nau8824); 1499 } 1500 break; 1501 1502 case SND_SOC_BIAS_OFF: 1503 regmap_update_bits(nau8824->regmap, 1504 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1505 regmap_update_bits(nau8824->regmap, 1506 NAU8824_REG_INTERRUPT_SETTING_1, 1507 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1508 break; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int nau8824_component_probe(struct snd_soc_component *component) 1515 { 1516 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1517 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1518 1519 nau8824->dapm = dapm; 1520 1521 return 0; 1522 } 1523 1524 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component) 1525 { 1526 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1527 1528 if (nau8824->irq) { 1529 disable_irq(nau8824->irq); 1530 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1531 } 1532 regcache_cache_only(nau8824->regmap, true); 1533 regcache_mark_dirty(nau8824->regmap); 1534 1535 return 0; 1536 } 1537 1538 static int __maybe_unused nau8824_resume(struct snd_soc_component *component) 1539 { 1540 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1541 1542 regcache_cache_only(nau8824->regmap, false); 1543 regcache_sync(nau8824->regmap); 1544 if (nau8824->irq) { 1545 /* Hold semaphore to postpone playback happening 1546 * until jack detection done. 1547 */ 1548 nau8824_sema_acquire(nau8824, 0); 1549 enable_irq(nau8824->irq); 1550 } 1551 1552 return 0; 1553 } 1554 1555 static const struct snd_soc_component_driver nau8824_component_driver = { 1556 .probe = nau8824_component_probe, 1557 .set_sysclk = nau8824_set_sysclk, 1558 .set_pll = nau8824_set_pll, 1559 .set_bias_level = nau8824_set_bias_level, 1560 .suspend = nau8824_suspend, 1561 .resume = nau8824_resume, 1562 .controls = nau8824_snd_controls, 1563 .num_controls = ARRAY_SIZE(nau8824_snd_controls), 1564 .dapm_widgets = nau8824_dapm_widgets, 1565 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), 1566 .dapm_routes = nau8824_dapm_routes, 1567 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), 1568 .suspend_bias_off = 1, 1569 .idle_bias_on = 1, 1570 .use_pmdown_time = 1, 1571 .endianness = 1, 1572 .non_legacy_dai_naming = 1, 1573 }; 1574 1575 static const struct snd_soc_dai_ops nau8824_dai_ops = { 1576 .hw_params = nau8824_hw_params, 1577 .set_fmt = nau8824_set_fmt, 1578 .set_tdm_slot = nau8824_set_tdm_slot, 1579 }; 1580 1581 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 1582 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1583 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1584 1585 static struct snd_soc_dai_driver nau8824_dai = { 1586 .name = NAU8824_CODEC_DAI, 1587 .playback = { 1588 .stream_name = "Playback", 1589 .channels_min = 1, 1590 .channels_max = 2, 1591 .rates = NAU8824_RATES, 1592 .formats = NAU8824_FORMATS, 1593 }, 1594 .capture = { 1595 .stream_name = "Capture", 1596 .channels_min = 1, 1597 .channels_max = 2, 1598 .rates = NAU8824_RATES, 1599 .formats = NAU8824_FORMATS, 1600 }, 1601 .ops = &nau8824_dai_ops, 1602 }; 1603 1604 static const struct regmap_config nau8824_regmap_config = { 1605 .val_bits = NAU8824_REG_ADDR_LEN, 1606 .reg_bits = NAU8824_REG_DATA_LEN, 1607 1608 .max_register = NAU8824_REG_MAX, 1609 .readable_reg = nau8824_readable_reg, 1610 .writeable_reg = nau8824_writeable_reg, 1611 .volatile_reg = nau8824_volatile_reg, 1612 1613 .cache_type = REGCACHE_RBTREE, 1614 .reg_defaults = nau8824_reg_defaults, 1615 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), 1616 }; 1617 1618 /** 1619 * nau8824_enable_jack_detect - Specify a jack for event reporting 1620 * 1621 * @component: component to register the jack with 1622 * @jack: jack to use to report headset and button events on 1623 * 1624 * After this function has been called the headset insert/remove and button 1625 * events will be routed to the given jack. Jack can be null to stop 1626 * reporting. 1627 */ 1628 int nau8824_enable_jack_detect(struct snd_soc_component *component, 1629 struct snd_soc_jack *jack) 1630 { 1631 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1632 int ret; 1633 1634 nau8824->jack = jack; 1635 /* Initiate jack detection work queue */ 1636 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); 1637 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, 1638 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1639 "nau8824", nau8824); 1640 if (ret) { 1641 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", 1642 nau8824->irq, ret); 1643 } 1644 1645 return ret; 1646 } 1647 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); 1648 1649 static void nau8824_reset_chip(struct regmap *regmap) 1650 { 1651 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1652 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1653 } 1654 1655 static void nau8824_setup_buttons(struct nau8824 *nau8824) 1656 { 1657 struct regmap *regmap = nau8824->regmap; 1658 1659 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1660 NAU8824_SAR_TRACKING_GAIN_MASK, 1661 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); 1662 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1663 NAU8824_SAR_COMPARE_TIME_MASK, 1664 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); 1665 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1666 NAU8824_SAR_SAMPLING_TIME_MASK, 1667 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); 1668 1669 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1670 NAU8824_LEVELS_NR_MASK, 1671 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); 1672 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1673 NAU8824_HYSTERESIS_MASK, 1674 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); 1675 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1676 NAU8824_SHORTKEY_DEBOUNCE_MASK, 1677 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); 1678 1679 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, 1680 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); 1681 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, 1682 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); 1683 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, 1684 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); 1685 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, 1686 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); 1687 } 1688 1689 static void nau8824_init_regs(struct nau8824 *nau8824) 1690 { 1691 struct regmap *regmap = nau8824->regmap; 1692 1693 /* Enable Bias/VMID/VMID Tieoff */ 1694 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, 1695 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | 1696 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); 1697 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1698 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); 1699 mdelay(2); 1700 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, 1701 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); 1702 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1703 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1704 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1705 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, 1706 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1707 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); 1708 /* Scaling for ADC and DAC clock */ 1709 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1710 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, 1711 (0x1 << NAU8824_CLK_ADC_SRC_SFT) | 1712 (0x1 << NAU8824_CLK_DAC_SRC_SFT)); 1713 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, 1714 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); 1715 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 1716 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1717 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1718 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, 1719 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1720 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1721 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); 1722 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, 1723 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1724 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1725 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1726 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, 1727 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1728 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1729 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1730 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); 1731 /* Class G timer 64ms */ 1732 regmap_update_bits(regmap, NAU8824_REG_CLASSG, 1733 NAU8824_CLASSG_TIMER_MASK, 1734 0x20 << NAU8824_CLASSG_TIMER_SFT); 1735 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, 1736 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); 1737 /* Disable DACR/L power */ 1738 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, 1739 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1740 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, 1741 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1742 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); 1743 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1744 * signal to avoid any glitches due to power up transients in both 1745 * the analog and digital DAC circuit. 1746 */ 1747 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1748 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 1749 /* Config L/R channel */ 1750 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 1751 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); 1752 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 1753 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); 1754 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1755 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, 1756 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); 1757 /* Default oversampling/decimations settings are unusable 1758 * (audible hiss). Set it to something better. 1759 */ 1760 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, 1761 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); 1762 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, 1763 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, 1764 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); 1765 /* DAC clock delay 2ns, VREF */ 1766 regmap_update_bits(regmap, NAU8824_REG_RDAC, 1767 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, 1768 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | 1769 (0x3 << NAU8824_RDAC_VREF_SFT)); 1770 /* PGA input mode selection */ 1771 regmap_update_bits(regmap, NAU8824_REG_FEPGA, 1772 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, 1773 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); 1774 /* Digital microphone control */ 1775 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, 1776 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, 1777 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); 1778 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, 1779 NAU8824_JACK_LOGIC, 1780 /* jkdet_polarity - 1 is for active-low */ 1781 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); 1782 regmap_update_bits(regmap, 1783 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, 1784 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); 1785 if (nau8824->sar_threshold_num) 1786 nau8824_setup_buttons(nau8824); 1787 } 1788 1789 static int nau8824_setup_irq(struct nau8824 *nau8824) 1790 { 1791 /* Disable interruption before codec initiation done */ 1792 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1793 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1794 regmap_update_bits(nau8824->regmap, 1795 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1796 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, 1797 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1798 1799 return 0; 1800 } 1801 1802 static void nau8824_print_device_properties(struct nau8824 *nau8824) 1803 { 1804 struct device *dev = nau8824->dev; 1805 int i; 1806 1807 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); 1808 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); 1809 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); 1810 1811 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); 1812 for (i = 0; i < nau8824->sar_threshold_num; i++) 1813 dev_dbg(dev, "sar-threshold[%d]=%x\n", i, 1814 nau8824->sar_threshold[i]); 1815 1816 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); 1817 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); 1818 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); 1819 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); 1820 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); 1821 dev_dbg(dev, "jack-eject-debounce: %d\n", 1822 nau8824->jack_eject_debounce); 1823 } 1824 1825 static int nau8824_read_device_properties(struct device *dev, 1826 struct nau8824 *nau8824) { 1827 int ret; 1828 1829 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1830 &nau8824->jkdet_polarity); 1831 if (ret) 1832 nau8824->jkdet_polarity = 1; 1833 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1834 &nau8824->micbias_voltage); 1835 if (ret) 1836 nau8824->micbias_voltage = 6; 1837 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1838 &nau8824->vref_impedance); 1839 if (ret) 1840 nau8824->vref_impedance = 2; 1841 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 1842 &nau8824->sar_threshold_num); 1843 if (ret) 1844 nau8824->sar_threshold_num = 4; 1845 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 1846 nau8824->sar_threshold, nau8824->sar_threshold_num); 1847 if (ret) { 1848 nau8824->sar_threshold[0] = 0x0a; 1849 nau8824->sar_threshold[1] = 0x14; 1850 nau8824->sar_threshold[2] = 0x26; 1851 nau8824->sar_threshold[3] = 0x73; 1852 } 1853 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 1854 &nau8824->sar_hysteresis); 1855 if (ret) 1856 nau8824->sar_hysteresis = 0; 1857 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 1858 &nau8824->sar_voltage); 1859 if (ret) 1860 nau8824->sar_voltage = 6; 1861 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 1862 &nau8824->sar_compare_time); 1863 if (ret) 1864 nau8824->sar_compare_time = 1; 1865 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 1866 &nau8824->sar_sampling_time); 1867 if (ret) 1868 nau8824->sar_sampling_time = 1; 1869 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 1870 &nau8824->key_debounce); 1871 if (ret) 1872 nau8824->key_debounce = 0; 1873 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1874 &nau8824->jack_eject_debounce); 1875 if (ret) 1876 nau8824->jack_eject_debounce = 1; 1877 1878 return 0; 1879 } 1880 1881 static int nau8824_i2c_probe(struct i2c_client *i2c, 1882 const struct i2c_device_id *id) 1883 { 1884 struct device *dev = &i2c->dev; 1885 struct nau8824 *nau8824 = dev_get_platdata(dev); 1886 int ret, value; 1887 1888 if (!nau8824) { 1889 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); 1890 if (!nau8824) 1891 return -ENOMEM; 1892 ret = nau8824_read_device_properties(dev, nau8824); 1893 if (ret) 1894 return ret; 1895 } 1896 i2c_set_clientdata(i2c, nau8824); 1897 1898 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); 1899 if (IS_ERR(nau8824->regmap)) 1900 return PTR_ERR(nau8824->regmap); 1901 nau8824->dev = dev; 1902 nau8824->irq = i2c->irq; 1903 sema_init(&nau8824->jd_sem, 1); 1904 1905 nau8824_print_device_properties(nau8824); 1906 1907 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); 1908 if (ret < 0) { 1909 dev_err(dev, "Failed to read device id from the NAU8824: %d\n", 1910 ret); 1911 return ret; 1912 } 1913 nau8824_reset_chip(nau8824->regmap); 1914 nau8824_init_regs(nau8824); 1915 1916 if (i2c->irq) 1917 nau8824_setup_irq(nau8824); 1918 1919 return devm_snd_soc_register_component(dev, 1920 &nau8824_component_driver, &nau8824_dai, 1); 1921 } 1922 1923 static const struct i2c_device_id nau8824_i2c_ids[] = { 1924 { "nau8824", 0 }, 1925 { } 1926 }; 1927 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); 1928 1929 #ifdef CONFIG_OF 1930 static const struct of_device_id nau8824_of_ids[] = { 1931 { .compatible = "nuvoton,nau8824", }, 1932 {} 1933 }; 1934 MODULE_DEVICE_TABLE(of, nau8824_of_ids); 1935 #endif 1936 1937 #ifdef CONFIG_ACPI 1938 static const struct acpi_device_id nau8824_acpi_match[] = { 1939 { "10508824", 0 }, 1940 {}, 1941 }; 1942 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); 1943 #endif 1944 1945 static struct i2c_driver nau8824_i2c_driver = { 1946 .driver = { 1947 .name = "nau8824", 1948 .of_match_table = of_match_ptr(nau8824_of_ids), 1949 .acpi_match_table = ACPI_PTR(nau8824_acpi_match), 1950 }, 1951 .probe = nau8824_i2c_probe, 1952 .id_table = nau8824_i2c_ids, 1953 }; 1954 module_i2c_driver(nau8824_i2c_driver); 1955 1956 1957 MODULE_DESCRIPTION("ASoC NAU88L24 driver"); 1958 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 1959 MODULE_LICENSE("GPL v2"); 1960