1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver 4 // 5 // Copyright 2021 Nuvoton Technology Corp. 6 // Author: John Hsu <kchsu0@nuvoton.com> 7 // Co-author: Seven Lee <wtli@nuvoton.com> 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/math64.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/initval.h> 21 #include <sound/jack.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/tlv.h> 26 #include "nau8821.h" 27 28 #define NAU_FREF_MAX 13500000 29 #define NAU_FVCO_MAX 100000000 30 #define NAU_FVCO_MIN 90000000 31 32 #define NAU8821_BUTTON SND_JACK_BTN_0 33 34 /* the maximum frequency of CLK_ADC and CLK_DAC */ 35 #define CLK_DA_AD_MAX 6144000 36 37 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 38 int clk_id, unsigned int freq); 39 static bool nau8821_is_jack_inserted(struct regmap *regmap); 40 41 struct nau8821_fll { 42 int mclk_src; 43 int ratio; 44 int fll_frac; 45 int fll_int; 46 int clk_ref_div; 47 }; 48 49 struct nau8821_fll_attr { 50 unsigned int param; 51 unsigned int val; 52 }; 53 54 /* scaling for mclk from sysclk_src output */ 55 static const struct nau8821_fll_attr mclk_src_scaling[] = { 56 { 1, 0x0 }, 57 { 2, 0x2 }, 58 { 4, 0x3 }, 59 { 8, 0x4 }, 60 { 16, 0x5 }, 61 { 32, 0x6 }, 62 { 3, 0x7 }, 63 { 6, 0xa }, 64 { 12, 0xb }, 65 { 24, 0xc }, 66 { 48, 0xd }, 67 { 96, 0xe }, 68 { 5, 0xf }, 69 }; 70 71 /* ratio for input clk freq */ 72 static const struct nau8821_fll_attr fll_ratio[] = { 73 { 512000, 0x01 }, 74 { 256000, 0x02 }, 75 { 128000, 0x04 }, 76 { 64000, 0x08 }, 77 { 32000, 0x10 }, 78 { 8000, 0x20 }, 79 { 4000, 0x40 }, 80 }; 81 82 static const struct nau8821_fll_attr fll_pre_scalar[] = { 83 { 0, 0x0 }, 84 { 1, 0x1 }, 85 { 2, 0x2 }, 86 { 3, 0x3 }, 87 }; 88 89 /* over sampling rate */ 90 struct nau8821_osr_attr { 91 unsigned int osr; 92 unsigned int clk_src; 93 }; 94 95 static const struct nau8821_osr_attr osr_dac_sel[] = { 96 { 64, 2 }, /* OSR 64, SRC 1/4 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 { 128, 1 }, /* OSR 128, SRC 1/2 */ 99 { 0, 0 }, 100 { 32, 3 }, /* OSR 32, SRC 1/8 */ 101 }; 102 103 static const struct nau8821_osr_attr osr_adc_sel[] = { 104 { 32, 3 }, /* OSR 32, SRC 1/8 */ 105 { 64, 2 }, /* OSR 64, SRC 1/4 */ 106 { 128, 1 }, /* OSR 128, SRC 1/2 */ 107 { 256, 0 }, /* OSR 256, SRC 1 */ 108 }; 109 110 struct nau8821_dmic_speed { 111 unsigned int param; 112 unsigned int val; 113 }; 114 115 static const struct nau8821_dmic_speed dmic_speed_sel[] = { 116 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 117 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 118 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 119 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 120 }; 121 122 static const struct reg_default nau8821_reg_defaults[] = { 123 { NAU8821_R01_ENA_CTRL, 0x00ff }, 124 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 125 { NAU8821_R04_FLL1, 0x0 }, 126 { NAU8821_R05_FLL2, 0x00bc }, 127 { NAU8821_R06_FLL3, 0x0008 }, 128 { NAU8821_R07_FLL4, 0x0010 }, 129 { NAU8821_R08_FLL5, 0x4000 }, 130 { NAU8821_R09_FLL6, 0x6900 }, 131 { NAU8821_R0A_FLL7, 0x0031 }, 132 { NAU8821_R0B_FLL8, 0x26e9 }, 133 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 134 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 135 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 136 { NAU8821_R13_DMIC_CTRL, 0x0 }, 137 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 138 { NAU8821_R1B_TDM_CTRL, 0x0 }, 139 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 140 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 141 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 142 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 143 { NAU8821_R21_BIQ0_COF1, 0x0 }, 144 { NAU8821_R22_BIQ0_COF2, 0x0 }, 145 { NAU8821_R23_BIQ0_COF3, 0x0 }, 146 { NAU8821_R24_BIQ0_COF4, 0x0 }, 147 { NAU8821_R25_BIQ0_COF5, 0x0 }, 148 { NAU8821_R26_BIQ0_COF6, 0x0 }, 149 { NAU8821_R27_BIQ0_COF7, 0x0 }, 150 { NAU8821_R28_BIQ0_COF8, 0x0 }, 151 { NAU8821_R29_BIQ0_COF9, 0x0 }, 152 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 153 { NAU8821_R2B_ADC_RATE, 0x0002 }, 154 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 155 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 156 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 157 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 158 { NAU8821_R31_MUTE_CTRL, 0x0 }, 159 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 160 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 161 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 162 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 163 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 164 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 165 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 166 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 167 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 168 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 169 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 170 { NAU8821_R41_BIQ1_COF1, 0x0 }, 171 { NAU8821_R42_BIQ1_COF2, 0x0 }, 172 { NAU8821_R43_BIQ1_COF3, 0x0 }, 173 { NAU8821_R44_BIQ1_COF4, 0x0 }, 174 { NAU8821_R45_BIQ1_COF5, 0x0 }, 175 { NAU8821_R46_BIQ1_COF6, 0x0 }, 176 { NAU8821_R47_BIQ1_COF7, 0x0 }, 177 { NAU8821_R48_BIQ1_COF8, 0x0 }, 178 { NAU8821_R49_BIQ1_COF9, 0x0 }, 179 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 180 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 181 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 182 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 183 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 184 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 185 { NAU8821_R55_MISC_CTRL, 0x0 }, 186 { NAU8821_R66_BIAS_ADJ, 0x0 }, 187 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 188 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 189 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 190 { NAU8821_R6B_PGA_MUTE, 0x0 }, 191 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 192 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 193 { NAU8821_R73_RDAC, 0x0008 }, 194 { NAU8821_R74_MIC_BIAS, 0x0006 }, 195 { NAU8821_R76_BOOST, 0x0 }, 196 { NAU8821_R77_FEPGA, 0x0 }, 197 { NAU8821_R7E_PGA_GAIN, 0x0 }, 198 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 199 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 200 }; 201 202 static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 206 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 207 case NAU8821_R0D_JACK_DET_CTRL: 208 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 209 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 210 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 211 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 212 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 213 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 214 case NAU8821_R51_FUSE_CTRL1: 215 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 216 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 217 case NAU8821_R66_BIAS_ADJ: 218 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 219 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 220 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 221 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 222 return true; 223 default: 224 return false; 225 } 226 } 227 228 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 229 { 230 switch (reg) { 231 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 232 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 233 case NAU8821_R0D_JACK_DET_CTRL: 234 case NAU8821_R0F_INTERRUPT_MASK: 235 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 236 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 237 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 238 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 239 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 240 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 241 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 242 case NAU8821_R51_FUSE_CTRL1: 243 case NAU8821_R55_MISC_CTRL: 244 case NAU8821_R5A_SOFTWARE_RST: 245 case NAU8821_R66_BIAS_ADJ: 246 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 247 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 248 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 249 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 250 return true; 251 default: 252 return false; 253 } 254 } 255 256 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 257 { 258 switch (reg) { 259 case NAU8821_R00_RESET: 260 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 261 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 262 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 263 case NAU8821_R4D_IMM_RMS_L: 264 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 265 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 266 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 267 return true; 268 default: 269 return false; 270 } 271 } 272 273 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 274 struct snd_ctl_elem_value *ucontrol) 275 { 276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 277 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 278 279 if (!component->regmap) 280 return -EINVAL; 281 282 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 283 ucontrol->value.bytes.data, params->max); 284 285 return 0; 286 } 287 288 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 289 struct snd_ctl_elem_value *ucontrol) 290 { 291 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 292 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 293 void *data; 294 295 if (!component->regmap) 296 return -EINVAL; 297 298 data = kmemdup(ucontrol->value.bytes.data, 299 params->max, GFP_KERNEL | GFP_DMA); 300 if (!data) 301 return -ENOMEM; 302 303 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 304 data, params->max); 305 306 kfree(data); 307 308 return 0; 309 } 310 311 static const char * const nau8821_adc_decimation[] = { 312 "32", "64", "128", "256" }; 313 314 static const struct soc_enum nau8821_adc_decimation_enum = 315 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 316 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 317 318 static const char * const nau8821_dac_oversampl[] = { 319 "64", "256", "128", "", "32" }; 320 321 static const struct soc_enum nau8821_dac_oversampl_enum = 322 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 323 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 324 325 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 326 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 327 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 328 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 329 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 330 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 331 332 static const struct snd_kcontrol_new nau8821_controls[] = { 333 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 334 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 335 0xff, 0, adc_vol_tlv), 336 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 337 12, 8, 0x0f, 0, sidetone_vol_tlv), 338 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 339 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 340 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 341 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 342 0xcf, 0, playback_vol_tlv), 343 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 344 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 345 37, 0, fepga_gain_tlv), 346 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 347 NAU8821_R2F_DAC_DGAIN_CTRL, 348 0, 8, 0xff, 0, crosstalk_vol_tlv), 349 350 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 351 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 352 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 353 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 354 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 355 NAU8821_ADCPHS_SFT, 1, 0), 356 }; 357 358 static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 359 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 360 NAU8821_DMIC_EN_SFT, 1, 0); 361 362 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 363 struct snd_kcontrol *k, int event) 364 { 365 struct snd_soc_component *component = 366 snd_soc_dapm_to_component(w->dapm); 367 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 368 int i, speed_selection = -1, clk_adc_src, clk_adc; 369 unsigned int clk_divider_r03; 370 371 /* The DMIC clock is gotten from adc clock divided by 372 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 373 * less than nau8821->dmic_clk_threshold. 374 */ 375 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 376 &clk_divider_r03); 377 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 378 >> NAU8821_CLK_ADC_SRC_SFT; 379 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 380 381 for (i = 0 ; i < 4 ; i++) 382 if ((clk_adc >> dmic_speed_sel[i].param) <= 383 nau8821->dmic_clk_threshold) { 384 speed_selection = dmic_speed_sel[i].val; 385 break; 386 } 387 if (i == 4) 388 return -EINVAL; 389 390 dev_dbg(nau8821->dev, 391 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 392 clk_adc, nau8821->dmic_clk_threshold, 393 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 394 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 395 NAU8821_DMIC_SRC_MASK, 396 (speed_selection << NAU8821_DMIC_SRC_SFT)); 397 398 return 0; 399 } 400 401 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 402 struct snd_kcontrol *kcontrol, int event) 403 { 404 struct snd_soc_component *component = 405 snd_soc_dapm_to_component(w->dapm); 406 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 407 408 switch (event) { 409 case SND_SOC_DAPM_POST_PMU: 410 msleep(125); 411 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 412 NAU8821_EN_ADCL, NAU8821_EN_ADCL); 413 break; 414 case SND_SOC_DAPM_POST_PMD: 415 regmap_update_bits(nau8821->regmap, 416 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0); 417 break; 418 default: 419 return -EINVAL; 420 } 421 422 return 0; 423 } 424 425 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 426 struct snd_kcontrol *kcontrol, int event) 427 { 428 struct snd_soc_component *component = 429 snd_soc_dapm_to_component(w->dapm); 430 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 431 432 switch (event) { 433 case SND_SOC_DAPM_POST_PMU: 434 msleep(125); 435 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 436 NAU8821_EN_ADCR, NAU8821_EN_ADCR); 437 break; 438 case SND_SOC_DAPM_POST_PMD: 439 regmap_update_bits(nau8821->regmap, 440 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0); 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 return 0; 447 } 448 449 static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 450 struct snd_kcontrol *kcontrol, int event) 451 { 452 struct snd_soc_component *component = 453 snd_soc_dapm_to_component(w->dapm); 454 struct nau8821 *nau8821 = 455 snd_soc_component_get_drvdata(component); 456 457 switch (event) { 458 case SND_SOC_DAPM_POST_PMU: 459 /* Prevent startup click by letting charge pump to ramp up */ 460 msleep(20); 461 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 462 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 463 break; 464 case SND_SOC_DAPM_PRE_PMD: 465 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 466 NAU8821_JAMNODCLOW, 0); 467 break; 468 default: 469 return -EINVAL; 470 } 471 472 return 0; 473 } 474 475 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 476 struct snd_kcontrol *kcontrol, int event) 477 { 478 struct snd_soc_component *component = 479 snd_soc_dapm_to_component(w->dapm); 480 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 481 482 switch (event) { 483 case SND_SOC_DAPM_PRE_PMU: 484 /* Disables the TESTDAC to let DAC signal pass through. */ 485 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 486 NAU8821_BIAS_TESTDAC_EN, 0); 487 break; 488 case SND_SOC_DAPM_POST_PMD: 489 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 490 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 return 0; 497 } 498 499 static int system_clock_control(struct snd_soc_dapm_widget *w, 500 struct snd_kcontrol *k, int event) 501 { 502 struct snd_soc_component *component = 503 snd_soc_dapm_to_component(w->dapm); 504 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 505 506 if (SND_SOC_DAPM_EVENT_OFF(event)) { 507 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 508 /* Set clock source to disable or internal clock before the 509 * playback or capture end. Codec needs clock for Jack 510 * detection and button press if jack inserted; otherwise, 511 * the clock should be closed. 512 */ 513 if (nau8821_is_jack_inserted(nau8821->regmap)) { 514 nau8821_configure_sysclk(nau8821, 515 NAU8821_CLK_INTERNAL, 0); 516 } else { 517 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 518 } 519 } 520 return 0; 521 } 522 523 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 524 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 525 system_clock_control, SND_SOC_DAPM_POST_PMD), 526 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 527 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 528 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 529 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 530 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 531 NAU8821_POWERUP_ADCL_SFT, 0), 532 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 533 NAU8821_POWERUP_ADCR_SFT, 0), 534 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 535 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0), 536 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 537 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 538 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 539 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 540 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 541 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 542 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 543 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 544 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 545 0, 0, &nau8821_dmic_mode_switch), 546 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 547 NAU8821_I2S_TRISTATE_SFT, 1), 548 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 549 550 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 551 NAU8821_DACL_EN_SFT, 0, NULL, 0), 552 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 553 NAU8821_DACR_EN_SFT, 0, NULL, 0), 554 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 555 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 556 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 557 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 558 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 559 NAU8821_EN_DACR_SFT, 0), 560 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 561 NAU8821_EN_DACL_SFT, 0), 562 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 563 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 564 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 565 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 566 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 567 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 569 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 570 NAU8821_R7F_POWER_UP_CONTROL, 571 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 572 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 573 NAU8821_R7F_POWER_UP_CONTROL, 574 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 575 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 576 NAU8821_R7F_POWER_UP_CONTROL, 577 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 578 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 579 NAU8821_R7F_POWER_UP_CONTROL, 580 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 581 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 582 NAU8821_R7F_POWER_UP_CONTROL, 583 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 584 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 585 NAU8821_R7F_POWER_UP_CONTROL, 586 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 587 SND_SOC_DAPM_PGA_S("Output DACL", 7, 588 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 589 0, nau8821_output_dac_event, 590 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 591 SND_SOC_DAPM_PGA_S("Output DACR", 7, 592 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 593 0, nau8821_output_dac_event, 594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 595 596 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 597 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 598 NAU8821_R0D_JACK_DET_CTRL, 599 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 600 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 601 NAU8821_R0D_JACK_DET_CTRL, 602 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 603 604 /* High current HPOL/R boost driver */ 605 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 606 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 607 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 608 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 609 610 SND_SOC_DAPM_INPUT("MICL"), 611 SND_SOC_DAPM_INPUT("MICR"), 612 SND_SOC_DAPM_INPUT("DMIC"), 613 SND_SOC_DAPM_OUTPUT("HPOL"), 614 SND_SOC_DAPM_OUTPUT("HPOR"), 615 }; 616 617 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 618 {"DMIC Enable", "Switch", "DMIC"}, 619 {"DMIC Enable", NULL, "DMIC Clock"}, 620 621 {"Frontend PGA L", NULL, "MICL"}, 622 {"Frontend PGA R", NULL, "MICR"}, 623 {"Frontend PGA L", NULL, "MICBIAS"}, 624 {"Frontend PGA R", NULL, "MICBIAS"}, 625 626 {"ADCL Power", NULL, "Frontend PGA L"}, 627 {"ADCR Power", NULL, "Frontend PGA R"}, 628 629 {"ADCL Digital path", NULL, "ADCL Power"}, 630 {"ADCR Digital path", NULL, "ADCR Power"}, 631 {"ADCL Digital path", NULL, "DMIC Enable"}, 632 {"ADCR Digital path", NULL, "DMIC Enable"}, 633 634 {"AIFTX", NULL, "ADCL Digital path"}, 635 {"AIFTX", NULL, "ADCR Digital path"}, 636 637 {"AIFTX", NULL, "System Clock"}, 638 {"AIFRX", NULL, "System Clock"}, 639 640 {"DDACL", NULL, "AIFRX"}, 641 {"DDACR", NULL, "AIFRX"}, 642 643 {"HP amp L", NULL, "DDACL"}, 644 {"HP amp R", NULL, "DDACR"}, 645 646 {"Charge Pump", NULL, "HP amp L"}, 647 {"Charge Pump", NULL, "HP amp R"}, 648 649 {"ADACL", NULL, "Charge Pump"}, 650 {"ADACR", NULL, "Charge Pump"}, 651 {"ADACL Clock", NULL, "ADACL"}, 652 {"ADACR Clock", NULL, "ADACR"}, 653 654 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 655 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 656 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 657 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 658 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 659 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 660 {"Output DACL", NULL, "Output Driver L Stage 3"}, 661 {"Output DACR", NULL, "Output Driver R Stage 3"}, 662 663 {"HPOL Pulldown", NULL, "Output DACL"}, 664 {"HPOR Pulldown", NULL, "Output DACR"}, 665 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 666 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 667 668 {"Class G", NULL, "HP Boost Driver"}, 669 {"HPOL", NULL, "Class G"}, 670 {"HPOR", NULL, "Class G"}, 671 }; 672 673 static int nau8821_clock_check(struct nau8821 *nau8821, 674 int stream, int rate, int osr) 675 { 676 int osrate = 0; 677 678 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 679 if (osr >= ARRAY_SIZE(osr_dac_sel)) 680 return -EINVAL; 681 osrate = osr_dac_sel[osr].osr; 682 } else { 683 if (osr >= ARRAY_SIZE(osr_adc_sel)) 684 return -EINVAL; 685 osrate = osr_adc_sel[osr].osr; 686 } 687 688 if (!osrate || rate * osrate > CLK_DA_AD_MAX) { 689 dev_err(nau8821->dev, 690 "exceed the maximum frequency of CLK_ADC or CLK_DAC"); 691 return -EINVAL; 692 } 693 694 return 0; 695 } 696 697 static int nau8821_hw_params(struct snd_pcm_substream *substream, 698 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 699 { 700 struct snd_soc_component *component = dai->component; 701 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 702 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, clk_div; 703 704 nau8821->fs = params_rate(params); 705 /* CLK_DAC or CLK_ADC = OSR * FS 706 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 707 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 708 * values must be selected such that the maximum frequency is less 709 * than 6.144 MHz. 710 */ 711 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 712 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 713 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 714 if (nau8821_clock_check(nau8821, substream->stream, 715 nau8821->fs, osr)) { 716 return -EINVAL; 717 } 718 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 719 NAU8821_CLK_DAC_SRC_MASK, 720 osr_dac_sel[osr].clk_src << NAU8821_CLK_DAC_SRC_SFT); 721 } else { 722 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 723 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 724 if (nau8821_clock_check(nau8821, substream->stream, 725 nau8821->fs, osr)) { 726 return -EINVAL; 727 } 728 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 729 NAU8821_CLK_ADC_SRC_MASK, 730 osr_adc_sel[osr].clk_src << NAU8821_CLK_ADC_SRC_SFT); 731 } 732 733 /* make BCLK and LRC divde configuration if the codec as master. */ 734 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 735 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 736 /* get the bclk and fs ratio */ 737 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 738 if (bclk_fs <= 32) 739 clk_div = 3; 740 else if (bclk_fs <= 64) 741 clk_div = 2; 742 else if (bclk_fs <= 128) 743 clk_div = 1; 744 else { 745 return -EINVAL; 746 } 747 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 748 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 749 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 750 } 751 752 switch (params_width(params)) { 753 case 16: 754 val_len |= NAU8821_I2S_DL_16; 755 break; 756 case 20: 757 val_len |= NAU8821_I2S_DL_20; 758 break; 759 case 24: 760 val_len |= NAU8821_I2S_DL_24; 761 break; 762 case 32: 763 val_len |= NAU8821_I2S_DL_32; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 770 NAU8821_I2S_DL_MASK, val_len); 771 772 return 0; 773 } 774 775 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 776 { 777 struct snd_soc_component *component = codec_dai->component; 778 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 779 unsigned int ctrl1_val = 0, ctrl2_val = 0; 780 781 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 782 case SND_SOC_DAIFMT_CBP_CFP: 783 ctrl2_val |= NAU8821_I2S_MS_MASTER; 784 break; 785 case SND_SOC_DAIFMT_CBC_CFC: 786 break; 787 default: 788 return -EINVAL; 789 } 790 791 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 792 case SND_SOC_DAIFMT_NB_NF: 793 break; 794 case SND_SOC_DAIFMT_IB_NF: 795 ctrl1_val |= NAU8821_I2S_BP_INV; 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 802 case SND_SOC_DAIFMT_I2S: 803 ctrl1_val |= NAU8821_I2S_DF_I2S; 804 break; 805 case SND_SOC_DAIFMT_LEFT_J: 806 ctrl1_val |= NAU8821_I2S_DF_LEFT; 807 break; 808 case SND_SOC_DAIFMT_RIGHT_J: 809 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 810 break; 811 case SND_SOC_DAIFMT_DSP_A: 812 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 813 break; 814 case SND_SOC_DAIFMT_DSP_B: 815 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 816 ctrl1_val |= NAU8821_I2S_PCMB_EN; 817 break; 818 default: 819 return -EINVAL; 820 } 821 822 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 823 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 824 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 825 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 826 NAU8821_I2S_MS_MASK, ctrl2_val); 827 828 return 0; 829 } 830 831 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 832 int direction) 833 { 834 struct snd_soc_component *component = dai->component; 835 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 836 unsigned int val = 0; 837 838 if (mute) 839 val = NAU8821_DAC_SOFT_MUTE; 840 841 return regmap_update_bits(nau8821->regmap, 842 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 843 } 844 845 static const struct snd_soc_dai_ops nau8821_dai_ops = { 846 .hw_params = nau8821_hw_params, 847 .set_fmt = nau8821_set_dai_fmt, 848 .mute_stream = nau8821_digital_mute, 849 .no_capture_mute = 1, 850 }; 851 852 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 853 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 854 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 855 856 static struct snd_soc_dai_driver nau8821_dai = { 857 .name = NUVOTON_CODEC_DAI, 858 .playback = { 859 .stream_name = "Playback", 860 .channels_min = 1, 861 .channels_max = 2, 862 .rates = NAU8821_RATES, 863 .formats = NAU8821_FORMATS, 864 }, 865 .capture = { 866 .stream_name = "Capture", 867 .channels_min = 1, 868 .channels_max = 2, 869 .rates = NAU8821_RATES, 870 .formats = NAU8821_FORMATS, 871 }, 872 .ops = &nau8821_dai_ops, 873 }; 874 875 876 static bool nau8821_is_jack_inserted(struct regmap *regmap) 877 { 878 bool active_high, is_high; 879 int status, jkdet; 880 881 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 882 active_high = jkdet & NAU8821_JACK_POLARITY; 883 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 884 is_high = status & NAU8821_GPIO2_IN; 885 /* return jack connection status according to jack insertion logic 886 * active high or active low. 887 */ 888 return active_high == is_high; 889 } 890 891 static void nau8821_int_status_clear_all(struct regmap *regmap) 892 { 893 int active_irq, clear_irq, i; 894 895 /* Reset the intrruption status from rightmost bit if the corres- 896 * ponding irq event occurs. 897 */ 898 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 899 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 900 clear_irq = (0x1 << i); 901 if (active_irq & clear_irq) 902 regmap_write(regmap, 903 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 904 } 905 } 906 907 static void nau8821_eject_jack(struct nau8821 *nau8821) 908 { 909 struct snd_soc_dapm_context *dapm = nau8821->dapm; 910 struct regmap *regmap = nau8821->regmap; 911 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 912 913 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 914 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 915 NAU8821_MICBIAS_JKR2, 0); 916 /* HPL/HPR short to ground */ 917 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 918 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 919 snd_soc_component_disable_pin(component, "MICBIAS"); 920 snd_soc_dapm_sync(dapm); 921 922 /* Clear all interruption status */ 923 nau8821_int_status_clear_all(regmap); 924 925 /* Enable the insertion interruption, disable the ejection inter- 926 * ruption, and then bypass de-bounce circuit. 927 */ 928 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 929 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS, 930 NAU8821_IRQ_EJECT_DIS); 931 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 932 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 933 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 934 NAU8821_IRQ_EJECT_EN); 935 936 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 937 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 938 939 /* Close clock for jack type detection at manual mode */ 940 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 941 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 942 943 /* Recover to normal channel input */ 944 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 945 NAU8821_ADC_R_SRC_EN, 0); 946 if (nau8821->key_enable) { 947 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 948 NAU8821_IRQ_KEY_RELEASE_EN | 949 NAU8821_IRQ_KEY_PRESS_EN, 950 NAU8821_IRQ_KEY_RELEASE_EN | 951 NAU8821_IRQ_KEY_PRESS_EN); 952 regmap_update_bits(regmap, 953 NAU8821_R12_INTERRUPT_DIS_CTRL, 954 NAU8821_IRQ_KEY_RELEASE_DIS | 955 NAU8821_IRQ_KEY_PRESS_DIS, 956 NAU8821_IRQ_KEY_RELEASE_DIS | 957 NAU8821_IRQ_KEY_PRESS_DIS); 958 } 959 960 } 961 962 static void nau8821_jdet_work(struct work_struct *work) 963 { 964 struct nau8821 *nau8821 = 965 container_of(work, struct nau8821, jdet_work); 966 struct snd_soc_dapm_context *dapm = nau8821->dapm; 967 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 968 struct regmap *regmap = nau8821->regmap; 969 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 970 971 snd_soc_component_force_enable_pin(component, "MICBIAS"); 972 snd_soc_dapm_sync(dapm); 973 msleep(20); 974 975 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 976 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 977 if (mic_detected) { 978 dev_dbg(nau8821->dev, "Headset connected\n"); 979 event |= SND_JACK_HEADSET; 980 981 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 982 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 983 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 984 /* Latch Right Channel Analog data 985 * input into the Right Channel Filter 986 */ 987 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 988 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 989 if (nau8821->key_enable) { 990 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 991 NAU8821_IRQ_KEY_RELEASE_EN | 992 NAU8821_IRQ_KEY_PRESS_EN, 0); 993 regmap_update_bits(regmap, 994 NAU8821_R12_INTERRUPT_DIS_CTRL, 995 NAU8821_IRQ_KEY_RELEASE_DIS | 996 NAU8821_IRQ_KEY_PRESS_DIS, 0); 997 } 998 } else { 999 dev_dbg(nau8821->dev, "Headphone connected\n"); 1000 event |= SND_JACK_HEADPHONE; 1001 snd_soc_component_disable_pin(component, "MICBIAS"); 1002 snd_soc_dapm_sync(dapm); 1003 } 1004 event_mask |= SND_JACK_HEADSET; 1005 snd_soc_jack_report(nau8821->jack, event, event_mask); 1006 } 1007 1008 /* Enable interruptions with internal clock. */ 1009 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1010 { 1011 struct regmap *regmap = nau8821->regmap; 1012 1013 /* Enable internal VCO needed for interruptions */ 1014 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE) 1015 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1016 1017 /* Chip needs one FSCLK cycle in order to generate interruptions, 1018 * as we cannot guarantee one will be provided by the system. Turning 1019 * master mode on then off enables us to generate that FSCLK cycle 1020 * with a minimum of contention on the clock bus. 1021 */ 1022 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1023 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1024 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1025 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1026 1027 /* Not bypass de-bounce circuit */ 1028 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1029 NAU8821_JACK_DET_DB_BYPASS, 0); 1030 1031 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1032 NAU8821_IRQ_EJECT_EN, 0); 1033 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1034 NAU8821_IRQ_EJECT_DIS, 0); 1035 } 1036 1037 static irqreturn_t nau8821_interrupt(int irq, void *data) 1038 { 1039 struct nau8821 *nau8821 = (struct nau8821 *)data; 1040 struct regmap *regmap = nau8821->regmap; 1041 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1042 1043 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1044 dev_err(nau8821->dev, "failed to read irq status\n"); 1045 return IRQ_NONE; 1046 } 1047 1048 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1049 1050 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1051 NAU8821_JACK_EJECT_DETECTED) { 1052 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1053 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1054 nau8821_eject_jack(nau8821); 1055 event_mask |= SND_JACK_HEADSET; 1056 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK; 1057 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1058 event |= NAU8821_BUTTON; 1059 event_mask |= NAU8821_BUTTON; 1060 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ; 1061 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1062 event_mask = NAU8821_BUTTON; 1063 clear_irq = NAU8821_KEY_RELEASE_IRQ; 1064 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1065 NAU8821_JACK_INSERT_DETECTED) { 1066 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1067 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1068 if (nau8821_is_jack_inserted(regmap)) { 1069 /* detect microphone and jack type */ 1070 cancel_work_sync(&nau8821->jdet_work); 1071 schedule_work(&nau8821->jdet_work); 1072 /* Turn off insertion interruption at manual mode */ 1073 regmap_update_bits(regmap, 1074 NAU8821_R12_INTERRUPT_DIS_CTRL, 1075 NAU8821_IRQ_INSERT_DIS, 1076 NAU8821_IRQ_INSERT_DIS); 1077 regmap_update_bits(regmap, 1078 NAU8821_R0F_INTERRUPT_MASK, 1079 NAU8821_IRQ_INSERT_EN, 1080 NAU8821_IRQ_INSERT_EN); 1081 nau8821_setup_inserted_irq(nau8821); 1082 } else { 1083 dev_warn(nau8821->dev, 1084 "Inserted IRQ fired but not connected\n"); 1085 nau8821_eject_jack(nau8821); 1086 } 1087 } 1088 1089 if (!clear_irq) 1090 clear_irq = active_irq; 1091 /* clears the rightmost interruption */ 1092 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1093 1094 if (event_mask) 1095 snd_soc_jack_report(nau8821->jack, event, event_mask); 1096 1097 return IRQ_HANDLED; 1098 } 1099 1100 static const struct regmap_config nau8821_regmap_config = { 1101 .val_bits = NAU8821_REG_DATA_LEN, 1102 .reg_bits = NAU8821_REG_ADDR_LEN, 1103 1104 .max_register = NAU8821_REG_MAX, 1105 .readable_reg = nau8821_readable_reg, 1106 .writeable_reg = nau8821_writeable_reg, 1107 .volatile_reg = nau8821_volatile_reg, 1108 1109 .cache_type = REGCACHE_RBTREE, 1110 .reg_defaults = nau8821_reg_defaults, 1111 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1112 }; 1113 1114 static int nau8821_component_probe(struct snd_soc_component *component) 1115 { 1116 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1117 struct snd_soc_dapm_context *dapm = 1118 snd_soc_component_get_dapm(component); 1119 1120 nau8821->dapm = dapm; 1121 1122 return 0; 1123 } 1124 1125 /** 1126 * nau8821_calc_fll_param - Calculate FLL parameters. 1127 * @fll_in: external clock provided to codec. 1128 * @fs: sampling rate. 1129 * @fll_param: Pointer to structure of FLL parameters. 1130 * 1131 * Calculate FLL parameters to configure codec. 1132 * 1133 * Returns 0 for success or negative error code. 1134 */ 1135 static int nau8821_calc_fll_param(unsigned int fll_in, 1136 unsigned int fs, struct nau8821_fll *fll_param) 1137 { 1138 u64 fvco, fvco_max; 1139 unsigned int fref, i, fvco_sel; 1140 1141 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1142 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1143 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1144 */ 1145 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1146 fref = fll_in >> fll_pre_scalar[i].param; 1147 if (fref <= NAU_FREF_MAX) 1148 break; 1149 } 1150 if (i == ARRAY_SIZE(fll_pre_scalar)) 1151 return -EINVAL; 1152 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1153 1154 /* Choose the FLL ratio based on FREF */ 1155 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1156 if (fref >= fll_ratio[i].param) 1157 break; 1158 } 1159 if (i == ARRAY_SIZE(fll_ratio)) 1160 return -EINVAL; 1161 fll_param->ratio = fll_ratio[i].val; 1162 1163 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1164 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1165 * guaranteed across the full range of operation. 1166 * FDCO = freq_out * 2 * mclk_src_scaling 1167 */ 1168 fvco_max = 0; 1169 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1170 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1171 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1172 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1173 fvco_max < fvco) { 1174 fvco_max = fvco; 1175 fvco_sel = i; 1176 } 1177 } 1178 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1179 return -EINVAL; 1180 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1181 1182 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1183 * input based on FDCO, FREF and FLL ratio. 1184 */ 1185 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1186 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1187 fll_param->fll_frac = fvco & 0xffffff; 1188 1189 return 0; 1190 } 1191 1192 static void nau8821_fll_apply(struct nau8821 *nau8821, 1193 struct nau8821_fll *fll_param) 1194 { 1195 struct regmap *regmap = nau8821->regmap; 1196 1197 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1198 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1199 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1200 /* Make DSP operate at high speed for better performance. */ 1201 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1202 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1203 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1204 /* FLL 24-bit fractional input */ 1205 regmap_write(regmap, NAU8821_R0A_FLL7, 1206 (fll_param->fll_frac >> 16) & 0xff); 1207 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1208 /* FLL 10-bit integer input */ 1209 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1210 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1211 /* FLL pre-scaler */ 1212 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1213 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1214 NAU8821_HIGHBW_EN | 1215 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1216 /* select divided VCO input */ 1217 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1218 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1219 /* Disable free-running mode */ 1220 regmap_update_bits(regmap, 1221 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1222 if (fll_param->fll_frac) { 1223 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1224 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1225 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1226 NAU8821_FLL_FTR_SW_MASK, 1227 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1228 NAU8821_FLL_FTR_SW_FILTER); 1229 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1230 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1231 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1232 } else { 1233 /* disable FLL loop filter and cutoff frequency */ 1234 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1235 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1236 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1237 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1238 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1239 } 1240 } 1241 1242 /** 1243 * nau8821_set_fll - FLL configuration of nau8821 1244 * @component: codec component 1245 * @pll_id: PLL requested 1246 * @source: clock source 1247 * @freq_in: frequency of input clock source 1248 * @freq_out: must be 256*Fs in order to achieve the best performance 1249 * 1250 * The FLL function can select BCLK or MCLK as the input clock source. 1251 * 1252 * Returns 0 if the parameters have been applied successfully 1253 * or negative error code. 1254 */ 1255 static int nau8821_set_fll(struct snd_soc_component *component, 1256 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1257 { 1258 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1259 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1260 int ret, fs; 1261 1262 fs = freq_out >> 8; 1263 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1264 if (ret) { 1265 dev_err(nau8821->dev, 1266 "Unsupported input clock %d to output clock %d\n", 1267 freq_in, freq_out); 1268 return ret; 1269 } 1270 dev_dbg(nau8821->dev, 1271 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1272 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1273 fll_param->fll_int, fll_param->clk_ref_div); 1274 1275 nau8821_fll_apply(nau8821, fll_param); 1276 mdelay(2); 1277 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1278 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1279 1280 return 0; 1281 } 1282 1283 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1284 { 1285 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1286 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1287 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1288 NAU8821_DCO_EN, 0); 1289 /* Make DSP operate as default setting for power saving. */ 1290 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1291 NAU8821_ICTRL_LATCH_MASK, 0); 1292 } 1293 1294 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1295 int clk_id, unsigned int freq) 1296 { 1297 struct regmap *regmap = nau8821->regmap; 1298 1299 switch (clk_id) { 1300 case NAU8821_CLK_DIS: 1301 /* Clock provided externally and disable internal VCO clock */ 1302 nau8821_configure_mclk_as_sysclk(regmap); 1303 break; 1304 case NAU8821_CLK_MCLK: 1305 nau8821_configure_mclk_as_sysclk(regmap); 1306 /* MCLK not changed by clock tree */ 1307 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1308 NAU8821_CLK_MCLK_SRC_MASK, 0); 1309 break; 1310 case NAU8821_CLK_INTERNAL: 1311 if (nau8821_is_jack_inserted(regmap)) { 1312 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1313 NAU8821_DCO_EN, NAU8821_DCO_EN); 1314 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1315 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1316 /* Decrease the VCO frequency and make DSP operate 1317 * as default setting for power saving. 1318 */ 1319 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1320 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1321 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1322 NAU8821_ICTRL_LATCH_MASK | 1323 NAU8821_FLL_RATIO_MASK, 0x10); 1324 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1325 NAU8821_SDM_EN, NAU8821_SDM_EN); 1326 } 1327 break; 1328 case NAU8821_CLK_FLL_MCLK: 1329 /* Higher FLL reference input frequency can only set lower 1330 * gain error, such as 0000 for input reference from MCLK 1331 * 12.288Mhz. 1332 */ 1333 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1334 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1335 NAU8821_FLL_CLK_SRC_MCLK | 0); 1336 break; 1337 case NAU8821_CLK_FLL_BLK: 1338 /* If FLL reference input is from low frequency source, 1339 * higher error gain can apply such as 0xf which has 1340 * the most sensitive gain error correction threshold, 1341 * Therefore, FLL has the most accurate DCO to 1342 * target frequency. 1343 */ 1344 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1345 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1346 NAU8821_FLL_CLK_SRC_BLK | 1347 (0xf << NAU8821_GAIN_ERR_SFT)); 1348 break; 1349 case NAU8821_CLK_FLL_FS: 1350 /* If FLL reference input is from low frequency source, 1351 * higher error gain can apply such as 0xf which has 1352 * the most sensitive gain error correction threshold, 1353 * Therefore, FLL has the most accurate DCO to 1354 * target frequency. 1355 */ 1356 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1357 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1358 NAU8821_FLL_CLK_SRC_FS | 1359 (0xf << NAU8821_GAIN_ERR_SFT)); 1360 break; 1361 default: 1362 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1363 return -EINVAL; 1364 } 1365 nau8821->clk_id = clk_id; 1366 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1367 nau8821->clk_id); 1368 1369 return 0; 1370 } 1371 1372 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1373 int source, unsigned int freq, int dir) 1374 { 1375 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1376 1377 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1378 } 1379 1380 static int nau8821_resume_setup(struct nau8821 *nau8821) 1381 { 1382 struct regmap *regmap = nau8821->regmap; 1383 1384 /* Close clock when jack type detection at manual mode */ 1385 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1386 if (nau8821->irq) { 1387 /* Clear all interruption status */ 1388 nau8821_int_status_clear_all(regmap); 1389 1390 /* Enable both insertion and ejection interruptions, and then 1391 * bypass de-bounce circuit. 1392 */ 1393 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1394 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1395 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1396 NAU8821_JACK_DET_DB_BYPASS, 1397 NAU8821_JACK_DET_DB_BYPASS); 1398 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1399 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int nau8821_set_bias_level(struct snd_soc_component *component, 1406 enum snd_soc_bias_level level) 1407 { 1408 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1409 struct regmap *regmap = nau8821->regmap; 1410 1411 switch (level) { 1412 case SND_SOC_BIAS_ON: 1413 break; 1414 1415 case SND_SOC_BIAS_PREPARE: 1416 break; 1417 1418 case SND_SOC_BIAS_STANDBY: 1419 /* Setup codec configuration after resume */ 1420 if (snd_soc_component_get_bias_level(component) == 1421 SND_SOC_BIAS_OFF) 1422 nau8821_resume_setup(nau8821); 1423 break; 1424 1425 case SND_SOC_BIAS_OFF: 1426 /* HPL/HPR short to ground */ 1427 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1428 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1429 if (nau8821->irq) { 1430 /* Reset the configuration of jack type for detection. 1431 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1432 */ 1433 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1434 NAU8821_MICBIAS_JKR2, 0); 1435 /* Turn off all interruptions before system shutdown. 1436 * Keep theinterruption quiet before resume 1437 * setup completes. 1438 */ 1439 regmap_write(regmap, 1440 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1441 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1442 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1443 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1444 } 1445 break; 1446 default: 1447 break; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1454 { 1455 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1456 1457 if (nau8821->irq) 1458 disable_irq(nau8821->irq); 1459 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1460 /* Power down codec power; don't support button wakeup */ 1461 snd_soc_component_disable_pin(component, "MICBIAS"); 1462 snd_soc_dapm_sync(nau8821->dapm); 1463 regcache_cache_only(nau8821->regmap, true); 1464 regcache_mark_dirty(nau8821->regmap); 1465 1466 return 0; 1467 } 1468 1469 static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1470 { 1471 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1472 1473 regcache_cache_only(nau8821->regmap, false); 1474 regcache_sync(nau8821->regmap); 1475 if (nau8821->irq) 1476 enable_irq(nau8821->irq); 1477 1478 return 0; 1479 } 1480 1481 static const struct snd_soc_component_driver nau8821_component_driver = { 1482 .probe = nau8821_component_probe, 1483 .set_sysclk = nau8821_set_sysclk, 1484 .set_pll = nau8821_set_fll, 1485 .set_bias_level = nau8821_set_bias_level, 1486 .suspend = nau8821_suspend, 1487 .resume = nau8821_resume, 1488 .controls = nau8821_controls, 1489 .num_controls = ARRAY_SIZE(nau8821_controls), 1490 .dapm_widgets = nau8821_dapm_widgets, 1491 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1492 .dapm_routes = nau8821_dapm_routes, 1493 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1494 .suspend_bias_off = 1, 1495 .idle_bias_on = 1, 1496 .use_pmdown_time = 1, 1497 .endianness = 1, 1498 }; 1499 1500 /** 1501 * nau8821_enable_jack_detect - Specify a jack for event reporting 1502 * 1503 * @component: component to register the jack with 1504 * @jack: jack to use to report headset and button events on 1505 * 1506 * After this function has been called the headset insert/remove and button 1507 * events will be routed to the given jack. Jack can be null to stop 1508 * reporting. 1509 */ 1510 int nau8821_enable_jack_detect(struct snd_soc_component *component, 1511 struct snd_soc_jack *jack) 1512 { 1513 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1514 int ret; 1515 1516 nau8821->jack = jack; 1517 /* Initiate jack detection work queue */ 1518 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1519 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1520 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1521 "nau8821", nau8821); 1522 if (ret) { 1523 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1524 nau8821->irq, ret); 1525 return ret; 1526 } 1527 1528 return ret; 1529 } 1530 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1531 1532 static void nau8821_reset_chip(struct regmap *regmap) 1533 { 1534 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1535 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1536 } 1537 1538 static void nau8821_print_device_properties(struct nau8821 *nau8821) 1539 { 1540 struct device *dev = nau8821->dev; 1541 1542 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1543 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1544 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1545 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1546 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1547 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1548 dev_dbg(dev, "jack-insert-debounce: %d\n", 1549 nau8821->jack_insert_debounce); 1550 dev_dbg(dev, "jack-eject-debounce: %d\n", 1551 nau8821->jack_eject_debounce); 1552 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1553 nau8821->dmic_clk_threshold); 1554 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1555 } 1556 1557 static int nau8821_read_device_properties(struct device *dev, 1558 struct nau8821 *nau8821) 1559 { 1560 int ret; 1561 1562 nau8821->jkdet_enable = device_property_read_bool(dev, 1563 "nuvoton,jkdet-enable"); 1564 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1565 "nuvoton,jkdet-pull-enable"); 1566 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1567 "nuvoton,jkdet-pull-up"); 1568 nau8821->key_enable = device_property_read_bool(dev, 1569 "nuvoton,key-enable"); 1570 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1571 &nau8821->jkdet_polarity); 1572 if (ret) 1573 nau8821->jkdet_polarity = 1; 1574 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1575 &nau8821->micbias_voltage); 1576 if (ret) 1577 nau8821->micbias_voltage = 6; 1578 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1579 &nau8821->vref_impedance); 1580 if (ret) 1581 nau8821->vref_impedance = 2; 1582 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1583 &nau8821->jack_insert_debounce); 1584 if (ret) 1585 nau8821->jack_insert_debounce = 7; 1586 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1587 &nau8821->jack_eject_debounce); 1588 if (ret) 1589 nau8821->jack_eject_debounce = 0; 1590 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1591 &nau8821->dmic_clk_threshold); 1592 if (ret) 1593 nau8821->dmic_clk_threshold = 3072000; 1594 1595 return 0; 1596 } 1597 1598 static void nau8821_init_regs(struct nau8821 *nau8821) 1599 { 1600 struct regmap *regmap = nau8821->regmap; 1601 1602 /* Enable Bias/Vmid */ 1603 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1604 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1605 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1606 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1607 /* VMID Tieoff setting and enable TESTDAC. 1608 * This sets the analog DAC inputs to a '0' input signal to avoid 1609 * any glitches due to power up transients in both the analog and 1610 * digital DAC circuit. 1611 */ 1612 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1613 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1614 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1615 NAU8821_BIAS_TESTDAC_EN); 1616 /* Disable short Frame Sync detection logic */ 1617 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1618 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1619 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1620 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1621 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1622 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1623 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1624 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1625 /* Class G timer 64ms */ 1626 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1627 NAU8821_CLASSG_TIMER_MASK, 1628 0x20 << NAU8821_CLASSG_TIMER_SFT); 1629 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1630 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1631 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1632 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1633 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1634 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1635 /* Disable DACR/L power */ 1636 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1637 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1638 /* DAC clock delay 2ns, VREF */ 1639 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1640 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1641 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1642 (0x3 << NAU8821_DAC_VREF_SFT)); 1643 1644 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1645 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1646 /* Default oversampling/decimations settings are unusable 1647 * (audible hiss). Set it to something better. 1648 */ 1649 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1650 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1651 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1652 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1653 } 1654 1655 static int nau8821_setup_irq(struct nau8821 *nau8821) 1656 { 1657 struct regmap *regmap = nau8821->regmap; 1658 1659 /* Jack detection */ 1660 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1661 NAU8821_JKDET_OUTPUT_EN, 1662 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1663 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1664 NAU8821_JKDET_PULL_EN, 1665 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1666 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1667 NAU8821_JKDET_PULL_UP, 1668 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1669 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1670 NAU8821_JACK_POLARITY, 1671 /* jkdet_polarity - 1 is for active-low */ 1672 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1673 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1674 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1675 nau8821->jack_insert_debounce << 1676 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1677 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1678 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1679 nau8821->jack_eject_debounce << 1680 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1681 /* Pull up IRQ pin */ 1682 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1683 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1684 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1685 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1686 /* Disable interruption before codec initiation done */ 1687 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1688 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1689 1690 return 0; 1691 } 1692 1693 static int nau8821_i2c_probe(struct i2c_client *i2c) 1694 { 1695 struct device *dev = &i2c->dev; 1696 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1697 int ret, value; 1698 1699 if (!nau8821) { 1700 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1701 if (!nau8821) 1702 return -ENOMEM; 1703 nau8821_read_device_properties(dev, nau8821); 1704 } 1705 i2c_set_clientdata(i2c, nau8821); 1706 1707 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1708 if (IS_ERR(nau8821->regmap)) 1709 return PTR_ERR(nau8821->regmap); 1710 1711 nau8821->dev = dev; 1712 nau8821->irq = i2c->irq; 1713 nau8821_print_device_properties(nau8821); 1714 1715 nau8821_reset_chip(nau8821->regmap); 1716 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1717 if (ret) { 1718 dev_err(dev, "Failed to read device id (%d)\n", ret); 1719 return ret; 1720 } 1721 nau8821_init_regs(nau8821); 1722 1723 if (i2c->irq) 1724 nau8821_setup_irq(nau8821); 1725 1726 ret = devm_snd_soc_register_component(&i2c->dev, 1727 &nau8821_component_driver, &nau8821_dai, 1); 1728 1729 return ret; 1730 } 1731 1732 static const struct i2c_device_id nau8821_i2c_ids[] = { 1733 { "nau8821", 0 }, 1734 { } 1735 }; 1736 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1737 1738 #ifdef CONFIG_OF 1739 static const struct of_device_id nau8821_of_ids[] = { 1740 { .compatible = "nuvoton,nau8821", }, 1741 {} 1742 }; 1743 MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1744 #endif 1745 1746 #ifdef CONFIG_ACPI 1747 static const struct acpi_device_id nau8821_acpi_match[] = { 1748 { "NVTN2020", 0 }, 1749 {}, 1750 }; 1751 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1752 #endif 1753 1754 static struct i2c_driver nau8821_driver = { 1755 .driver = { 1756 .name = "nau8821", 1757 .of_match_table = of_match_ptr(nau8821_of_ids), 1758 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1759 }, 1760 .probe_new = nau8821_i2c_probe, 1761 .id_table = nau8821_i2c_ids, 1762 }; 1763 module_i2c_driver(nau8821_driver); 1764 1765 MODULE_DESCRIPTION("ASoC nau8821 driver"); 1766 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 1767 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 1768 MODULE_LICENSE("GPL"); 1769