1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * nau8810.c -- NAU8810 ALSA Soc Audio driver 4 * 5 * Copyright 2016 Nuvoton Technology Corp. 6 * 7 * Author: David Lin <ctlin0@nuvoton.com> 8 * 9 * Based on WM8974.c 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/initval.h> 26 #include <sound/tlv.h> 27 28 #include "nau8810.h" 29 30 #define NAU_PLL_FREQ_MAX 100000000 31 #define NAU_PLL_FREQ_MIN 90000000 32 #define NAU_PLL_REF_MAX 33000000 33 #define NAU_PLL_REF_MIN 8000000 34 #define NAU_PLL_OPTOP_MIN 6 35 36 37 static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 }; 38 39 static const struct reg_default nau8810_reg_defaults[] = { 40 { NAU8810_REG_POWER1, 0x0000 }, 41 { NAU8810_REG_POWER2, 0x0000 }, 42 { NAU8810_REG_POWER3, 0x0000 }, 43 { NAU8810_REG_IFACE, 0x0050 }, 44 { NAU8810_REG_COMP, 0x0000 }, 45 { NAU8810_REG_CLOCK, 0x0140 }, 46 { NAU8810_REG_SMPLR, 0x0000 }, 47 { NAU8810_REG_DAC, 0x0000 }, 48 { NAU8810_REG_DACGAIN, 0x00FF }, 49 { NAU8810_REG_ADC, 0x0100 }, 50 { NAU8810_REG_ADCGAIN, 0x00FF }, 51 { NAU8810_REG_EQ1, 0x012C }, 52 { NAU8810_REG_EQ2, 0x002C }, 53 { NAU8810_REG_EQ3, 0x002C }, 54 { NAU8810_REG_EQ4, 0x002C }, 55 { NAU8810_REG_EQ5, 0x002C }, 56 { NAU8810_REG_DACLIM1, 0x0032 }, 57 { NAU8810_REG_DACLIM2, 0x0000 }, 58 { NAU8810_REG_NOTCH1, 0x0000 }, 59 { NAU8810_REG_NOTCH2, 0x0000 }, 60 { NAU8810_REG_NOTCH3, 0x0000 }, 61 { NAU8810_REG_NOTCH4, 0x0000 }, 62 { NAU8810_REG_ALC1, 0x0038 }, 63 { NAU8810_REG_ALC2, 0x000B }, 64 { NAU8810_REG_ALC3, 0x0032 }, 65 { NAU8810_REG_NOISEGATE, 0x0000 }, 66 { NAU8810_REG_PLLN, 0x0008 }, 67 { NAU8810_REG_PLLK1, 0x000C }, 68 { NAU8810_REG_PLLK2, 0x0093 }, 69 { NAU8810_REG_PLLK3, 0x00E9 }, 70 { NAU8810_REG_ATTEN, 0x0000 }, 71 { NAU8810_REG_INPUT_SIGNAL, 0x0003 }, 72 { NAU8810_REG_PGAGAIN, 0x0010 }, 73 { NAU8810_REG_ADCBOOST, 0x0100 }, 74 { NAU8810_REG_OUTPUT, 0x0002 }, 75 { NAU8810_REG_SPKMIX, 0x0001 }, 76 { NAU8810_REG_SPKGAIN, 0x0039 }, 77 { NAU8810_REG_MONOMIX, 0x0001 }, 78 { NAU8810_REG_POWER4, 0x0000 }, 79 { NAU8810_REG_TSLOTCTL1, 0x0000 }, 80 { NAU8810_REG_TSLOTCTL2, 0x0020 }, 81 { NAU8810_REG_DEVICE_REVID, 0x0000 }, 82 { NAU8810_REG_I2C_DEVICEID, 0x001A }, 83 { NAU8810_REG_ADDITIONID, 0x00CA }, 84 { NAU8810_REG_RESERVE, 0x0124 }, 85 { NAU8810_REG_OUTCTL, 0x0001 }, 86 { NAU8810_REG_ALC1ENHAN1, 0x0010 }, 87 { NAU8810_REG_ALC1ENHAN2, 0x0000 }, 88 { NAU8810_REG_MISCCTL, 0x0000 }, 89 { NAU8810_REG_OUTTIEOFF, 0x0000 }, 90 { NAU8810_REG_AGCP2POUT, 0x0000 }, 91 { NAU8810_REG_AGCPOUT, 0x0000 }, 92 { NAU8810_REG_AMTCTL, 0x0000 }, 93 { NAU8810_REG_OUTTIEOFFMAN, 0x0000 }, 94 }; 95 96 static bool nau8810_readable_reg(struct device *dev, unsigned int reg) 97 { 98 switch (reg) { 99 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: 100 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: 101 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: 102 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: 103 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: 104 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: 105 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: 106 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: 107 case NAU8810_REG_ADCBOOST: 108 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: 109 case NAU8810_REG_SPKGAIN: 110 case NAU8810_REG_MONOMIX: 111 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: 112 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE: 113 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2: 114 case NAU8810_REG_MISCCTL: 115 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: 116 return true; 117 default: 118 return false; 119 } 120 } 121 122 static bool nau8810_writeable_reg(struct device *dev, unsigned int reg) 123 { 124 switch (reg) { 125 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: 126 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: 127 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: 128 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: 129 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: 130 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: 131 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: 132 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: 133 case NAU8810_REG_ADCBOOST: 134 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: 135 case NAU8810_REG_SPKGAIN: 136 case NAU8810_REG_MONOMIX: 137 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: 138 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2: 139 case NAU8810_REG_MISCCTL: 140 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: 141 return true; 142 default: 143 return false; 144 } 145 } 146 147 static bool nau8810_volatile_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case NAU8810_REG_RESET: 151 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE: 152 return true; 153 default: 154 return false; 155 } 156 } 157 158 /* The EQ parameters get function is to get the 5 band equalizer control. 159 * The regmap raw read can't work here because regmap doesn't provide 160 * value format for value width of 9 bits. Therefore, the driver reads data 161 * from cache and makes value format according to the endianness of 162 * bytes type control element. 163 */ 164 static int nau8810_eq_get(struct snd_kcontrol *kcontrol, 165 struct snd_ctl_elem_value *ucontrol) 166 { 167 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 168 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 169 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 170 int i, reg, reg_val; 171 u16 *val; 172 173 val = (u16 *)ucontrol->value.bytes.data; 174 reg = NAU8810_REG_EQ1; 175 for (i = 0; i < params->max / sizeof(u16); i++) { 176 regmap_read(nau8810->regmap, reg + i, ®_val); 177 /* conversion of 16-bit integers between native CPU format 178 * and big endian format 179 */ 180 reg_val = cpu_to_be16(reg_val); 181 memcpy(val + i, ®_val, sizeof(reg_val)); 182 } 183 184 return 0; 185 } 186 187 /* The EQ parameters put function is to make configuration of 5 band equalizer 188 * control. These configuration includes central frequency, equalizer gain, 189 * cut-off frequency, bandwidth control, and equalizer path. 190 * The regmap raw write can't work here because regmap doesn't provide 191 * register and value format for register with address 7 bits and value 9 bits. 192 * Therefore, the driver makes value format according to the endianness of 193 * bytes type control element and writes data to codec. 194 */ 195 static int nau8810_eq_put(struct snd_kcontrol *kcontrol, 196 struct snd_ctl_elem_value *ucontrol) 197 { 198 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 199 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 200 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 201 void *data; 202 u16 *val, value; 203 int i, reg, ret; 204 205 data = kmemdup(ucontrol->value.bytes.data, 206 params->max, GFP_KERNEL | GFP_DMA); 207 if (!data) 208 return -ENOMEM; 209 210 val = (u16 *)data; 211 reg = NAU8810_REG_EQ1; 212 for (i = 0; i < params->max / sizeof(u16); i++) { 213 /* conversion of 16-bit integers between native CPU format 214 * and big endian format 215 */ 216 value = be16_to_cpu(*(val + i)); 217 ret = regmap_write(nau8810->regmap, reg + i, value); 218 if (ret) { 219 dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n", 220 reg + i, ret); 221 kfree(data); 222 return ret; 223 } 224 } 225 kfree(data); 226 227 return 0; 228 } 229 230 static const char * const nau8810_companding[] = { 231 "Off", "NC", "u-law", "A-law" }; 232 233 static const struct soc_enum nau8810_companding_adc_enum = 234 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT, 235 ARRAY_SIZE(nau8810_companding), nau8810_companding); 236 237 static const struct soc_enum nau8810_companding_dac_enum = 238 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT, 239 ARRAY_SIZE(nau8810_companding), nau8810_companding); 240 241 static const char * const nau8810_deemp[] = { 242 "None", "32kHz", "44.1kHz", "48kHz" }; 243 244 static const struct soc_enum nau8810_deemp_enum = 245 SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT, 246 ARRAY_SIZE(nau8810_deemp), nau8810_deemp); 247 248 static const char * const nau8810_eqmode[] = {"Capture", "Playback" }; 249 250 static const struct soc_enum nau8810_eqmode_enum = 251 SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT, 252 ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode); 253 254 static const char * const nau8810_alc[] = {"Normal", "Limiter" }; 255 256 static const struct soc_enum nau8810_alc_enum = 257 SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT, 258 ARRAY_SIZE(nau8810_alc), nau8810_alc); 259 260 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 261 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 262 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); 263 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); 264 265 static const struct snd_kcontrol_new nau8810_snd_controls[] = { 266 SOC_ENUM("ADC Companding", nau8810_companding_adc_enum), 267 SOC_ENUM("DAC Companding", nau8810_companding_dac_enum), 268 SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum), 269 270 SOC_ENUM("EQ Function", nau8810_eqmode_enum), 271 SND_SOC_BYTES_EXT("EQ Parameters", 10, 272 nau8810_eq_get, nau8810_eq_put), 273 274 SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC, 275 NAU8810_DACPL_SFT, 1, 0), 276 SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN, 277 NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv), 278 279 SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC, 280 NAU8810_HPFEN_SFT, 1, 0), 281 SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC, 282 NAU8810_HPF_SFT, 0x7, 0), 283 284 SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC, 285 NAU8810_ADCPL_SFT, 1, 0), 286 SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN, 287 NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv), 288 289 SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1, 290 NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv), 291 SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2, 292 NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv), 293 SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3, 294 NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv), 295 SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4, 296 NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv), 297 SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5, 298 NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv), 299 300 SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1, 301 NAU8810_DACLIMEN_SFT, 1, 0), 302 SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1, 303 NAU8810_DACLIMDCY_SFT, 0xf, 0), 304 SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1, 305 NAU8810_DACLIMATK_SFT, 0xf, 0), 306 SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2, 307 NAU8810_DACLIMTHL_SFT, 0x7, 0), 308 SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2, 309 NAU8810_DACLIMBST_SFT, 0xf, 0), 310 311 SOC_ENUM("ALC Mode", nau8810_alc_enum), 312 SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1, 313 NAU8810_ALCEN_SFT, 1, 0), 314 SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1, 315 NAU8810_ALCMXGAIN_SFT, 0x7, 0), 316 SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1, 317 NAU8810_ALCMINGAIN_SFT, 0x7, 0), 318 SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2, 319 NAU8810_ALCZC_SFT, 1, 0), 320 SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2, 321 NAU8810_ALCHT_SFT, 0xf, 0), 322 SOC_SINGLE("ALC Target", NAU8810_REG_ALC2, 323 NAU8810_ALCSL_SFT, 0xf, 0), 324 SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3, 325 NAU8810_ALCDCY_SFT, 0xf, 0), 326 SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3, 327 NAU8810_ALCATK_SFT, 0xf, 0), 328 SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE, 329 NAU8810_ALCNEN_SFT, 1, 0), 330 SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE, 331 NAU8810_ALCNTH_SFT, 0x7, 0), 332 333 SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN, 334 NAU8810_PGAZC_SFT, 1, 0), 335 SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN, 336 NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv), 337 338 SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN, 339 NAU8810_SPKZC_SFT, 1, 0), 340 SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN, 341 NAU8810_SPKMT_SFT, 1, 0), 342 SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN, 343 NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv), 344 345 SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST, 346 NAU8810_PGABST_SFT, 1, 0), 347 SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX, 348 NAU8810_MOUTMXMT_SFT, 1, 0), 349 350 SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC, 351 NAU8810_DACOS_SFT, 1, 0), 352 SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC, 353 NAU8810_ADCOS_SFT, 1, 0), 354 }; 355 356 /* Speaker Output Mixer */ 357 static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = { 358 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX, 359 NAU8810_BYPSPK_SFT, 1, 0), 360 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX, 361 NAU8810_DACSPK_SFT, 1, 0), 362 }; 363 364 /* Mono Output Mixer */ 365 static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = { 366 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX, 367 NAU8810_BYPMOUT_SFT, 1, 0), 368 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX, 369 NAU8810_DACMOUT_SFT, 1, 0), 370 }; 371 372 /* PGA Mute */ 373 static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = { 374 SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN, 375 NAU8810_PGAMT_SFT, 1, 1), 376 SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST, 377 NAU8810_PMICBSTGAIN_SFT, 0x7, 0), 378 }; 379 380 /* Input PGA */ 381 static const struct snd_kcontrol_new nau8810_inpga[] = { 382 SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL, 383 NAU8810_NMICPGA_SFT, 1, 0), 384 SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL, 385 NAU8810_PMICPGA_SFT, 1, 0), 386 }; 387 388 /* Loopback Switch */ 389 static const struct snd_kcontrol_new nau8810_loopback = 390 SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP, 391 NAU8810_ADDAP_SFT, 1, 0); 392 393 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source, 394 struct snd_soc_dapm_widget *sink) 395 { 396 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 397 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 398 unsigned int value; 399 400 regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value); 401 return (value & NAU8810_CLKM_MASK); 402 } 403 404 static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = { 405 SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3, 406 NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0], 407 ARRAY_SIZE(nau8810_speaker_mixer_controls)), 408 SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3, 409 NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0], 410 ARRAY_SIZE(nau8810_mono_mixer_controls)), 411 SND_SOC_DAPM_DAC("DAC", "Playback", NAU8810_REG_POWER3, 412 NAU8810_DAC_EN_SFT, 0), 413 SND_SOC_DAPM_ADC("ADC", "Capture", NAU8810_REG_POWER2, 414 NAU8810_ADC_EN_SFT, 0), 415 SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3, 416 NAU8810_NSPK_EN_SFT, 0, NULL, 0), 417 SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3, 418 NAU8810_PSPK_EN_SFT, 0, NULL, 0), 419 SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3, 420 NAU8810_MOUT_EN_SFT, 0, NULL, 0), 421 422 SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2, 423 NAU8810_PGA_EN_SFT, 0, nau8810_inpga, 424 ARRAY_SIZE(nau8810_inpga)), 425 SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2, 426 NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls, 427 ARRAY_SIZE(nau8810_pgaboost_mixer_controls)), 428 429 SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1, 430 NAU8810_MICBIAS_EN_SFT, 0, NULL, 0), 431 SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1, 432 NAU8810_PLL_EN_SFT, 0, NULL, 0), 433 434 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0, 435 &nau8810_loopback), 436 437 SND_SOC_DAPM_INPUT("MICN"), 438 SND_SOC_DAPM_INPUT("MICP"), 439 SND_SOC_DAPM_OUTPUT("MONOOUT"), 440 SND_SOC_DAPM_OUTPUT("SPKOUTP"), 441 SND_SOC_DAPM_OUTPUT("SPKOUTN"), 442 }; 443 444 static const struct snd_soc_dapm_route nau8810_dapm_routes[] = { 445 {"DAC", NULL, "PLL", check_mclk_select_pll}, 446 447 /* Mono output mixer */ 448 {"Mono Mixer", "PCM Playback Switch", "DAC"}, 449 {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"}, 450 451 /* Speaker output mixer */ 452 {"Speaker Mixer", "PCM Playback Switch", "DAC"}, 453 {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"}, 454 455 /* Outputs */ 456 {"Mono Out", NULL, "Mono Mixer"}, 457 {"MONOOUT", NULL, "Mono Out"}, 458 {"SpkN Out", NULL, "Speaker Mixer"}, 459 {"SpkP Out", NULL, "Speaker Mixer"}, 460 {"SPKOUTN", NULL, "SpkN Out"}, 461 {"SPKOUTP", NULL, "SpkP Out"}, 462 463 /* Input Boost Stage */ 464 {"ADC", NULL, "Input Boost Stage"}, 465 {"ADC", NULL, "PLL", check_mclk_select_pll}, 466 {"Input Boost Stage", "PGA Mute Switch", "Input PGA"}, 467 {"Input Boost Stage", "PMIC PGA Switch", "MICP"}, 468 469 /* Input PGA */ 470 {"Input PGA", NULL, "Mic Bias"}, 471 {"Input PGA", "MicN Switch", "MICN"}, 472 {"Input PGA", "MicP Switch", "MICP"}, 473 474 /* Digital Looptack */ 475 {"Digital Loopback", "Switch", "ADC"}, 476 {"DAC", NULL, "Digital Loopback"}, 477 }; 478 479 static int nau8810_set_sysclk(struct snd_soc_dai *dai, 480 int clk_id, unsigned int freq, int dir) 481 { 482 struct snd_soc_component *component = dai->component; 483 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 484 485 nau8810->clk_id = clk_id; 486 nau8810->sysclk = freq; 487 dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n", 488 freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK"); 489 490 return 0; 491 } 492 493 static int nau8810_calc_pll(unsigned int pll_in, 494 unsigned int fs, struct nau8810_pll *pll_param) 495 { 496 u64 f2, f2_max, pll_ratio; 497 int i, scal_sel; 498 499 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN) 500 return -EINVAL; 501 502 f2_max = 0; 503 scal_sel = ARRAY_SIZE(nau8810_mclk_scaler); 504 for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) { 505 f2 = 256ULL * fs * 4 * nau8810_mclk_scaler[i]; 506 f2 = div_u64(f2, 10); 507 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX && 508 f2_max < f2) { 509 f2_max = f2; 510 scal_sel = i; 511 } 512 } 513 if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel) 514 return -EINVAL; 515 pll_param->mclk_scaler = scal_sel; 516 f2 = f2_max; 517 518 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional 519 * input; round up the 24+4bit. 520 */ 521 pll_ratio = div_u64(f2 << 28, pll_in); 522 pll_param->pre_factor = 0; 523 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { 524 pll_ratio <<= 1; 525 pll_param->pre_factor = 1; 526 } 527 pll_param->pll_int = (pll_ratio >> 28) & 0xF; 528 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); 529 530 return 0; 531 } 532 533 static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id, 534 int source, unsigned int freq_in, unsigned int freq_out) 535 { 536 struct snd_soc_component *component = codec_dai->component; 537 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 538 struct regmap *map = nau8810->regmap; 539 struct nau8810_pll *pll_param = &nau8810->pll; 540 int ret, fs; 541 542 fs = freq_out / 256; 543 ret = nau8810_calc_pll(freq_in, fs, pll_param); 544 if (ret < 0) { 545 dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in); 546 return ret; 547 } 548 dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n", 549 pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler, 550 pll_param->pre_factor); 551 552 regmap_update_bits(map, NAU8810_REG_PLLN, 553 NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK, 554 (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) | 555 pll_param->pll_int); 556 regmap_write(map, NAU8810_REG_PLLK1, 557 (pll_param->pll_frac >> NAU8810_PLLK1_SFT) & 558 NAU8810_PLLK1_MASK); 559 regmap_write(map, NAU8810_REG_PLLK2, 560 (pll_param->pll_frac >> NAU8810_PLLK2_SFT) & 561 NAU8810_PLLK2_MASK); 562 regmap_write(map, NAU8810_REG_PLLK3, 563 pll_param->pll_frac & NAU8810_PLLK3_MASK); 564 regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK, 565 pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT); 566 regmap_update_bits(map, NAU8810_REG_CLOCK, 567 NAU8810_CLKM_MASK, NAU8810_CLKM_PLL); 568 569 return 0; 570 } 571 572 static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai, 573 unsigned int fmt) 574 { 575 struct snd_soc_component *component = codec_dai->component; 576 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 577 u16 ctrl1_val = 0, ctrl2_val = 0; 578 579 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 580 case SND_SOC_DAIFMT_CBM_CFM: 581 ctrl2_val |= NAU8810_CLKIO_MASTER; 582 break; 583 case SND_SOC_DAIFMT_CBS_CFS: 584 break; 585 default: 586 return -EINVAL; 587 } 588 589 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 590 case SND_SOC_DAIFMT_I2S: 591 ctrl1_val |= NAU8810_AIFMT_I2S; 592 break; 593 case SND_SOC_DAIFMT_RIGHT_J: 594 break; 595 case SND_SOC_DAIFMT_LEFT_J: 596 ctrl1_val |= NAU8810_AIFMT_LEFT; 597 break; 598 case SND_SOC_DAIFMT_DSP_A: 599 ctrl1_val |= NAU8810_AIFMT_PCM_A; 600 break; 601 default: 602 return -EINVAL; 603 } 604 605 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 606 case SND_SOC_DAIFMT_NB_NF: 607 break; 608 case SND_SOC_DAIFMT_IB_IF: 609 ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF; 610 break; 611 case SND_SOC_DAIFMT_IB_NF: 612 ctrl1_val |= NAU8810_BCLKP_IB; 613 break; 614 case SND_SOC_DAIFMT_NB_IF: 615 ctrl1_val |= NAU8810_FSP_IF; 616 break; 617 default: 618 return -EINVAL; 619 } 620 621 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, 622 NAU8810_AIFMT_MASK | NAU8810_FSP_IF | 623 NAU8810_BCLKP_IB, ctrl1_val); 624 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 625 NAU8810_CLKIO_MASK, ctrl2_val); 626 627 return 0; 628 } 629 630 static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate) 631 { 632 int i, sclk, imclk = rate * 256, div = 0; 633 634 if (!nau8810->sysclk) { 635 dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n"); 636 return -EINVAL; 637 } 638 639 /* Configure the master clock prescaler div to make system 640 * clock to approximate the internal master clock (IMCLK); 641 * and large or equal to IMCLK. 642 */ 643 for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) { 644 sclk = (nau8810->sysclk * 10) / 645 nau8810_mclk_scaler[i]; 646 if (sclk < imclk) 647 break; 648 div = i; 649 } 650 dev_dbg(nau8810->dev, 651 "master clock prescaler %x for fs %d\n", div, rate); 652 653 /* master clock from MCLK and disable PLL */ 654 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 655 NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT)); 656 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 657 NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK); 658 659 return 0; 660 } 661 662 static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream, 663 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 664 { 665 struct snd_soc_component *component = dai->component; 666 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 667 int val_len = 0, val_rate = 0, ret = 0; 668 unsigned int ctrl_val, bclk_fs, bclk_div; 669 670 /* Select BCLK configuration if the codec as master. */ 671 regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &ctrl_val); 672 if (ctrl_val & NAU8810_CLKIO_MASTER) { 673 /* get the bclk and fs ratio */ 674 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 675 if (bclk_fs <= 32) 676 bclk_div = NAU8810_BCLKDIV_8; 677 else if (bclk_fs <= 64) 678 bclk_div = NAU8810_BCLKDIV_4; 679 else if (bclk_fs <= 128) 680 bclk_div = NAU8810_BCLKDIV_2; 681 else 682 return -EINVAL; 683 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 684 NAU8810_BCLKSEL_MASK, bclk_div); 685 } 686 687 switch (params_width(params)) { 688 case 16: 689 break; 690 case 20: 691 val_len |= NAU8810_WLEN_20; 692 break; 693 case 24: 694 val_len |= NAU8810_WLEN_24; 695 break; 696 case 32: 697 val_len |= NAU8810_WLEN_32; 698 break; 699 } 700 701 switch (params_rate(params)) { 702 case 8000: 703 val_rate |= NAU8810_SMPLR_8K; 704 break; 705 case 11025: 706 val_rate |= NAU8810_SMPLR_12K; 707 break; 708 case 16000: 709 val_rate |= NAU8810_SMPLR_16K; 710 break; 711 case 22050: 712 val_rate |= NAU8810_SMPLR_24K; 713 break; 714 case 32000: 715 val_rate |= NAU8810_SMPLR_32K; 716 break; 717 case 44100: 718 case 48000: 719 break; 720 } 721 722 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, 723 NAU8810_WLEN_MASK, val_len); 724 regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR, 725 NAU8810_SMPLR_MASK, val_rate); 726 727 /* If the master clock is from MCLK, provide the runtime FS for driver 728 * to get the master clock prescaler configuration. 729 */ 730 if (nau8810->clk_id == NAU8810_SCLK_MCLK) { 731 ret = nau8810_mclk_clkdiv(nau8810, params_rate(params)); 732 if (ret < 0) 733 dev_err(nau8810->dev, "MCLK div configuration fail\n"); 734 } 735 736 return ret; 737 } 738 739 static int nau8810_set_bias_level(struct snd_soc_component *component, 740 enum snd_soc_bias_level level) 741 { 742 struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component); 743 struct regmap *map = nau8810->regmap; 744 745 switch (level) { 746 case SND_SOC_BIAS_ON: 747 case SND_SOC_BIAS_PREPARE: 748 regmap_update_bits(map, NAU8810_REG_POWER1, 749 NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K); 750 break; 751 752 case SND_SOC_BIAS_STANDBY: 753 regmap_update_bits(map, NAU8810_REG_POWER1, 754 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN, 755 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN); 756 757 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 758 regcache_sync(map); 759 regmap_update_bits(map, NAU8810_REG_POWER1, 760 NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K); 761 mdelay(100); 762 } 763 regmap_update_bits(map, NAU8810_REG_POWER1, 764 NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K); 765 break; 766 767 case SND_SOC_BIAS_OFF: 768 regmap_write(map, NAU8810_REG_POWER1, 0); 769 regmap_write(map, NAU8810_REG_POWER2, 0); 770 regmap_write(map, NAU8810_REG_POWER3, 0); 771 break; 772 } 773 774 return 0; 775 } 776 777 778 #define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000) 779 780 #define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 781 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 782 783 static const struct snd_soc_dai_ops nau8810_ops = { 784 .hw_params = nau8810_pcm_hw_params, 785 .set_fmt = nau8810_set_dai_fmt, 786 .set_sysclk = nau8810_set_sysclk, 787 .set_pll = nau8810_set_pll, 788 }; 789 790 static struct snd_soc_dai_driver nau8810_dai = { 791 .name = "nau8810-hifi", 792 .playback = { 793 .stream_name = "Playback", 794 .channels_min = 1, 795 .channels_max = 2, /* Only 1 channel of data */ 796 .rates = NAU8810_RATES, 797 .formats = NAU8810_FORMATS, 798 }, 799 .capture = { 800 .stream_name = "Capture", 801 .channels_min = 1, 802 .channels_max = 2, /* Only 1 channel of data */ 803 .rates = NAU8810_RATES, 804 .formats = NAU8810_FORMATS, 805 }, 806 .ops = &nau8810_ops, 807 .symmetric_rates = 1, 808 }; 809 810 static const struct regmap_config nau8810_regmap_config = { 811 .reg_bits = 7, 812 .val_bits = 9, 813 814 .max_register = NAU8810_REG_MAX, 815 .readable_reg = nau8810_readable_reg, 816 .writeable_reg = nau8810_writeable_reg, 817 .volatile_reg = nau8810_volatile_reg, 818 819 .cache_type = REGCACHE_RBTREE, 820 .reg_defaults = nau8810_reg_defaults, 821 .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults), 822 }; 823 824 static const struct snd_soc_component_driver nau8810_component_driver = { 825 .set_bias_level = nau8810_set_bias_level, 826 .controls = nau8810_snd_controls, 827 .num_controls = ARRAY_SIZE(nau8810_snd_controls), 828 .dapm_widgets = nau8810_dapm_widgets, 829 .num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets), 830 .dapm_routes = nau8810_dapm_routes, 831 .num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes), 832 .suspend_bias_off = 1, 833 .idle_bias_on = 1, 834 .use_pmdown_time = 1, 835 .endianness = 1, 836 .non_legacy_dai_naming = 1, 837 }; 838 839 static int nau8810_i2c_probe(struct i2c_client *i2c, 840 const struct i2c_device_id *id) 841 { 842 struct device *dev = &i2c->dev; 843 struct nau8810 *nau8810 = dev_get_platdata(dev); 844 845 if (!nau8810) { 846 nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL); 847 if (!nau8810) 848 return -ENOMEM; 849 } 850 i2c_set_clientdata(i2c, nau8810); 851 852 nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config); 853 if (IS_ERR(nau8810->regmap)) 854 return PTR_ERR(nau8810->regmap); 855 nau8810->dev = dev; 856 857 regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00); 858 859 return devm_snd_soc_register_component(dev, 860 &nau8810_component_driver, &nau8810_dai, 1); 861 } 862 863 static const struct i2c_device_id nau8810_i2c_id[] = { 864 { "nau8810", 0 }, 865 { } 866 }; 867 MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id); 868 869 #ifdef CONFIG_OF 870 static const struct of_device_id nau8810_of_match[] = { 871 { .compatible = "nuvoton,nau8810", }, 872 { } 873 }; 874 MODULE_DEVICE_TABLE(of, nau8810_of_match); 875 #endif 876 877 static struct i2c_driver nau8810_i2c_driver = { 878 .driver = { 879 .name = "nau8810", 880 .of_match_table = of_match_ptr(nau8810_of_match), 881 }, 882 .probe = nau8810_i2c_probe, 883 .id_table = nau8810_i2c_id, 884 }; 885 886 module_i2c_driver(nau8810_i2c_driver); 887 888 MODULE_DESCRIPTION("ASoC NAU8810 driver"); 889 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>"); 890 MODULE_LICENSE("GPL v2"); 891