1 /* 2 * nau8810.c -- NAU8810 ALSA Soc Audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * 6 * Author: David Lin <ctlin0@nuvoton.com> 7 * 8 * Based on WM8974.c 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/pm.h> 21 #include <linux/i2c.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 31 #include "nau8810.h" 32 33 #define NAU_PLL_FREQ_MAX 100000000 34 #define NAU_PLL_FREQ_MIN 90000000 35 #define NAU_PLL_REF_MAX 33000000 36 #define NAU_PLL_REF_MIN 8000000 37 #define NAU_PLL_OPTOP_MIN 6 38 39 40 static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 }; 41 42 static const struct reg_default nau8810_reg_defaults[] = { 43 { NAU8810_REG_POWER1, 0x0000 }, 44 { NAU8810_REG_POWER2, 0x0000 }, 45 { NAU8810_REG_POWER3, 0x0000 }, 46 { NAU8810_REG_IFACE, 0x0050 }, 47 { NAU8810_REG_COMP, 0x0000 }, 48 { NAU8810_REG_CLOCK, 0x0140 }, 49 { NAU8810_REG_SMPLR, 0x0000 }, 50 { NAU8810_REG_DAC, 0x0000 }, 51 { NAU8810_REG_DACGAIN, 0x00FF }, 52 { NAU8810_REG_ADC, 0x0100 }, 53 { NAU8810_REG_ADCGAIN, 0x00FF }, 54 { NAU8810_REG_EQ1, 0x012C }, 55 { NAU8810_REG_EQ2, 0x002C }, 56 { NAU8810_REG_EQ3, 0x002C }, 57 { NAU8810_REG_EQ4, 0x002C }, 58 { NAU8810_REG_EQ5, 0x002C }, 59 { NAU8810_REG_DACLIM1, 0x0032 }, 60 { NAU8810_REG_DACLIM2, 0x0000 }, 61 { NAU8810_REG_NOTCH1, 0x0000 }, 62 { NAU8810_REG_NOTCH2, 0x0000 }, 63 { NAU8810_REG_NOTCH3, 0x0000 }, 64 { NAU8810_REG_NOTCH4, 0x0000 }, 65 { NAU8810_REG_ALC1, 0x0038 }, 66 { NAU8810_REG_ALC2, 0x000B }, 67 { NAU8810_REG_ALC3, 0x0032 }, 68 { NAU8810_REG_NOISEGATE, 0x0000 }, 69 { NAU8810_REG_PLLN, 0x0008 }, 70 { NAU8810_REG_PLLK1, 0x000C }, 71 { NAU8810_REG_PLLK2, 0x0093 }, 72 { NAU8810_REG_PLLK3, 0x00E9 }, 73 { NAU8810_REG_ATTEN, 0x0000 }, 74 { NAU8810_REG_INPUT_SIGNAL, 0x0003 }, 75 { NAU8810_REG_PGAGAIN, 0x0010 }, 76 { NAU8810_REG_ADCBOOST, 0x0100 }, 77 { NAU8810_REG_OUTPUT, 0x0002 }, 78 { NAU8810_REG_SPKMIX, 0x0001 }, 79 { NAU8810_REG_SPKGAIN, 0x0039 }, 80 { NAU8810_REG_MONOMIX, 0x0001 }, 81 { NAU8810_REG_POWER4, 0x0000 }, 82 { NAU8810_REG_TSLOTCTL1, 0x0000 }, 83 { NAU8810_REG_TSLOTCTL2, 0x0020 }, 84 { NAU8810_REG_DEVICE_REVID, 0x0000 }, 85 { NAU8810_REG_I2C_DEVICEID, 0x001A }, 86 { NAU8810_REG_ADDITIONID, 0x00CA }, 87 { NAU8810_REG_RESERVE, 0x0124 }, 88 { NAU8810_REG_OUTCTL, 0x0001 }, 89 { NAU8810_REG_ALC1ENHAN1, 0x0010 }, 90 { NAU8810_REG_ALC1ENHAN2, 0x0000 }, 91 { NAU8810_REG_MISCCTL, 0x0000 }, 92 { NAU8810_REG_OUTTIEOFF, 0x0000 }, 93 { NAU8810_REG_AGCP2POUT, 0x0000 }, 94 { NAU8810_REG_AGCPOUT, 0x0000 }, 95 { NAU8810_REG_AMTCTL, 0x0000 }, 96 { NAU8810_REG_OUTTIEOFFMAN, 0x0000 }, 97 }; 98 99 static bool nau8810_readable_reg(struct device *dev, unsigned int reg) 100 { 101 switch (reg) { 102 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: 103 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: 104 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: 105 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: 106 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: 107 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: 108 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: 109 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: 110 case NAU8810_REG_ADCBOOST: 111 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: 112 case NAU8810_REG_SPKGAIN: 113 case NAU8810_REG_MONOMIX: 114 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: 115 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE: 116 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2: 117 case NAU8810_REG_MISCCTL: 118 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: 119 return true; 120 default: 121 return false; 122 } 123 } 124 125 static bool nau8810_writeable_reg(struct device *dev, unsigned int reg) 126 { 127 switch (reg) { 128 case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: 129 case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: 130 case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: 131 case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: 132 case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: 133 case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: 134 case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: 135 case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: 136 case NAU8810_REG_ADCBOOST: 137 case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: 138 case NAU8810_REG_SPKGAIN: 139 case NAU8810_REG_MONOMIX: 140 case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: 141 case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2: 142 case NAU8810_REG_MISCCTL: 143 case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: 144 return true; 145 default: 146 return false; 147 } 148 } 149 150 static bool nau8810_volatile_reg(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case NAU8810_REG_RESET: 154 case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE: 155 return true; 156 default: 157 return false; 158 } 159 } 160 161 /* The EQ parameters get function is to get the 5 band equalizer control. 162 * The regmap raw read can't work here because regmap doesn't provide 163 * value format for value width of 9 bits. Therefore, the driver reads data 164 * from cache and makes value format according to the endianness of 165 * bytes type control element. 166 */ 167 static int nau8810_eq_get(struct snd_kcontrol *kcontrol, 168 struct snd_ctl_elem_value *ucontrol) 169 { 170 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 171 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 172 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 173 int i, reg, reg_val; 174 u16 *val; 175 176 val = (u16 *)ucontrol->value.bytes.data; 177 reg = NAU8810_REG_EQ1; 178 for (i = 0; i < params->max / sizeof(u16); i++) { 179 regmap_read(nau8810->regmap, reg + i, ®_val); 180 /* conversion of 16-bit integers between native CPU format 181 * and big endian format 182 */ 183 reg_val = cpu_to_be16(reg_val); 184 memcpy(val + i, ®_val, sizeof(reg_val)); 185 } 186 187 return 0; 188 } 189 190 /* The EQ parameters put function is to make configuration of 5 band equalizer 191 * control. These configuration includes central frequency, equalizer gain, 192 * cut-off frequency, bandwidth control, and equalizer path. 193 * The regmap raw write can't work here because regmap doesn't provide 194 * register and value format for register with address 7 bits and value 9 bits. 195 * Therefore, the driver makes value format according to the endianness of 196 * bytes type control element and writes data to codec. 197 */ 198 static int nau8810_eq_put(struct snd_kcontrol *kcontrol, 199 struct snd_ctl_elem_value *ucontrol) 200 { 201 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 202 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 203 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 204 void *data; 205 u16 *val, value; 206 int i, reg, ret; 207 208 data = kmemdup(ucontrol->value.bytes.data, 209 params->max, GFP_KERNEL | GFP_DMA); 210 if (!data) 211 return -ENOMEM; 212 213 val = (u16 *)data; 214 reg = NAU8810_REG_EQ1; 215 for (i = 0; i < params->max / sizeof(u16); i++) { 216 /* conversion of 16-bit integers between native CPU format 217 * and big endian format 218 */ 219 value = be16_to_cpu(*(val + i)); 220 ret = regmap_write(nau8810->regmap, reg + i, value); 221 if (ret) { 222 dev_err(codec->dev, "EQ configuration fail, register: %x ret: %d\n", 223 reg + i, ret); 224 kfree(data); 225 return ret; 226 } 227 } 228 kfree(data); 229 230 return 0; 231 } 232 233 static const char * const nau8810_companding[] = { 234 "Off", "NC", "u-law", "A-law" }; 235 236 static const struct soc_enum nau8810_companding_adc_enum = 237 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT, 238 ARRAY_SIZE(nau8810_companding), nau8810_companding); 239 240 static const struct soc_enum nau8810_companding_dac_enum = 241 SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT, 242 ARRAY_SIZE(nau8810_companding), nau8810_companding); 243 244 static const char * const nau8810_deemp[] = { 245 "None", "32kHz", "44.1kHz", "48kHz" }; 246 247 static const struct soc_enum nau8810_deemp_enum = 248 SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT, 249 ARRAY_SIZE(nau8810_deemp), nau8810_deemp); 250 251 static const char * const nau8810_eqmode[] = {"Capture", "Playback" }; 252 253 static const struct soc_enum nau8810_eqmode_enum = 254 SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT, 255 ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode); 256 257 static const char * const nau8810_alc[] = {"Normal", "Limiter" }; 258 259 static const struct soc_enum nau8810_alc_enum = 260 SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT, 261 ARRAY_SIZE(nau8810_alc), nau8810_alc); 262 263 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 264 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 265 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); 266 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); 267 268 static const struct snd_kcontrol_new nau8810_snd_controls[] = { 269 SOC_ENUM("ADC Companding", nau8810_companding_adc_enum), 270 SOC_ENUM("DAC Companding", nau8810_companding_dac_enum), 271 SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum), 272 273 SOC_ENUM("EQ Function", nau8810_eqmode_enum), 274 SND_SOC_BYTES_EXT("EQ Parameters", 10, 275 nau8810_eq_get, nau8810_eq_put), 276 277 SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC, 278 NAU8810_DACPL_SFT, 1, 0), 279 SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN, 280 NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv), 281 282 SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC, 283 NAU8810_HPFEN_SFT, 1, 0), 284 SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC, 285 NAU8810_HPF_SFT, 0x7, 0), 286 287 SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC, 288 NAU8810_ADCPL_SFT, 1, 0), 289 SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN, 290 NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv), 291 292 SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1, 293 NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv), 294 SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2, 295 NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv), 296 SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3, 297 NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv), 298 SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4, 299 NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv), 300 SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5, 301 NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv), 302 303 SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1, 304 NAU8810_DACLIMEN_SFT, 1, 0), 305 SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1, 306 NAU8810_DACLIMDCY_SFT, 0xf, 0), 307 SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1, 308 NAU8810_DACLIMATK_SFT, 0xf, 0), 309 SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2, 310 NAU8810_DACLIMTHL_SFT, 0x7, 0), 311 SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2, 312 NAU8810_DACLIMBST_SFT, 0xf, 0), 313 314 SOC_ENUM("ALC Mode", nau8810_alc_enum), 315 SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1, 316 NAU8810_ALCEN_SFT, 1, 0), 317 SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1, 318 NAU8810_ALCMXGAIN_SFT, 0x7, 0), 319 SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1, 320 NAU8810_ALCMINGAIN_SFT, 0x7, 0), 321 SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2, 322 NAU8810_ALCZC_SFT, 1, 0), 323 SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2, 324 NAU8810_ALCHT_SFT, 0xf, 0), 325 SOC_SINGLE("ALC Target", NAU8810_REG_ALC2, 326 NAU8810_ALCSL_SFT, 0xf, 0), 327 SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3, 328 NAU8810_ALCDCY_SFT, 0xf, 0), 329 SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3, 330 NAU8810_ALCATK_SFT, 0xf, 0), 331 SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE, 332 NAU8810_ALCNEN_SFT, 1, 0), 333 SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE, 334 NAU8810_ALCNTH_SFT, 0x7, 0), 335 336 SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN, 337 NAU8810_PGAZC_SFT, 1, 0), 338 SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN, 339 NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv), 340 341 SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN, 342 NAU8810_SPKZC_SFT, 1, 0), 343 SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN, 344 NAU8810_SPKMT_SFT, 1, 0), 345 SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN, 346 NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv), 347 348 SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST, 349 NAU8810_PGABST_SFT, 1, 0), 350 SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX, 351 NAU8810_MOUTMXMT_SFT, 1, 0), 352 353 SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC, 354 NAU8810_DACOS_SFT, 1, 0), 355 SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC, 356 NAU8810_ADCOS_SFT, 1, 0), 357 }; 358 359 /* Speaker Output Mixer */ 360 static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = { 361 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX, 362 NAU8810_BYPSPK_SFT, 1, 0), 363 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX, 364 NAU8810_DACSPK_SFT, 1, 0), 365 }; 366 367 /* Mono Output Mixer */ 368 static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = { 369 SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX, 370 NAU8810_BYPMOUT_SFT, 1, 0), 371 SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX, 372 NAU8810_DACMOUT_SFT, 1, 0), 373 }; 374 375 /* PGA Mute */ 376 static const struct snd_kcontrol_new nau8810_inpga_mute[] = { 377 SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN, 378 NAU8810_PGAMT_SFT, 1, 0), 379 }; 380 381 /* Input PGA */ 382 static const struct snd_kcontrol_new nau8810_inpga[] = { 383 SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL, 384 NAU8810_NMICPGA_SFT, 1, 0), 385 SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL, 386 NAU8810_PMICPGA_SFT, 1, 0), 387 }; 388 389 /* Mic Input boost vol */ 390 static const struct snd_kcontrol_new nau8810_mic_boost_controls = 391 SOC_DAPM_SINGLE("Mic Volume", NAU8810_REG_ADCBOOST, 392 NAU8810_PMICBSTGAIN_SFT, 0x7, 0); 393 394 /* Loopback Switch */ 395 static const struct snd_kcontrol_new nau8810_loopback = 396 SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP, 397 NAU8810_ADDAP_SFT, 1, 0); 398 399 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source, 400 struct snd_soc_dapm_widget *sink) 401 { 402 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 403 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 404 unsigned int value; 405 406 regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value); 407 return (value & NAU8810_CLKM_MASK); 408 } 409 410 static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = { 411 SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3, 412 NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0], 413 ARRAY_SIZE(nau8810_speaker_mixer_controls)), 414 SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3, 415 NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0], 416 ARRAY_SIZE(nau8810_mono_mixer_controls)), 417 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", NAU8810_REG_POWER3, 418 NAU8810_DAC_EN_SFT, 0), 419 SND_SOC_DAPM_ADC("ADC", "HiFi Capture", NAU8810_REG_POWER2, 420 NAU8810_ADC_EN_SFT, 0), 421 SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3, 422 NAU8810_NSPK_EN_SFT, 0, NULL, 0), 423 SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3, 424 NAU8810_PSPK_EN_SFT, 0, NULL, 0), 425 SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3, 426 NAU8810_MOUT_EN_SFT, 0, NULL, 0), 427 428 SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2, 429 NAU8810_PGA_EN_SFT, 0, nau8810_inpga, 430 ARRAY_SIZE(nau8810_inpga)), 431 SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2, 432 NAU8810_BST_EN_SFT, 0, nau8810_inpga_mute, 433 ARRAY_SIZE(nau8810_inpga_mute)), 434 435 SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1, 436 NAU8810_MICBIAS_EN_SFT, 0, NULL, 0), 437 SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1, 438 NAU8810_PLL_EN_SFT, 0, NULL, 0), 439 440 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0, 441 &nau8810_loopback), 442 443 SND_SOC_DAPM_INPUT("MICN"), 444 SND_SOC_DAPM_INPUT("MICP"), 445 SND_SOC_DAPM_OUTPUT("MONOOUT"), 446 SND_SOC_DAPM_OUTPUT("SPKOUTP"), 447 SND_SOC_DAPM_OUTPUT("SPKOUTN"), 448 }; 449 450 static const struct snd_soc_dapm_route nau8810_dapm_routes[] = { 451 {"DAC", NULL, "PLL", check_mclk_select_pll}, 452 453 /* Mono output mixer */ 454 {"Mono Mixer", "PCM Playback Switch", "DAC"}, 455 {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"}, 456 457 /* Speaker output mixer */ 458 {"Speaker Mixer", "PCM Playback Switch", "DAC"}, 459 {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"}, 460 461 /* Outputs */ 462 {"Mono Out", NULL, "Mono Mixer"}, 463 {"MONOOUT", NULL, "Mono Out"}, 464 {"SpkN Out", NULL, "Speaker Mixer"}, 465 {"SpkP Out", NULL, "Speaker Mixer"}, 466 {"SPKOUTN", NULL, "SpkN Out"}, 467 {"SPKOUTP", NULL, "SpkP Out"}, 468 469 /* Input Boost Stage */ 470 {"ADC", NULL, "Input Boost Stage"}, 471 {"ADC", NULL, "PLL", check_mclk_select_pll}, 472 {"Input Boost Stage", NULL, "Input PGA"}, 473 {"Input Boost Stage", NULL, "MICP"}, 474 475 /* Input PGA */ 476 {"Input PGA", NULL, "Mic Bias"}, 477 {"Input PGA", "MicN Switch", "MICN"}, 478 {"Input PGA", "MicP Switch", "MICP"}, 479 480 /* Digital Looptack */ 481 {"Digital Loopback", "Switch", "ADC"}, 482 {"DAC", NULL, "Digital Loopback"}, 483 }; 484 485 static int nau8810_set_sysclk(struct snd_soc_dai *dai, 486 int clk_id, unsigned int freq, int dir) 487 { 488 struct snd_soc_codec *codec = dai->codec; 489 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 490 491 nau8810->clk_id = clk_id; 492 nau8810->sysclk = freq; 493 dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n", 494 freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK"); 495 496 return 0; 497 } 498 499 static int nau88l0_calc_pll(unsigned int pll_in, 500 unsigned int fs, struct nau8810_pll *pll_param) 501 { 502 u64 f2, f2_max, pll_ratio; 503 int i, scal_sel; 504 505 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN) 506 return -EINVAL; 507 508 f2_max = 0; 509 scal_sel = ARRAY_SIZE(nau8810_mclk_scaler); 510 for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) { 511 f2 = 256 * fs * 4 * nau8810_mclk_scaler[i] / 10; 512 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX && 513 f2_max < f2) { 514 f2_max = f2; 515 scal_sel = i; 516 } 517 } 518 if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel) 519 return -EINVAL; 520 pll_param->mclk_scaler = scal_sel; 521 f2 = f2_max; 522 523 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional 524 * input; round up the 24+4bit. 525 */ 526 pll_ratio = div_u64(f2 << 28, pll_in); 527 pll_param->pre_factor = 0; 528 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { 529 pll_ratio <<= 1; 530 pll_param->pre_factor = 1; 531 } 532 pll_param->pll_int = (pll_ratio >> 28) & 0xF; 533 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); 534 535 return 0; 536 } 537 538 static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id, 539 int source, unsigned int freq_in, unsigned int freq_out) 540 { 541 struct snd_soc_codec *codec = codec_dai->codec; 542 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 543 struct regmap *map = nau8810->regmap; 544 struct nau8810_pll *pll_param = &nau8810->pll; 545 int ret, fs; 546 547 fs = freq_out / 256; 548 ret = nau88l0_calc_pll(freq_in, fs, pll_param); 549 if (ret < 0) { 550 dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in); 551 return ret; 552 } 553 dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n", 554 pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler, 555 pll_param->pre_factor); 556 557 regmap_update_bits(map, NAU8810_REG_PLLN, 558 NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK, 559 (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) | 560 pll_param->pll_int); 561 regmap_write(map, NAU8810_REG_PLLK1, 562 (pll_param->pll_frac >> NAU8810_PLLK1_SFT) & 563 NAU8810_PLLK1_MASK); 564 regmap_write(map, NAU8810_REG_PLLK2, 565 (pll_param->pll_frac >> NAU8810_PLLK2_SFT) & 566 NAU8810_PLLK2_MASK); 567 regmap_write(map, NAU8810_REG_PLLK3, 568 pll_param->pll_frac & NAU8810_PLLK3_MASK); 569 regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK, 570 pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT); 571 regmap_update_bits(map, NAU8810_REG_CLOCK, 572 NAU8810_CLKM_MASK, NAU8810_CLKM_PLL); 573 574 return 0; 575 } 576 577 static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai, 578 unsigned int fmt) 579 { 580 struct snd_soc_codec *codec = codec_dai->codec; 581 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 582 u16 ctrl1_val = 0, ctrl2_val = 0; 583 584 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 585 case SND_SOC_DAIFMT_CBM_CFM: 586 ctrl2_val |= NAU8810_CLKIO_MASTER; 587 break; 588 case SND_SOC_DAIFMT_CBS_CFS: 589 break; 590 default: 591 return -EINVAL; 592 } 593 594 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 595 case SND_SOC_DAIFMT_I2S: 596 ctrl1_val |= NAU8810_AIFMT_I2S; 597 break; 598 case SND_SOC_DAIFMT_RIGHT_J: 599 break; 600 case SND_SOC_DAIFMT_LEFT_J: 601 ctrl1_val |= NAU8810_AIFMT_LEFT; 602 break; 603 case SND_SOC_DAIFMT_DSP_A: 604 ctrl1_val |= NAU8810_AIFMT_PCM_A; 605 break; 606 default: 607 return -EINVAL; 608 } 609 610 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 611 case SND_SOC_DAIFMT_NB_NF: 612 break; 613 case SND_SOC_DAIFMT_IB_IF: 614 ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF; 615 break; 616 case SND_SOC_DAIFMT_IB_NF: 617 ctrl1_val |= NAU8810_BCLKP_IB; 618 break; 619 case SND_SOC_DAIFMT_NB_IF: 620 ctrl1_val |= NAU8810_FSP_IF; 621 break; 622 default: 623 return -EINVAL; 624 } 625 626 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, 627 NAU8810_AIFMT_MASK | NAU8810_FSP_IF | 628 NAU8810_BCLKP_IB, ctrl1_val); 629 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 630 NAU8810_CLKIO_MASK, ctrl2_val); 631 632 return 0; 633 } 634 635 static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate) 636 { 637 int i, sclk, imclk = rate * 256, div = 0; 638 639 if (!nau8810->sysclk) { 640 dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n"); 641 return -EINVAL; 642 } 643 644 /* Configure the master clock prescaler div to make system 645 * clock to approximate the internal master clock (IMCLK); 646 * and large or equal to IMCLK. 647 */ 648 for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) { 649 sclk = (nau8810->sysclk * 10) / 650 nau8810_mclk_scaler[i]; 651 if (sclk < imclk) 652 break; 653 div = i; 654 } 655 dev_dbg(nau8810->dev, 656 "master clock prescaler %x for fs %d\n", div, rate); 657 658 /* master clock from MCLK and disable PLL */ 659 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 660 NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT)); 661 regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, 662 NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK); 663 664 return 0; 665 } 666 667 static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream, 668 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 669 { 670 struct snd_soc_codec *codec = dai->codec; 671 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 672 int val_len = 0, val_rate = 0, ret = 0; 673 674 switch (params_width(params)) { 675 case 16: 676 break; 677 case 20: 678 val_len |= NAU8810_WLEN_20; 679 break; 680 case 24: 681 val_len |= NAU8810_WLEN_24; 682 break; 683 case 32: 684 val_len |= NAU8810_WLEN_32; 685 break; 686 } 687 688 switch (params_rate(params)) { 689 case 8000: 690 val_rate |= NAU8810_SMPLR_8K; 691 break; 692 case 11025: 693 val_rate |= NAU8810_SMPLR_12K; 694 break; 695 case 16000: 696 val_rate |= NAU8810_SMPLR_16K; 697 break; 698 case 22050: 699 val_rate |= NAU8810_SMPLR_24K; 700 break; 701 case 32000: 702 val_rate |= NAU8810_SMPLR_32K; 703 break; 704 case 44100: 705 case 48000: 706 break; 707 } 708 709 regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, 710 NAU8810_WLEN_MASK, val_len); 711 regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR, 712 NAU8810_SMPLR_MASK, val_rate); 713 714 /* If the master clock is from MCLK, provide the runtime FS for driver 715 * to get the master clock prescaler configuration. 716 */ 717 if (nau8810->clk_id == NAU8810_SCLK_MCLK) { 718 ret = nau8810_mclk_clkdiv(nau8810, params_rate(params)); 719 if (ret < 0) 720 dev_err(nau8810->dev, "MCLK div configuration fail\n"); 721 } 722 723 return ret; 724 } 725 726 static int nau8810_set_bias_level(struct snd_soc_codec *codec, 727 enum snd_soc_bias_level level) 728 { 729 struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); 730 struct regmap *map = nau8810->regmap; 731 732 switch (level) { 733 case SND_SOC_BIAS_ON: 734 case SND_SOC_BIAS_PREPARE: 735 regmap_update_bits(map, NAU8810_REG_POWER1, 736 NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K); 737 break; 738 739 case SND_SOC_BIAS_STANDBY: 740 regmap_update_bits(map, NAU8810_REG_POWER1, 741 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN, 742 NAU8810_IOBUF_EN | NAU8810_ABIAS_EN); 743 744 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 745 regcache_sync(map); 746 regmap_update_bits(map, NAU8810_REG_POWER1, 747 NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K); 748 mdelay(100); 749 } 750 regmap_update_bits(map, NAU8810_REG_POWER1, 751 NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K); 752 break; 753 754 case SND_SOC_BIAS_OFF: 755 regmap_write(map, NAU8810_REG_POWER1, 0); 756 regmap_write(map, NAU8810_REG_POWER2, 0); 757 regmap_write(map, NAU8810_REG_POWER3, 0); 758 break; 759 } 760 761 return 0; 762 } 763 764 765 #define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000) 766 767 #define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 768 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 769 770 static const struct snd_soc_dai_ops nau8810_ops = { 771 .hw_params = nau8810_pcm_hw_params, 772 .set_fmt = nau8810_set_dai_fmt, 773 .set_sysclk = nau8810_set_sysclk, 774 .set_pll = nau8810_set_pll, 775 }; 776 777 static struct snd_soc_dai_driver nau8810_dai = { 778 .name = "nau8810-hifi", 779 .playback = { 780 .stream_name = "Playback", 781 .channels_min = 1, 782 .channels_max = 2, /* Only 1 channel of data */ 783 .rates = NAU8810_RATES, 784 .formats = NAU8810_FORMATS, 785 }, 786 .capture = { 787 .stream_name = "Capture", 788 .channels_min = 1, 789 .channels_max = 2, /* Only 1 channel of data */ 790 .rates = NAU8810_RATES, 791 .formats = NAU8810_FORMATS, 792 }, 793 .ops = &nau8810_ops, 794 .symmetric_rates = 1, 795 }; 796 797 static const struct regmap_config nau8810_regmap_config = { 798 .reg_bits = 7, 799 .val_bits = 9, 800 801 .max_register = NAU8810_REG_MAX, 802 .readable_reg = nau8810_readable_reg, 803 .writeable_reg = nau8810_writeable_reg, 804 .volatile_reg = nau8810_volatile_reg, 805 806 .cache_type = REGCACHE_RBTREE, 807 .reg_defaults = nau8810_reg_defaults, 808 .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults), 809 }; 810 811 static const struct snd_soc_codec_driver nau8810_codec_driver = { 812 .set_bias_level = nau8810_set_bias_level, 813 .suspend_bias_off = true, 814 815 .component_driver = { 816 .controls = nau8810_snd_controls, 817 .num_controls = ARRAY_SIZE(nau8810_snd_controls), 818 .dapm_widgets = nau8810_dapm_widgets, 819 .num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets), 820 .dapm_routes = nau8810_dapm_routes, 821 .num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes), 822 }, 823 }; 824 825 static int nau8810_i2c_probe(struct i2c_client *i2c, 826 const struct i2c_device_id *id) 827 { 828 struct device *dev = &i2c->dev; 829 struct nau8810 *nau8810 = dev_get_platdata(dev); 830 831 if (!nau8810) { 832 nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL); 833 if (!nau8810) 834 return -ENOMEM; 835 } 836 i2c_set_clientdata(i2c, nau8810); 837 838 nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config); 839 if (IS_ERR(nau8810->regmap)) 840 return PTR_ERR(nau8810->regmap); 841 nau8810->dev = dev; 842 843 regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00); 844 845 return snd_soc_register_codec(dev, 846 &nau8810_codec_driver, &nau8810_dai, 1); 847 } 848 849 static int nau8810_i2c_remove(struct i2c_client *client) 850 { 851 snd_soc_unregister_codec(&client->dev); 852 853 return 0; 854 } 855 856 static const struct i2c_device_id nau8810_i2c_id[] = { 857 { "nau8810", 0 }, 858 { } 859 }; 860 MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id); 861 862 #ifdef CONFIG_OF 863 static const struct of_device_id nau8810_of_match[] = { 864 { .compatible = "nuvoton,nau8810", }, 865 { } 866 }; 867 MODULE_DEVICE_TABLE(of, nau8810_of_match); 868 #endif 869 870 static struct i2c_driver nau8810_i2c_driver = { 871 .driver = { 872 .name = "nau8810", 873 .of_match_table = of_match_ptr(nau8810_of_match), 874 }, 875 .probe = nau8810_i2c_probe, 876 .remove = nau8810_i2c_remove, 877 .id_table = nau8810_i2c_id, 878 }; 879 880 module_i2c_driver(nau8810_i2c_driver); 881 882 MODULE_DESCRIPTION("ASoC NAU8810 driver"); 883 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>"); 884 MODULE_LICENSE("GPL v2"); 885