1 /* 2 * NAU85L40 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __NAU8540_H__ 13 #define __NAU8540_H__ 14 15 #define NAU8540_REG_SW_RESET 0x00 16 #define NAU8540_REG_POWER_MANAGEMENT 0x01 17 #define NAU8540_REG_CLOCK_CTRL 0x02 18 #define NAU8540_REG_CLOCK_SRC 0x03 19 #define NAU8540_REG_FLL1 0x04 20 #define NAU8540_REG_FLL2 0x05 21 #define NAU8540_REG_FLL3 0x06 22 #define NAU8540_REG_FLL4 0x07 23 #define NAU8540_REG_FLL5 0x08 24 #define NAU8540_REG_FLL6 0x09 25 #define NAU8540_REG_FLL_VCO_RSV 0x0A 26 #define NAU8540_REG_PCM_CTRL0 0x10 27 #define NAU8540_REG_PCM_CTRL1 0x11 28 #define NAU8540_REG_PCM_CTRL2 0x12 29 #define NAU8540_REG_PCM_CTRL3 0x13 30 #define NAU8540_REG_PCM_CTRL4 0x14 31 #define NAU8540_REG_ALC_CONTROL_1 0x20 32 #define NAU8540_REG_ALC_CONTROL_2 0x21 33 #define NAU8540_REG_ALC_CONTROL_3 0x22 34 #define NAU8540_REG_ALC_CONTROL_4 0x23 35 #define NAU8540_REG_ALC_CONTROL_5 0x24 36 #define NAU8540_REG_ALC_GAIN_CH12 0x2D 37 #define NAU8540_REG_ALC_GAIN_CH34 0x2E 38 #define NAU8540_REG_ALC_STATUS 0x2F 39 #define NAU8540_REG_NOTCH_FIL1_CH1 0x30 40 #define NAU8540_REG_NOTCH_FIL2_CH1 0x31 41 #define NAU8540_REG_NOTCH_FIL1_CH2 0x32 42 #define NAU8540_REG_NOTCH_FIL2_CH2 0x33 43 #define NAU8540_REG_NOTCH_FIL1_CH3 0x34 44 #define NAU8540_REG_NOTCH_FIL2_CH3 0x35 45 #define NAU8540_REG_NOTCH_FIL1_CH4 0x36 46 #define NAU8540_REG_NOTCH_FIL2_CH4 0x37 47 #define NAU8540_REG_HPF_FILTER_CH12 0x38 48 #define NAU8540_REG_HPF_FILTER_CH34 0x39 49 #define NAU8540_REG_ADC_SAMPLE_RATE 0x3A 50 #define NAU8540_REG_DIGITAL_GAIN_CH1 0x40 51 #define NAU8540_REG_DIGITAL_GAIN_CH2 0x41 52 #define NAU8540_REG_DIGITAL_GAIN_CH3 0x42 53 #define NAU8540_REG_DIGITAL_GAIN_CH4 0x43 54 #define NAU8540_REG_DIGITAL_MUX 0x44 55 #define NAU8540_REG_P2P_CH1 0x48 56 #define NAU8540_REG_P2P_CH2 0x49 57 #define NAU8540_REG_P2P_CH3 0x4A 58 #define NAU8540_REG_P2P_CH4 0x4B 59 #define NAU8540_REG_PEAK_CH1 0x4C 60 #define NAU8540_REG_PEAK_CH2 0x4D 61 #define NAU8540_REG_PEAK_CH3 0x4E 62 #define NAU8540_REG_PEAK_CH4 0x4F 63 #define NAU8540_REG_GPIO_CTRL 0x50 64 #define NAU8540_REG_MISC_CTRL 0x51 65 #define NAU8540_REG_I2C_CTRL 0x52 66 #define NAU8540_REG_I2C_DEVICE_ID 0x58 67 #define NAU8540_REG_RST 0x5A 68 #define NAU8540_REG_VMID_CTRL 0x60 69 #define NAU8540_REG_MUTE 0x61 70 #define NAU8540_REG_ANALOG_ADC1 0x64 71 #define NAU8540_REG_ANALOG_ADC2 0x65 72 #define NAU8540_REG_ANALOG_PWR 0x66 73 #define NAU8540_REG_MIC_BIAS 0x67 74 #define NAU8540_REG_REFERENCE 0x68 75 #define NAU8540_REG_FEPGA1 0x69 76 #define NAU8540_REG_FEPGA2 0x6A 77 #define NAU8540_REG_FEPGA3 0x6B 78 #define NAU8540_REG_FEPGA4 0x6C 79 #define NAU8540_REG_PWR 0x6D 80 #define NAU8540_REG_MAX NAU8540_REG_PWR 81 82 83 /* POWER_MANAGEMENT (0x01) */ 84 #define NAU8540_ADC4_EN (0x1 << 3) 85 #define NAU8540_ADC3_EN (0x1 << 2) 86 #define NAU8540_ADC2_EN (0x1 << 1) 87 #define NAU8540_ADC1_EN 0x1 88 89 /* CLOCK_CTRL (0x02) */ 90 #define NAU8540_CLK_ADC_EN (0x1 << 15) 91 #define NAU8540_CLK_I2S_EN (0x1 << 1) 92 93 /* CLOCK_SRC (0x03) */ 94 #define NAU8540_CLK_SRC_SFT 15 95 #define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT) 96 #define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT) 97 #define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT) 98 #define NAU8540_CLK_ADC_SRC_SFT 6 99 #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT) 100 #define NAU8540_CLK_MCLK_SRC_MASK 0xf 101 102 /* FLL1 (0x04) */ 103 #define NAU8540_ICTRL_LATCH_SFT 10 104 #define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT) 105 #define NAU8540_FLL_RATIO_MASK 0x7f 106 107 /* FLL3 (0x06) */ 108 #define NAU8540_GAIN_ERR_SFT 12 109 #define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT) 110 #define NAU8540_FLL_CLK_SRC_SFT 10 111 #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) 112 #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) 113 #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT) 114 #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT) 115 #define NAU8540_FLL_INTEGER_MASK 0x3ff 116 117 /* FLL4 (0x07) */ 118 #define NAU8540_FLL_REF_DIV_SFT 10 119 #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT) 120 121 /* FLL5 (0x08) */ 122 #define NAU8540_FLL_PDB_DAC_EN (0x1 << 15) 123 #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14) 124 #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13) 125 #define NAU8540_FLL_CLK_SW_N2 (0x1 << 13) 126 #define NAU8540_FLL_CLK_SW_REF (0x0 << 13) 127 #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12) 128 #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12) 129 #define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12) 130 131 /* FLL6 (0x9) */ 132 #define NAU8540_DCO_EN (0x1 << 15) 133 #define NAU8540_SDM_EN (0x1 << 14) 134 #define NAU8540_CUTOFF500 (0x1 << 13) 135 136 /* PCM_CTRL0 (0x10) */ 137 #define NAU8540_I2S_BP_SFT 7 138 #define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT) 139 #define NAU8540_I2S_PCMB_SFT 6 140 #define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT) 141 #define NAU8540_I2S_DL_SFT 2 142 #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT) 143 #define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT) 144 #define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT) 145 #define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT) 146 #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT) 147 #define NAU8540_I2S_DF_MASK 0x3 148 #define NAU8540_I2S_DF_RIGTH 0 149 #define NAU8540_I2S_DF_LEFT 0x1 150 #define NAU8540_I2S_DF_I2S 0x2 151 #define NAU8540_I2S_DF_PCM_AB 0x3 152 153 /* PCM_CTRL1 (0x11) */ 154 #define NAU8540_I2S_DO12_TRI (0x1 << 15) 155 #define NAU8540_I2S_LRC_DIV_SFT 12 156 #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) 157 #define NAU8540_I2S_DO12_OE (0x1 << 4) 158 #define NAU8540_I2S_MS_SFT 3 159 #define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT) 160 #define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT) 161 #define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT) 162 #define NAU8540_I2S_BLK_DIV_MASK 0x7 163 164 /* PCM_CTRL1 (0x12) */ 165 #define NAU8540_I2S_DO34_TRI (0x1 << 15) 166 #define NAU8540_I2S_DO34_OE (0x1 << 11) 167 #define NAU8540_I2S_TSLOT_L_MASK 0x3ff 168 169 /* PCM_CTRL4 (0x14) */ 170 #define NAU8540_TDM_MODE (0x1 << 15) 171 #define NAU8540_TDM_OFFSET_EN (0x1 << 14) 172 #define NAU8540_TDM_TX_MASK 0xf 173 174 /* ADC_SAMPLE_RATE (0x3A) */ 175 #define NAU8540_CH_SYNC (0x1 << 14) 176 #define NAU8540_ADC_OSR_MASK 0x3 177 #define NAU8540_ADC_OSR_256 0x3 178 #define NAU8540_ADC_OSR_128 0x2 179 #define NAU8540_ADC_OSR_64 0x1 180 #define NAU8540_ADC_OSR_32 0x0 181 182 /* VMID_CTRL (0x60) */ 183 #define NAU8540_VMID_EN (1 << 6) 184 #define NAU8540_VMID_SEL_SFT 4 185 #define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT) 186 187 /* MIC_BIAS (0x67) */ 188 #define NAU8540_PU_PRE (0x1 << 8) 189 190 /* REFERENCE (0x68) */ 191 #define NAU8540_PRECHARGE_DIS (0x1 << 13) 192 #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) 193 194 /* FEPGA1 (0x69) */ 195 #define NAU8540_FEPGA1_MODCH2_SHT_SFT 7 196 #define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT) 197 #define NAU8540_FEPGA1_MODCH1_SHT_SFT 3 198 #define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT) 199 200 /* FEPGA2 (0x6A) */ 201 #define NAU8540_FEPGA2_MODCH4_SHT_SFT 7 202 #define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT) 203 #define NAU8540_FEPGA2_MODCH3_SHT_SFT 3 204 #define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT) 205 206 207 /* System Clock Source */ 208 enum { 209 NAU8540_CLK_DIS, 210 NAU8540_CLK_MCLK, 211 NAU8540_CLK_INTERNAL, 212 NAU8540_CLK_FLL_MCLK, 213 NAU8540_CLK_FLL_BLK, 214 NAU8540_CLK_FLL_FS, 215 }; 216 217 struct nau8540 { 218 struct device *dev; 219 struct regmap *regmap; 220 }; 221 222 struct nau8540_fll { 223 int mclk_src; 224 int ratio; 225 int fll_frac; 226 int fll_int; 227 int clk_ref_div; 228 }; 229 230 struct nau8540_fll_attr { 231 unsigned int param; 232 unsigned int val; 233 }; 234 235 /* over sampling rate */ 236 struct nau8540_osr_attr { 237 unsigned int osr; 238 unsigned int clk_src; 239 }; 240 241 242 #endif /* __NAU8540_H__ */ 243