1c1644e3dSJohn Hsu /* 2c1644e3dSJohn Hsu * NAU85L40 ALSA SoC audio driver 3c1644e3dSJohn Hsu * 4c1644e3dSJohn Hsu * Copyright 2016 Nuvoton Technology Corp. 5c1644e3dSJohn Hsu * Author: John Hsu <KCHSU0@nuvoton.com> 6c1644e3dSJohn Hsu * 7c1644e3dSJohn Hsu * This program is free software; you can redistribute it and/or modify 8c1644e3dSJohn Hsu * it under the terms of the GNU General Public License version 2 as 9c1644e3dSJohn Hsu * published by the Free Software Foundation. 10c1644e3dSJohn Hsu */ 11c1644e3dSJohn Hsu 12c1644e3dSJohn Hsu #ifndef __NAU8540_H__ 13c1644e3dSJohn Hsu #define __NAU8540_H__ 14c1644e3dSJohn Hsu 15c1644e3dSJohn Hsu #define NAU8540_REG_SW_RESET 0x00 16c1644e3dSJohn Hsu #define NAU8540_REG_POWER_MANAGEMENT 0x01 17c1644e3dSJohn Hsu #define NAU8540_REG_CLOCK_CTRL 0x02 18c1644e3dSJohn Hsu #define NAU8540_REG_CLOCK_SRC 0x03 19c1644e3dSJohn Hsu #define NAU8540_REG_FLL1 0x04 20c1644e3dSJohn Hsu #define NAU8540_REG_FLL2 0x05 21c1644e3dSJohn Hsu #define NAU8540_REG_FLL3 0x06 22c1644e3dSJohn Hsu #define NAU8540_REG_FLL4 0x07 23c1644e3dSJohn Hsu #define NAU8540_REG_FLL5 0x08 24c1644e3dSJohn Hsu #define NAU8540_REG_FLL6 0x09 25c1644e3dSJohn Hsu #define NAU8540_REG_FLL_VCO_RSV 0x0A 26c1644e3dSJohn Hsu #define NAU8540_REG_PCM_CTRL0 0x10 27c1644e3dSJohn Hsu #define NAU8540_REG_PCM_CTRL1 0x11 28c1644e3dSJohn Hsu #define NAU8540_REG_PCM_CTRL2 0x12 29c1644e3dSJohn Hsu #define NAU8540_REG_PCM_CTRL3 0x13 30c1644e3dSJohn Hsu #define NAU8540_REG_PCM_CTRL4 0x14 31c1644e3dSJohn Hsu #define NAU8540_REG_ALC_CONTROL_1 0x20 32c1644e3dSJohn Hsu #define NAU8540_REG_ALC_CONTROL_2 0x21 33c1644e3dSJohn Hsu #define NAU8540_REG_ALC_CONTROL_3 0x22 34c1644e3dSJohn Hsu #define NAU8540_REG_ALC_CONTROL_4 0x23 35c1644e3dSJohn Hsu #define NAU8540_REG_ALC_CONTROL_5 0x24 36c1644e3dSJohn Hsu #define NAU8540_REG_ALC_GAIN_CH12 0x2D 37c1644e3dSJohn Hsu #define NAU8540_REG_ALC_GAIN_CH34 0x2E 38c1644e3dSJohn Hsu #define NAU8540_REG_ALC_STATUS 0x2F 39c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL1_CH1 0x30 40c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL2_CH1 0x31 41c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL1_CH2 0x32 42c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL2_CH2 0x33 43c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL1_CH3 0x34 44c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL2_CH3 0x35 45c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL1_CH4 0x36 46c1644e3dSJohn Hsu #define NAU8540_REG_NOTCH_FIL2_CH4 0x37 47c1644e3dSJohn Hsu #define NAU8540_REG_HPF_FILTER_CH12 0x38 48c1644e3dSJohn Hsu #define NAU8540_REG_HPF_FILTER_CH34 0x39 49c1644e3dSJohn Hsu #define NAU8540_REG_ADC_SAMPLE_RATE 0x3A 50c1644e3dSJohn Hsu #define NAU8540_REG_DIGITAL_GAIN_CH1 0x40 51c1644e3dSJohn Hsu #define NAU8540_REG_DIGITAL_GAIN_CH2 0x41 52c1644e3dSJohn Hsu #define NAU8540_REG_DIGITAL_GAIN_CH3 0x42 53c1644e3dSJohn Hsu #define NAU8540_REG_DIGITAL_GAIN_CH4 0x43 54c1644e3dSJohn Hsu #define NAU8540_REG_DIGITAL_MUX 0x44 55c1644e3dSJohn Hsu #define NAU8540_REG_P2P_CH1 0x48 56c1644e3dSJohn Hsu #define NAU8540_REG_P2P_CH2 0x49 57c1644e3dSJohn Hsu #define NAU8540_REG_P2P_CH3 0x4A 58c1644e3dSJohn Hsu #define NAU8540_REG_P2P_CH4 0x4B 59c1644e3dSJohn Hsu #define NAU8540_REG_PEAK_CH1 0x4C 60c1644e3dSJohn Hsu #define NAU8540_REG_PEAK_CH2 0x4D 61c1644e3dSJohn Hsu #define NAU8540_REG_PEAK_CH3 0x4E 62c1644e3dSJohn Hsu #define NAU8540_REG_PEAK_CH4 0x4F 63c1644e3dSJohn Hsu #define NAU8540_REG_GPIO_CTRL 0x50 64c1644e3dSJohn Hsu #define NAU8540_REG_MISC_CTRL 0x51 65c1644e3dSJohn Hsu #define NAU8540_REG_I2C_CTRL 0x52 66c1644e3dSJohn Hsu #define NAU8540_REG_I2C_DEVICE_ID 0x58 67c1644e3dSJohn Hsu #define NAU8540_REG_RST 0x5A 68c1644e3dSJohn Hsu #define NAU8540_REG_VMID_CTRL 0x60 69c1644e3dSJohn Hsu #define NAU8540_REG_MUTE 0x61 70c1644e3dSJohn Hsu #define NAU8540_REG_ANALOG_ADC1 0x64 71c1644e3dSJohn Hsu #define NAU8540_REG_ANALOG_ADC2 0x65 72c1644e3dSJohn Hsu #define NAU8540_REG_ANALOG_PWR 0x66 73c1644e3dSJohn Hsu #define NAU8540_REG_MIC_BIAS 0x67 74c1644e3dSJohn Hsu #define NAU8540_REG_REFERENCE 0x68 75c1644e3dSJohn Hsu #define NAU8540_REG_FEPGA1 0x69 76c1644e3dSJohn Hsu #define NAU8540_REG_FEPGA2 0x6A 77c1644e3dSJohn Hsu #define NAU8540_REG_FEPGA3 0x6B 78c1644e3dSJohn Hsu #define NAU8540_REG_FEPGA4 0x6C 79c1644e3dSJohn Hsu #define NAU8540_REG_PWR 0x6D 80c1644e3dSJohn Hsu #define NAU8540_REG_MAX NAU8540_REG_PWR 81c1644e3dSJohn Hsu 82c1644e3dSJohn Hsu 83c1644e3dSJohn Hsu /* POWER_MANAGEMENT (0x01) */ 84c1644e3dSJohn Hsu #define NAU8540_ADC4_EN (0x1 << 3) 85c1644e3dSJohn Hsu #define NAU8540_ADC3_EN (0x1 << 2) 86c1644e3dSJohn Hsu #define NAU8540_ADC2_EN (0x1 << 1) 87c1644e3dSJohn Hsu #define NAU8540_ADC1_EN 0x1 88c1644e3dSJohn Hsu 89c1644e3dSJohn Hsu /* CLOCK_CTRL (0x02) */ 90c1644e3dSJohn Hsu #define NAU8540_CLK_ADC_EN (0x1 << 15) 91c1644e3dSJohn Hsu #define NAU8540_CLK_I2S_EN (0x1 << 1) 92c1644e3dSJohn Hsu 93c1644e3dSJohn Hsu /* CLOCK_SRC (0x03) */ 94c1644e3dSJohn Hsu #define NAU8540_CLK_SRC_SFT 15 95c1644e3dSJohn Hsu #define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT) 96c1644e3dSJohn Hsu #define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT) 97c1644e3dSJohn Hsu #define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT) 98c1644e3dSJohn Hsu #define NAU8540_CLK_ADC_SRC_SFT 6 99c1644e3dSJohn Hsu #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT) 100c1644e3dSJohn Hsu #define NAU8540_CLK_MCLK_SRC_MASK 0xf 101c1644e3dSJohn Hsu 102c1644e3dSJohn Hsu /* FLL1 (0x04) */ 103c1644e3dSJohn Hsu #define NAU8540_FLL_RATIO_MASK 0x7f 104c1644e3dSJohn Hsu 105c1644e3dSJohn Hsu /* FLL3 (0x06) */ 106c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SRC_SFT 10 107c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) 108c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) 109c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT) 110c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT) 111c1644e3dSJohn Hsu #define NAU8540_FLL_INTEGER_MASK 0x3ff 112c1644e3dSJohn Hsu 113c1644e3dSJohn Hsu /* FLL4 (0x07) */ 114c1644e3dSJohn Hsu #define NAU8540_FLL_REF_DIV_SFT 10 115c1644e3dSJohn Hsu #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT) 116c1644e3dSJohn Hsu 117c1644e3dSJohn Hsu /* FLL5 (0x08) */ 118c1644e3dSJohn Hsu #define NAU8540_FLL_PDB_DAC_EN (0x1 << 15) 119c1644e3dSJohn Hsu #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14) 120c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13) 121c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SW_N2 (0x1 << 13) 122c1644e3dSJohn Hsu #define NAU8540_FLL_CLK_SW_REF (0x0 << 13) 123c1644e3dSJohn Hsu #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12) 124c1644e3dSJohn Hsu #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12) 125c1644e3dSJohn Hsu #define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12) 126c1644e3dSJohn Hsu 127c1644e3dSJohn Hsu /* FLL6 (0x9) */ 128c1644e3dSJohn Hsu #define NAU8540_DCO_EN (0x1 << 15) 129c1644e3dSJohn Hsu #define NAU8540_SDM_EN (0x1 << 14) 130c1644e3dSJohn Hsu 131c1644e3dSJohn Hsu /* PCM_CTRL0 (0x10) */ 132c1644e3dSJohn Hsu #define NAU8540_I2S_BP_SFT 7 133c1644e3dSJohn Hsu #define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT) 134c1644e3dSJohn Hsu #define NAU8540_I2S_PCMB_SFT 6 135c1644e3dSJohn Hsu #define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT) 136c1644e3dSJohn Hsu #define NAU8540_I2S_DL_SFT 2 137c1644e3dSJohn Hsu #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT) 138c1644e3dSJohn Hsu #define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT) 139c1644e3dSJohn Hsu #define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT) 140c1644e3dSJohn Hsu #define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT) 141c1644e3dSJohn Hsu #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT) 142c1644e3dSJohn Hsu #define NAU8540_I2S_DF_MASK 0x3 143c1644e3dSJohn Hsu #define NAU8540_I2S_DF_RIGTH 0 144c1644e3dSJohn Hsu #define NAU8540_I2S_DF_LEFT 0x1 145c1644e3dSJohn Hsu #define NAU8540_I2S_DF_I2S 0x2 146c1644e3dSJohn Hsu #define NAU8540_I2S_DF_PCM_AB 0x3 147c1644e3dSJohn Hsu 148c1644e3dSJohn Hsu /* PCM_CTRL1 (0x11) */ 149c1644e3dSJohn Hsu #define NAU8540_I2S_LRC_DIV_SFT 12 150c1644e3dSJohn Hsu #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) 151c1644e3dSJohn Hsu #define NAU8540_I2S_DO12_OE (0x1 << 4) 152c1644e3dSJohn Hsu #define NAU8540_I2S_MS_SFT 3 153c1644e3dSJohn Hsu #define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT) 154c1644e3dSJohn Hsu #define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT) 155c1644e3dSJohn Hsu #define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT) 156c1644e3dSJohn Hsu #define NAU8540_I2S_BLK_DIV_MASK 0x7 157c1644e3dSJohn Hsu 158c1644e3dSJohn Hsu /* PCM_CTRL1 (0x12) */ 159c1644e3dSJohn Hsu #define NAU8540_I2S_DO34_OE (0x1 << 11) 160c1644e3dSJohn Hsu #define NAU8540_I2S_TSLOT_L_MASK 0x3ff 161c1644e3dSJohn Hsu 162c1644e3dSJohn Hsu /* PCM_CTRL4 (0x14) */ 163c1644e3dSJohn Hsu #define NAU8540_TDM_MODE (0x1 << 15) 164c1644e3dSJohn Hsu #define NAU8540_TDM_OFFSET_EN (0x1 << 14) 165c1644e3dSJohn Hsu #define NAU8540_TDM_TX_MASK 0xf 166c1644e3dSJohn Hsu 167c1644e3dSJohn Hsu /* ADC_SAMPLE_RATE (0x3A) */ 168c1644e3dSJohn Hsu #define NAU8540_ADC_OSR_MASK 0x3 169c1644e3dSJohn Hsu #define NAU8540_ADC_OSR_256 0x3 170c1644e3dSJohn Hsu #define NAU8540_ADC_OSR_128 0x2 171c1644e3dSJohn Hsu #define NAU8540_ADC_OSR_64 0x1 172c1644e3dSJohn Hsu #define NAU8540_ADC_OSR_32 0x0 173c1644e3dSJohn Hsu 174c1644e3dSJohn Hsu /* VMID_CTRL (0x60) */ 175c1644e3dSJohn Hsu #define NAU8540_VMID_EN (1 << 6) 176c1644e3dSJohn Hsu #define NAU8540_VMID_SEL_SFT 4 177c1644e3dSJohn Hsu #define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT) 178c1644e3dSJohn Hsu 179c1644e3dSJohn Hsu /* MIC_BIAS (0x67) */ 180c1644e3dSJohn Hsu #define NAU8540_PU_PRE (0x1 << 8) 181c1644e3dSJohn Hsu 182c1644e3dSJohn Hsu /* REFERENCE (0x68) */ 183c1644e3dSJohn Hsu #define NAU8540_PRECHARGE_DIS (0x1 << 13) 184c1644e3dSJohn Hsu #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) 185c1644e3dSJohn Hsu 186c1644e3dSJohn Hsu 187c1644e3dSJohn Hsu /* System Clock Source */ 188c1644e3dSJohn Hsu enum { 189c1644e3dSJohn Hsu NAU8540_CLK_DIS, 190c1644e3dSJohn Hsu NAU8540_CLK_MCLK, 191c1644e3dSJohn Hsu NAU8540_CLK_INTERNAL, 192c1644e3dSJohn Hsu NAU8540_CLK_FLL_MCLK, 193c1644e3dSJohn Hsu NAU8540_CLK_FLL_BLK, 194c1644e3dSJohn Hsu NAU8540_CLK_FLL_FS, 195c1644e3dSJohn Hsu }; 196c1644e3dSJohn Hsu 197c1644e3dSJohn Hsu struct nau8540 { 198c1644e3dSJohn Hsu struct device *dev; 199c1644e3dSJohn Hsu struct regmap *regmap; 200c1644e3dSJohn Hsu }; 201c1644e3dSJohn Hsu 202c1644e3dSJohn Hsu struct nau8540_fll { 203c1644e3dSJohn Hsu int mclk_src; 204c1644e3dSJohn Hsu int ratio; 205c1644e3dSJohn Hsu int fll_frac; 206c1644e3dSJohn Hsu int fll_int; 207c1644e3dSJohn Hsu int clk_ref_div; 208c1644e3dSJohn Hsu }; 209c1644e3dSJohn Hsu 210c1644e3dSJohn Hsu struct nau8540_fll_attr { 211c1644e3dSJohn Hsu unsigned int param; 212c1644e3dSJohn Hsu unsigned int val; 213c1644e3dSJohn Hsu }; 214c1644e3dSJohn Hsu 215c1644e3dSJohn Hsu /* over sampling rate */ 216c1644e3dSJohn Hsu struct nau8540_osr_attr { 217c1644e3dSJohn Hsu unsigned int osr; 218c1644e3dSJohn Hsu unsigned int clk_src; 219c1644e3dSJohn Hsu }; 220c1644e3dSJohn Hsu 221c1644e3dSJohn Hsu 222c1644e3dSJohn Hsu #endif /* __NAU8540_H__ */ 223