xref: /openbmc/linux/sound/soc/codecs/mt6359.h (revision 31e67366)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2020 MediaTek Inc.
4  * Author: Argus Lin <argus.lin@mediatek.com>
5  */
6 
7 #ifndef _MT6359_H_
8 #define _MT6359_H_
9 
10 /*************Register Bit Define*************/
11 #define PMIC_ACCDET_IRQ_SHIFT				0
12 #define PMIC_ACCDET_EINT0_IRQ_SHIFT			2
13 #define PMIC_ACCDET_EINT1_IRQ_SHIFT			3
14 #define PMIC_ACCDET_IRQ_CLR_SHIFT			8
15 #define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT			10
16 #define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT			11
17 #define PMIC_RG_INT_STATUS_ACCDET_SHIFT			5
18 #define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT		6
19 #define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT		7
20 #define PMIC_RG_EINT0CONFIGACCDET_SHIFT			11
21 #define PMIC_RG_EINT1CONFIGACCDET_SHIFT			0
22 #define PMIC_ACCDET_EINT0_INVERTER_SW_EN_SHIFT		6
23 #define PMIC_ACCDET_EINT1_INVERTER_SW_EN_SHIFT		8
24 #define PMIC_RG_MTEST_EN_SHIFT				8
25 #define PMIC_RG_MTEST_SEL_SHIFT				9
26 #define PMIC_ACCDET_EINT0_M_SW_EN_SHIFT			10
27 #define PMIC_ACCDET_EINT1_M_SW_EN_SHIFT			11
28 #define PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT		5
29 #define PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT		10
30 #define PMIC_ACCDET_DA_STABLE_SHIFT			0
31 #define PMIC_ACCDET_EINT0_EN_STABLE_SHIFT		1
32 #define PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT		2
33 #define PMIC_ACCDET_EINT1_EN_STABLE_SHIFT		6
34 #define PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT		7
35 #define PMIC_ACCDET_EINT_CTURBO_SEL_SHIFT		7
36 #define PMIC_ACCDET_EINT0_CTURBO_SW_SHIFT		7
37 #define PMIC_RG_EINTCOMPVTH_SHIFT			4
38 #define PMIC_RG_EINT0HIRENB_SHIFT			12
39 #define PMIC_RG_EINT0NOHYS_SHIFT			10
40 #define PMIC_ACCDET_SW_EN_SHIFT				0
41 #define PMIC_ACCDET_EINT0_MEM_IN_SHIFT			6
42 #define PMIC_ACCDET_MEM_IN_SHIFT			6
43 #define PMIC_ACCDET_EINT_DEBOUNCE0_SHIFT		0
44 #define PMIC_ACCDET_EINT_DEBOUNCE1_SHIFT		4
45 #define PMIC_ACCDET_EINT_DEBOUNCE2_SHIFT		8
46 #define PMIC_ACCDET_EINT_DEBOUNCE3_SHIFT		12
47 #define PMIC_RG_ACCDET2AUXSWEN_SHIFT			14
48 #define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT		9
49 #define PMIC_AUDACCDETAUXADCSWCTRL_SW_SHIFT		10
50 #define PMIC_RG_EINT0CTURBO_SHIFT			5
51 #define PMIC_RG_EINT1CTURBO_SHIFT			13
52 #define PMIC_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT		12
53 #define PMIC_ACCDET_EINT_M_DETECT_EN_SHIFT		12
54 #define PMIC_ACCDET_EINT0_SW_EN_SHIFT			2
55 #define PMIC_ACCDET_EINT1_SW_EN_SHIFT			4
56 #define PMIC_ACCDET_EINT_CMPMOUT_SEL_SHIFT		12
57 #define PMIC_ACCDET_EINT_CMPMEN_SEL_SHIFT		6
58 #define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT		0
59 #define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT		4
60 #define PMIC_RG_EINT0EN_SHIFT				2
61 #define PMIC_RG_EINT1EN_SHIFT				10
62 #define PMIC_RG_NCP_PDDIS_EN_SHIFT			0
63 #define PMIC_RG_ACCDETSPARE_SHIFT			0
64 #define PMIC_RG_ACCDET_RST_SHIFT			1
65 #define PMIC_RG_AUDMICBIAS1HVEN_SHIFT			12
66 #define PMIC_RG_AUDMICBIAS1VREF_SHIFT			4
67 #define PMIC_RG_ANALOGFDEN_SHIFT			12
68 #define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT		8
69 #define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT			2
70 #define PMIC_ACCDET_SEQ_INIT_SHIFT			1
71 #define PMIC_RG_EINTCOMPVTH_MASK			0xf
72 #define PMIC_ACCDET_EINT0_MEM_IN_MASK			0x3
73 #define PMIC_ACCDET_EINT_DEBOUNCE0_MASK			0xf
74 #define PMIC_ACCDET_EINT_DEBOUNCE1_MASK			0xf
75 #define PMIC_ACCDET_EINT_DEBOUNCE2_MASK			0xf
76 #define PMIC_ACCDET_EINT_DEBOUNCE3_MASK			0xf
77 #define PMIC_ACCDET_EINT0_IRQ_SHIFT			2
78 #define PMIC_ACCDET_EINT1_IRQ_SHIFT			3
79 
80 /* AUDENC_ANA_CON16: */
81 #define RG_AUD_MICBIAS1_LOWP_EN		BIT(PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT)
82 
83 /* AUDENC_ANA_CON18: */
84 #define RG_ACCDET_MODE_ANA11_MODE1			(0x000f)
85 #define RG_ACCDET_MODE_ANA11_MODE2			(0x008f)
86 #define RG_ACCDET_MODE_ANA11_MODE6			(0x008f)
87 
88 /* AUXADC_ADC5:  Auxadc CH5 read data */
89 #define AUXADC_DATA_RDY_CH5		BIT(15)
90 #define AUXADC_DATA_PROCEED_CH5		BIT(15)
91 #define AUXADC_DATA_MASK				(0x0fff)
92 
93 /* AUXADC_RQST0_SET:  Auxadc CH5 request, relevant 0x07EC */
94 #define AUXADC_RQST_CH5_SET		BIT(5)
95 /* AUXADC_RQST0_CLR:  Auxadc CH5 request, relevant 0x07EC */
96 #define AUXADC_RQST_CH5_CLR		BIT(5)
97 
98 #define ACCDET_CALI_MASK0				(0xff)
99 #define ACCDET_CALI_MASK1				(0xff << 8)
100 #define ACCDET_CALI_MASK2				(0xff)
101 #define ACCDET_CALI_MASK3				(0xff << 8)
102 #define ACCDET_CALI_MASK4				(0xff)
103 
104 #define ACCDET_EINT1_IRQ_CLR_B11	BIT(PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT)
105 #define ACCDET_EINT0_IRQ_CLR_B10	BIT(PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
106 #define ACCDET_EINT_IRQ_CLR_B10_11	(0x03 << \
107 					 PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
108 #define ACCDET_IRQ_CLR_B8		BIT(PMIC_ACCDET_IRQ_CLR_SHIFT)
109 
110 #define ACCDET_EINT1_IRQ_B3		BIT(PMIC_ACCDET_EINT1_IRQ_SHIFT)
111 #define ACCDET_EINT0_IRQ_B2		BIT(PMIC_ACCDET_EINT0_IRQ_SHIFT)
112 #define ACCDET_EINT_IRQ_B2_B3		(0x03 << PMIC_ACCDET_EINT0_IRQ_SHIFT)
113 #define ACCDET_IRQ_B0			BIT(PMIC_ACCDET_IRQ_SHIFT)
114 
115 /* ACCDET_CON25: RO, accdet FSM state,etc.*/
116 #define ACCDET_STATE_MEM_IN_OFFSET	(PMIC_ACCDET_MEM_IN_SHIFT)
117 #define ACCDET_STATE_AB_MASK				(0x03)
118 #define ACCDET_STATE_AB_00				(0x00)
119 #define ACCDET_STATE_AB_01				(0x01)
120 #define ACCDET_STATE_AB_10				(0x02)
121 #define ACCDET_STATE_AB_11				(0x03)
122 
123 /* ACCDET_CON19 */
124 #define ACCDET_EINT0_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
125 				(1 << PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \
126 				(1 << PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \
127 				(1 << PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT))
128 
129 #define ACCDET_EINT1_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
130 				(1 << PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \
131 				(1 << PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \
132 				(1 << PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT))
133 
134 /* The following are used for mt6359.c */
135 /* MT6359_DCXO_CW12 */
136 #define RG_XO_AUDIO_EN_M_SFT				13
137 
138 /* AUD_TOP_CKPDN_CON0 */
139 #define RG_VOW13M_CK_PDN_SFT				13
140 #define RG_VOW13M_CK_PDN_MASK				0x1
141 #define RG_VOW13M_CK_PDN_MASK_SFT			(0x1 << 13)
142 #define RG_VOW32K_CK_PDN_SFT				12
143 #define RG_VOW32K_CK_PDN_MASK				0x1
144 #define RG_VOW32K_CK_PDN_MASK_SFT			(0x1 << 12)
145 #define RG_AUD_INTRP_CK_PDN_SFT				8
146 #define RG_AUD_INTRP_CK_PDN_MASK			0x1
147 #define RG_AUD_INTRP_CK_PDN_MASK_SFT			(0x1 << 8)
148 #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT			7
149 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK			0x1
150 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT		(0x1 << 7)
151 #define RG_AUDNCP_CK_PDN_SFT				6
152 #define RG_AUDNCP_CK_PDN_MASK				0x1
153 #define RG_AUDNCP_CK_PDN_MASK_SFT			(0x1 << 6)
154 #define RG_ZCD13M_CK_PDN_SFT				5
155 #define RG_ZCD13M_CK_PDN_MASK				0x1
156 #define RG_ZCD13M_CK_PDN_MASK_SFT			(0x1 << 5)
157 #define RG_AUDIF_CK_PDN_SFT				2
158 #define RG_AUDIF_CK_PDN_MASK				0x1
159 #define RG_AUDIF_CK_PDN_MASK_SFT			(0x1 << 2)
160 #define RG_AUD_CK_PDN_SFT				1
161 #define RG_AUD_CK_PDN_MASK				0x1
162 #define RG_AUD_CK_PDN_MASK_SFT				(0x1 << 1)
163 #define RG_ACCDET_CK_PDN_SFT				0
164 #define RG_ACCDET_CK_PDN_MASK				0x1
165 #define RG_ACCDET_CK_PDN_MASK_SFT			(0x1 << 0)
166 
167 /* AUD_TOP_CKPDN_CON0_SET */
168 #define RG_AUD_TOP_CKPDN_CON0_SET_SFT			0
169 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK			0x3fff
170 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT		(0x3fff << 0)
171 
172 /* AUD_TOP_CKPDN_CON0_CLR */
173 #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT			0
174 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK			0x3fff
175 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT		(0x3fff << 0)
176 
177 /* AUD_TOP_CKSEL_CON0 */
178 #define RG_AUDIF_CK_CKSEL_SFT				3
179 #define RG_AUDIF_CK_CKSEL_MASK				0x1
180 #define RG_AUDIF_CK_CKSEL_MASK_SFT			(0x1 << 3)
181 #define RG_AUD_CK_CKSEL_SFT				2
182 #define RG_AUD_CK_CKSEL_MASK				0x1
183 #define RG_AUD_CK_CKSEL_MASK_SFT			(0x1 << 2)
184 
185 /* AUD_TOP_CKSEL_CON0_SET */
186 #define RG_AUD_TOP_CKSEL_CON0_SET_SFT			0
187 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK			0xf
188 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT		(0xf << 0)
189 
190 /* AUD_TOP_CKSEL_CON0_CLR */
191 #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT			0
192 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK			0xf
193 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT		(0xf << 0)
194 
195 /* AUD_TOP_CKTST_CON0 */
196 #define RG_VOW13M_CK_TSTSEL_SFT				9
197 #define RG_VOW13M_CK_TSTSEL_MASK			0x1
198 #define RG_VOW13M_CK_TSTSEL_MASK_SFT			(0x1 << 9)
199 #define RG_VOW13M_CK_TST_DIS_SFT			8
200 #define RG_VOW13M_CK_TST_DIS_MASK			0x1
201 #define RG_VOW13M_CK_TST_DIS_MASK_SFT			(0x1 << 8)
202 #define RG_AUD26M_CK_TSTSEL_SFT				4
203 #define RG_AUD26M_CK_TSTSEL_MASK			0x1
204 #define RG_AUD26M_CK_TSTSEL_MASK_SFT			(0x1 << 4)
205 #define RG_AUDIF_CK_TSTSEL_SFT				3
206 #define RG_AUDIF_CK_TSTSEL_MASK				0x1
207 #define RG_AUDIF_CK_TSTSEL_MASK_SFT			(0x1 << 3)
208 #define RG_AUD_CK_TSTSEL_SFT				2
209 #define RG_AUD_CK_TSTSEL_MASK				0x1
210 #define RG_AUD_CK_TSTSEL_MASK_SFT			(0x1 << 2)
211 #define RG_AUD26M_CK_TST_DIS_SFT			0
212 #define RG_AUD26M_CK_TST_DIS_MASK			0x1
213 #define RG_AUD26M_CK_TST_DIS_MASK_SFT			(0x1 << 0)
214 
215 /* AUD_TOP_CLK_HWEN_CON0 */
216 #define RG_AUD_INTRP_CK_PDN_HWEN_SFT			0
217 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK			0x1
218 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT		(0x1 << 0)
219 
220 /* AUD_TOP_CLK_HWEN_CON0_SET */
221 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT		0
222 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK		0xffff
223 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT	(0xffff << 0)
224 
225 /* AUD_TOP_CLK_HWEN_CON0_CLR */
226 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT		0
227 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK		0xffff
228 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT	(0xffff << 0)
229 
230 /* AUD_TOP_RST_CON0 */
231 #define RG_AUDNCP_RST_SFT				3
232 #define RG_AUDNCP_RST_MASK				0x1
233 #define RG_AUDNCP_RST_MASK_SFT				(0x1 << 3)
234 #define RG_ZCD_RST_SFT					2
235 #define RG_ZCD_RST_MASK					0x1
236 #define RG_ZCD_RST_MASK_SFT				(0x1 << 2)
237 #define RG_ACCDET_RST_SFT				1
238 #define RG_ACCDET_RST_MASK				0x1
239 #define RG_ACCDET_RST_MASK_SFT				(0x1 << 1)
240 #define RG_AUDIO_RST_SFT				0
241 #define RG_AUDIO_RST_MASK				0x1
242 #define RG_AUDIO_RST_MASK_SFT				(0x1 << 0)
243 
244 /* AUD_TOP_RST_CON0_SET */
245 #define RG_AUD_TOP_RST_CON0_SET_SFT			0
246 #define RG_AUD_TOP_RST_CON0_SET_MASK			0xf
247 #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT		(0xf << 0)
248 
249 /* AUD_TOP_RST_CON0_CLR */
250 #define RG_AUD_TOP_RST_CON0_CLR_SFT			0
251 #define RG_AUD_TOP_RST_CON0_CLR_MASK			0xf
252 #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT		(0xf << 0)
253 
254 /* AUD_TOP_RST_BANK_CON0 */
255 #define BANK_AUDZCD_SWRST_SFT				2
256 #define BANK_AUDZCD_SWRST_MASK				0x1
257 #define BANK_AUDZCD_SWRST_MASK_SFT			(0x1 << 2)
258 #define BANK_AUDIO_SWRST_SFT				1
259 #define BANK_AUDIO_SWRST_MASK				0x1
260 #define BANK_AUDIO_SWRST_MASK_SFT			(0x1 << 1)
261 #define BANK_ACCDET_SWRST_SFT				0
262 #define BANK_ACCDET_SWRST_MASK				0x1
263 #define BANK_ACCDET_SWRST_MASK_SFT			(0x1 << 0)
264 
265 /* AFE_UL_DL_CON0 */
266 #define AFE_UL_LR_SWAP_SFT				15
267 #define AFE_UL_LR_SWAP_MASK				0x1
268 #define AFE_UL_LR_SWAP_MASK_SFT				(0x1 << 15)
269 #define AFE_DL_LR_SWAP_SFT				14
270 #define AFE_DL_LR_SWAP_MASK				0x1
271 #define AFE_DL_LR_SWAP_MASK_SFT				(0x1 << 14)
272 #define AFE_ON_SFT					0
273 #define AFE_ON_MASK					0x1
274 #define AFE_ON_MASK_SFT					(0x1 << 0)
275 
276 /* AFE_DL_SRC2_CON0_L */
277 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT			0
278 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK			0x1
279 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT		(0x1 << 0)
280 
281 /* AFE_UL_SRC_CON0_H */
282 #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT			11
283 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK			0x7
284 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT		(0x7 << 11)
285 #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT			8
286 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK			0x7
287 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT		(0x7 << 8)
288 #define C_TWO_DIGITAL_MIC_CTL_SFT			7
289 #define C_TWO_DIGITAL_MIC_CTL_MASK			0x1
290 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT			(0x1 << 7)
291 
292 /* AFE_UL_SRC_CON0_L */
293 #define DMIC_LOW_POWER_MODE_CTL_SFT			14
294 #define DMIC_LOW_POWER_MODE_CTL_MASK			0x3
295 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT		(0x3 << 14)
296 #define DIGMIC_4P33M_SEL_CTL_SFT			6
297 #define DIGMIC_4P33M_SEL_CTL_MASK			0x1
298 #define DIGMIC_4P33M_SEL_CTL_MASK_SFT			(0x1 << 6)
299 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT			5
300 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK		0x1
301 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT		(0x1 << 5)
302 #define UL_LOOP_BACK_MODE_CTL_SFT			2
303 #define UL_LOOP_BACK_MODE_CTL_MASK			0x1
304 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT			(0x1 << 2)
305 #define UL_SDM_3_LEVEL_CTL_SFT				1
306 #define UL_SDM_3_LEVEL_CTL_MASK				0x1
307 #define UL_SDM_3_LEVEL_CTL_MASK_SFT			(0x1 << 1)
308 #define UL_SRC_ON_TMP_CTL_SFT				0
309 #define UL_SRC_ON_TMP_CTL_MASK				0x1
310 #define UL_SRC_ON_TMP_CTL_MASK_SFT			(0x1 << 0)
311 
312 /* AFE_ADDA6_L_SRC_CON0_H */
313 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_SFT		11
314 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK		0x7
315 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT	(0x7 << 11)
316 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_SFT		8
317 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK		0x7
318 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT	(0x7 << 8)
319 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_SFT			7
320 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK		0x1
321 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT		(0x1 << 7)
322 
323 /* AFE_ADDA6_UL_SRC_CON0_L */
324 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT		14
325 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK		0x3
326 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT		(0x3 << 14)
327 #define ADDA6_DIGMIC_4P33M_SEL_CTL_SFT			6
328 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK			0x1
329 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT		(0x1 << 6)
330 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT		5
331 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK		0x1
332 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT	(0x1 << 5)
333 #define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT			2
334 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK		0x1
335 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT		(0x1 << 2)
336 #define ADDA6_UL_SDM_3_LEVEL_CTL_SFT			1
337 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK			0x1
338 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT		(0x1 << 1)
339 #define ADDA6_UL_SRC_ON_TMP_CTL_SFT			0
340 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK			0x1
341 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT		(0x1 << 0)
342 
343 /* AFE_TOP_CON0 */
344 #define ADDA6_MTKAIF_SINE_ON_SFT			4
345 #define ADDA6_MTKAIF_SINE_ON_MASK			0x1
346 #define ADDA6_MTKAIF_SINE_ON_MASK_SFT			(0x1 << 4)
347 #define ADDA6_UL_SINE_ON_SFT				3
348 #define ADDA6_UL_SINE_ON_MASK				0x1
349 #define ADDA6_UL_SINE_ON_MASK_SFT			(0x1 << 3)
350 #define MTKAIF_SINE_ON_SFT				2
351 #define MTKAIF_SINE_ON_MASK				0x1
352 #define MTKAIF_SINE_ON_MASK_SFT				(0x1 << 2)
353 #define UL_SINE_ON_SFT					1
354 #define UL_SINE_ON_MASK					0x1
355 #define UL_SINE_ON_MASK_SFT				(0x1 << 1)
356 #define DL_SINE_ON_SFT					0
357 #define DL_SINE_ON_MASK					0x1
358 #define DL_SINE_ON_MASK_SFT				(0x1 << 0)
359 
360 /* AUDIO_TOP_CON0 */
361 #define PDN_AFE_CTL_SFT					7
362 #define PDN_AFE_CTL_MASK				0x1
363 #define PDN_AFE_CTL_MASK_SFT				(0x1 << 7)
364 #define PDN_DAC_CTL_SFT					6
365 #define PDN_DAC_CTL_MASK				0x1
366 #define PDN_DAC_CTL_MASK_SFT				(0x1 << 6)
367 #define PDN_ADC_CTL_SFT					5
368 #define PDN_ADC_CTL_MASK				0x1
369 #define PDN_ADC_CTL_MASK_SFT				(0x1 << 5)
370 #define PDN_ADDA6_ADC_CTL_SFT				4
371 #define PDN_ADDA6_ADC_CTL_MASK				0x1
372 #define PDN_ADDA6_ADC_CTL_MASK_SFT			(0x1 << 4)
373 #define PDN_I2S_DL_CTL_SFT				3
374 #define PDN_I2S_DL_CTL_MASK				0x1
375 #define PDN_I2S_DL_CTL_MASK_SFT				(0x1 << 3)
376 #define PWR_CLK_DIS_CTL_SFT				2
377 #define PWR_CLK_DIS_CTL_MASK				0x1
378 #define PWR_CLK_DIS_CTL_MASK_SFT			(0x1 << 2)
379 #define PDN_AFE_TESTMODEL_CTL_SFT			1
380 #define PDN_AFE_TESTMODEL_CTL_MASK			0x1
381 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT			(0x1 << 1)
382 #define PDN_RESERVED_SFT				0
383 #define PDN_RESERVED_MASK				0x1
384 #define PDN_RESERVED_MASK_SFT				(0x1 << 0)
385 
386 /* AFE_MON_DEBUG0 */
387 #define AUDIO_SYS_TOP_MON_SWAP_SFT			14
388 #define AUDIO_SYS_TOP_MON_SWAP_MASK			0x3
389 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT			(0x3 << 14)
390 #define AUDIO_SYS_TOP_MON_SEL_SFT			8
391 #define AUDIO_SYS_TOP_MON_SEL_MASK			0x1f
392 #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT			(0x1f << 8)
393 #define AFE_MON_SEL_SFT					0
394 #define AFE_MON_SEL_MASK				0xff
395 #define AFE_MON_SEL_MASK_SFT				(0xff << 0)
396 
397 /* AFUNC_AUD_CON0 */
398 #define CCI_AUD_ANACK_SEL_SFT				15
399 #define CCI_AUD_ANACK_SEL_MASK				0x1
400 #define CCI_AUD_ANACK_SEL_MASK_SFT			(0x1 << 15)
401 #define CCI_AUDIO_FIFO_WPTR_SFT				12
402 #define CCI_AUDIO_FIFO_WPTR_MASK			0x7
403 #define CCI_AUDIO_FIFO_WPTR_MASK_SFT			(0x7 << 12)
404 #define CCI_SCRAMBLER_CG_EN_SFT				11
405 #define CCI_SCRAMBLER_CG_EN_MASK			0x1
406 #define CCI_SCRAMBLER_CG_EN_MASK_SFT			(0x1 << 11)
407 #define CCI_LCH_INV_SFT					10
408 #define CCI_LCH_INV_MASK				0x1
409 #define CCI_LCH_INV_MASK_SFT				(0x1 << 10)
410 #define CCI_RAND_EN_SFT					9
411 #define CCI_RAND_EN_MASK				0x1
412 #define CCI_RAND_EN_MASK_SFT				(0x1 << 9)
413 #define CCI_SPLT_SCRMB_CLK_ON_SFT			8
414 #define CCI_SPLT_SCRMB_CLK_ON_MASK			0x1
415 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT			(0x1 << 8)
416 #define CCI_SPLT_SCRMB_ON_SFT				7
417 #define CCI_SPLT_SCRMB_ON_MASK				0x1
418 #define CCI_SPLT_SCRMB_ON_MASK_SFT			(0x1 << 7)
419 #define CCI_AUD_IDAC_TEST_EN_SFT			6
420 #define CCI_AUD_IDAC_TEST_EN_MASK			0x1
421 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT			(0x1 << 6)
422 #define CCI_ZERO_PAD_DISABLE_SFT			5
423 #define CCI_ZERO_PAD_DISABLE_MASK			0x1
424 #define CCI_ZERO_PAD_DISABLE_MASK_SFT			(0x1 << 5)
425 #define CCI_AUD_SPLIT_TEST_EN_SFT			4
426 #define CCI_AUD_SPLIT_TEST_EN_MASK			0x1
427 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT			(0x1 << 4)
428 #define CCI_AUD_SDM_MUTEL_SFT				3
429 #define CCI_AUD_SDM_MUTEL_MASK				0x1
430 #define CCI_AUD_SDM_MUTEL_MASK_SFT			(0x1 << 3)
431 #define CCI_AUD_SDM_MUTER_SFT				2
432 #define CCI_AUD_SDM_MUTER_MASK				0x1
433 #define CCI_AUD_SDM_MUTER_MASK_SFT			(0x1 << 2)
434 #define CCI_AUD_SDM_7BIT_SEL_SFT			1
435 #define CCI_AUD_SDM_7BIT_SEL_MASK			0x1
436 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT			(0x1 << 1)
437 #define CCI_SCRAMBLER_EN_SFT				0
438 #define CCI_SCRAMBLER_EN_MASK				0x1
439 #define CCI_SCRAMBLER_EN_MASK_SFT			(0x1 << 0)
440 
441 /* AFUNC_AUD_CON1 */
442 #define AUD_SDM_TEST_L_SFT				8
443 #define AUD_SDM_TEST_L_MASK				0xff
444 #define AUD_SDM_TEST_L_MASK_SFT				(0xff << 8)
445 #define AUD_SDM_TEST_R_SFT				0
446 #define AUD_SDM_TEST_R_MASK				0xff
447 #define AUD_SDM_TEST_R_MASK_SFT				(0xff << 0)
448 
449 /* AFUNC_AUD_CON2 */
450 #define CCI_AUD_DAC_ANA_MUTE_SFT			7
451 #define CCI_AUD_DAC_ANA_MUTE_MASK			0x1
452 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT			(0x1 << 7)
453 #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT			6
454 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK			0x1
455 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT		(0x1 << 6)
456 #define CCI_AUDIO_FIFO_CLKIN_INV_SFT			4
457 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK			0x1
458 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT		(0x1 << 4)
459 #define CCI_AUDIO_FIFO_ENABLE_SFT			3
460 #define CCI_AUDIO_FIFO_ENABLE_MASK			0x1
461 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT			(0x1 << 3)
462 #define CCI_ACD_MODE_SFT				2
463 #define CCI_ACD_MODE_MASK				0x1
464 #define CCI_ACD_MODE_MASK_SFT				(0x1 << 2)
465 #define CCI_AFIFO_CLK_PWDB_SFT				1
466 #define CCI_AFIFO_CLK_PWDB_MASK				0x1
467 #define CCI_AFIFO_CLK_PWDB_MASK_SFT			(0x1 << 1)
468 #define CCI_ACD_FUNC_RSTB_SFT				0
469 #define CCI_ACD_FUNC_RSTB_MASK				0x1
470 #define CCI_ACD_FUNC_RSTB_MASK_SFT			(0x1 << 0)
471 
472 /* AFUNC_AUD_CON3 */
473 #define SDM_ANA13M_TESTCK_SEL_SFT			15
474 #define SDM_ANA13M_TESTCK_SEL_MASK			0x1
475 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT			(0x1 << 15)
476 #define SDM_ANA13M_TESTCK_SRC_SEL_SFT			12
477 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK			0x7
478 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT		(0x7 << 12)
479 #define SDM_TESTCK_SRC_SEL_SFT				8
480 #define SDM_TESTCK_SRC_SEL_MASK				0x7
481 #define SDM_TESTCK_SRC_SEL_MASK_SFT			(0x7 << 8)
482 #define DIGMIC_TESTCK_SRC_SEL_SFT			4
483 #define DIGMIC_TESTCK_SRC_SEL_MASK			0x7
484 #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT			(0x7 << 4)
485 #define DIGMIC_TESTCK_SEL_SFT				0
486 #define DIGMIC_TESTCK_SEL_MASK				0x1
487 #define DIGMIC_TESTCK_SEL_MASK_SFT			(0x1 << 0)
488 
489 /* AFUNC_AUD_CON4 */
490 #define UL_FIFO_WCLK_INV_SFT				8
491 #define UL_FIFO_WCLK_INV_MASK				0x1
492 #define UL_FIFO_WCLK_INV_MASK_SFT			(0x1 << 8)
493 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT		6
494 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK		0x1
495 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT	(0x1 << 6)
496 #define UL_FIFO_WDATA_TESTEN_SFT			5
497 #define UL_FIFO_WDATA_TESTEN_MASK			0x1
498 #define UL_FIFO_WDATA_TESTEN_MASK_SFT			(0x1 << 5)
499 #define UL_FIFO_WDATA_TESTSRC_SEL_SFT			4
500 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK			0x1
501 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT		(0x1 << 4)
502 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT		 3
503 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK		0x1
504 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT		(0x1 << 3)
505 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT		0
506 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK		0x7
507 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT	(0x7 << 0)
508 
509 /* AFUNC_AUD_CON5 */
510 #define R_AUD_DAC_POS_LARGE_MONO_SFT			8
511 #define R_AUD_DAC_POS_LARGE_MONO_MASK			0xff
512 #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT		(0xff << 8)
513 #define R_AUD_DAC_NEG_LARGE_MONO_SFT			0
514 #define R_AUD_DAC_NEG_LARGE_MONO_MASK			0xff
515 #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT		(0xff << 0)
516 
517 /* AFUNC_AUD_CON6 */
518 #define R_AUD_DAC_POS_SMALL_MONO_SFT			12
519 #define R_AUD_DAC_POS_SMALL_MONO_MASK			0xf
520 #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT		(0xf << 12)
521 #define R_AUD_DAC_NEG_SMALL_MONO_SFT			8
522 #define R_AUD_DAC_NEG_SMALL_MONO_MASK			0xf
523 #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT		(0xf << 8)
524 #define R_AUD_DAC_POS_TINY_MONO_SFT			6
525 #define R_AUD_DAC_POS_TINY_MONO_MASK			0x3
526 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT		(0x3 << 6)
527 #define R_AUD_DAC_NEG_TINY_MONO_SFT			4
528 #define R_AUD_DAC_NEG_TINY_MONO_MASK			0x3
529 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT		(0x3 << 4)
530 #define R_AUD_DAC_MONO_SEL_SFT				3
531 #define R_AUD_DAC_MONO_SEL_MASK				0x1
532 #define R_AUD_DAC_MONO_SEL_MASK_SFT			(0x1 << 3)
533 #define R_AUD_DAC_3TH_SEL_SFT				1
534 #define R_AUD_DAC_3TH_SEL_MASK				0x1
535 #define R_AUD_DAC_3TH_SEL_MASK_SFT			(0x1 << 1)
536 #define R_AUD_DAC_SW_RSTB_SFT				0
537 #define R_AUD_DAC_SW_RSTB_MASK				0x1
538 #define R_AUD_DAC_SW_RSTB_MASK_SFT			(0x1 << 0)
539 
540 /* AFUNC_AUD_CON7 */
541 #define UL2_DIGMIC_TESTCK_SRC_SEL_SFT			10
542 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK			0x7
543 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT		(0x7 << 10)
544 #define UL2_DIGMIC_TESTCK_SEL_SFT			9
545 #define UL2_DIGMIC_TESTCK_SEL_MASK			0x1
546 #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT			(0x1 << 9)
547 #define UL2_FIFO_WCLK_INV_SFT				8
548 #define UL2_FIFO_WCLK_INV_MASK				0x1
549 #define UL2_FIFO_WCLK_INV_MASK_SFT			(0x1 << 8)
550 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT		6
551 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK		0x1
552 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT	(0x1 << 6)
553 #define UL2_FIFO_WDATA_TESTEN_SFT			5
554 #define UL2_FIFO_WDATA_TESTEN_MASK			0x1
555 #define UL2_FIFO_WDATA_TESTEN_MASK_SFT			(0x1 << 5)
556 #define UL2_FIFO_WDATA_TESTSRC_SEL_SFT			4
557 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK			0x1
558 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT		(0x1 << 4)
559 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT		3
560 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK		0x1
561 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT		(0x1 << 3)
562 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT		0
563 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK		0x7
564 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT	(0x7 << 0)
565 
566 /* AFUNC_AUD_CON8 */
567 #define SPLITTER2_DITHER_EN_SFT				9
568 #define SPLITTER2_DITHER_EN_MASK			0x1
569 #define SPLITTER2_DITHER_EN_MASK_SFT			(0x1 << 9)
570 #define SPLITTER1_DITHER_EN_SFT				8
571 #define SPLITTER1_DITHER_EN_MASK			0x1
572 #define SPLITTER1_DITHER_EN_MASK_SFT			(0x1 << 8)
573 #define SPLITTER2_DITHER_GAIN_SFT			4
574 #define SPLITTER2_DITHER_GAIN_MASK			0xf
575 #define SPLITTER2_DITHER_GAIN_MASK_SFT			(0xf << 4)
576 #define SPLITTER1_DITHER_GAIN_SFT			0
577 #define SPLITTER1_DITHER_GAIN_MASK			0xf
578 #define SPLITTER1_DITHER_GAIN_MASK_SFT			(0xf << 0)
579 
580 /* AFUNC_AUD_CON9 */
581 #define CCI_AUD_ANACK_SEL_2ND_SFT			15
582 #define CCI_AUD_ANACK_SEL_2ND_MASK			0x1
583 #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT			(0x1 << 15)
584 #define CCI_AUDIO_FIFO_WPTR_2ND_SFT			12
585 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK			0x7
586 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT		(0x7 << 12)
587 #define CCI_SCRAMBLER_CG_EN_2ND_SFT			11
588 #define CCI_SCRAMBLER_CG_EN_2ND_MASK			0x1
589 #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT		 (0x1 << 11)
590 #define CCI_LCH_INV_2ND_SFT				10
591 #define CCI_LCH_INV_2ND_MASK				0x1
592 #define CCI_LCH_INV_2ND_MASK_SFT			(0x1 << 10)
593 #define CCI_RAND_EN_2ND_SFT				9
594 #define CCI_RAND_EN_2ND_MASK				0x1
595 #define CCI_RAND_EN_2ND_MASK_SFT			(0x1 << 9)
596 #define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT			8
597 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK			0x1
598 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT		(0x1 << 8)
599 #define CCI_SPLT_SCRMB_ON_2ND_SFT			7
600 #define CCI_SPLT_SCRMB_ON_2ND_MASK			0x1
601 #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT			(0x1 << 7)
602 #define CCI_AUD_IDAC_TEST_EN_2ND_SFT			6
603 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK			0x1
604 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT		(0x1 << 6)
605 #define CCI_ZERO_PAD_DISABLE_2ND_SFT			5
606 #define CCI_ZERO_PAD_DISABLE_2ND_MASK			0x1
607 #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT		(0x1 << 5)
608 #define CCI_AUD_SPLIT_TEST_EN_2ND_SFT			4
609 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK			0x1
610 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT		(0x1 << 4)
611 #define CCI_AUD_SDM_MUTEL_2ND_SFT			3
612 #define CCI_AUD_SDM_MUTEL_2ND_MASK			0x1
613 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT			(0x1 << 3)
614 #define CCI_AUD_SDM_MUTER_2ND_SFT			2
615 #define CCI_AUD_SDM_MUTER_2ND_MASK			0x1
616 #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT			(0x1 << 2)
617 #define CCI_AUD_SDM_7BIT_SEL_2ND_SFT			1
618 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK			0x1
619 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT		(0x1 << 1)
620 #define CCI_SCRAMBLER_EN_2ND_SFT			0
621 #define CCI_SCRAMBLER_EN_2ND_MASK			0x1
622 #define CCI_SCRAMBLER_EN_2ND_MASK_SFT			(0x1 << 0)
623 
624 /* AFUNC_AUD_CON10 */
625 #define AUD_SDM_TEST_L_2ND_SFT				8
626 #define AUD_SDM_TEST_L_2ND_MASK				0xff
627 #define AUD_SDM_TEST_L_2ND_MASK_SFT			(0xff << 8)
628 #define AUD_SDM_TEST_R_2ND_SFT				0
629 #define AUD_SDM_TEST_R_2ND_MASK				0xff
630 #define AUD_SDM_TEST_R_2ND_MASK_SFT			(0xff << 0)
631 
632 /* AFUNC_AUD_CON11 */
633 #define CCI_AUD_DAC_ANA_MUTE_2ND_SFT			7
634 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK			0x1
635 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT		(0x1 << 7)
636 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT		6
637 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK		0x1
638 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT		(0x1 << 6)
639 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT		4
640 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK		0x1
641 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT		(0x1 << 4)
642 #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT			3
643 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK			0x1
644 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT		(0x1 << 3)
645 #define CCI_ACD_MODE_2ND_SFT				2
646 #define CCI_ACD_MODE_2ND_MASK				0x1
647 #define CCI_ACD_MODE_2ND_MASK_SFT			(0x1 << 2)
648 #define CCI_AFIFO_CLK_PWDB_2ND_SFT			1
649 #define CCI_AFIFO_CLK_PWDB_2ND_MASK			0x1
650 #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT			(0x1 << 1)
651 #define CCI_ACD_FUNC_RSTB_2ND_SFT			0
652 #define CCI_ACD_FUNC_RSTB_2ND_MASK			0x1
653 #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT			(0x1 << 0)
654 
655 /* AFUNC_AUD_CON12 */
656 #define SPLITTER2_DITHER_EN_2ND_SFT			9
657 #define SPLITTER2_DITHER_EN_2ND_MASK			0x1
658 #define SPLITTER2_DITHER_EN_2ND_MASK_SFT		(0x1 << 9)
659 #define SPLITTER1_DITHER_EN_2ND_SFT			8
660 #define SPLITTER1_DITHER_EN_2ND_MASK			0x1
661 #define SPLITTER1_DITHER_EN_2ND_MASK_SFT		(0x1 << 8)
662 #define SPLITTER2_DITHER_GAIN_2ND_SFT			4
663 #define SPLITTER2_DITHER_GAIN_2ND_MASK			0xf
664 #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT		(0xf << 4)
665 #define SPLITTER1_DITHER_GAIN_2ND_SFT			0
666 #define SPLITTER1_DITHER_GAIN_2ND_MASK			0xf
667 #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT		(0xf << 0)
668 
669 /* AFUNC_AUD_MON0 */
670 #define AUD_SCR_OUT_L_SFT				8
671 #define AUD_SCR_OUT_L_MASK				0xff
672 #define AUD_SCR_OUT_L_MASK_SFT				(0xff << 8)
673 #define AUD_SCR_OUT_R_SFT				0
674 #define AUD_SCR_OUT_R_MASK				0xff
675 #define AUD_SCR_OUT_R_MASK_SFT				(0xff << 0)
676 
677 /* AFUNC_AUD_MON1 */
678 #define AUD_SCR_OUT_L_2ND_SFT				8
679 #define AUD_SCR_OUT_L_2ND_MASK				0xff
680 #define AUD_SCR_OUT_L_2ND_MASK_SFT			(0xff << 8)
681 #define AUD_SCR_OUT_R_2ND_SFT				0
682 #define AUD_SCR_OUT_R_2ND_MASK				0xff
683 #define AUD_SCR_OUT_R_2ND_MASK_SFT			(0xff << 0)
684 
685 /* AUDRC_TUNE_MON0 */
686 #define ASYNC_TEST_OUT_BCK_SFT				15
687 #define ASYNC_TEST_OUT_BCK_MASK				0x1
688 #define ASYNC_TEST_OUT_BCK_MASK_SFT			(0x1 << 15)
689 #define RGS_AUDRCTUNE1READ_SFT				8
690 #define RGS_AUDRCTUNE1READ_MASK				0x1f
691 #define RGS_AUDRCTUNE1READ_MASK_SFT			(0x1f << 8)
692 #define RGS_AUDRCTUNE0READ_SFT				0
693 #define RGS_AUDRCTUNE0READ_MASK				0x1f
694 #define RGS_AUDRCTUNE0READ_MASK_SFT			(0x1f << 0)
695 
696 /* AFE_ADDA_MTKAIF_FIFO_CFG0 */
697 #define AFE_RESERVED_SFT				1
698 #define AFE_RESERVED_MASK				0x7fff
699 #define AFE_RESERVED_MASK_SFT				(0x7fff << 1)
700 #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT			0
701 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK			0x1
702 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT		(0x1 << 0)
703 
704 /* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */
705 #define MTKAIF_RXIF_WR_FULL_STATUS_SFT			1
706 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK			0x1
707 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT		(0x1 << 1)
708 #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT			0
709 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK		0x1
710 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT		(0x1 << 0)
711 
712 /* AFE_ADDA_MTKAIF_MON0 */
713 #define MTKAIFTX_V3_SYNC_OUT_SFT			15
714 #define MTKAIFTX_V3_SYNC_OUT_MASK			0x1
715 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT			(0x1 << 15)
716 #define MTKAIFTX_V3_SDATA_OUT3_SFT			14
717 #define MTKAIFTX_V3_SDATA_OUT3_MASK			0x1
718 #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT			(0x1 << 14)
719 #define MTKAIFTX_V3_SDATA_OUT2_SFT			13
720 #define MTKAIFTX_V3_SDATA_OUT2_MASK			0x1
721 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT			(0x1 << 13)
722 #define MTKAIFTX_V3_SDATA_OUT1_SFT			12
723 #define MTKAIFTX_V3_SDATA_OUT1_MASK			0x1
724 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT			(0x1 << 12)
725 #define MTKAIF_RXIF_FIFO_STATUS_SFT			0
726 #define MTKAIF_RXIF_FIFO_STATUS_MASK			0xfff
727 #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT		(0xfff << 0)
728 
729 /* AFE_ADDA_MTKAIF_MON1 */
730 #define MTKAIFRX_V3_SYNC_IN_SFT				15
731 #define MTKAIFRX_V3_SYNC_IN_MASK			0x1
732 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT			(0x1 << 15)
733 #define MTKAIFRX_V3_SDATA_IN3_SFT			14
734 #define MTKAIFRX_V3_SDATA_IN3_MASK			0x1
735 #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT			(0x1 << 14)
736 #define MTKAIFRX_V3_SDATA_IN2_SFT			13
737 #define MTKAIFRX_V3_SDATA_IN2_MASK			0x1
738 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT			(0x1 << 13)
739 #define MTKAIFRX_V3_SDATA_IN1_SFT			12
740 #define MTKAIFRX_V3_SDATA_IN1_MASK			0x1
741 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT			(0x1 << 12)
742 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT		11
743 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK		0x1
744 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT		(0x1 << 11)
745 #define MTKAIF_RXIF_INVALID_FLAG_SFT			8
746 #define MTKAIF_RXIF_INVALID_FLAG_MASK			0x1
747 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT		(0x1 << 8)
748 #define MTKAIF_RXIF_INVALID_CYCLE_SFT			0
749 #define MTKAIF_RXIF_INVALID_CYCLE_MASK			0xff
750 #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT		(0xff << 0)
751 
752 /* AFE_ADDA_MTKAIF_MON2 */
753 #define MTKAIF_TXIF_IN_CH2_SFT				8
754 #define MTKAIF_TXIF_IN_CH2_MASK				0xff
755 #define MTKAIF_TXIF_IN_CH2_MASK_SFT			(0xff << 8)
756 #define MTKAIF_TXIF_IN_CH1_SFT				0
757 #define MTKAIF_TXIF_IN_CH1_MASK				0xff
758 #define MTKAIF_TXIF_IN_CH1_MASK_SFT			(0xff << 0)
759 
760 /* AFE_ADDA6_MTKAIF_MON3 */
761 #define ADDA6_MTKAIF_TXIF_IN_CH2_SFT			8
762 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK			0xff
763 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT		(0xff << 8)
764 #define ADDA6_MTKAIF_TXIF_IN_CH1_SFT			0
765 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK			0xff
766 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT		(0xff << 0)
767 
768 /* AFE_ADDA_MTKAIF_MON4 */
769 #define MTKAIF_RXIF_OUT_CH2_SFT				8
770 #define MTKAIF_RXIF_OUT_CH2_MASK			0xff
771 #define MTKAIF_RXIF_OUT_CH2_MASK_SFT			(0xff << 8)
772 #define MTKAIF_RXIF_OUT_CH1_SFT				0
773 #define MTKAIF_RXIF_OUT_CH1_MASK			0xff
774 #define MTKAIF_RXIF_OUT_CH1_MASK_SFT			(0xff << 0)
775 
776 /* AFE_ADDA_MTKAIF_MON5 */
777 #define MTKAIF_RXIF_OUT_CH3_SFT				0
778 #define MTKAIF_RXIF_OUT_CH3_MASK			0xff
779 #define MTKAIF_RXIF_OUT_CH3_MASK_SFT			(0xff << 0)
780 
781 /* AFE_ADDA_MTKAIF_CFG0 */
782 #define RG_MTKAIF_RXIF_CLKINV_SFT			15
783 #define RG_MTKAIF_RXIF_CLKINV_MASK			0x1
784 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT			(0x1 << 15)
785 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_SFT		9
786 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK		0x1
787 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT		(0x1 << 9)
788 #define RG_MTKAIF_RXIF_PROTOCOL2_SFT			8
789 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK			0x1
790 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT		(0x1 << 8)
791 #define RG_MTKAIF_BYPASS_SRC_MODE_SFT			6
792 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK			0x3
793 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT		(0x3 << 6)
794 #define RG_MTKAIF_BYPASS_SRC_TEST_SFT			5
795 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK			0x1
796 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT		(0x1 << 5)
797 #define RG_MTKAIF_TXIF_PROTOCOL2_SFT			4
798 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK			0x1
799 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT		(0x1 << 4)
800 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT		3
801 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK		0x1
802 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT		(0x1 << 3)
803 #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT			2
804 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK			0x1
805 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT		(0x1 << 2)
806 #define RG_MTKAIF_LOOPBACK_TEST2_SFT			1
807 #define RG_MTKAIF_LOOPBACK_TEST2_MASK			0x1
808 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT		(0x1 << 1)
809 #define RG_MTKAIF_LOOPBACK_TEST1_SFT			0
810 #define RG_MTKAIF_LOOPBACK_TEST1_MASK			0x1
811 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT		(0x1 << 0)
812 
813 /* AFE_ADDA_MTKAIF_RX_CFG0 */
814 #define RG_MTKAIF_RXIF_VOICE_MODE_SFT			12
815 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK			0xf
816 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT		(0xf << 12)
817 #define RG_MTKAIF_RXIF_DATA_BIT_SFT			8
818 #define RG_MTKAIF_RXIF_DATA_BIT_MASK			0x7
819 #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT		(0x7 << 8)
820 #define RG_MTKAIF_RXIF_FIFO_RSP_SFT			4
821 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK			0x7
822 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT		(0x7 << 4)
823 #define RG_MTKAIF_RXIF_DETECT_ON_SFT			3
824 #define RG_MTKAIF_RXIF_DETECT_ON_MASK			0x1
825 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT		(0x1 << 3)
826 #define RG_MTKAIF_RXIF_DATA_MODE_SFT			0
827 #define RG_MTKAIF_RXIF_DATA_MODE_MASK			0x1
828 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT		(0x1 << 0)
829 
830 /* AFE_ADDA_MTKAIF_RX_CFG1 */
831 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT		12
832 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK		0xf
833 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT	(0xf << 12)
834 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT	8
835 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK	0xf
836 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT	(0xf << 8)
837 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT		4
838 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK		0xf
839 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT	(0xf << 4)
840 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT		0
841 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK	0xf
842 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT	(0xf << 0)
843 
844 /* AFE_ADDA_MTKAIF_RX_CFG2 */
845 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_SFT			15
846 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK		0x1
847 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT		(0x1 << 15)
848 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_SFT		14
849 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK		0x1
850 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT	(0x1 << 14)
851 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_SFT		13
852 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK		0x1
853 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT	(0x1 << 13)
854 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT		12
855 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK		0x1
856 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT		(0x1 << 12)
857 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT		0
858 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK		0xfff
859 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT		(0xfff << 0)
860 
861 /* AFE_ADDA_MTKAIF_RX_CFG3 */
862 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT		7
863 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK		0x1
864 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT	(0x1 << 7)
865 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT		4
866 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK		0x7
867 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT	(0x7 << 4)
868 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT		3
869 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK		0x1
870 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT	(0x1 << 3)
871 
872 /* AFE_ADDA_MTKAIF_SYNCWORD_CFG0 */
873 #define RG_MTKAIF_RX_SYNC_WORD2_SFT			4
874 #define RG_MTKAIF_RX_SYNC_WORD2_MASK			0x7
875 #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT		(0x7 << 4)
876 #define RG_MTKAIF_RX_SYNC_WORD1_SFT			0
877 #define RG_MTKAIF_RX_SYNC_WORD1_MASK			0x7
878 #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT		(0x7 << 0)
879 
880 /* AFE_ADDA_MTKAIF_SYNCWORD_CFG1 */
881 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_SFT		12
882 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK		0x7
883 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT		(0x7 << 12)
884 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_SFT		8
885 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK		0x7
886 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT		(0x7 << 8)
887 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_SFT		4
888 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK		0x7
889 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT		(0x7 << 4)
890 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT		0
891 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK		0x7
892 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT		(0x7 << 0)
893 
894 /* AFE_SGEN_CFG0 */
895 #define SGEN_AMP_DIV_CH1_CTL_SFT			12
896 #define SGEN_AMP_DIV_CH1_CTL_MASK			0xf
897 #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT			(0xf << 12)
898 #define SGEN_DAC_EN_CTL_SFT				7
899 #define SGEN_DAC_EN_CTL_MASK				0x1
900 #define SGEN_DAC_EN_CTL_MASK_SFT			(0x1 << 7)
901 #define SGEN_MUTE_SW_CTL_SFT				6
902 #define SGEN_MUTE_SW_CTL_MASK				0x1
903 #define SGEN_MUTE_SW_CTL_MASK_SFT			(0x1 << 6)
904 #define R_AUD_SDM_MUTE_L_SFT				5
905 #define R_AUD_SDM_MUTE_L_MASK				0x1
906 #define R_AUD_SDM_MUTE_L_MASK_SFT			(0x1 << 5)
907 #define R_AUD_SDM_MUTE_R_SFT				4
908 #define R_AUD_SDM_MUTE_R_MASK				0x1
909 #define R_AUD_SDM_MUTE_R_MASK_SFT			(0x1 << 4)
910 #define R_AUD_SDM_MUTE_L_2ND_SFT			3
911 #define R_AUD_SDM_MUTE_L_2ND_MASK			0x1
912 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT			(0x1 << 3)
913 #define R_AUD_SDM_MUTE_R_2ND_SFT			2
914 #define R_AUD_SDM_MUTE_R_2ND_MASK			0x1
915 #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT			(0x1 << 2)
916 
917 /* AFE_SGEN_CFG1 */
918 #define C_SGEN_RCH_INV_5BIT_SFT				15
919 #define C_SGEN_RCH_INV_5BIT_MASK			0x1
920 #define C_SGEN_RCH_INV_5BIT_MASK_SFT			(0x1 << 15)
921 #define C_SGEN_RCH_INV_8BIT_SFT				14
922 #define C_SGEN_RCH_INV_8BIT_MASK			0x1
923 #define C_SGEN_RCH_INV_8BIT_MASK_SFT			(0x1 << 14)
924 #define SGEN_FREQ_DIV_CH1_CTL_SFT			0
925 #define SGEN_FREQ_DIV_CH1_CTL_MASK			0x1f
926 #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT			(0x1f << 0)
927 
928 /* AFE_ADC_ASYNC_FIFO_CFG */
929 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT		5
930 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK		0x1
931 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT		(0x1 << 5)
932 #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT			4
933 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK			0x1
934 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT		(0x1 << 4)
935 #define RG_AMIC_UL_ADC_CLK_SEL_SFT			1
936 #define RG_AMIC_UL_ADC_CLK_SEL_MASK			0x1
937 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT			(0x1 << 1)
938 
939 /* AFE_ADC_ASYNC_FIFO_CFG1 */
940 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT		5
941 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK		0x1
942 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT		(0x1 << 5)
943 #define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT			4
944 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK			0x1
945 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT		(0x1 << 4)
946 
947 /* AFE_DCCLK_CFG0 */
948 #define DCCLK_DIV_SFT					5
949 #define DCCLK_DIV_MASK					0x7ff
950 #define DCCLK_DIV_MASK_SFT				(0x7ff << 5)
951 #define DCCLK_INV_SFT					4
952 #define DCCLK_INV_MASK					0x1
953 #define DCCLK_INV_MASK_SFT				(0x1 << 4)
954 #define DCCLK_REF_CK_SEL_SFT				2
955 #define DCCLK_REF_CK_SEL_MASK				0x3
956 #define DCCLK_REF_CK_SEL_MASK_SFT			(0x3 << 2)
957 #define DCCLK_PDN_SFT					1
958 #define DCCLK_PDN_MASK					0x1
959 #define DCCLK_PDN_MASK_SFT				(0x1 << 1)
960 #define DCCLK_GEN_ON_SFT				0
961 #define DCCLK_GEN_ON_MASK				0x1
962 #define DCCLK_GEN_ON_MASK_SFT				(0x1 << 0)
963 
964 /* AFE_DCCLK_CFG1 */
965 #define RESYNC_SRC_SEL_SFT				10
966 #define RESYNC_SRC_SEL_MASK				0x3
967 #define RESYNC_SRC_SEL_MASK_SFT				(0x3 << 10)
968 #define RESYNC_SRC_CK_INV_SFT				9
969 #define RESYNC_SRC_CK_INV_MASK				0x1
970 #define RESYNC_SRC_CK_INV_MASK_SFT			(0x1 << 9)
971 #define DCCLK_RESYNC_BYPASS_SFT				8
972 #define DCCLK_RESYNC_BYPASS_MASK			0x1
973 #define DCCLK_RESYNC_BYPASS_MASK_SFT			(0x1 << 8)
974 #define DCCLK_PHASE_SEL_SFT				4
975 #define DCCLK_PHASE_SEL_MASK				0xf
976 #define DCCLK_PHASE_SEL_MASK_SFT			(0xf << 4)
977 
978 /* AUDIO_DIG_CFG */
979 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT		15
980 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK		0x1
981 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT	(0x1 << 15)
982 #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT			8
983 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK			0x7f
984 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT		(0x7f << 8)
985 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT		7
986 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK		0x1
987 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT	(0x1 << 7)
988 #define RG_AUD_PAD_TOP_PHASE_MODE_SFT			0
989 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK			0x7f
990 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT		(0x7f << 0)
991 
992 /* AUDIO_DIG_CFG1 */
993 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT		7
994 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK		0x1
995 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT	(0x1 << 7)
996 #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT			0
997 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK			0x7f
998 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT		(0x7f << 0)
999 
1000 /* AFE_AUD_PAD_TOP */
1001 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT			12
1002 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK			0x7
1003 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT		(0x7 << 12)
1004 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT		11
1005 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK	0x1
1006 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT	(0x1 << 11)
1007 #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT			8
1008 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK			0x1
1009 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT		(0x1 << 8)
1010 
1011 /* AFE_AUD_PAD_TOP_MON */
1012 #define ADDA_AUD_PAD_TOP_MON_SFT			0
1013 #define ADDA_AUD_PAD_TOP_MON_MASK			0xffff
1014 #define ADDA_AUD_PAD_TOP_MON_MASK_SFT			(0xffff << 0)
1015 
1016 /* AFE_AUD_PAD_TOP_MON1 */
1017 #define ADDA_AUD_PAD_TOP_MON1_SFT			0
1018 #define ADDA_AUD_PAD_TOP_MON1_MASK			0xffff
1019 #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT			(0xffff << 0)
1020 
1021 /* AFE_AUD_PAD_TOP_MON2 */
1022 #define ADDA_AUD_PAD_TOP_MON2_SFT			0
1023 #define ADDA_AUD_PAD_TOP_MON2_MASK			0xffff
1024 #define ADDA_AUD_PAD_TOP_MON2_MASK_SFT			(0xffff << 0)
1025 
1026 /* AFE_DL_NLE_CFG */
1027 #define NLE_RCH_HPGAIN_SEL_SFT				10
1028 #define NLE_RCH_HPGAIN_SEL_MASK				0x1
1029 #define NLE_RCH_HPGAIN_SEL_MASK_SFT			(0x1 << 10)
1030 #define NLE_RCH_CH_SEL_SFT				9
1031 #define NLE_RCH_CH_SEL_MASK				0x1
1032 #define NLE_RCH_CH_SEL_MASK_SFT				(0x1 << 9)
1033 #define NLE_RCH_ON_SFT					8
1034 #define NLE_RCH_ON_MASK					0x1
1035 #define NLE_RCH_ON_MASK_SFT				(0x1 << 8)
1036 #define NLE_LCH_HPGAIN_SEL_SFT				2
1037 #define NLE_LCH_HPGAIN_SEL_MASK				0x1
1038 #define NLE_LCH_HPGAIN_SEL_MASK_SFT			(0x1 << 2)
1039 #define NLE_LCH_CH_SEL_SFT				1
1040 #define NLE_LCH_CH_SEL_MASK				0x1
1041 #define NLE_LCH_CH_SEL_MASK_SFT				(0x1 << 1)
1042 #define NLE_LCH_ON_SFT					0
1043 #define NLE_LCH_ON_MASK					0x1
1044 #define NLE_LCH_ON_MASK_SFT				(0x1 << 0)
1045 
1046 /* AFE_DL_NLE_MON */
1047 #define NLE_MONITOR_SFT					0
1048 #define NLE_MONITOR_MASK				0x3fff
1049 #define NLE_MONITOR_MASK_SFT				(0x3fff << 0)
1050 
1051 /* AFE_CG_EN_MON */
1052 #define CK_CG_EN_MON_SFT				0
1053 #define CK_CG_EN_MON_MASK				0x3f
1054 #define CK_CG_EN_MON_MASK_SFT				(0x3f << 0)
1055 
1056 /* AFE_MIC_ARRAY_CFG */
1057 #define RG_AMIC_ADC1_SOURCE_SEL_SFT			10
1058 #define RG_AMIC_ADC1_SOURCE_SEL_MASK			0x3
1059 #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT		(0x3 << 10)
1060 #define RG_AMIC_ADC2_SOURCE_SEL_SFT			8
1061 #define RG_AMIC_ADC2_SOURCE_SEL_MASK			0x3
1062 #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT		(0x3 << 8)
1063 #define RG_AMIC_ADC3_SOURCE_SEL_SFT			6
1064 #define RG_AMIC_ADC3_SOURCE_SEL_MASK			0x3
1065 #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT		(0x3 << 6)
1066 #define RG_DMIC_ADC1_SOURCE_SEL_SFT			4
1067 #define RG_DMIC_ADC1_SOURCE_SEL_MASK			0x3
1068 #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT		(0x3 << 4)
1069 #define RG_DMIC_ADC2_SOURCE_SEL_SFT			2
1070 #define RG_DMIC_ADC2_SOURCE_SEL_MASK			0x3
1071 #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT		(0x3 << 2)
1072 #define RG_DMIC_ADC3_SOURCE_SEL_SFT			0
1073 #define RG_DMIC_ADC3_SOURCE_SEL_MASK			0x3
1074 #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT		(0x3 << 0)
1075 
1076 /* AFE_CHOP_CFG0 */
1077 #define RG_CHOP_DIV_SEL_SFT				4
1078 #define RG_CHOP_DIV_SEL_MASK				0x1f
1079 #define RG_CHOP_DIV_SEL_MASK_SFT			(0x1f << 4)
1080 #define RG_CHOP_DIV_EN_SFT				0
1081 #define RG_CHOP_DIV_EN_MASK				0x1
1082 #define RG_CHOP_DIV_EN_MASK_SFT				(0x1 << 0)
1083 
1084 /* AFE_MTKAIF_MUX_CFG */
1085 #define RG_ADDA6_EN_SEL_SFT				12
1086 #define RG_ADDA6_EN_SEL_MASK				0x1
1087 #define RG_ADDA6_EN_SEL_MASK_SFT			(0x1 << 12)
1088 #define RG_ADDA6_CH2_SEL_SFT				10
1089 #define RG_ADDA6_CH2_SEL_MASK				0x3
1090 #define RG_ADDA6_CH2_SEL_MASK_SFT			(0x3 << 10)
1091 #define RG_ADDA6_CH1_SEL_SFT				8
1092 #define RG_ADDA6_CH1_SEL_MASK				0x3
1093 #define RG_ADDA6_CH1_SEL_MASK_SFT			(0x3 << 8)
1094 #define RG_ADDA_EN_SEL_SFT				4
1095 #define RG_ADDA_EN_SEL_MASK				0x1
1096 #define RG_ADDA_EN_SEL_MASK_SFT				(0x1 << 4)
1097 #define RG_ADDA_CH2_SEL_SFT				2
1098 #define RG_ADDA_CH2_SEL_MASK				0x3
1099 #define RG_ADDA_CH2_SEL_MASK_SFT			(0x3 << 2)
1100 #define RG_ADDA_CH1_SEL_SFT				0
1101 #define RG_ADDA_CH1_SEL_MASK				0x3
1102 #define RG_ADDA_CH1_SEL_MASK_SFT			(0x3 << 0)
1103 
1104 /* AFE_PMIC_NEWIF_CFG3 */
1105 #define RG_UP8X_SYNC_WORD_SFT				0
1106 #define RG_UP8X_SYNC_WORD_MASK				0xffff
1107 #define RG_UP8X_SYNC_WORD_MASK_SFT			(0xffff << 0)
1108 
1109 /* AFE_NCP_CFG0 */
1110 #define  RG_NCP_CK1_VALID_CNT_SFT			9
1111 #define  RG_NCP_CK1_VALID_CNT_MASK			0x7f
1112 #define  RG_NCP_CK1_VALID_CNT_MASK_SFT			(0x7f << 9)
1113 #define RG_NCP_ADITH_SFT				8
1114 #define RG_NCP_ADITH_MASK				0x1
1115 #define RG_NCP_ADITH_MASK_SFT				(0x1 << 8)
1116 #define RG_NCP_DITHER_EN_SFT				7
1117 #define RG_NCP_DITHER_EN_MASK				0x1
1118 #define RG_NCP_DITHER_EN_MASK_SFT			(0x1 << 7)
1119 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT		4
1120 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK		0x7
1121 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT	(0x7 << 4)
1122 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT		1
1123 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK		0x7
1124 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT	(0x7 << 1)
1125 #define RG_NCP_ON_SFT					0
1126 #define RG_NCP_ON_MASK					0x1
1127 #define RG_NCP_ON_MASK_SFT				(0x1 << 0)
1128 
1129 /* AFE_NCP_CFG1 */
1130 #define RG_XY_VAL_CFG_EN_SFT				15
1131 #define RG_XY_VAL_CFG_EN_MASK				0x1
1132 #define RG_XY_VAL_CFG_EN_MASK_SFT			(0x1 << 15)
1133 #define RG_X_VAL_CFG_SFT				8
1134 #define RG_X_VAL_CFG_MASK				0x7f
1135 #define RG_X_VAL_CFG_MASK_SFT				(0x7f << 8)
1136 #define RG_Y_VAL_CFG_SFT				0
1137 #define RG_Y_VAL_CFG_MASK				0x7f
1138 #define RG_Y_VAL_CFG_MASK_SFT				(0x7f << 0)
1139 
1140 /* AFE_NCP_CFG2 */
1141 #define RG_NCP_NONCLK_SET_SFT				1
1142 #define RG_NCP_NONCLK_SET_MASK				0x1
1143 #define RG_NCP_NONCLK_SET_MASK_SFT			(0x1 << 1)
1144 #define RG_NCP_PDDIS_EN_SFT				0
1145 #define RG_NCP_PDDIS_EN_MASK				0x1
1146 #define RG_NCP_PDDIS_EN_MASK_SFT			(0x1 << 0)
1147 
1148 /* AUDENC_ANA_CON0 */
1149 #define RG_AUDPREAMPLON_SFT				0
1150 #define RG_AUDPREAMPLON_MASK				0x1
1151 #define RG_AUDPREAMPLON_MASK_SFT			(0x1 << 0)
1152 #define RG_AUDPREAMPLDCCEN_SFT				1
1153 #define RG_AUDPREAMPLDCCEN_MASK				0x1
1154 #define RG_AUDPREAMPLDCCEN_MASK_SFT			(0x1 << 1)
1155 #define RG_AUDPREAMPLDCPRECHARGE_SFT			2
1156 #define RG_AUDPREAMPLDCPRECHARGE_MASK			0x1
1157 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT		(0x1 << 2)
1158 #define RG_AUDPREAMPLPGATEST_SFT			3
1159 #define RG_AUDPREAMPLPGATEST_MASK			0x1
1160 #define RG_AUDPREAMPLPGATEST_MASK_SFT			(0x1 << 3)
1161 #define RG_AUDPREAMPLVSCALE_SFT				4
1162 #define RG_AUDPREAMPLVSCALE_MASK			0x3
1163 #define RG_AUDPREAMPLVSCALE_MASK_SFT			(0x3 << 4)
1164 #define RG_AUDPREAMPLINPUTSEL_SFT			6
1165 #define RG_AUDPREAMPLINPUTSEL_MASK			0x3
1166 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT			(0x3 << 6)
1167 #define RG_AUDPREAMPLGAIN_SFT				8
1168 #define RG_AUDPREAMPLGAIN_MASK				0x7
1169 #define RG_AUDPREAMPLGAIN_MASK_SFT			(0x7 << 8)
1170 #define RG_BULKL_VCM_EN_SFT				11
1171 #define RG_BULKL_VCM_EN_MASK				0x1
1172 #define RG_BULKL_VCM_EN_MASK_SFT			(0x1 << 11)
1173 #define RG_AUDADCLPWRUP_SFT				12
1174 #define RG_AUDADCLPWRUP_MASK				0x1
1175 #define RG_AUDADCLPWRUP_MASK_SFT			(0x1 << 12)
1176 #define RG_AUDADCLINPUTSEL_SFT				13
1177 #define RG_AUDADCLINPUTSEL_MASK				0x3
1178 #define RG_AUDADCLINPUTSEL_MASK_SFT			(0x3 << 13)
1179 
1180 /* AUDENC_ANA_CON1 */
1181 #define RG_AUDPREAMPRON_SFT				0
1182 #define RG_AUDPREAMPRON_MASK				0x1
1183 #define RG_AUDPREAMPRON_MASK_SFT			(0x1 << 0)
1184 #define RG_AUDPREAMPRDCCEN_SFT				1
1185 #define RG_AUDPREAMPRDCCEN_MASK				0x1
1186 #define RG_AUDPREAMPRDCCEN_MASK_SFT			(0x1 << 1)
1187 #define RG_AUDPREAMPRDCPRECHARGE_SFT			2
1188 #define RG_AUDPREAMPRDCPRECHARGE_MASK			0x1
1189 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT		(0x1 << 2)
1190 #define RG_AUDPREAMPRPGATEST_SFT			3
1191 #define RG_AUDPREAMPRPGATEST_MASK			0x1
1192 #define RG_AUDPREAMPRPGATEST_MASK_SFT			(0x1 << 3)
1193 #define RG_AUDPREAMPRVSCALE_SFT				4
1194 #define RG_AUDPREAMPRVSCALE_MASK			0x3
1195 #define RG_AUDPREAMPRVSCALE_MASK_SFT			(0x3 << 4)
1196 #define RG_AUDPREAMPRINPUTSEL_SFT			6
1197 #define RG_AUDPREAMPRINPUTSEL_MASK			0x3
1198 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT			(0x3 << 6)
1199 #define RG_AUDPREAMPRGAIN_SFT				8
1200 #define RG_AUDPREAMPRGAIN_MASK				0x7
1201 #define RG_AUDPREAMPRGAIN_MASK_SFT			(0x7 << 8)
1202 #define RG_BULKR_VCM_EN_SFT				11
1203 #define RG_BULKR_VCM_EN_MASK				0x1
1204 #define RG_BULKR_VCM_EN_MASK_SFT			(0x1 << 11)
1205 #define RG_AUDADCRPWRUP_SFT				12
1206 #define RG_AUDADCRPWRUP_MASK				0x1
1207 #define RG_AUDADCRPWRUP_MASK_SFT			(0x1 << 12)
1208 #define RG_AUDADCRINPUTSEL_SFT				13
1209 #define RG_AUDADCRINPUTSEL_MASK				0x3
1210 #define RG_AUDADCRINPUTSEL_MASK_SFT			(0x3 << 13)
1211 
1212 /* AUDENC_ANA_CON2 */
1213 #define RG_AUDPREAMP3ON_SFT				0
1214 #define RG_AUDPREAMP3ON_MASK				0x1
1215 #define RG_AUDPREAMP3ON_MASK_SFT			(0x1 << 0)
1216 #define RG_AUDPREAMP3DCCEN_SFT				1
1217 #define RG_AUDPREAMP3DCCEN_MASK				0x1
1218 #define RG_AUDPREAMP3DCCEN_MASK_SFT			(0x1 << 1)
1219 #define RG_AUDPREAMP3DCPRECHARGE_SFT			2
1220 #define RG_AUDPREAMP3DCPRECHARGE_MASK			0x1
1221 #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT		(0x1 << 2)
1222 #define RG_AUDPREAMP3PGATEST_SFT			3
1223 #define RG_AUDPREAMP3PGATEST_MASK			0x1
1224 #define RG_AUDPREAMP3PGATEST_MASK_SFT			(0x1 << 3)
1225 #define RG_AUDPREAMP3VSCALE_SFT				4
1226 #define RG_AUDPREAMP3VSCALE_MASK			0x3
1227 #define RG_AUDPREAMP3VSCALE_MASK_SFT			(0x3 << 4)
1228 #define RG_AUDPREAMP3INPUTSEL_SFT			6
1229 #define RG_AUDPREAMP3INPUTSEL_MASK			0x3
1230 #define RG_AUDPREAMP3INPUTSEL_MASK_SFT			(0x3 << 6)
1231 #define RG_AUDPREAMP3GAIN_SFT				8
1232 #define RG_AUDPREAMP3GAIN_MASK				0x7
1233 #define RG_AUDPREAMP3GAIN_MASK_SFT			(0x7 << 8)
1234 #define RG_BULK3_VCM_EN_SFT				11
1235 #define RG_BULK3_VCM_EN_MASK				0x1
1236 #define RG_BULK3_VCM_EN_MASK_SFT			(0x1 << 11)
1237 #define RG_AUDADC3PWRUP_SFT				12
1238 #define RG_AUDADC3PWRUP_MASK				0x1
1239 #define RG_AUDADC3PWRUP_MASK_SFT			(0x1 << 12)
1240 #define RG_AUDADC3INPUTSEL_SFT				13
1241 #define RG_AUDADC3INPUTSEL_MASK				0x3
1242 #define RG_AUDADC3INPUTSEL_MASK_SFT			(0x3 << 13)
1243 
1244 /* AUDENC_ANA_CON3 */
1245 #define RG_AUDULHALFBIAS_SFT				0
1246 #define RG_AUDULHALFBIAS_MASK				0x1
1247 #define RG_AUDULHALFBIAS_MASK_SFT			(0x1 << 0)
1248 #define RG_AUDGLBVOWLPWEN_SFT				1
1249 #define RG_AUDGLBVOWLPWEN_MASK				0x1
1250 #define RG_AUDGLBVOWLPWEN_MASK_SFT			(0x1 << 1)
1251 #define RG_AUDPREAMPLPEN_SFT				2
1252 #define RG_AUDPREAMPLPEN_MASK				0x1
1253 #define RG_AUDPREAMPLPEN_MASK_SFT			(0x1 << 2)
1254 #define RG_AUDADC1STSTAGELPEN_SFT			3
1255 #define RG_AUDADC1STSTAGELPEN_MASK			0x1
1256 #define RG_AUDADC1STSTAGELPEN_MASK_SFT			(0x1 << 3)
1257 #define RG_AUDADC2NDSTAGELPEN_SFT			4
1258 #define RG_AUDADC2NDSTAGELPEN_MASK			0x1
1259 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT			(0x1 << 4)
1260 #define RG_AUDADCFLASHLPEN_SFT				5
1261 #define RG_AUDADCFLASHLPEN_MASK				0x1
1262 #define RG_AUDADCFLASHLPEN_MASK_SFT			(0x1 << 5)
1263 #define RG_AUDPREAMPIDDTEST_SFT				6
1264 #define RG_AUDPREAMPIDDTEST_MASK			0x3
1265 #define RG_AUDPREAMPIDDTEST_MASK_SFT			(0x3 << 6)
1266 #define RG_AUDADC1STSTAGEIDDTEST_SFT			8
1267 #define RG_AUDADC1STSTAGEIDDTEST_MASK			0x3
1268 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT		(0x3 << 8)
1269 #define RG_AUDADC2NDSTAGEIDDTEST_SFT			10
1270 #define RG_AUDADC2NDSTAGEIDDTEST_MASK			0x3
1271 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT		(0x3 << 10)
1272 #define RG_AUDADCREFBUFIDDTEST_SFT			12
1273 #define RG_AUDADCREFBUFIDDTEST_MASK			0x3
1274 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT			(0x3 << 12)
1275 #define RG_AUDADCFLASHIDDTEST_SFT			14
1276 #define RG_AUDADCFLASHIDDTEST_MASK			0x3
1277 #define RG_AUDADCFLASHIDDTEST_MASK_SFT			(0x3 << 14)
1278 
1279 /* AUDENC_ANA_CON4 */
1280 #define RG_AUDRULHALFBIAS_SFT				0
1281 #define RG_AUDRULHALFBIAS_MASK				0x1
1282 #define RG_AUDRULHALFBIAS_MASK_SFT			(0x1 << 0)
1283 #define RG_AUDGLBRVOWLPWEN_SFT				1
1284 #define RG_AUDGLBRVOWLPWEN_MASK				0x1
1285 #define RG_AUDGLBRVOWLPWEN_MASK_SFT			(0x1 << 1)
1286 #define RG_AUDRPREAMPLPEN_SFT				2
1287 #define RG_AUDRPREAMPLPEN_MASK				0x1
1288 #define RG_AUDRPREAMPLPEN_MASK_SFT			(0x1 << 2)
1289 #define RG_AUDRADC1STSTAGELPEN_SFT			3
1290 #define RG_AUDRADC1STSTAGELPEN_MASK			0x1
1291 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT			(0x1 << 3)
1292 #define RG_AUDRADC2NDSTAGELPEN_SFT			4
1293 #define RG_AUDRADC2NDSTAGELPEN_MASK			0x1
1294 #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT			(0x1 << 4)
1295 #define RG_AUDRADCFLASHLPEN_SFT				5
1296 #define RG_AUDRADCFLASHLPEN_MASK			0x1
1297 #define RG_AUDRADCFLASHLPEN_MASK_SFT			(0x1 << 5)
1298 #define RG_AUDRPREAMPIDDTEST_SFT			6
1299 #define RG_AUDRPREAMPIDDTEST_MASK			0x3
1300 #define RG_AUDRPREAMPIDDTEST_MASK_SFT			(0x3 << 6)
1301 #define RG_AUDRADC1STSTAGEIDDTEST_SFT			8
1302 #define RG_AUDRADC1STSTAGEIDDTEST_MASK			0x3
1303 #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT		(0x3 << 8)
1304 #define RG_AUDRADC2NDSTAGEIDDTEST_SFT			10
1305 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK			0x3
1306 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT		(0x3 << 10)
1307 #define RG_AUDRADCREFBUFIDDTEST_SFT			12
1308 #define RG_AUDRADCREFBUFIDDTEST_MASK			0x3
1309 #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT		(0x3 << 12)
1310 #define RG_AUDRADCFLASHIDDTEST_SFT			14
1311 #define RG_AUDRADCFLASHIDDTEST_MASK			0x3
1312 #define RG_AUDRADCFLASHIDDTEST_MASK_SFT			(0x3 << 14)
1313 
1314 /* AUDENC_ANA_CON5 */
1315 #define RG_AUDADCCLKRSTB_SFT				0
1316 #define RG_AUDADCCLKRSTB_MASK				0x1
1317 #define RG_AUDADCCLKRSTB_MASK_SFT			(0x1 << 0)
1318 #define RG_AUDADCCLKSEL_SFT				1
1319 #define RG_AUDADCCLKSEL_MASK				0x3
1320 #define RG_AUDADCCLKSEL_MASK_SFT			(0x3 << 1)
1321 #define RG_AUDADCCLKSOURCE_SFT				3
1322 #define RG_AUDADCCLKSOURCE_MASK				0x3
1323 #define RG_AUDADCCLKSOURCE_MASK_SFT			(0x3 << 3)
1324 #define RG_AUDADCCLKGENMODE_SFT				5
1325 #define RG_AUDADCCLKGENMODE_MASK			0x3
1326 #define RG_AUDADCCLKGENMODE_MASK_SFT			(0x3 << 5)
1327 #define RG_AUDPREAMP_ACCFS_SFT				7
1328 #define RG_AUDPREAMP_ACCFS_MASK				0x1
1329 #define RG_AUDPREAMP_ACCFS_MASK_SFT			(0x1 << 7)
1330 #define RG_AUDPREAMPAAFEN_SFT				8
1331 #define RG_AUDPREAMPAAFEN_MASK				0x1
1332 #define RG_AUDPREAMPAAFEN_MASK_SFT			(0x1 << 8)
1333 #define RG_DCCVCMBUFLPMODSEL_SFT			9
1334 #define RG_DCCVCMBUFLPMODSEL_MASK			0x1
1335 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT			(0x1 << 9)
1336 #define RG_DCCVCMBUFLPSWEN_SFT				10
1337 #define RG_DCCVCMBUFLPSWEN_MASK				0x1
1338 #define RG_DCCVCMBUFLPSWEN_MASK_SFT			(0x1 << 10)
1339 #define RG_AUDSPAREPGA_SFT				11
1340 #define RG_AUDSPAREPGA_MASK				0x1f
1341 #define RG_AUDSPAREPGA_MASK_SFT				(0x1f << 11)
1342 
1343 /* AUDENC_ANA_CON6 */
1344 #define RG_AUDADC1STSTAGESDENB_SFT			0
1345 #define RG_AUDADC1STSTAGESDENB_MASK			0x1
1346 #define RG_AUDADC1STSTAGESDENB_MASK_SFT			(0x1 << 0)
1347 #define RG_AUDADC2NDSTAGERESET_SFT			1
1348 #define RG_AUDADC2NDSTAGERESET_MASK			0x1
1349 #define RG_AUDADC2NDSTAGERESET_MASK_SFT			(0x1 << 1)
1350 #define RG_AUDADC3RDSTAGERESET_SFT			2
1351 #define RG_AUDADC3RDSTAGERESET_MASK			0x1
1352 #define RG_AUDADC3RDSTAGERESET_MASK_SFT			(0x1 << 2)
1353 #define RG_AUDADCFSRESET_SFT				3
1354 #define RG_AUDADCFSRESET_MASK				0x1
1355 #define RG_AUDADCFSRESET_MASK_SFT			(0x1 << 3)
1356 #define RG_AUDADCWIDECM_SFT				4
1357 #define RG_AUDADCWIDECM_MASK				0x1
1358 #define RG_AUDADCWIDECM_MASK_SFT			(0x1 << 4)
1359 #define RG_AUDADCNOPATEST_SFT				5
1360 #define RG_AUDADCNOPATEST_MASK				0x1
1361 #define RG_AUDADCNOPATEST_MASK_SFT			(0x1 << 5)
1362 #define RG_AUDADCBYPASS_SFT				6
1363 #define RG_AUDADCBYPASS_MASK				0x1
1364 #define RG_AUDADCBYPASS_MASK_SFT			(0x1 << 6)
1365 #define RG_AUDADCFFBYPASS_SFT				7
1366 #define RG_AUDADCFFBYPASS_MASK				0x1
1367 #define RG_AUDADCFFBYPASS_MASK_SFT			(0x1 << 7)
1368 #define RG_AUDADCDACFBCURRENT_SFT			8
1369 #define RG_AUDADCDACFBCURRENT_MASK			0x1
1370 #define RG_AUDADCDACFBCURRENT_MASK_SFT			(0x1 << 8)
1371 #define RG_AUDADCDACIDDTEST_SFT				9
1372 #define RG_AUDADCDACIDDTEST_MASK			0x3
1373 #define RG_AUDADCDACIDDTEST_MASK_SFT			(0x3 << 9)
1374 #define RG_AUDADCDACNRZ_SFT				11
1375 #define RG_AUDADCDACNRZ_MASK				0x1
1376 #define RG_AUDADCDACNRZ_MASK_SFT			(0x1 << 11)
1377 #define RG_AUDADCNODEM_SFT				12
1378 #define RG_AUDADCNODEM_MASK				0x1
1379 #define RG_AUDADCNODEM_MASK_SFT				(0x1 << 12)
1380 #define RG_AUDADCDACTEST_SFT				13
1381 #define RG_AUDADCDACTEST_MASK				0x1
1382 #define RG_AUDADCDACTEST_MASK_SFT			(0x1 << 13)
1383 #define RG_AUDADCDAC0P25FS_SFT				14
1384 #define RG_AUDADCDAC0P25FS_MASK				0x1
1385 #define RG_AUDADCDAC0P25FS_MASK_SFT			(0x1 << 14)
1386 #define RG_AUDADCRDAC0P25FS_SFT				15
1387 #define RG_AUDADCRDAC0P25FS_MASK			0x1
1388 #define RG_AUDADCRDAC0P25FS_MASK_SFT			(0x1 << 15)
1389 
1390 /* AUDENC_ANA_CON7 */
1391 #define RG_AUDADCTESTDATA_SFT				0
1392 #define RG_AUDADCTESTDATA_MASK				0xffff
1393 #define RG_AUDADCTESTDATA_MASK_SFT			(0xffff << 0)
1394 
1395 /* AUDENC_ANA_CON8 */
1396 #define RG_AUDRCTUNEL_SFT				0
1397 #define RG_AUDRCTUNEL_MASK				0x1f
1398 #define RG_AUDRCTUNEL_MASK_SFT				(0x1f << 0)
1399 #define RG_AUDRCTUNELSEL_SFT				5
1400 #define RG_AUDRCTUNELSEL_MASK				0x1
1401 #define RG_AUDRCTUNELSEL_MASK_SFT			(0x1 << 5)
1402 #define RG_AUDRCTUNER_SFT				8
1403 #define RG_AUDRCTUNER_MASK				0x1f
1404 #define RG_AUDRCTUNER_MASK_SFT				(0x1f << 8)
1405 #define RG_AUDRCTUNERSEL_SFT				13
1406 #define RG_AUDRCTUNERSEL_MASK				0x1
1407 #define RG_AUDRCTUNERSEL_MASK_SFT			(0x1 << 13)
1408 
1409 /* AUDENC_ANA_CON9 */
1410 #define RG_AUD3CTUNEL_SFT				0
1411 #define RG_AUD3CTUNEL_MASK				0x1f
1412 #define RG_AUD3CTUNEL_MASK_SFT				(0x1f << 0)
1413 #define RG_AUD3CTUNELSEL_SFT				5
1414 #define RG_AUD3CTUNELSEL_MASK				0x1
1415 #define RG_AUD3CTUNELSEL_MASK_SFT			(0x1 << 5)
1416 #define RGS_AUDRCTUNE3READ_SFT				6
1417 #define RGS_AUDRCTUNE3READ_MASK				0x1f
1418 #define RGS_AUDRCTUNE3READ_MASK_SFT			(0x1f << 6)
1419 #define RG_AUD3SPARE_SFT				11
1420 #define RG_AUD3SPARE_MASK				0x1f
1421 #define RG_AUD3SPARE_MASK_SFT				(0x1f << 11)
1422 
1423 /* AUDENC_ANA_CON10 */
1424 #define RGS_AUDRCTUNELREAD_SFT				0
1425 #define RGS_AUDRCTUNELREAD_MASK				0x1f
1426 #define RGS_AUDRCTUNELREAD_MASK_SFT			(0x1f << 0)
1427 #define RGS_AUDRCTUNERREAD_SFT				8
1428 #define RGS_AUDRCTUNERREAD_MASK				0x1f
1429 #define RGS_AUDRCTUNERREAD_MASK_SFT			(0x1f << 8)
1430 
1431 /* AUDENC_ANA_CON11 */
1432 #define RG_AUDSPAREVA30_SFT				0
1433 #define RG_AUDSPAREVA30_MASK				0xff
1434 #define RG_AUDSPAREVA30_MASK_SFT			(0xff << 0)
1435 #define RG_AUDSPAREVA18_SFT				8
1436 #define RG_AUDSPAREVA18_MASK				0xff
1437 #define RG_AUDSPAREVA18_MASK_SFT			(0xff << 8)
1438 
1439 /* AUDENC_ANA_CON12 */
1440 #define RG_AUDPGA_DECAP_SFT				0
1441 #define RG_AUDPGA_DECAP_MASK				0x1
1442 #define RG_AUDPGA_DECAP_MASK_SFT			(0x1 << 0)
1443 #define RG_AUDPGA_CAPRA_SFT				1
1444 #define RG_AUDPGA_CAPRA_MASK				0x1
1445 #define RG_AUDPGA_CAPRA_MASK_SFT			(0x1 << 1)
1446 #define RG_AUDPGA_ACCCMP_SFT				2
1447 #define RG_AUDPGA_ACCCMP_MASK				0x1
1448 #define RG_AUDPGA_ACCCMP_MASK_SFT			(0x1 << 2)
1449 #define RG_AUDENC_SPARE2_SFT				3
1450 #define RG_AUDENC_SPARE2_MASK				0x1fff
1451 #define RG_AUDENC_SPARE2_MASK_SFT			(0x1fff << 3)
1452 
1453 /* AUDENC_ANA_CON13 */
1454 #define RG_AUDDIGMICEN_SFT				0
1455 #define RG_AUDDIGMICEN_MASK				0x1
1456 #define RG_AUDDIGMICEN_MASK_SFT				(0x1 << 0)
1457 #define RG_AUDDIGMICBIAS_SFT				1
1458 #define RG_AUDDIGMICBIAS_MASK				0x3
1459 #define RG_AUDDIGMICBIAS_MASK_SFT			(0x3 << 1)
1460 #define RG_DMICHPCLKEN_SFT				3
1461 #define RG_DMICHPCLKEN_MASK				0x1
1462 #define RG_DMICHPCLKEN_MASK_SFT				(0x1 << 3)
1463 #define RG_AUDDIGMICPDUTY_SFT				4
1464 #define RG_AUDDIGMICPDUTY_MASK				0x3
1465 #define RG_AUDDIGMICPDUTY_MASK_SFT			(0x3 << 4)
1466 #define RG_AUDDIGMICNDUTY_SFT				6
1467 #define RG_AUDDIGMICNDUTY_MASK				0x3
1468 #define RG_AUDDIGMICNDUTY_MASK_SFT			(0x3 << 6)
1469 #define RG_DMICMONEN_SFT				8
1470 #define RG_DMICMONEN_MASK				0x1
1471 #define RG_DMICMONEN_MASK_SFT				(0x1 << 8)
1472 #define RG_DMICMONSEL_SFT				9
1473 #define RG_DMICMONSEL_MASK				0x7
1474 #define RG_DMICMONSEL_MASK_SFT				(0x7 << 9)
1475 
1476 /* AUDENC_ANA_CON14 */
1477 #define RG_AUDDIGMIC1EN_SFT				0
1478 #define RG_AUDDIGMIC1EN_MASK				0x1
1479 #define RG_AUDDIGMIC1EN_MASK_SFT			(0x1 << 0)
1480 #define RG_AUDDIGMICBIAS1_SFT				1
1481 #define RG_AUDDIGMICBIAS1_MASK				0x3
1482 #define RG_AUDDIGMICBIAS1_MASK_SFT			(0x3 << 1)
1483 #define RG_DMIC1HPCLKEN_SFT				3
1484 #define RG_DMIC1HPCLKEN_MASK				0x1
1485 #define RG_DMIC1HPCLKEN_MASK_SFT			(0x1 << 3)
1486 #define RG_AUDDIGMIC1PDUTY_SFT				4
1487 #define RG_AUDDIGMIC1PDUTY_MASK				0x3
1488 #define RG_AUDDIGMIC1PDUTY_MASK_SFT			(0x3 << 4)
1489 #define RG_AUDDIGMIC1NDUTY_SFT				6
1490 #define RG_AUDDIGMIC1NDUTY_MASK				0x3
1491 #define RG_AUDDIGMIC1NDUTY_MASK_SFT			(0x3 << 6)
1492 #define RG_DMIC1MONEN_SFT				8
1493 #define RG_DMIC1MONEN_MASK				0x1
1494 #define RG_DMIC1MONEN_MASK_SFT				(0x1 << 8)
1495 #define RG_DMIC1MONSEL_SFT				9
1496 #define RG_DMIC1MONSEL_MASK				0x7
1497 #define RG_DMIC1MONSEL_MASK_SFT				(0x7 << 9)
1498 #define RG_AUDSPAREVMIC_SFT				12
1499 #define RG_AUDSPAREVMIC_MASK				0xf
1500 #define RG_AUDSPAREVMIC_MASK_SFT			(0xf << 12)
1501 
1502 /* AUDENC_ANA_CON15 */
1503 #define RG_AUDPWDBMICBIAS0_SFT				0
1504 #define RG_AUDPWDBMICBIAS0_MASK				0x1
1505 #define RG_AUDPWDBMICBIAS0_MASK_SFT			(0x1 << 0)
1506 #define RG_AUDMICBIAS0BYPASSEN_SFT			1
1507 #define RG_AUDMICBIAS0BYPASSEN_MASK			0x1
1508 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT			(0x1 << 1)
1509 #define RG_AUDMICBIAS0LOWPEN_SFT			2
1510 #define RG_AUDMICBIAS0LOWPEN_MASK			0x1
1511 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT			(0x1 << 2)
1512 #define RG_AUDPWDBMICBIAS3_SFT				3
1513 #define RG_AUDPWDBMICBIAS3_MASK				0x1
1514 #define RG_AUDPWDBMICBIAS3_MASK_SFT			(0x1 << 3)
1515 #define RG_AUDMICBIAS0VREF_SFT				4
1516 #define RG_AUDMICBIAS0VREF_MASK				0x7
1517 #define RG_AUDMICBIAS0VREF_MASK_SFT			(0x7 << 4)
1518 #define RG_AUDMICBIAS0DCSW0P1EN_SFT			8
1519 #define RG_AUDMICBIAS0DCSW0P1EN_MASK			0x1
1520 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT		(0x1 << 8)
1521 #define RG_AUDMICBIAS0DCSW0P2EN_SFT			9
1522 #define RG_AUDMICBIAS0DCSW0P2EN_MASK			0x1
1523 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT		(0x1 << 9)
1524 #define RG_AUDMICBIAS0DCSW0NEN_SFT			10
1525 #define RG_AUDMICBIAS0DCSW0NEN_MASK			0x1
1526 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT			(0x1 << 10)
1527 #define RG_AUDMICBIAS0DCSW2P1EN_SFT			12
1528 #define RG_AUDMICBIAS0DCSW2P1EN_MASK			0x1
1529 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT		(0x1 << 12)
1530 #define RG_AUDMICBIAS0DCSW2P2EN_SFT			13
1531 #define RG_AUDMICBIAS0DCSW2P2EN_MASK			0x1
1532 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT		(0x1 << 13)
1533 #define RG_AUDMICBIAS0DCSW2NEN_SFT			14
1534 #define RG_AUDMICBIAS0DCSW2NEN_MASK			0x1
1535 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT			(0x1 << 14)
1536 
1537 /* AUDENC_ANA_CON16 */
1538 #define RG_AUDPWDBMICBIAS1_SFT				0
1539 #define RG_AUDPWDBMICBIAS1_MASK				0x1
1540 #define RG_AUDPWDBMICBIAS1_MASK_SFT			(0x1 << 0)
1541 #define RG_AUDMICBIAS1BYPASSEN_SFT			1
1542 #define RG_AUDMICBIAS1BYPASSEN_MASK			0x1
1543 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT			(0x1 << 1)
1544 #define RG_AUDMICBIAS1LOWPEN_SFT			2
1545 #define RG_AUDMICBIAS1LOWPEN_MASK			0x1
1546 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT			(0x1 << 2)
1547 #define RG_AUDMICBIAS1VREF_SFT				4
1548 #define RG_AUDMICBIAS1VREF_MASK				0x7
1549 #define RG_AUDMICBIAS1VREF_MASK_SFT			(0x7 << 4)
1550 #define RG_AUDMICBIAS1DCSW1PEN_SFT			8
1551 #define RG_AUDMICBIAS1DCSW1PEN_MASK			0x1
1552 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT			(0x1 << 8)
1553 #define RG_AUDMICBIAS1DCSW1NEN_SFT			9
1554 #define RG_AUDMICBIAS1DCSW1NEN_MASK			0x1
1555 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT			(0x1 << 9)
1556 #define RG_BANDGAPGEN_SFT				10
1557 #define RG_BANDGAPGEN_MASK				0x1
1558 #define RG_BANDGAPGEN_MASK_SFT				(0x1 << 10)
1559 #define RG_AUDMICBIAS1HVEN_SFT				12
1560 #define RG_AUDMICBIAS1HVEN_MASK				0x1
1561 #define RG_AUDMICBIAS1HVEN_MASK_SFT			(0x1 << 12)
1562 #define RG_AUDMICBIAS1HVVREF_SFT			13
1563 #define RG_AUDMICBIAS1HVVREF_MASK			0x1
1564 #define RG_AUDMICBIAS1HVVREF_MASK_SFT			(0x1 << 13)
1565 
1566 /* AUDENC_ANA_CON17 */
1567 #define RG_AUDPWDBMICBIAS2_SFT				0
1568 #define RG_AUDPWDBMICBIAS2_MASK				0x1
1569 #define RG_AUDPWDBMICBIAS2_MASK_SFT			(0x1 << 0)
1570 #define RG_AUDMICBIAS2BYPASSEN_SFT			1
1571 #define RG_AUDMICBIAS2BYPASSEN_MASK			0x1
1572 #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT			(0x1 << 1)
1573 #define RG_AUDMICBIAS2LOWPEN_SFT			2
1574 #define RG_AUDMICBIAS2LOWPEN_MASK			0x1
1575 #define RG_AUDMICBIAS2LOWPEN_MASK_SFT			(0x1 << 2)
1576 #define RG_AUDMICBIAS2VREF_SFT				4
1577 #define RG_AUDMICBIAS2VREF_MASK				0x7
1578 #define RG_AUDMICBIAS2VREF_MASK_SFT			(0x7 << 4)
1579 #define RG_AUDMICBIAS2DCSW3P1EN_SFT			8
1580 #define RG_AUDMICBIAS2DCSW3P1EN_MASK			0x1
1581 #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT		(0x1 << 8)
1582 #define RG_AUDMICBIAS2DCSW3P2EN_SFT			9
1583 #define RG_AUDMICBIAS2DCSW3P2EN_MASK			0x1
1584 #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT		(0x1 << 9)
1585 #define RG_AUDMICBIAS2DCSW3NEN_SFT			10
1586 #define RG_AUDMICBIAS2DCSW3NEN_MASK			0x1
1587 #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT			(0x1 << 10)
1588 #define RG_AUDMICBIASSPARE_SFT				12
1589 #define RG_AUDMICBIASSPARE_MASK				0xf
1590 #define RG_AUDMICBIASSPARE_MASK_SFT			(0xf << 12)
1591 
1592 /* AUDENC_ANA_CON18 */
1593 #define RG_AUDACCDETMICBIAS0PULLLOW_SFT			0
1594 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK		0x1
1595 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT		(0x1 << 0)
1596 #define RG_AUDACCDETMICBIAS1PULLLOW_SFT			1
1597 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK		0x1
1598 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT		(0x1 << 1)
1599 #define RG_AUDACCDETMICBIAS2PULLLOW_SFT			2
1600 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK		0x1
1601 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT		(0x1 << 2)
1602 #define RG_AUDACCDETVIN1PULLLOW_SFT			3
1603 #define RG_AUDACCDETVIN1PULLLOW_MASK			0x1
1604 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT		(0x1 << 3)
1605 #define RG_AUDACCDETVTHACAL_SFT				4
1606 #define RG_AUDACCDETVTHACAL_MASK			0x1
1607 #define RG_AUDACCDETVTHACAL_MASK_SFT			(0x1 << 4)
1608 #define RG_AUDACCDETVTHBCAL_SFT				5
1609 #define RG_AUDACCDETVTHBCAL_MASK			0x1
1610 #define RG_AUDACCDETVTHBCAL_MASK_SFT			(0x1 << 5)
1611 #define RG_AUDACCDETTVDET_SFT				6
1612 #define RG_AUDACCDETTVDET_MASK				0x1
1613 #define RG_AUDACCDETTVDET_MASK_SFT			(0x1 << 6)
1614 #define RG_ACCDETSEL_SFT				7
1615 #define RG_ACCDETSEL_MASK				0x1
1616 #define RG_ACCDETSEL_MASK_SFT				(0x1 << 7)
1617 #define RG_SWBUFMODSEL_SFT				8
1618 #define RG_SWBUFMODSEL_MASK				0x1
1619 #define RG_SWBUFMODSEL_MASK_SFT				(0x1 << 8)
1620 #define RG_SWBUFSWEN_SFT				9
1621 #define RG_SWBUFSWEN_MASK				0x1
1622 #define RG_SWBUFSWEN_MASK_SFT				(0x1 << 9)
1623 #define RG_EINT0NOHYS_SFT				10
1624 #define RG_EINT0NOHYS_MASK				0x1
1625 #define RG_EINT0NOHYS_MASK_SFT				(0x1 << 10)
1626 #define RG_EINT0CONFIGACCDET_SFT			11
1627 #define RG_EINT0CONFIGACCDET_MASK			0x1
1628 #define RG_EINT0CONFIGACCDET_MASK_SFT			(0x1 << 11)
1629 #define RG_EINT0HIRENB_SFT				12
1630 #define RG_EINT0HIRENB_MASK				0x1
1631 #define RG_EINT0HIRENB_MASK_SFT				(0x1 << 12)
1632 #define RG_ACCDET2AUXRESBYPASS_SFT			13
1633 #define RG_ACCDET2AUXRESBYPASS_MASK			0x1
1634 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT			(0x1 << 13)
1635 #define RG_ACCDET2AUXSWEN_SFT				14
1636 #define RG_ACCDET2AUXSWEN_MASK				0x1
1637 #define RG_ACCDET2AUXSWEN_MASK_SFT			(0x1 << 14)
1638 #define RG_AUDACCDETMICBIAS3PULLLOW_SFT			15
1639 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK		0x1
1640 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT		(0x1 << 15)
1641 
1642 /* AUDENC_ANA_CON19 */
1643 #define RG_EINT1CONFIGACCDET_SFT			0
1644 #define RG_EINT1CONFIGACCDET_MASK			0x1
1645 #define RG_EINT1CONFIGACCDET_MASK_SFT			(0x1 << 0)
1646 #define RG_EINT1HIRENB_SFT				1
1647 #define RG_EINT1HIRENB_MASK				0x1
1648 #define RG_EINT1HIRENB_MASK_SFT				(0x1 << 1)
1649 #define RG_EINT1NOHYS_SFT				2
1650 #define RG_EINT1NOHYS_MASK				0x1
1651 #define RG_EINT1NOHYS_MASK_SFT				(0x1 << 2)
1652 #define RG_EINTCOMPVTH_SFT				4
1653 #define RG_EINTCOMPVTH_MASK				0xf
1654 #define RG_EINTCOMPVTH_MASK_SFT				(0xf << 4)
1655 #define RG_MTEST_EN_SFT					8
1656 #define RG_MTEST_EN_MASK				0x1
1657 #define RG_MTEST_EN_MASK_SFT				(0x1 << 8)
1658 #define RG_MTEST_SEL_SFT				9
1659 #define RG_MTEST_SEL_MASK				0x1
1660 #define RG_MTEST_SEL_MASK_SFT				(0x1 << 9)
1661 #define RG_MTEST_CURRENT_SFT				10
1662 #define RG_MTEST_CURRENT_MASK				0x1
1663 #define RG_MTEST_CURRENT_MASK_SFT			(0x1 << 10)
1664 #define RG_ANALOGFDEN_SFT				12
1665 #define RG_ANALOGFDEN_MASK				0x1
1666 #define RG_ANALOGFDEN_MASK_SFT				(0x1 << 12)
1667 #define RG_FDVIN1PPULLLOW_SFT				13
1668 #define RG_FDVIN1PPULLLOW_MASK				0x1
1669 #define RG_FDVIN1PPULLLOW_MASK_SFT			(0x1 << 13)
1670 #define RG_FDEINT0TYPE_SFT				14
1671 #define RG_FDEINT0TYPE_MASK				0x1
1672 #define RG_FDEINT0TYPE_MASK_SFT				(0x1 << 14)
1673 #define RG_FDEINT1TYPE_SFT				15
1674 #define RG_FDEINT1TYPE_MASK				0x1
1675 #define RG_FDEINT1TYPE_MASK_SFT				(0x1 << 15)
1676 
1677 /* AUDENC_ANA_CON20 */
1678 #define RG_EINT0CMPEN_SFT				0
1679 #define RG_EINT0CMPEN_MASK				0x1
1680 #define RG_EINT0CMPEN_MASK_SFT				(0x1 << 0)
1681 #define RG_EINT0CMPMEN_SFT				1
1682 #define RG_EINT0CMPMEN_MASK				0x1
1683 #define RG_EINT0CMPMEN_MASK_SFT				(0x1 << 1)
1684 #define RG_EINT0EN_SFT					2
1685 #define RG_EINT0EN_MASK					0x1
1686 #define RG_EINT0EN_MASK_SFT				(0x1 << 2)
1687 #define RG_EINT0CEN_SFT					3
1688 #define RG_EINT0CEN_MASK				0x1
1689 #define RG_EINT0CEN_MASK_SFT				(0x1 << 3)
1690 #define RG_EINT0INVEN_SFT				4
1691 #define RG_EINT0INVEN_MASK				0x1
1692 #define RG_EINT0INVEN_MASK_SFT				(0x1 << 4)
1693 #define RG_EINT0CTURBO_SFT				5
1694 #define RG_EINT0CTURBO_MASK				0x7
1695 #define RG_EINT0CTURBO_MASK_SFT				(0x7 << 5)
1696 #define RG_EINT1CMPEN_SFT				8
1697 #define RG_EINT1CMPEN_MASK				0x1
1698 #define RG_EINT1CMPEN_MASK_SFT				(0x1 << 8)
1699 #define RG_EINT1CMPMEN_SFT				9
1700 #define RG_EINT1CMPMEN_MASK				0x1
1701 #define RG_EINT1CMPMEN_MASK_SFT				(0x1 << 9)
1702 #define RG_EINT1EN_SFT					10
1703 #define RG_EINT1EN_MASK					0x1
1704 #define RG_EINT1EN_MASK_SFT				(0x1 << 10)
1705 #define RG_EINT1CEN_SFT					11
1706 #define RG_EINT1CEN_MASK				0x1
1707 #define RG_EINT1CEN_MASK_SFT				(0x1 << 11)
1708 #define RG_EINT1INVEN_SFT				12
1709 #define RG_EINT1INVEN_MASK				0x1
1710 #define RG_EINT1INVEN_MASK_SFT				(0x1 << 12)
1711 #define RG_EINT1CTURBO_SFT				13
1712 #define RG_EINT1CTURBO_MASK				0x7
1713 #define RG_EINT1CTURBO_MASK_SFT				(0x7 << 13)
1714 
1715 /* AUDENC_ANA_CON21 */
1716 #define RG_ACCDETSPARE_SFT				0
1717 #define RG_ACCDETSPARE_MASK				0xffff
1718 #define RG_ACCDETSPARE_MASK_SFT				(0xffff << 0)
1719 
1720 /* AUDENC_ANA_CON22 */
1721 #define RG_AUDENCSPAREVA30_SFT				0
1722 #define RG_AUDENCSPAREVA30_MASK				0xff
1723 #define RG_AUDENCSPAREVA30_MASK_SFT			(0xff << 0)
1724 #define RG_AUDENCSPAREVA18_SFT				8
1725 #define RG_AUDENCSPAREVA18_MASK				0xff
1726 #define RG_AUDENCSPAREVA18_MASK_SFT			(0xff << 8)
1727 
1728 /* AUDENC_ANA_CON23 */
1729 #define RG_CLKSQ_EN_SFT					0
1730 #define RG_CLKSQ_EN_MASK				0x1
1731 #define RG_CLKSQ_EN_MASK_SFT				(0x1 << 0)
1732 #define RG_CLKSQ_IN_SEL_TEST_SFT			1
1733 #define RG_CLKSQ_IN_SEL_TEST_MASK			0x1
1734 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT			(0x1 << 1)
1735 #define RG_CM_REFGENSEL_SFT				2
1736 #define RG_CM_REFGENSEL_MASK				0x1
1737 #define RG_CM_REFGENSEL_MASK_SFT			(0x1 << 2)
1738 #define RG_AUDIO_VOW_EN_SFT				3
1739 #define RG_AUDIO_VOW_EN_MASK				0x1
1740 #define RG_AUDIO_VOW_EN_MASK_SFT			(0x1 << 3)
1741 #define RG_CLKSQ_EN_VOW_SFT				4
1742 #define RG_CLKSQ_EN_VOW_MASK				0x1
1743 #define RG_CLKSQ_EN_VOW_MASK_SFT			(0x1 << 4)
1744 #define RG_CLKAND_EN_VOW_SFT				5
1745 #define RG_CLKAND_EN_VOW_MASK				0x1
1746 #define RG_CLKAND_EN_VOW_MASK_SFT			(0x1 << 5)
1747 #define RG_VOWCLK_SEL_EN_VOW_SFT			6
1748 #define RG_VOWCLK_SEL_EN_VOW_MASK			0x1
1749 #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT			(0x1 << 6)
1750 #define RG_SPARE_VOW_SFT				7
1751 #define RG_SPARE_VOW_MASK				0x7
1752 #define RG_SPARE_VOW_MASK_SFT				(0x7 << 7)
1753 
1754 /* AUDDEC_ANA_CON0 */
1755 #define RG_AUDDACLPWRUP_VAUDP32_SFT			0
1756 #define RG_AUDDACLPWRUP_VAUDP32_MASK			0x1
1757 #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT		(0x1 << 0)
1758 #define RG_AUDDACRPWRUP_VAUDP32_SFT			1
1759 #define RG_AUDDACRPWRUP_VAUDP32_MASK			0x1
1760 #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT		(0x1 << 1)
1761 #define RG_AUD_DAC_PWR_UP_VA32_SFT			2
1762 #define RG_AUD_DAC_PWR_UP_VA32_MASK			0x1
1763 #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT			(0x1 << 2)
1764 #define RG_AUD_DAC_PWL_UP_VA32_SFT			3
1765 #define RG_AUD_DAC_PWL_UP_VA32_MASK			0x1
1766 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT			(0x1 << 3)
1767 #define RG_AUDHPLPWRUP_VAUDP32_SFT			4
1768 #define RG_AUDHPLPWRUP_VAUDP32_MASK			0x1
1769 #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT			(0x1 << 4)
1770 #define RG_AUDHPRPWRUP_VAUDP32_SFT			5
1771 #define RG_AUDHPRPWRUP_VAUDP32_MASK			0x1
1772 #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT			(0x1 << 5)
1773 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_SFT		6
1774 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK		0x1
1775 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 6)
1776 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_SFT		7
1777 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK		0x1
1778 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 7)
1779 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT		8
1780 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK		0x3
1781 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 8)
1782 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT		10
1783 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK		0x3
1784 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 10)
1785 #define RG_AUDHPLSCDISABLE_VAUDP32_SFT			12
1786 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK			0x1
1787 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 12)
1788 #define RG_AUDHPRSCDISABLE_VAUDP32_SFT			13
1789 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK			0x1
1790 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 13)
1791 #define RG_AUDHPLBSCCURRENT_VAUDP32_SFT			14
1792 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK		0x1
1793 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 14)
1794 #define RG_AUDHPRBSCCURRENT_VAUDP32_SFT			15
1795 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK		0x1
1796 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 15)
1797 
1798 /* AUDDEC_ANA_CON1 */
1799 #define RG_AUDHPLOUTPWRUP_VAUDP32_SFT			0
1800 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK			0x1
1801 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT		(0x1 << 0)
1802 #define RG_AUDHPROUTPWRUP_VAUDP32_SFT			1
1803 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK			0x1
1804 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT		(0x1 << 1)
1805 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_SFT		2
1806 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK		0x1
1807 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT		(0x1 << 2)
1808 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT		3
1809 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK		0x1
1810 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT		(0x1 << 3)
1811 #define RG_HPLAUXFBRSW_EN_VAUDP32_SFT			4
1812 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK			0x1
1813 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT		(0x1 << 4)
1814 #define RG_HPRAUXFBRSW_EN_VAUDP32_SFT			5
1815 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK			0x1
1816 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT		(0x1 << 5)
1817 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_SFT		6
1818 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK		0x1
1819 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT		(0x1 << 6)
1820 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_SFT		7
1821 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK		0x1
1822 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT		(0x1 << 7)
1823 #define RG_HPLOUTSTGCTRL_VAUDP32_SFT			8
1824 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK			0x7
1825 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT		(0x7 << 8)
1826 #define RG_HPROUTSTGCTRL_VAUDP32_SFT			12
1827 #define RG_HPROUTSTGCTRL_VAUDP32_MASK			0x7
1828 #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT		(0x7 << 12)
1829 
1830 /* AUDDEC_ANA_CON2 */
1831 #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT			0
1832 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK			0x7
1833 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x7 << 0)
1834 #define RG_HPROUTPUTSTBENH_VAUDP32_SFT			4
1835 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK			0x7
1836 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT		(0x7 << 4)
1837 #define RG_AUDHPSTARTUP_VAUDP32_SFT			7
1838 #define RG_AUDHPSTARTUP_VAUDP32_MASK			0x1
1839 #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT		(0x1 << 7)
1840 #define RG_AUDREFN_DERES_EN_VAUDP32_SFT			8
1841 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK		0x1
1842 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT		(0x1 << 8)
1843 #define RG_HPINPUTSTBENH_VAUDP32_SFT			9
1844 #define RG_HPINPUTSTBENH_VAUDP32_MASK			0x1
1845 #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 9)
1846 #define RG_HPINPUTRESET0_VAUDP32_SFT			10
1847 #define RG_HPINPUTRESET0_VAUDP32_MASK			0x1
1848 #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
1849 #define RG_HPOUTPUTRESET0_VAUDP32_SFT			11
1850 #define RG_HPOUTPUTRESET0_VAUDP32_MASK			0x1
1851 #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 11)
1852 #define RG_HPPSHORT2VCM_VAUDP32_SFT			12
1853 #define RG_HPPSHORT2VCM_VAUDP32_MASK			0x7
1854 #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT		(0x7 << 12)
1855 #define RG_AUDHPTRIM_EN_VAUDP32_SFT			15
1856 #define RG_AUDHPTRIM_EN_VAUDP32_MASK			0x1
1857 #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT		(0x1 << 15)
1858 
1859 /* AUDDEC_ANA_CON3 */
1860 #define RG_AUDHPLTRIM_VAUDP32_SFT			0
1861 #define RG_AUDHPLTRIM_VAUDP32_MASK			0x1f
1862 #define RG_AUDHPLTRIM_VAUDP32_MASK_SFT			(0x1f << 0)
1863 #define RG_AUDHPLFINETRIM_VAUDP32_SFT			5
1864 #define RG_AUDHPLFINETRIM_VAUDP32_MASK			0x7
1865 #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT		(0x7 << 5)
1866 #define RG_AUDHPRTRIM_VAUDP32_SFT			8
1867 #define RG_AUDHPRTRIM_VAUDP32_MASK			0x1f
1868 #define RG_AUDHPRTRIM_VAUDP32_MASK_SFT			(0x1f << 8)
1869 #define RG_AUDHPRFINETRIM_VAUDP32_SFT			13
1870 #define RG_AUDHPRFINETRIM_VAUDP32_MASK			0x7
1871 #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT		(0x7 << 13)
1872 
1873 /* AUDDEC_ANA_CON4 */
1874 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT		0
1875 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK		0x7
1876 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT		(0x7 << 0)
1877 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_SFT		4
1878 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK		0x7
1879 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT		(0x7 << 4)
1880 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_SFT		8
1881 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK		0x7
1882 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT		(0x7 << 8)
1883 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT		12
1884 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK		0x3
1885 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT	(0x3 << 12)
1886 #define RG_AUDHPCOMP_EN_VAUDP32_SFT			15
1887 #define RG_AUDHPCOMP_EN_VAUDP32_MASK			0x1
1888 #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT		(0x1 << 15)
1889 
1890 /* AUDDEC_ANA_CON5 */
1891 #define RG_AUDHPDECMGAINADJ_VAUDP32_SFT			0
1892 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK		0x7
1893 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT		(0x7 << 0)
1894 #define RG_AUDHPDEDMGAINADJ_VAUDP32_SFT			4
1895 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK		0x7
1896 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT		(0x7 << 4)
1897 
1898 /* AUDDEC_ANA_CON6 */
1899 #define RG_AUDHSPWRUP_VAUDP32_SFT			0
1900 #define RG_AUDHSPWRUP_VAUDP32_MASK			0x1
1901 #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT			(0x1 << 0)
1902 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_SFT			1
1903 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK		0x1
1904 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 1)
1905 #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT			2
1906 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK		0x3
1907 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 2)
1908 #define RG_AUDHSSCDISABLE_VAUDP32_SFT			4
1909 #define RG_AUDHSSCDISABLE_VAUDP32_MASK			0x1
1910 #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 4)
1911 #define RG_AUDHSBSCCURRENT_VAUDP32_SFT			5
1912 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK			0x1
1913 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 5)
1914 #define RG_AUDHSSTARTUP_VAUDP32_SFT			6
1915 #define RG_AUDHSSTARTUP_VAUDP32_MASK			0x1
1916 #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT		(0x1 << 6)
1917 #define RG_HSOUTPUTSTBENH_VAUDP32_SFT			7
1918 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK			0x1
1919 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 7)
1920 #define RG_HSINPUTSTBENH_VAUDP32_SFT			8
1921 #define RG_HSINPUTSTBENH_VAUDP32_MASK			0x1
1922 #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 8)
1923 #define RG_HSINPUTRESET0_VAUDP32_SFT			9
1924 #define RG_HSINPUTRESET0_VAUDP32_MASK			0x1
1925 #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 9)
1926 #define RG_HSOUTPUTRESET0_VAUDP32_SFT			10
1927 #define RG_HSOUTPUTRESET0_VAUDP32_MASK			0x1
1928 #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
1929 #define RG_HSOUT_SHORTVCM_VAUDP32_SFT			11
1930 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK			0x1
1931 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT		(0x1 << 11)
1932 
1933 /* AUDDEC_ANA_CON7 */
1934 #define RG_AUDLOLPWRUP_VAUDP32_SFT			0
1935 #define RG_AUDLOLPWRUP_VAUDP32_MASK			0x1
1936 #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT			(0x1 << 0)
1937 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_SFT		1
1938 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK		0x1
1939 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 1)
1940 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT		2
1941 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK		0x3
1942 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 2)
1943 #define RG_AUDLOLSCDISABLE_VAUDP32_SFT			4
1944 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK			0x1
1945 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 4)
1946 #define RG_AUDLOLBSCCURRENT_VAUDP32_SFT			5
1947 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK		0x1
1948 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 5)
1949 #define RG_AUDLOSTARTUP_VAUDP32_SFT			6
1950 #define RG_AUDLOSTARTUP_VAUDP32_MASK			0x1
1951 #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT		(0x1 << 6)
1952 #define RG_LOINPUTSTBENH_VAUDP32_SFT			7
1953 #define RG_LOINPUTSTBENH_VAUDP32_MASK			0x1
1954 #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 7)
1955 #define RG_LOOUTPUTSTBENH_VAUDP32_SFT			8
1956 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK			0x1
1957 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 8)
1958 #define RG_LOINPUTRESET0_VAUDP32_SFT			9
1959 #define RG_LOINPUTRESET0_VAUDP32_MASK			0x1
1960 #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 9)
1961 #define RG_LOOUTPUTRESET0_VAUDP32_SFT			10
1962 #define RG_LOOUTPUTRESET0_VAUDP32_MASK			0x1
1963 #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
1964 #define RG_LOOUT_SHORTVCM_VAUDP32_SFT			11
1965 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK			0x1
1966 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT		(0x1 << 11)
1967 #define RG_AUDDACTPWRUP_VAUDP32_SFT			12
1968 #define RG_AUDDACTPWRUP_VAUDP32_MASK			0x1
1969 #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT		(0x1 << 12)
1970 #define RG_AUD_DAC_PWT_UP_VA32_SFT			13
1971 #define RG_AUD_DAC_PWT_UP_VA32_MASK			0x1
1972 #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT			(0x1 << 13)
1973 
1974 /* AUDDEC_ANA_CON8 */
1975 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT		0
1976 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK		0xf
1977 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT	(0xf << 0)
1978 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_SFT		4
1979 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK		0x3
1980 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT		(0x3 << 4)
1981 #define RG_AUDTRIMBUF_EN_VAUDP32_SFT			6
1982 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK			0x1
1983 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT		(0x1 << 6)
1984 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SFT		8
1985 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK		0x3
1986 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT	(0x3 << 8)
1987 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SFT		10
1988 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK	0x3
1989 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT	(0x3 << 10)
1990 #define RG_AUDHPSPKDET_EN_VAUDP32_SFT			12
1991 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK			0x1
1992 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT		(0x1 << 12)
1993 
1994 /* AUDDEC_ANA_CON9 */
1995 #define RG_ABIDEC_RSVD0_VA32_SFT			0
1996 #define RG_ABIDEC_RSVD0_VA32_MASK			0xff
1997 #define RG_ABIDEC_RSVD0_VA32_MASK_SFT			(0xff << 0)
1998 #define RG_ABIDEC_RSVD0_VAUDP32_SFT			8
1999 #define RG_ABIDEC_RSVD0_VAUDP32_MASK			0xff
2000 #define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT		(0xff << 8)
2001 
2002 /* AUDDEC_ANA_CON10 */
2003 #define RG_ABIDEC_RSVD1_VAUDP32_SFT			0
2004 #define RG_ABIDEC_RSVD1_VAUDP32_MASK			0xff
2005 #define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT		(0xff << 0)
2006 #define RG_ABIDEC_RSVD2_VAUDP32_SFT			8
2007 #define RG_ABIDEC_RSVD2_VAUDP32_MASK			0xff
2008 #define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT		(0xff << 8)
2009 
2010 /* AUDDEC_ANA_CON11 */
2011 #define RG_AUDZCDMUXSEL_VAUDP32_SFT			0
2012 #define RG_AUDZCDMUXSEL_VAUDP32_MASK			0x7
2013 #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT		(0x7 << 0)
2014 #define RG_AUDZCDCLKSEL_VAUDP32_SFT			3
2015 #define RG_AUDZCDCLKSEL_VAUDP32_MASK			0x1
2016 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT		(0x1 << 3)
2017 #define RG_AUDBIASADJ_0_VAUDP32_SFT			7
2018 #define RG_AUDBIASADJ_0_VAUDP32_MASK			0x1ff
2019 #define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT		(0x1ff << 7)
2020 
2021 /* AUDDEC_ANA_CON12 */
2022 #define RG_AUDBIASADJ_1_VAUDP32_SFT			0
2023 #define RG_AUDBIASADJ_1_VAUDP32_MASK			0xff
2024 #define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT		(0xff << 0)
2025 #define RG_AUDIBIASPWRDN_VAUDP32_SFT			8
2026 #define RG_AUDIBIASPWRDN_VAUDP32_MASK			0x1
2027 #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT		(0x1 << 8)
2028 
2029 /* AUDDEC_ANA_CON13 */
2030 #define RG_RSTB_DECODER_VA32_SFT			0
2031 #define RG_RSTB_DECODER_VA32_MASK			0x1
2032 #define RG_RSTB_DECODER_VA32_MASK_SFT			(0x1 << 0)
2033 #define RG_SEL_DECODER_96K_VA32_SFT			1
2034 #define RG_SEL_DECODER_96K_VA32_MASK			0x1
2035 #define RG_SEL_DECODER_96K_VA32_MASK_SFT		(0x1 << 1)
2036 #define RG_SEL_DELAY_VCORE_SFT				2
2037 #define RG_SEL_DELAY_VCORE_MASK				0x1
2038 #define RG_SEL_DELAY_VCORE_MASK_SFT			(0x1 << 2)
2039 #define RG_AUDGLB_PWRDN_VA32_SFT			4
2040 #define RG_AUDGLB_PWRDN_VA32_MASK			0x1
2041 #define RG_AUDGLB_PWRDN_VA32_MASK_SFT			(0x1 << 4)
2042 #define RG_AUDGLB_LP_VOW_EN_VA32_SFT			5
2043 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK			0x1
2044 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT		(0x1 << 5)
2045 #define RG_AUDGLB_LP2_VOW_EN_VA32_SFT			6
2046 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK			0x1
2047 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT		(0x1 << 6)
2048 
2049 /* AUDDEC_ANA_CON14 */
2050 #define RG_LCLDO_DEC_EN_VA32_SFT			0
2051 #define RG_LCLDO_DEC_EN_VA32_MASK			0x1
2052 #define RG_LCLDO_DEC_EN_VA32_MASK_SFT			(0x1 << 0)
2053 #define RG_LCLDO_DEC_PDDIS_EN_VA18_SFT			1
2054 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK			0x1
2055 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT		(0x1 << 1)
2056 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT		2
2057 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK		0x1
2058 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT		(0x1 << 2)
2059 #define RG_NVREG_EN_VAUDP32_SFT				4
2060 #define RG_NVREG_EN_VAUDP32_MASK			0x1
2061 #define RG_NVREG_EN_VAUDP32_MASK_SFT			(0x1 << 4)
2062 #define RG_NVREG_PULL0V_VAUDP32_SFT			5
2063 #define RG_NVREG_PULL0V_VAUDP32_MASK			0x1
2064 #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT		(0x1 << 5)
2065 #define RG_AUDPMU_RSVD_VA18_SFT				8
2066 #define RG_AUDPMU_RSVD_VA18_MASK			0xff
2067 #define RG_AUDPMU_RSVD_VA18_MASK_SFT			(0xff << 8)
2068 
2069 /* MT6359_ZCD_CON0 */
2070 #define RG_AUDZCDENABLE_SFT				0
2071 #define RG_AUDZCDENABLE_MASK				0x1
2072 #define RG_AUDZCDENABLE_MASK_SFT			(0x1 << 0)
2073 #define RG_AUDZCDGAINSTEPTIME_SFT			1
2074 #define RG_AUDZCDGAINSTEPTIME_MASK			0x7
2075 #define RG_AUDZCDGAINSTEPTIME_MASK_SFT			(0x7 << 1)
2076 #define RG_AUDZCDGAINSTEPSIZE_SFT			4
2077 #define RG_AUDZCDGAINSTEPSIZE_MASK			0x3
2078 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT			(0x3 << 4)
2079 #define RG_AUDZCDTIMEOUTMODESEL_SFT			6
2080 #define RG_AUDZCDTIMEOUTMODESEL_MASK			0x1
2081 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT		(0x1 << 6)
2082 
2083 /* MT6359_ZCD_CON1 */
2084 #define RG_AUDLOLGAIN_SFT				0
2085 #define RG_AUDLOLGAIN_MASK				0x1f
2086 #define RG_AUDLOLGAIN_MASK_SFT				(0x1f << 0)
2087 #define RG_AUDLORGAIN_SFT				7
2088 #define RG_AUDLORGAIN_MASK				0x1f
2089 #define RG_AUDLORGAIN_MASK_SFT				(0x1f << 7)
2090 
2091 /* MT6359_ZCD_CON2 */
2092 #define RG_AUDHPLGAIN_SFT				0
2093 #define RG_AUDHPLGAIN_MASK				0x1f
2094 #define RG_AUDHPLGAIN_MASK_SFT				(0x1f << 0)
2095 #define RG_AUDHPRGAIN_SFT				7
2096 #define RG_AUDHPRGAIN_MASK				0x1f
2097 #define RG_AUDHPRGAIN_MASK_SFT				(0x1f << 7)
2098 
2099 /* MT6359_ZCD_CON3 */
2100 #define RG_AUDHSGAIN_SFT				0
2101 #define RG_AUDHSGAIN_MASK				0x1f
2102 #define RG_AUDHSGAIN_MASK_SFT				(0x1f << 0)
2103 
2104 /* MT6359_ZCD_CON4 */
2105 #define RG_AUDIVLGAIN_SFT				0
2106 #define RG_AUDIVLGAIN_MASK				0x7
2107 #define RG_AUDIVLGAIN_MASK_SFT				(0x7 << 0)
2108 #define RG_AUDIVRGAIN_SFT				8
2109 #define RG_AUDIVRGAIN_MASK				0x7
2110 #define RG_AUDIVRGAIN_MASK_SFT				(0x7 << 8)
2111 
2112 /* MT6359_ZCD_CON5 */
2113 #define RG_AUDINTGAIN1_SFT				0
2114 #define RG_AUDINTGAIN1_MASK				0x3f
2115 #define RG_AUDINTGAIN1_MASK_SFT				(0x3f << 0)
2116 #define RG_AUDINTGAIN2_SFT				8
2117 #define RG_AUDINTGAIN2_MASK				0x3f
2118 #define RG_AUDINTGAIN2_MASK_SFT				(0x3f << 8)
2119 
2120 /* audio register */
2121 #define MT6359_GPIO_DIR0				0x88
2122 #define MT6359_GPIO_DIR0_SET				0x8a
2123 #define MT6359_GPIO_DIR0_CLR				0x8c
2124 #define MT6359_GPIO_DIR1				0x8e
2125 #define MT6359_GPIO_DIR1_SET				0x90
2126 #define MT6359_GPIO_DIR1_CLR				0x92
2127 
2128 #define MT6359_DCXO_CW11				0x7a6
2129 #define MT6359_DCXO_CW12				0x7a8
2130 
2131 #define MT6359_GPIO_MODE0				0xcc
2132 #define MT6359_GPIO_MODE0_SET				0xce
2133 #define MT6359_GPIO_MODE0_CLR				0xd0
2134 #define MT6359_GPIO_MODE1				0xd2
2135 #define MT6359_GPIO_MODE1_SET				0xd4
2136 #define MT6359_GPIO_MODE1_CLR				0xd6
2137 #define MT6359_GPIO_MODE2				0xd8
2138 #define MT6359_GPIO_MODE2_SET				0xda
2139 #define MT6359_GPIO_MODE2_CLR				0xdc
2140 #define MT6359_GPIO_MODE3				0xde
2141 #define MT6359_GPIO_MODE3_SET				0xe0
2142 #define MT6359_GPIO_MODE3_CLR				0xe2
2143 #define MT6359_GPIO_MODE4				0xe4
2144 #define MT6359_GPIO_MODE4_SET				0xe6
2145 #define MT6359_GPIO_MODE4_CLR				0xe8
2146 
2147 #define MT6359_AUD_TOP_ID				0x2300
2148 #define MT6359_AUD_TOP_REV0				0x2302
2149 #define MT6359_AUD_TOP_DBI				0x2304
2150 #define MT6359_AUD_TOP_DXI				0x2306
2151 #define MT6359_AUD_TOP_CKPDN_TPM0			0x2308
2152 #define MT6359_AUD_TOP_CKPDN_TPM1			0x230a
2153 #define MT6359_AUD_TOP_CKPDN_CON0			0x230c
2154 #define MT6359_AUD_TOP_CKPDN_CON0_SET			0x230e
2155 #define MT6359_AUD_TOP_CKPDN_CON0_CLR			0x2310
2156 #define MT6359_AUD_TOP_CKSEL_CON0			0x2312
2157 #define MT6359_AUD_TOP_CKSEL_CON0_SET			0x2314
2158 #define MT6359_AUD_TOP_CKSEL_CON0_CLR			0x2316
2159 #define MT6359_AUD_TOP_CKTST_CON0			0x2318
2160 #define MT6359_AUD_TOP_CLK_HWEN_CON0			0x231a
2161 #define MT6359_AUD_TOP_CLK_HWEN_CON0_SET		0x231c
2162 #define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR		0x231e
2163 #define MT6359_AUD_TOP_RST_CON0				0x2320
2164 #define MT6359_AUD_TOP_RST_CON0_SET			0x2322
2165 #define MT6359_AUD_TOP_RST_CON0_CLR			0x2324
2166 #define MT6359_AUD_TOP_RST_BANK_CON0			0x2326
2167 #define MT6359_AUD_TOP_INT_CON0				0x2328
2168 #define MT6359_AUD_TOP_INT_CON0_SET			0x232a
2169 #define MT6359_AUD_TOP_INT_CON0_CLR			0x232c
2170 #define MT6359_AUD_TOP_INT_MASK_CON0			0x232e
2171 #define MT6359_AUD_TOP_INT_MASK_CON0_SET		0x2330
2172 #define MT6359_AUD_TOP_INT_MASK_CON0_CLR		0x2332
2173 #define MT6359_AUD_TOP_INT_STATUS0			0x2334
2174 #define MT6359_AUD_TOP_INT_RAW_STATUS0			0x2336
2175 #define MT6359_AUD_TOP_INT_MISC_CON0			0x2338
2176 #define MT6359_AUD_TOP_MON_CON0				0x233a
2177 #define MT6359_AUDIO_DIG_DSN_ID				0x2380
2178 #define MT6359_AUDIO_DIG_DSN_REV0			0x2382
2179 #define MT6359_AUDIO_DIG_DSN_DBI			0x2384
2180 #define MT6359_AUDIO_DIG_DSN_DXI			0x2386
2181 #define MT6359_AFE_UL_DL_CON0				0x2388
2182 #define MT6359_AFE_DL_SRC2_CON0_L			0x238a
2183 #define MT6359_AFE_UL_SRC_CON0_H			0x238c
2184 #define MT6359_AFE_UL_SRC_CON0_L			0x238e
2185 #define MT6359_AFE_ADDA6_L_SRC_CON0_H			0x2390
2186 #define MT6359_AFE_ADDA6_UL_SRC_CON0_L			0x2392
2187 #define MT6359_AFE_TOP_CON0				0x2394
2188 #define MT6359_AUDIO_TOP_CON0				0x2396
2189 #define MT6359_AFE_MON_DEBUG0				0x2398
2190 #define MT6359_AFUNC_AUD_CON0				0x239a
2191 #define MT6359_AFUNC_AUD_CON1				0x239c
2192 #define MT6359_AFUNC_AUD_CON2				0x239e
2193 #define MT6359_AFUNC_AUD_CON3				0x23a0
2194 #define MT6359_AFUNC_AUD_CON4				0x23a2
2195 #define MT6359_AFUNC_AUD_CON5				0x23a4
2196 #define MT6359_AFUNC_AUD_CON6				0x23a6
2197 #define MT6359_AFUNC_AUD_CON7				0x23a8
2198 #define MT6359_AFUNC_AUD_CON8				0x23aa
2199 #define MT6359_AFUNC_AUD_CON9				0x23ac
2200 #define MT6359_AFUNC_AUD_CON10				0x23ae
2201 #define MT6359_AFUNC_AUD_CON11				0x23b0
2202 #define MT6359_AFUNC_AUD_CON12				0x23b2
2203 #define MT6359_AFUNC_AUD_MON0				0x23b4
2204 #define MT6359_AFUNC_AUD_MON1				0x23b6
2205 #define MT6359_AUDRC_TUNE_MON0				0x23b8
2206 #define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0		0x23ba
2207 #define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1		0x23bc
2208 #define MT6359_AFE_ADDA_MTKAIF_MON0			0x23be
2209 #define MT6359_AFE_ADDA_MTKAIF_MON1			0x23c0
2210 #define MT6359_AFE_ADDA_MTKAIF_MON2			0x23c2
2211 #define MT6359_AFE_ADDA6_MTKAIF_MON3			0x23c4
2212 #define MT6359_AFE_ADDA_MTKAIF_MON4			0x23c6
2213 #define MT6359_AFE_ADDA_MTKAIF_MON5			0x23c8
2214 #define MT6359_AFE_ADDA_MTKAIF_CFG0			0x23ca
2215 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG0			0x23cc
2216 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG1			0x23ce
2217 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG2			0x23d0
2218 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG3			0x23d2
2219 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0		0x23d4
2220 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1		0x23d6
2221 #define MT6359_AFE_SGEN_CFG0				0x23d8
2222 #define MT6359_AFE_SGEN_CFG1				0x23da
2223 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG			0x23dc
2224 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG1			0x23de
2225 #define MT6359_AFE_DCCLK_CFG0				0x23e0
2226 #define MT6359_AFE_DCCLK_CFG1				0x23e2
2227 #define MT6359_AUDIO_DIG_CFG				0x23e4
2228 #define MT6359_AUDIO_DIG_CFG1				0x23e6
2229 #define MT6359_AFE_AUD_PAD_TOP				0x23e8
2230 #define MT6359_AFE_AUD_PAD_TOP_MON			0x23ea
2231 #define MT6359_AFE_AUD_PAD_TOP_MON1			0x23ec
2232 #define MT6359_AFE_AUD_PAD_TOP_MON2			0x23ee
2233 #define MT6359_AFE_DL_NLE_CFG				0x23f0
2234 #define MT6359_AFE_DL_NLE_MON				0x23f2
2235 #define MT6359_AFE_CG_EN_MON				0x23f4
2236 #define MT6359_AFE_MIC_ARRAY_CFG			0x23f6
2237 #define MT6359_AFE_CHOP_CFG0				0x23f8
2238 #define MT6359_AFE_MTKAIF_MUX_CFG			0x23fa
2239 #define MT6359_AUDIO_DIG_2ND_DSN_ID			0x2400
2240 #define MT6359_AUDIO_DIG_2ND_DSN_REV0			0x2402
2241 #define MT6359_AUDIO_DIG_2ND_DSN_DBI			0x2404
2242 #define MT6359_AUDIO_DIG_2ND_DSN_DXI			0x2406
2243 #define MT6359_AFE_PMIC_NEWIF_CFG3			0x2408
2244 #define MT6359_AUDIO_DIG_3RD_DSN_ID			0x2480
2245 #define MT6359_AUDIO_DIG_3RD_DSN_REV0			0x2482
2246 #define MT6359_AUDIO_DIG_3RD_DSN_DBI			0x2484
2247 #define MT6359_AUDIO_DIG_3RD_DSN_DXI			0x2486
2248 #define MT6359_AFE_NCP_CFG0				0x24de
2249 #define MT6359_AFE_NCP_CFG1				0x24e0
2250 #define MT6359_AFE_NCP_CFG2				0x24e2
2251 #define MT6359_AUDENC_DSN_ID				0x2500
2252 #define MT6359_AUDENC_DSN_REV0				0x2502
2253 #define MT6359_AUDENC_DSN_DBI				0x2504
2254 #define MT6359_AUDENC_DSN_FPI				0x2506
2255 #define MT6359_AUDENC_ANA_CON0				0x2508
2256 #define MT6359_AUDENC_ANA_CON1				0x250a
2257 #define MT6359_AUDENC_ANA_CON2				0x250c
2258 #define MT6359_AUDENC_ANA_CON3				0x250e
2259 #define MT6359_AUDENC_ANA_CON4				0x2510
2260 #define MT6359_AUDENC_ANA_CON5				0x2512
2261 #define MT6359_AUDENC_ANA_CON6				0x2514
2262 #define MT6359_AUDENC_ANA_CON7				0x2516
2263 #define MT6359_AUDENC_ANA_CON8				0x2518
2264 #define MT6359_AUDENC_ANA_CON9				0x251a
2265 #define MT6359_AUDENC_ANA_CON10				0x251c
2266 #define MT6359_AUDENC_ANA_CON11				0x251e
2267 #define MT6359_AUDENC_ANA_CON12				0x2520
2268 #define MT6359_AUDENC_ANA_CON13				0x2522
2269 #define MT6359_AUDENC_ANA_CON14				0x2524
2270 #define MT6359_AUDENC_ANA_CON15				0x2526
2271 #define MT6359_AUDENC_ANA_CON16				0x2528
2272 #define MT6359_AUDENC_ANA_CON17				0x252a
2273 #define MT6359_AUDENC_ANA_CON18				0x252c
2274 #define MT6359_AUDENC_ANA_CON19				0x252e
2275 #define MT6359_AUDENC_ANA_CON20				0x2530
2276 #define MT6359_AUDENC_ANA_CON21				0x2532
2277 #define MT6359_AUDENC_ANA_CON22				0x2534
2278 #define MT6359_AUDENC_ANA_CON23				0x2536
2279 #define MT6359_AUDDEC_DSN_ID				0x2580
2280 #define MT6359_AUDDEC_DSN_REV0				0x2582
2281 #define MT6359_AUDDEC_DSN_DBI				0x2584
2282 #define MT6359_AUDDEC_DSN_FPI				0x2586
2283 #define MT6359_AUDDEC_ANA_CON0				0x2588
2284 #define MT6359_AUDDEC_ANA_CON1				0x258a
2285 #define MT6359_AUDDEC_ANA_CON2				0x258c
2286 #define MT6359_AUDDEC_ANA_CON3				0x258e
2287 #define MT6359_AUDDEC_ANA_CON4				0x2590
2288 #define MT6359_AUDDEC_ANA_CON5				0x2592
2289 #define MT6359_AUDDEC_ANA_CON6				0x2594
2290 #define MT6359_AUDDEC_ANA_CON7				0x2596
2291 #define MT6359_AUDDEC_ANA_CON8				0x2598
2292 #define MT6359_AUDDEC_ANA_CON9				0x259a
2293 #define MT6359_AUDDEC_ANA_CON10				0x259c
2294 #define MT6359_AUDDEC_ANA_CON11				0x259e
2295 #define MT6359_AUDDEC_ANA_CON12				0x25a0
2296 #define MT6359_AUDDEC_ANA_CON13				0x25a2
2297 #define MT6359_AUDDEC_ANA_CON14				0x25a4
2298 #define MT6359_AUDZCD_DSN_ID				0x2600
2299 #define MT6359_AUDZCD_DSN_REV0				0x2602
2300 #define MT6359_AUDZCD_DSN_DBI				0x2604
2301 #define MT6359_AUDZCD_DSN_FPI				0x2606
2302 #define MT6359_ZCD_CON0					0x2608
2303 #define MT6359_ZCD_CON1					0x260a
2304 #define MT6359_ZCD_CON2					0x260c
2305 #define MT6359_ZCD_CON3					0x260e
2306 #define MT6359_ZCD_CON4					0x2610
2307 #define MT6359_ZCD_CON5					0x2612
2308 #define MT6359_ACCDET_DSN_DIG_ID			0x2680
2309 #define MT6359_ACCDET_DSN_DIG_REV0			0x2682
2310 #define MT6359_ACCDET_DSN_DBI				0x2684
2311 #define MT6359_ACCDET_DSN_FPI				0x2686
2312 #define MT6359_ACCDET_CON0				0x2688
2313 #define MT6359_ACCDET_CON1				0x268a
2314 #define MT6359_ACCDET_CON2				0x268c
2315 #define MT6359_ACCDET_CON3				0x268e
2316 #define MT6359_ACCDET_CON4				0x2690
2317 #define MT6359_ACCDET_CON5				0x2692
2318 #define MT6359_ACCDET_CON6				0x2694
2319 #define MT6359_ACCDET_CON7				0x2696
2320 #define MT6359_ACCDET_CON8				0x2698
2321 #define MT6359_ACCDET_CON9				0x269a
2322 #define MT6359_ACCDET_CON10				0x269c
2323 #define MT6359_ACCDET_CON11				0x269e
2324 #define MT6359_ACCDET_CON12				0x26a0
2325 #define MT6359_ACCDET_CON13				0x26a2
2326 #define MT6359_ACCDET_CON14				0x26a4
2327 #define MT6359_ACCDET_CON15				0x26a6
2328 #define MT6359_ACCDET_CON16				0x26a8
2329 #define MT6359_ACCDET_CON17				0x26aa
2330 #define MT6359_ACCDET_CON18				0x26ac
2331 #define MT6359_ACCDET_CON19				0x26ae
2332 #define MT6359_ACCDET_CON20				0x26b0
2333 #define MT6359_ACCDET_CON21				0x26b2
2334 #define MT6359_ACCDET_CON22				0x26b4
2335 #define MT6359_ACCDET_CON23				0x26b6
2336 #define MT6359_ACCDET_CON24				0x26b8
2337 #define MT6359_ACCDET_CON25				0x26ba
2338 #define MT6359_ACCDET_CON26				0x26bc
2339 #define MT6359_ACCDET_CON27				0x26be
2340 #define MT6359_ACCDET_CON28				0x26c0
2341 #define MT6359_ACCDET_CON29				0x26c2
2342 #define MT6359_ACCDET_CON30				0x26c4
2343 #define MT6359_ACCDET_CON31				0x26c6
2344 #define MT6359_ACCDET_CON32				0x26c8
2345 #define MT6359_ACCDET_CON33				0x26ca
2346 #define MT6359_ACCDET_CON34				0x26cc
2347 #define MT6359_ACCDET_CON35				0x26ce
2348 #define MT6359_ACCDET_CON36				0x26d0
2349 #define MT6359_ACCDET_CON37				0x26d2
2350 #define MT6359_ACCDET_CON38				0x26d4
2351 #define MT6359_ACCDET_CON39				0x26d6
2352 #define MT6359_ACCDET_CON40				0x26d8
2353 #define MT6359_MAX_REGISTER				MT6359_ZCD_CON5
2354 
2355 /* dl bias */
2356 #define DRBIAS_MASK 0x7
2357 #define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
2358 #define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)
2359 #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
2360 #define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)
2361 #define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)
2362 #define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)
2363 #define IBIAS_MASK 0x3
2364 #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
2365 #define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)
2366 #define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)
2367 #define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)
2368 #define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)
2369 #define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)
2370 #define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)
2371 #define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)
2372 
2373 /* dl gain */
2374 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
2375 #define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)
2376 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
2377 #define DL_GAIN_REG_MASK 0x0f9f
2378 
2379 /* mic type mux */
2380 #define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
2381 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
2382 	.info = snd_soc_info_enum_double, \
2383 	.get = xhandler_get, .put = xhandler_put, \
2384 	.private_value = (unsigned long)&(xenum) }
2385 
2386 enum {
2387 	MT6359_MTKAIF_PROTOCOL_1 = 0,
2388 	MT6359_MTKAIF_PROTOCOL_2,
2389 	MT6359_MTKAIF_PROTOCOL_2_CLK_P2,
2390 };
2391 
2392 enum {
2393 	MT6359_AIF_1 = 0,	/* dl: hp, rcv, hp+lo */
2394 	MT6359_AIF_2,		/* dl: lo only */
2395 	MT6359_AIF_NUM,
2396 };
2397 
2398 enum {
2399 	AUDIO_ANALOG_VOLUME_HSOUTL,
2400 	AUDIO_ANALOG_VOLUME_HSOUTR,
2401 	AUDIO_ANALOG_VOLUME_HPOUTL,
2402 	AUDIO_ANALOG_VOLUME_HPOUTR,
2403 	AUDIO_ANALOG_VOLUME_LINEOUTL,
2404 	AUDIO_ANALOG_VOLUME_LINEOUTR,
2405 	AUDIO_ANALOG_VOLUME_MICAMP1,
2406 	AUDIO_ANALOG_VOLUME_MICAMP2,
2407 	AUDIO_ANALOG_VOLUME_MICAMP3,
2408 	AUDIO_ANALOG_VOLUME_TYPE_MAX
2409 };
2410 
2411 enum {
2412 	MUX_MIC_TYPE_0,	/* ain0, micbias 0 */
2413 	MUX_MIC_TYPE_1,	/* ain1, micbias 1 */
2414 	MUX_MIC_TYPE_2,	/* ain2/3, micbias 2 */
2415 	MUX_PGA_L,
2416 	MUX_PGA_R,
2417 	MUX_PGA_3,
2418 	MUX_HP,
2419 	MUX_NUM,
2420 };
2421 
2422 enum {
2423 	DEVICE_HP,
2424 	DEVICE_LO,
2425 	DEVICE_RCV,
2426 	DEVICE_MIC1,
2427 	DEVICE_MIC2,
2428 	DEVICE_NUM
2429 };
2430 
2431 enum {
2432 	HP_GAIN_CTL_ZCD = 0,
2433 	HP_GAIN_CTL_NLE,
2434 	HP_GAIN_CTL_NUM,
2435 };
2436 
2437 enum {
2438 	HP_MUX_OPEN = 0,
2439 	HP_MUX_HPSPK,
2440 	HP_MUX_HP,
2441 	HP_MUX_TEST_MODE,
2442 	HP_MUX_HP_IMPEDANCE,
2443 	HP_MUX_MASK = 0x7,
2444 };
2445 
2446 enum {
2447 	RCV_MUX_OPEN = 0,
2448 	RCV_MUX_MUTE,
2449 	RCV_MUX_VOICE_PLAYBACK,
2450 	RCV_MUX_TEST_MODE,
2451 	RCV_MUX_MASK = 0x3,
2452 };
2453 
2454 enum {
2455 	LO_MUX_OPEN = 0,
2456 	LO_MUX_L_DAC,
2457 	LO_MUX_3RD_DAC,
2458 	LO_MUX_TEST_MODE,
2459 	LO_MUX_MASK = 0x3,
2460 };
2461 
2462 /* Supply widget subseq */
2463 enum {
2464 	/* common */
2465 	SUPPLY_SEQ_CLK_BUF,
2466 	SUPPLY_SEQ_AUD_GLB,
2467 	SUPPLY_SEQ_HP_PULL_DOWN,
2468 	SUPPLY_SEQ_CLKSQ,
2469 	SUPPLY_SEQ_ADC_CLKGEN,
2470 	SUPPLY_SEQ_TOP_CK,
2471 	SUPPLY_SEQ_TOP_CK_LAST,
2472 	SUPPLY_SEQ_DCC_CLK,
2473 	SUPPLY_SEQ_MIC_BIAS,
2474 	SUPPLY_SEQ_DMIC,
2475 	SUPPLY_SEQ_AUD_TOP,
2476 	SUPPLY_SEQ_AUD_TOP_LAST,
2477 	SUPPLY_SEQ_DL_SDM_FIFO_CLK,
2478 	SUPPLY_SEQ_DL_SDM,
2479 	SUPPLY_SEQ_DL_NCP,
2480 	SUPPLY_SEQ_AFE,
2481 	/* playback */
2482 	SUPPLY_SEQ_DL_SRC,
2483 	SUPPLY_SEQ_DL_ESD_RESIST,
2484 	SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
2485 	SUPPLY_SEQ_HP_MUTE,
2486 	SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
2487 	SUPPLY_SEQ_DL_LDO,
2488 	SUPPLY_SEQ_DL_NV,
2489 	SUPPLY_SEQ_HP_ANA_TRIM,
2490 	SUPPLY_SEQ_DL_IBIST,
2491 	/* capture */
2492 	SUPPLY_SEQ_UL_PGA,
2493 	SUPPLY_SEQ_UL_ADC,
2494 	SUPPLY_SEQ_UL_MTKAIF,
2495 	SUPPLY_SEQ_UL_SRC_DMIC,
2496 	SUPPLY_SEQ_UL_SRC,
2497 };
2498 
2499 enum {
2500 	CH_L = 0,
2501 	CH_R,
2502 	NUM_CH,
2503 };
2504 
2505 enum {
2506 	DRBIAS_4UA = 0,
2507 	DRBIAS_5UA,
2508 	DRBIAS_6UA,
2509 	DRBIAS_7UA,
2510 	DRBIAS_8UA,
2511 	DRBIAS_9UA,
2512 	DRBIAS_10UA,
2513 	DRBIAS_11UA,
2514 };
2515 
2516 enum {
2517 	IBIAS_4UA = 0,
2518 	IBIAS_5UA,
2519 	IBIAS_6UA,
2520 	IBIAS_7UA,
2521 };
2522 
2523 enum {
2524 	IBIAS_ZCD_3UA = 0,
2525 	IBIAS_ZCD_4UA,
2526 	IBIAS_ZCD_5UA,
2527 	IBIAS_ZCD_6UA,
2528 };
2529 
2530 enum {
2531 	MIC_BIAS_1P7 = 0,
2532 	MIC_BIAS_1P8,
2533 	MIC_BIAS_1P9,
2534 	MIC_BIAS_2P0,
2535 	MIC_BIAS_2P1,
2536 	MIC_BIAS_2P5,
2537 	MIC_BIAS_2P6,
2538 	MIC_BIAS_2P7,
2539 };
2540 
2541 /* dl pga gain */
2542 enum {
2543 	DL_GAIN_8DB = 0,
2544 	DL_GAIN_0DB = 8,
2545 	DL_GAIN_N_1DB = 9,
2546 	DL_GAIN_N_10DB = 18,
2547 	DL_GAIN_N_22DB = 30,
2548 	DL_GAIN_N_40DB = 0x1f,
2549 };
2550 
2551 /* Mic Type MUX */
2552 enum {
2553 	MIC_TYPE_MUX_IDLE = 0,
2554 	MIC_TYPE_MUX_ACC,
2555 	MIC_TYPE_MUX_DMIC,
2556 	MIC_TYPE_MUX_DCC,
2557 	MIC_TYPE_MUX_DCC_ECM_DIFF,
2558 	MIC_TYPE_MUX_DCC_ECM_SINGLE,
2559 };
2560 
2561 /* UL SRC MUX */
2562 enum {
2563 	UL_SRC_MUX_AMIC = 0,
2564 	UL_SRC_MUX_DMIC,
2565 };
2566 
2567 /* MISO MUX */
2568 enum {
2569 	MISO_MUX_UL1_CH1 = 0,
2570 	MISO_MUX_UL1_CH2,
2571 	MISO_MUX_UL2_CH1,
2572 	MISO_MUX_UL2_CH2,
2573 };
2574 
2575 /* DMIC MUX */
2576 enum {
2577 	DMIC_MUX_DMIC_DATA0 = 0,
2578 	DMIC_MUX_DMIC_DATA1_L,
2579 	DMIC_MUX_DMIC_DATA1_L_1,
2580 	DMIC_MUX_DMIC_DATA1_R,
2581 };
2582 
2583 /* ADC L MUX */
2584 enum {
2585 	ADC_MUX_IDLE = 0,
2586 	ADC_MUX_AIN0,
2587 	ADC_MUX_PREAMPLIFIER,
2588 	ADC_MUX_IDLE1,
2589 };
2590 
2591 /* PGA L MUX */
2592 enum {
2593 	PGA_L_MUX_NONE = 0,
2594 	PGA_L_MUX_AIN0,
2595 	PGA_L_MUX_AIN1,
2596 };
2597 
2598 /* PGA R MUX */
2599 enum {
2600 	PGA_R_MUX_NONE = 0,
2601 	PGA_R_MUX_AIN2,
2602 	PGA_R_MUX_AIN3,
2603 	PGA_R_MUX_AIN0,
2604 };
2605 
2606 /* PGA 3 MUX */
2607 enum {
2608 	PGA_3_MUX_NONE = 0,
2609 	PGA_3_MUX_AIN3,
2610 	PGA_3_MUX_AIN2,
2611 };
2612 
2613 struct mt6359_priv {
2614 	struct device *dev;
2615 	struct regmap *regmap;
2616 	unsigned int dl_rate[MT6359_AIF_NUM];
2617 	unsigned int ul_rate[MT6359_AIF_NUM];
2618 	int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
2619 	unsigned int mux_select[MUX_NUM];
2620 	unsigned int dmic_one_wire_mode;
2621 	int dev_counter[DEVICE_NUM];
2622 	int hp_gain_ctl;
2623 	int hp_hifi_mode;
2624 	int mtkaif_protocol;
2625 };
2626 
2627 #define CODEC_MT6359_NAME "mtk-codec-mt6359"
2628 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
2629 			   (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
2630 			   (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
2631 
2632 void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
2633 				int mtkaif_protocol);
2634 void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);
2635 void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);
2636 void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
2637 					 int phase_1, int phase_2, int phase_3);
2638 
2639 #endif/* end _MT6359_H_ */
2640