1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet driver 4 // 5 // Copyright (C) 2021 MediaTek Inc. 6 // Author: Argus Lin <argus.lin@mediatek.com> 7 // 8 9 #include <linux/of_gpio.h> 10 #include <linux/of.h> 11 #include <linux/of_irq.h> 12 #include <linux/of_device.h> 13 #include <linux/of_address.h> 14 #include <linux/input.h> 15 #include <linux/kthread.h> 16 #include <linux/io.h> 17 #include <linux/sched/clock.h> 18 #include <linux/workqueue.h> 19 #include <linux/timer.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/init.h> 24 #include <linux/irqdomain.h> 25 #include <linux/irq.h> 26 #include <linux/regmap.h> 27 #include <sound/soc.h> 28 #include <sound/jack.h> 29 #include <linux/mfd/mt6397/core.h> 30 31 #include "mt6359-accdet.h" 32 #include "mt6359.h" 33 34 /* global variable definitions */ 35 #define REGISTER_VAL(x) ((x) - 1) 36 37 /* mt6359 accdet capability */ 38 #define ACCDET_PMIC_EINT_IRQ BIT(0) 39 #define ACCDET_AP_GPIO_EINT BIT(1) 40 41 #define ACCDET_PMIC_EINT0 BIT(2) 42 #define ACCDET_PMIC_EINT1 BIT(3) 43 #define ACCDET_PMIC_BI_EINT BIT(4) 44 45 #define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5) 46 #define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6) 47 #define ACCDET_PMIC_RSV_EINT BIT(7) 48 49 #define ACCDET_THREE_KEY BIT(8) 50 #define ACCDET_FOUR_KEY BIT(9) 51 #define ACCDET_TRI_KEY_CDD BIT(10) 52 #define ACCDET_RSV_KEY BIT(11) 53 54 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12) 55 #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13) 56 #define ACCDET_AD_FASTDISCHRAGE BIT(14) 57 58 static struct platform_driver mt6359_accdet_driver; 59 static const struct snd_soc_component_driver mt6359_accdet_soc_driver; 60 61 /* local function declaration */ 62 static void accdet_set_debounce(struct mt6359_accdet *priv, int state, 63 unsigned int debounce); 64 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv); 65 static void config_digital_init_by_mode(struct mt6359_accdet *priv); 66 static void config_eint_init_by_mode(struct mt6359_accdet *priv); 67 static inline void mt6359_accdet_init(struct mt6359_accdet *priv); 68 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv); 69 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv); 70 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv); 71 static void recover_eint_analog_setting(struct mt6359_accdet *priv); 72 static void recover_eint_digital_setting(struct mt6359_accdet *priv); 73 static void recover_eint_setting(struct mt6359_accdet *priv); 74 75 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv) 76 { 77 if (priv->data->eint_detect_mode == 0x3 || 78 priv->data->eint_detect_mode == 0x4) { 79 /* ESD switches off */ 80 regmap_update_bits(priv->regmap, 81 RG_ACCDETSPARE_ADDR, 1 << 8, 0); 82 } 83 if (priv->data->eint_detect_mode == 0x4) { 84 if (priv->caps & ACCDET_PMIC_EINT0) { 85 /* enable RG_EINT0CONFIGACCDET */ 86 regmap_update_bits(priv->regmap, 87 RG_EINT0CONFIGACCDET_ADDR, 88 RG_EINT0CONFIGACCDET_MASK_SFT, 89 BIT(RG_EINT0CONFIGACCDET_SFT)); 90 } else if (priv->caps & ACCDET_PMIC_EINT1) { 91 /* enable RG_EINT1CONFIGACCDET */ 92 regmap_update_bits(priv->regmap, 93 RG_EINT1CONFIGACCDET_ADDR, 94 RG_EINT1CONFIGACCDET_MASK_SFT, 95 BIT(RG_EINT1CONFIGACCDET_SFT)); 96 } 97 if (priv->data->eint_use_ext_res == 0x3 || 98 priv->data->eint_use_ext_res == 0x4) { 99 /*select 500k, use internal resistor */ 100 regmap_update_bits(priv->regmap, 101 RG_EINT0HIRENB_ADDR, 102 RG_EINT0HIRENB_MASK_SFT, 103 BIT(RG_EINT0HIRENB_SFT)); 104 } 105 } 106 return 0; 107 } 108 109 static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv) 110 { 111 if (priv->caps & ACCDET_PMIC_EINT0) { 112 /* disable inverter */ 113 regmap_update_bits(priv->regmap, 114 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 115 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0); 116 } else if (priv->caps & ACCDET_PMIC_EINT1) { 117 /* disable inverter */ 118 regmap_update_bits(priv->regmap, 119 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 120 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0); 121 } 122 123 if (priv->data->eint_detect_mode == 0x4) { 124 if (priv->caps & ACCDET_PMIC_EINT0) { 125 /* set DA stable signal */ 126 regmap_update_bits(priv->regmap, 127 ACCDET_DA_STABLE_ADDR, 128 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); 129 } else if (priv->caps & ACCDET_PMIC_EINT1) { 130 /* set DA stable signal */ 131 regmap_update_bits(priv->regmap, 132 ACCDET_DA_STABLE_ADDR, 133 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0); 134 } 135 } 136 return 0; 137 } 138 139 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv) 140 { 141 if (priv->jd_sts == M_PLUG_IN) { 142 /* adjust digital setting */ 143 adjust_eint_digital_setting(priv); 144 /* adjust analog setting */ 145 adjust_eint_analog_setting(priv); 146 } else if (priv->jd_sts == M_PLUG_OUT) { 147 /* set debounce to 1ms */ 148 accdet_set_debounce(priv, eint_state000, 149 priv->data->pwm_deb->eint_debounce0); 150 } else { 151 dev_dbg(priv->dev, "should not be here %s()\n", __func__); 152 } 153 154 return 0; 155 } 156 157 static void recover_eint_analog_setting(struct mt6359_accdet *priv) 158 { 159 if (priv->data->eint_detect_mode == 0x3 || 160 priv->data->eint_detect_mode == 0x4) { 161 /* ESD switches on */ 162 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 163 1 << 8, 1 << 8); 164 } 165 if (priv->data->eint_detect_mode == 0x4) { 166 if (priv->caps & ACCDET_PMIC_EINT0) { 167 /* disable RG_EINT0CONFIGACCDET */ 168 regmap_update_bits(priv->regmap, 169 RG_EINT0CONFIGACCDET_ADDR, 170 RG_EINT0CONFIGACCDET_MASK_SFT, 0); 171 } else if (priv->caps & ACCDET_PMIC_EINT1) { 172 /* disable RG_EINT1CONFIGACCDET */ 173 regmap_update_bits(priv->regmap, 174 RG_EINT1CONFIGACCDET_ADDR, 175 RG_EINT1CONFIGACCDET_MASK_SFT, 0); 176 } 177 regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, 178 RG_EINT0HIRENB_MASK_SFT, 0); 179 } 180 } 181 182 static void recover_eint_digital_setting(struct mt6359_accdet *priv) 183 { 184 if (priv->caps & ACCDET_PMIC_EINT0) { 185 regmap_update_bits(priv->regmap, 186 ACCDET_EINT0_M_SW_EN_ADDR, 187 ACCDET_EINT0_M_SW_EN_MASK_SFT, 0); 188 } else if (priv->caps & ACCDET_PMIC_EINT1) { 189 regmap_update_bits(priv->regmap, 190 ACCDET_EINT1_M_SW_EN_ADDR, 191 ACCDET_EINT1_M_SW_EN_MASK_SFT, 0); 192 } 193 if (priv->data->eint_detect_mode == 0x4) { 194 /* enable eint0cen */ 195 if (priv->caps & ACCDET_PMIC_EINT0) { 196 /* enable eint0cen */ 197 regmap_update_bits(priv->regmap, 198 ACCDET_DA_STABLE_ADDR, 199 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 200 BIT(ACCDET_EINT0_CEN_STABLE_SFT)); 201 } else if (priv->caps & ACCDET_PMIC_EINT1) { 202 /* enable eint1cen */ 203 regmap_update_bits(priv->regmap, 204 ACCDET_DA_STABLE_ADDR, 205 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 206 BIT(ACCDET_EINT1_CEN_STABLE_SFT)); 207 } 208 } 209 210 if (priv->data->eint_detect_mode != 0x1) { 211 if (priv->caps & ACCDET_PMIC_EINT0) { 212 /* enable inverter */ 213 regmap_update_bits(priv->regmap, 214 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 215 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 216 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); 217 } else if (priv->caps & ACCDET_PMIC_EINT1) { 218 /* enable inverter */ 219 regmap_update_bits(priv->regmap, 220 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 221 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 222 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); 223 } 224 } 225 } 226 227 static void recover_eint_setting(struct mt6359_accdet *priv) 228 { 229 if (priv->jd_sts == M_PLUG_OUT) { 230 recover_eint_analog_setting(priv); 231 recover_eint_digital_setting(priv); 232 } 233 } 234 235 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv) 236 { 237 int ret = 0; 238 unsigned int value = 0; 239 240 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 241 ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT)); 242 usleep_range(200, 300); 243 ret = regmap_read_poll_timeout(priv->regmap, 244 ACCDET_IRQ_ADDR, 245 value, 246 (value & ACCDET_IRQ_MASK_SFT) == 0, 247 0, 248 1000); 249 if (ret) 250 dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret); 251 /* clear accdet int, modify for fix interrupt trigger twice error */ 252 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 253 ACCDET_IRQ_CLR_MASK_SFT, 0); 254 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR, 255 RG_INT_STATUS_ACCDET_MASK_SFT, 256 BIT(RG_INT_STATUS_ACCDET_SFT)); 257 258 /* recover accdet debounce0,3 */ 259 accdet_set_debounce(priv, accdet_state000, 260 priv->data->pwm_deb->debounce0); 261 accdet_set_debounce(priv, accdet_state001, 262 priv->data->pwm_deb->debounce1); 263 accdet_set_debounce(priv, accdet_state011, 264 priv->data->pwm_deb->debounce3); 265 266 priv->jack_type = 0; 267 priv->btn_type = 0; 268 priv->accdet_status = 0x3; 269 mt6359_accdet_jack_report(priv); 270 } 271 272 static void accdet_set_debounce(struct mt6359_accdet *priv, int state, 273 unsigned int debounce) 274 { 275 switch (state) { 276 case accdet_state000: 277 regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce); 278 break; 279 case accdet_state001: 280 regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce); 281 break; 282 case accdet_state010: 283 regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce); 284 break; 285 case accdet_state011: 286 regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce); 287 break; 288 case accdet_auxadc: 289 regmap_write(priv->regmap, 290 ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce); 291 break; 292 case eint_state000: 293 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR, 294 0xF << ACCDET_EINT_DEBOUNCE0_SFT, 295 debounce << ACCDET_EINT_DEBOUNCE0_SFT); 296 break; 297 case eint_state001: 298 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR, 299 0xF << ACCDET_EINT_DEBOUNCE1_SFT, 300 debounce << ACCDET_EINT_DEBOUNCE1_SFT); 301 break; 302 case eint_state010: 303 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR, 304 0xF << ACCDET_EINT_DEBOUNCE2_SFT, 305 debounce << ACCDET_EINT_DEBOUNCE2_SFT); 306 break; 307 case eint_state011: 308 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR, 309 0xF << ACCDET_EINT_DEBOUNCE3_SFT, 310 debounce << ACCDET_EINT_DEBOUNCE3_SFT); 311 break; 312 case eint_inverter_state000: 313 regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR, 314 debounce); 315 break; 316 default: 317 dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__, 318 state); 319 break; 320 } 321 } 322 323 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv) 324 { 325 int report = 0; 326 327 if (!priv->jack) 328 return; 329 330 report = priv->jack_type | priv->btn_type; 331 snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK); 332 } 333 334 static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v) 335 { 336 if (priv->caps & ACCDET_FOUR_KEY) { 337 if (v < priv->data->four_key.down && 338 v >= priv->data->four_key.up) 339 priv->btn_type = SND_JACK_BTN_1; 340 if (v < priv->data->four_key.up && 341 v >= priv->data->four_key.voice) 342 priv->btn_type = SND_JACK_BTN_2; 343 if (v < priv->data->four_key.voice && 344 v >= priv->data->four_key.mid) 345 priv->btn_type = SND_JACK_BTN_3; 346 if (v < priv->data->four_key.mid) 347 priv->btn_type = SND_JACK_BTN_0; 348 } else { 349 if (v < priv->data->three_key.down && 350 v >= priv->data->three_key.up) 351 priv->btn_type = SND_JACK_BTN_1; 352 if (v < priv->data->three_key.up && 353 v >= priv->data->three_key.mid) 354 priv->btn_type = SND_JACK_BTN_2; 355 if (v < priv->data->three_key.mid) 356 priv->btn_type = SND_JACK_BTN_0; 357 } 358 return 0; 359 } 360 361 static void is_key_pressed(struct mt6359_accdet *priv, bool pressed) 362 { 363 priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK; 364 365 if (pressed) 366 check_button(priv, priv->cali_voltage); 367 } 368 369 static inline void check_jack_btn_type(struct mt6359_accdet *priv) 370 { 371 unsigned int val = 0; 372 373 regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val); 374 375 priv->accdet_status = 376 (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK; 377 378 switch (priv->accdet_status) { 379 case 0: 380 if (priv->jack_type == SND_JACK_HEADSET) 381 is_key_pressed(priv, true); 382 else 383 priv->jack_type = SND_JACK_HEADPHONE; 384 break; 385 case 1: 386 if (priv->jack_type == SND_JACK_HEADSET) { 387 is_key_pressed(priv, false); 388 } else { 389 priv->jack_type = SND_JACK_HEADSET; 390 accdet_set_debounce(priv, eint_state011, 0x1); 391 } 392 break; 393 case 3: 394 default: 395 priv->jack_type = 0; 396 break; 397 } 398 } 399 400 static void mt6359_accdet_work(struct work_struct *work) 401 { 402 struct mt6359_accdet *priv = 403 container_of(work, struct mt6359_accdet, accdet_work); 404 405 mutex_lock(&priv->res_lock); 406 priv->pre_accdet_status = priv->accdet_status; 407 check_jack_btn_type(priv); 408 409 if (priv->jack_plugged && 410 priv->pre_accdet_status != priv->accdet_status) 411 mt6359_accdet_jack_report(priv); 412 mutex_unlock(&priv->res_lock); 413 } 414 415 static void mt6359_accdet_jd_work(struct work_struct *work) 416 { 417 int ret = 0; 418 unsigned int value = 0; 419 420 struct mt6359_accdet *priv = 421 container_of(work, struct mt6359_accdet, jd_work); 422 423 mutex_lock(&priv->res_lock); 424 if (priv->jd_sts == M_PLUG_IN) { 425 priv->jack_plugged = true; 426 427 /* set and clear initial bit every eint interrupt */ 428 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 429 ACCDET_SEQ_INIT_MASK_SFT, 430 BIT(ACCDET_SEQ_INIT_SFT)); 431 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 432 ACCDET_SEQ_INIT_MASK_SFT, 0); 433 ret = regmap_read_poll_timeout(priv->regmap, 434 ACCDET_SEQ_INIT_ADDR, 435 value, 436 (value & ACCDET_SEQ_INIT_MASK_SFT) == 0, 437 0, 438 1000); 439 if (ret) 440 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret); 441 442 /* enable ACCDET unit */ 443 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR, 444 ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT)); 445 } else if (priv->jd_sts == M_PLUG_OUT) { 446 priv->jack_plugged = false; 447 448 accdet_set_debounce(priv, accdet_state011, 449 priv->data->pwm_deb->debounce3); 450 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR, 451 ACCDET_SW_EN_MASK_SFT, 0); 452 mt6359_accdet_recover_jd_setting(priv); 453 } 454 455 if (priv->caps & ACCDET_PMIC_EINT_IRQ) 456 recover_eint_setting(priv); 457 mutex_unlock(&priv->res_lock); 458 } 459 460 static irqreturn_t mt6359_accdet_irq(int irq, void *data) 461 { 462 struct mt6359_accdet *priv = data; 463 unsigned int irq_val = 0, val = 0, value = 0; 464 int ret = 0; 465 466 mutex_lock(&priv->res_lock); 467 regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val); 468 469 if (irq_val & ACCDET_IRQ_MASK_SFT) { 470 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 471 ACCDET_IRQ_CLR_MASK_SFT, 472 BIT(ACCDET_IRQ_CLR_SFT)); 473 ret = regmap_read_poll_timeout(priv->regmap, 474 ACCDET_IRQ_ADDR, 475 value, 476 (value & ACCDET_IRQ_MASK_SFT) == 0, 477 0, 478 1000); 479 if (ret) { 480 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret); 481 mutex_unlock(&priv->res_lock); 482 return IRQ_NONE; 483 } 484 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 485 ACCDET_IRQ_CLR_MASK_SFT, 0); 486 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR, 487 RG_INT_STATUS_ACCDET_MASK_SFT, 488 BIT(RG_INT_STATUS_ACCDET_SFT)); 489 490 queue_work(priv->accdet_workqueue, &priv->accdet_work); 491 } else { 492 if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) { 493 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 494 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 495 BIT(ACCDET_EINT0_IRQ_CLR_SFT)); 496 ret = regmap_read_poll_timeout(priv->regmap, 497 ACCDET_IRQ_ADDR, 498 value, 499 (value & ACCDET_EINT0_IRQ_MASK_SFT) == 0, 500 0, 501 1000); 502 if (ret) { 503 dev_err(priv->dev, "%s(), ret %d\n", __func__, 504 ret); 505 mutex_unlock(&priv->res_lock); 506 return IRQ_NONE; 507 } 508 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 509 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0); 510 regmap_update_bits(priv->regmap, 511 RG_INT_STATUS_ACCDET_ADDR, 512 RG_INT_STATUS_ACCDET_EINT0_MASK_SFT, 513 BIT(RG_INT_STATUS_ACCDET_EINT0_SFT)); 514 } 515 if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) { 516 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 517 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 518 BIT(ACCDET_EINT1_IRQ_CLR_SFT)); 519 ret = regmap_read_poll_timeout(priv->regmap, 520 ACCDET_IRQ_ADDR, 521 value, 522 (value & ACCDET_EINT1_IRQ_MASK_SFT) == 0, 523 0, 524 1000); 525 if (ret) { 526 dev_err(priv->dev, "%s(), ret %d\n", __func__, 527 ret); 528 mutex_unlock(&priv->res_lock); 529 return IRQ_NONE; 530 } 531 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 532 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0); 533 regmap_update_bits(priv->regmap, 534 RG_INT_STATUS_ACCDET_ADDR, 535 RG_INT_STATUS_ACCDET_EINT1_MASK_SFT, 536 BIT(RG_INT_STATUS_ACCDET_EINT1_SFT)); 537 } 538 /* get jack detection status */ 539 regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val); 540 priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) & 541 ACCDET_EINT0_MEM_IN_MASK); 542 /* adjust eint digital/analog setting */ 543 mt6359_accdet_jd_setting(priv); 544 545 queue_work(priv->jd_workqueue, &priv->jd_work); 546 } 547 mutex_unlock(&priv->res_lock); 548 549 return IRQ_HANDLED; 550 } 551 552 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) 553 { 554 int ret = 0; 555 struct device *dev = priv->dev; 556 struct device_node *node = NULL; 557 int pwm_deb[15] = {0}; 558 unsigned int tmp = 0; 559 560 node = of_get_child_by_name(dev->parent->of_node, "accdet"); 561 if (!node) 562 return -EINVAL; 563 564 ret = of_property_read_u32(node, "mediatek,mic-vol", 565 &priv->data->mic_vol); 566 if (ret) 567 priv->data->mic_vol = 8; 568 569 ret = of_property_read_u32(node, "mediatek,plugout-debounce", 570 &priv->data->plugout_deb); 571 if (ret) 572 priv->data->plugout_deb = 1; 573 574 ret = of_property_read_u32(node, "mediatek,mic-mode", 575 &priv->data->mic_mode); 576 if (ret) 577 priv->data->mic_mode = 2; 578 579 ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting", 580 pwm_deb, ARRAY_SIZE(pwm_deb)); 581 /* debounce8(auxadc debounce) is default, needn't get from dts */ 582 if (!ret) 583 memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb)); 584 585 ret = of_property_read_u32(node, "mediatek,eint-level-pol", 586 &priv->data->eint_pol); 587 if (ret) 588 priv->data->eint_pol = 8; 589 590 ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp); 591 if (ret) 592 tmp = 0; 593 if (tmp == 0) 594 priv->caps |= ACCDET_PMIC_EINT_IRQ; 595 else if (tmp == 1) 596 priv->caps |= ACCDET_AP_GPIO_EINT; 597 598 ret = of_property_read_u32(node, "mediatek,eint-detect-mode", 599 &priv->data->eint_detect_mode); 600 if (ret) { 601 /* eint detection mode equals to EINT HW Mode */ 602 priv->data->eint_detect_mode = 0x4; 603 } 604 605 ret = of_property_read_u32(node, "mediatek,eint-num", &tmp); 606 if (ret) 607 tmp = 0; 608 if (tmp == 0) 609 priv->caps |= ACCDET_PMIC_EINT0; 610 else if (tmp == 1) 611 priv->caps |= ACCDET_PMIC_EINT1; 612 else if (tmp == 2) 613 priv->caps |= ACCDET_PMIC_BI_EINT; 614 615 ret = of_property_read_u32(node, "mediatek,eint-trig-mode", 616 &tmp); 617 if (ret) 618 tmp = 0; 619 if (tmp == 0) 620 priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT; 621 else if (tmp == 1) 622 priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT; 623 624 ret = of_property_read_u32(node, "mediatek,eint-use-ext-res", 625 &priv->data->eint_use_ext_res); 626 if (ret) { 627 /* eint use internal resister */ 628 priv->data->eint_use_ext_res = 0x0; 629 } 630 631 ret = of_property_read_u32(node, "mediatek,eint-comp-vth", 632 &priv->data->eint_comp_vth); 633 if (ret) 634 priv->data->eint_comp_vth = 0x0; 635 636 ret = of_property_read_u32(node, "mediatek,key-mode", &tmp); 637 if (ret) 638 tmp = 0; 639 if (tmp == 0) { 640 int three_key[4]; 641 642 priv->caps |= ACCDET_THREE_KEY; 643 ret = of_property_read_u32_array(node, 644 "mediatek,three-key-thr", 645 three_key, 646 ARRAY_SIZE(three_key)); 647 if (!ret) 648 memcpy(&priv->data->three_key, three_key + 1, 649 sizeof(struct three_key_threshold)); 650 } else if (tmp == 1) { 651 int four_key[5]; 652 653 priv->caps |= ACCDET_FOUR_KEY; 654 ret = of_property_read_u32_array(node, 655 "mediatek,four-key-thr", 656 four_key, 657 ARRAY_SIZE(four_key)); 658 if (!ret) { 659 memcpy(&priv->data->four_key, four_key + 1, 660 sizeof(struct four_key_threshold)); 661 } else { 662 dev_warn(priv->dev, 663 "accdet no 4-key-thrsh dts, use efuse\n"); 664 } 665 } else if (tmp == 2) { 666 int three_key[4]; 667 668 priv->caps |= ACCDET_TRI_KEY_CDD; 669 ret = of_property_read_u32_array(node, 670 "mediatek,tri-key-cdd-thr", 671 three_key, 672 ARRAY_SIZE(three_key)); 673 if (!ret) 674 memcpy(&priv->data->three_key, three_key + 1, 675 sizeof(struct three_key_threshold)); 676 } 677 678 dev_warn(priv->dev, "accdet caps=%x\n", priv->caps); 679 680 return 0; 681 } 682 683 static void config_digital_init_by_mode(struct mt6359_accdet *priv) 684 { 685 /* enable eint cmpmem pwm */ 686 regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR, 687 (priv->data->pwm_deb->eint_pwm_width << 4 | 688 priv->data->pwm_deb->eint_pwm_thresh)); 689 /* DA signal stable */ 690 if (priv->caps & ACCDET_PMIC_EINT0) { 691 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, 692 ACCDET_EINT0_STABLE_VAL); 693 } else if (priv->caps & ACCDET_PMIC_EINT1) { 694 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, 695 ACCDET_EINT1_STABLE_VAL); 696 } 697 /* after receive n+1 number, interrupt issued. */ 698 regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR, 699 ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT, 700 BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT)); 701 /* setting HW mode, enable digital fast discharge 702 * if use EINT0 & EINT1 detection, please modify 703 * ACCDET_HWMODE_EN_ADDR[2:1] 704 */ 705 regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100); 706 707 regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR, 708 ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0); 709 710 /* enable PWM */ 711 regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67); 712 /* enable inverter detection */ 713 if (priv->data->eint_detect_mode == 0x1) { 714 /* disable inverter detection */ 715 if (priv->caps & ACCDET_PMIC_EINT0) { 716 regmap_update_bits(priv->regmap, 717 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 718 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 719 0); 720 } else if (priv->caps & ACCDET_PMIC_EINT1) { 721 regmap_update_bits(priv->regmap, 722 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 723 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 724 0); 725 } 726 } else { 727 if (priv->caps & ACCDET_PMIC_EINT0) { 728 regmap_update_bits(priv->regmap, 729 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 730 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 731 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); 732 } else if (priv->caps & ACCDET_PMIC_EINT1) { 733 regmap_update_bits(priv->regmap, 734 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 735 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 736 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); 737 } 738 } 739 } 740 741 static void config_eint_init_by_mode(struct mt6359_accdet *priv) 742 { 743 unsigned int val = 0; 744 745 if (priv->caps & ACCDET_PMIC_EINT0) { 746 regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR, 747 RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT)); 748 } else if (priv->caps & ACCDET_PMIC_EINT1) { 749 regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR, 750 RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT)); 751 } 752 /* ESD switches on */ 753 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 754 1 << 8, 1 << 8); 755 /* before playback, set NCP pull low before nagative voltage */ 756 regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR, 757 RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT)); 758 759 if (priv->data->eint_detect_mode == 0x1 || 760 priv->data->eint_detect_mode == 0x2 || 761 priv->data->eint_detect_mode == 0x3) { 762 if (priv->data->eint_use_ext_res == 0x1) { 763 if (priv->caps & ACCDET_PMIC_EINT0) { 764 regmap_update_bits(priv->regmap, 765 RG_EINT0CONFIGACCDET_ADDR, 766 RG_EINT0CONFIGACCDET_MASK_SFT, 767 0); 768 } else if (priv->caps & ACCDET_PMIC_EINT1) { 769 regmap_update_bits(priv->regmap, 770 RG_EINT1CONFIGACCDET_ADDR, 771 RG_EINT1CONFIGACCDET_MASK_SFT, 772 0); 773 } 774 } else { 775 if (priv->caps & ACCDET_PMIC_EINT0) { 776 regmap_update_bits(priv->regmap, 777 RG_EINT0CONFIGACCDET_ADDR, 778 RG_EINT0CONFIGACCDET_MASK_SFT, 779 BIT(RG_EINT0CONFIGACCDET_SFT)); 780 } else if (priv->caps & ACCDET_PMIC_EINT1) { 781 regmap_update_bits(priv->regmap, 782 RG_EINT1CONFIGACCDET_ADDR, 783 RG_EINT1CONFIGACCDET_MASK_SFT, 784 BIT(RG_EINT1CONFIGACCDET_SFT)); 785 } 786 } 787 } 788 789 if (priv->data->eint_detect_mode != 0x1) { 790 /* current detect set 0.25uA */ 791 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 792 0x3 << RG_ACCDETSPARE_SFT, 793 0x3 << RG_ACCDETSPARE_SFT); 794 } 795 regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR, 796 val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT); 797 } 798 799 static void mt6359_accdet_init(struct mt6359_accdet *priv) 800 { 801 unsigned int reg = 0; 802 803 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 804 ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT)); 805 mdelay(2); 806 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 807 ACCDET_SEQ_INIT_MASK_SFT, 0); 808 mdelay(1); 809 /* init the debounce time (debounce/32768)sec */ 810 accdet_set_debounce(priv, accdet_state000, 811 priv->data->pwm_deb->debounce0); 812 accdet_set_debounce(priv, accdet_state001, 813 priv->data->pwm_deb->debounce1); 814 accdet_set_debounce(priv, accdet_state011, 815 priv->data->pwm_deb->debounce3); 816 accdet_set_debounce(priv, accdet_auxadc, 817 priv->data->pwm_deb->debounce4); 818 819 accdet_set_debounce(priv, eint_state000, 820 priv->data->pwm_deb->eint_debounce0); 821 accdet_set_debounce(priv, eint_state001, 822 priv->data->pwm_deb->eint_debounce1); 823 accdet_set_debounce(priv, eint_state011, 824 priv->data->pwm_deb->eint_debounce3); 825 accdet_set_debounce(priv, eint_inverter_state000, 826 priv->data->pwm_deb->eint_inverter_debounce); 827 828 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR, 829 RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT)); 830 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR, 831 RG_ACCDET_RST_MASK_SFT, 0); 832 833 /* clear high micbias1 voltage setting */ 834 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 835 0x3 << RG_AUDMICBIAS1HVEN_SFT, 0); 836 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 837 0x7 << RG_AUDMICBIAS1VREF_SFT, 0); 838 839 /* init pwm frequency, duty & rise/falling delay */ 840 regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR, 841 REGISTER_VAL(priv->data->pwm_deb->pwm_width)); 842 regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR, 843 REGISTER_VAL(priv->data->pwm_deb->pwm_thresh)); 844 regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR, 845 (priv->data->pwm_deb->fall_delay << 15 | 846 priv->data->pwm_deb->rise_delay)); 847 848 regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®); 849 if (priv->data->mic_vol <= 7) { 850 /* micbias1 <= 2.7V */ 851 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 852 reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) | 853 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 854 } else if (priv->data->mic_vol == 8) { 855 /* micbias1 = 2.8v */ 856 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 857 reg | (3 << RG_AUDMICBIAS1HVEN_SFT) | 858 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 859 } else if (priv->data->mic_vol == 9) { 860 /* micbias1 = 2.85v */ 861 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 862 reg | (1 << RG_AUDMICBIAS1HVEN_SFT) | 863 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 864 } 865 /* mic mode setting */ 866 regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®); 867 if (priv->data->mic_mode == HEADSET_MODE_1) { 868 /* ACC mode*/ 869 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 870 reg | RG_ACCDET_MODE_ANA11_MODE1); 871 /* enable analog fast discharge */ 872 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 873 RG_ANALOGFDEN_MASK_SFT, 874 BIT(RG_ANALOGFDEN_SFT)); 875 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 876 0x3 << 11, 0x3 << 11); 877 } else if (priv->data->mic_mode == HEADSET_MODE_2) { 878 /* DCC mode Low cost mode without internal bias */ 879 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 880 reg | RG_ACCDET_MODE_ANA11_MODE2); 881 /* enable analog fast discharge */ 882 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 883 0x3 << RG_ANALOGFDEN_SFT, 884 0x3 << RG_ANALOGFDEN_SFT); 885 } else if (priv->data->mic_mode == HEADSET_MODE_6) { 886 /* DCC mode Low cost mode with internal bias, 887 * bit8 = 1 to use internal bias 888 */ 889 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 890 reg | RG_ACCDET_MODE_ANA11_MODE6); 891 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 892 RG_AUDMICBIAS1DCSW1PEN_MASK_SFT, 893 BIT(RG_AUDMICBIAS1DCSW1PEN_SFT)); 894 /* enable analog fast discharge */ 895 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 896 0x3 << RG_ANALOGFDEN_SFT, 897 0x3 << RG_ANALOGFDEN_SFT); 898 } 899 900 if (priv->caps & ACCDET_PMIC_EINT_IRQ) { 901 config_eint_init_by_mode(priv); 902 config_digital_init_by_mode(priv); 903 } 904 } 905 906 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component, 907 struct snd_soc_jack *jack) 908 { 909 struct mt6359_accdet *priv = 910 snd_soc_component_get_drvdata(component); 911 912 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 913 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN); 914 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP); 915 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND); 916 917 priv->jack = jack; 918 919 mt6359_accdet_jack_report(priv); 920 921 return 0; 922 } 923 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect); 924 925 static int mt6359_accdet_probe(struct platform_device *pdev) 926 { 927 struct mt6359_accdet *priv; 928 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 929 int ret = 0; 930 931 dev_dbg(&pdev->dev, "%s(), dev name %s\n", 932 __func__, dev_name(&pdev->dev)); 933 934 priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet), 935 GFP_KERNEL); 936 if (!priv) 937 return -ENOMEM; 938 939 priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data), 940 GFP_KERNEL); 941 if (!priv->data) 942 return -ENOMEM; 943 944 priv->data->pwm_deb = devm_kzalloc(&pdev->dev, 945 sizeof(struct pwm_deb_settings), 946 GFP_KERNEL); 947 if (!priv->data->pwm_deb) 948 return -ENOMEM; 949 950 priv->regmap = mt6397->regmap; 951 if (IS_ERR(priv->regmap)) { 952 ret = PTR_ERR(priv->regmap); 953 dev_err(&pdev->dev, "Failed to allocate register map: %d\n", 954 ret); 955 return ret; 956 } 957 priv->dev = &pdev->dev; 958 959 ret = mt6359_accdet_parse_dt(priv); 960 if (ret) { 961 dev_err(&pdev->dev, "Failed to parse dts\n"); 962 return ret; 963 } 964 mutex_init(&priv->res_lock); 965 966 priv->accdet_irq = platform_get_irq(pdev, 0); 967 if (priv->accdet_irq) { 968 ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq, 969 NULL, mt6359_accdet_irq, 970 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 971 "ACCDET_IRQ", priv); 972 if (ret) { 973 dev_err(&pdev->dev, 974 "Failed to request IRQ: (%d)\n", ret); 975 return ret; 976 } 977 } 978 979 if (priv->caps & ACCDET_PMIC_EINT0) { 980 priv->accdet_eint0 = platform_get_irq(pdev, 1); 981 if (priv->accdet_eint0) { 982 ret = devm_request_threaded_irq(&pdev->dev, 983 priv->accdet_eint0, 984 NULL, mt6359_accdet_irq, 985 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 986 "ACCDET_EINT0", priv); 987 if (ret) { 988 dev_err(&pdev->dev, 989 "Failed to request eint0 IRQ (%d)\n", 990 ret); 991 return ret; 992 } 993 } 994 } else if (priv->caps & ACCDET_PMIC_EINT1) { 995 priv->accdet_eint1 = platform_get_irq(pdev, 2); 996 if (priv->accdet_eint1) { 997 ret = devm_request_threaded_irq(&pdev->dev, 998 priv->accdet_eint1, 999 NULL, mt6359_accdet_irq, 1000 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1001 "ACCDET_EINT1", priv); 1002 if (ret) { 1003 dev_err(&pdev->dev, 1004 "Failed to request eint1 IRQ (%d)\n", 1005 ret); 1006 return ret; 1007 } 1008 } 1009 } 1010 1011 priv->accdet_workqueue = create_singlethread_workqueue("accdet"); 1012 INIT_WORK(&priv->accdet_work, mt6359_accdet_work); 1013 if (!priv->accdet_workqueue) { 1014 dev_err(&pdev->dev, "Failed to create accdet workqueue\n"); 1015 ret = -1; 1016 goto err_accdet_wq; 1017 } 1018 1019 priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd"); 1020 INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work); 1021 if (!priv->jd_workqueue) { 1022 dev_err(&pdev->dev, "Failed to create jack detect workqueue\n"); 1023 ret = -1; 1024 goto err_eint_wq; 1025 } 1026 1027 platform_set_drvdata(pdev, priv); 1028 ret = devm_snd_soc_register_component(&pdev->dev, 1029 &mt6359_accdet_soc_driver, 1030 NULL, 0); 1031 if (ret) { 1032 dev_err(&pdev->dev, "Failed to register component\n"); 1033 return ret; 1034 } 1035 1036 priv->jd_sts = M_PLUG_OUT; 1037 priv->jack_type = 0; 1038 priv->btn_type = 0; 1039 priv->accdet_status = 0x3; 1040 mt6359_accdet_init(priv); 1041 1042 mt6359_accdet_jack_report(priv); 1043 1044 return 0; 1045 1046 err_eint_wq: 1047 destroy_workqueue(priv->accdet_workqueue); 1048 err_accdet_wq: 1049 dev_err(&pdev->dev, "%s error. now exit.!\n", __func__); 1050 return ret; 1051 } 1052 1053 static struct platform_driver mt6359_accdet_driver = { 1054 .driver = { 1055 .name = "pmic-codec-accdet", 1056 }, 1057 .probe = mt6359_accdet_probe, 1058 }; 1059 1060 static int __init mt6359_accdet_driver_init(void) 1061 { 1062 int ret = 0; 1063 1064 ret = platform_driver_register(&mt6359_accdet_driver); 1065 if (ret) 1066 return -ENODEV; 1067 return 0; 1068 } 1069 1070 static void __exit mt6359_accdet_driver_exit(void) 1071 { 1072 platform_driver_unregister(&mt6359_accdet_driver); 1073 } 1074 module_init(mt6359_accdet_driver_init); 1075 module_exit(mt6359_accdet_driver_exit); 1076 1077 /* Module information */ 1078 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver"); 1079 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>"); 1080 MODULE_LICENSE("GPL v2"); 1081