1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet driver
4 //
5 // Copyright (C) 2021 MediaTek Inc.
6 // Author: Argus Lin <argus.lin@mediatek.com>
7 //
8
9 #include <linux/of_gpio.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/input.h>
15 #include <linux/kthread.h>
16 #include <linux/io.h>
17 #include <linux/sched/clock.h>
18 #include <linux/workqueue.h>
19 #include <linux/timer.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/init.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/regmap.h>
27 #include <sound/soc.h>
28 #include <sound/jack.h>
29 #include <linux/mfd/mt6397/core.h>
30
31 #include "mt6359-accdet.h"
32 #include "mt6359.h"
33
34 /* global variable definitions */
35 #define REGISTER_VAL(x) ((x) - 1)
36
37 /* mt6359 accdet capability */
38 #define ACCDET_PMIC_EINT_IRQ BIT(0)
39 #define ACCDET_AP_GPIO_EINT BIT(1)
40
41 #define ACCDET_PMIC_EINT0 BIT(2)
42 #define ACCDET_PMIC_EINT1 BIT(3)
43 #define ACCDET_PMIC_BI_EINT BIT(4)
44
45 #define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5)
46 #define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6)
47 #define ACCDET_PMIC_RSV_EINT BIT(7)
48
49 #define ACCDET_THREE_KEY BIT(8)
50 #define ACCDET_FOUR_KEY BIT(9)
51 #define ACCDET_TRI_KEY_CDD BIT(10)
52 #define ACCDET_RSV_KEY BIT(11)
53
54 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12)
55 #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13)
56 #define ACCDET_AD_FASTDISCHRAGE BIT(14)
57
58 static struct platform_driver mt6359_accdet_driver;
59 static const struct snd_soc_component_driver mt6359_accdet_soc_driver;
60
61 /* local function declaration */
62 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
63 unsigned int debounce);
64 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv);
65 static void config_digital_init_by_mode(struct mt6359_accdet *priv);
66 static void config_eint_init_by_mode(struct mt6359_accdet *priv);
67 static inline void mt6359_accdet_init(struct mt6359_accdet *priv);
68 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv);
69 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv);
70 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv);
71 static void recover_eint_analog_setting(struct mt6359_accdet *priv);
72 static void recover_eint_digital_setting(struct mt6359_accdet *priv);
73 static void recover_eint_setting(struct mt6359_accdet *priv);
74
adjust_eint_analog_setting(struct mt6359_accdet * priv)75 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv)
76 {
77 if (priv->data->eint_detect_mode == 0x3 ||
78 priv->data->eint_detect_mode == 0x4) {
79 /* ESD switches off */
80 regmap_update_bits(priv->regmap,
81 RG_ACCDETSPARE_ADDR, 1 << 8, 0);
82 }
83 if (priv->data->eint_detect_mode == 0x4) {
84 if (priv->caps & ACCDET_PMIC_EINT0) {
85 /* enable RG_EINT0CONFIGACCDET */
86 regmap_update_bits(priv->regmap,
87 RG_EINT0CONFIGACCDET_ADDR,
88 RG_EINT0CONFIGACCDET_MASK_SFT,
89 BIT(RG_EINT0CONFIGACCDET_SFT));
90 } else if (priv->caps & ACCDET_PMIC_EINT1) {
91 /* enable RG_EINT1CONFIGACCDET */
92 regmap_update_bits(priv->regmap,
93 RG_EINT1CONFIGACCDET_ADDR,
94 RG_EINT1CONFIGACCDET_MASK_SFT,
95 BIT(RG_EINT1CONFIGACCDET_SFT));
96 }
97 if (priv->data->eint_use_ext_res == 0x3 ||
98 priv->data->eint_use_ext_res == 0x4) {
99 /*select 500k, use internal resistor */
100 regmap_update_bits(priv->regmap,
101 RG_EINT0HIRENB_ADDR,
102 RG_EINT0HIRENB_MASK_SFT,
103 BIT(RG_EINT0HIRENB_SFT));
104 }
105 }
106 return 0;
107 }
108
adjust_eint_digital_setting(struct mt6359_accdet * priv)109 static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv)
110 {
111 if (priv->caps & ACCDET_PMIC_EINT0) {
112 /* disable inverter */
113 regmap_update_bits(priv->regmap,
114 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
115 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0);
116 } else if (priv->caps & ACCDET_PMIC_EINT1) {
117 /* disable inverter */
118 regmap_update_bits(priv->regmap,
119 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
120 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0);
121 }
122
123 if (priv->data->eint_detect_mode == 0x4) {
124 if (priv->caps & ACCDET_PMIC_EINT0) {
125 /* set DA stable signal */
126 regmap_update_bits(priv->regmap,
127 ACCDET_DA_STABLE_ADDR,
128 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0);
129 } else if (priv->caps & ACCDET_PMIC_EINT1) {
130 /* set DA stable signal */
131 regmap_update_bits(priv->regmap,
132 ACCDET_DA_STABLE_ADDR,
133 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0);
134 }
135 }
136 return 0;
137 }
138
mt6359_accdet_jd_setting(struct mt6359_accdet * priv)139 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv)
140 {
141 if (priv->jd_sts == M_PLUG_IN) {
142 /* adjust digital setting */
143 adjust_eint_digital_setting(priv);
144 /* adjust analog setting */
145 adjust_eint_analog_setting(priv);
146 } else if (priv->jd_sts == M_PLUG_OUT) {
147 /* set debounce to 1ms */
148 accdet_set_debounce(priv, eint_state000,
149 priv->data->pwm_deb->eint_debounce0);
150 } else {
151 dev_dbg(priv->dev, "should not be here %s()\n", __func__);
152 }
153
154 return 0;
155 }
156
recover_eint_analog_setting(struct mt6359_accdet * priv)157 static void recover_eint_analog_setting(struct mt6359_accdet *priv)
158 {
159 if (priv->data->eint_detect_mode == 0x3 ||
160 priv->data->eint_detect_mode == 0x4) {
161 /* ESD switches on */
162 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
163 1 << 8, 1 << 8);
164 }
165 if (priv->data->eint_detect_mode == 0x4) {
166 if (priv->caps & ACCDET_PMIC_EINT0) {
167 /* disable RG_EINT0CONFIGACCDET */
168 regmap_update_bits(priv->regmap,
169 RG_EINT0CONFIGACCDET_ADDR,
170 RG_EINT0CONFIGACCDET_MASK_SFT, 0);
171 } else if (priv->caps & ACCDET_PMIC_EINT1) {
172 /* disable RG_EINT1CONFIGACCDET */
173 regmap_update_bits(priv->regmap,
174 RG_EINT1CONFIGACCDET_ADDR,
175 RG_EINT1CONFIGACCDET_MASK_SFT, 0);
176 }
177 regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR,
178 RG_EINT0HIRENB_MASK_SFT, 0);
179 }
180 }
181
recover_eint_digital_setting(struct mt6359_accdet * priv)182 static void recover_eint_digital_setting(struct mt6359_accdet *priv)
183 {
184 if (priv->caps & ACCDET_PMIC_EINT0) {
185 regmap_update_bits(priv->regmap,
186 ACCDET_EINT0_M_SW_EN_ADDR,
187 ACCDET_EINT0_M_SW_EN_MASK_SFT, 0);
188 } else if (priv->caps & ACCDET_PMIC_EINT1) {
189 regmap_update_bits(priv->regmap,
190 ACCDET_EINT1_M_SW_EN_ADDR,
191 ACCDET_EINT1_M_SW_EN_MASK_SFT, 0);
192 }
193 if (priv->data->eint_detect_mode == 0x4) {
194 /* enable eint0cen */
195 if (priv->caps & ACCDET_PMIC_EINT0) {
196 /* enable eint0cen */
197 regmap_update_bits(priv->regmap,
198 ACCDET_DA_STABLE_ADDR,
199 ACCDET_EINT0_CEN_STABLE_MASK_SFT,
200 BIT(ACCDET_EINT0_CEN_STABLE_SFT));
201 } else if (priv->caps & ACCDET_PMIC_EINT1) {
202 /* enable eint1cen */
203 regmap_update_bits(priv->regmap,
204 ACCDET_DA_STABLE_ADDR,
205 ACCDET_EINT1_CEN_STABLE_MASK_SFT,
206 BIT(ACCDET_EINT1_CEN_STABLE_SFT));
207 }
208 }
209
210 if (priv->data->eint_detect_mode != 0x1) {
211 if (priv->caps & ACCDET_PMIC_EINT0) {
212 /* enable inverter */
213 regmap_update_bits(priv->regmap,
214 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
215 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
216 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
217 } else if (priv->caps & ACCDET_PMIC_EINT1) {
218 /* enable inverter */
219 regmap_update_bits(priv->regmap,
220 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
221 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
222 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
223 }
224 }
225 }
226
recover_eint_setting(struct mt6359_accdet * priv)227 static void recover_eint_setting(struct mt6359_accdet *priv)
228 {
229 if (priv->jd_sts == M_PLUG_OUT) {
230 recover_eint_analog_setting(priv);
231 recover_eint_digital_setting(priv);
232 }
233 }
234
mt6359_accdet_recover_jd_setting(struct mt6359_accdet * priv)235 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv)
236 {
237 int ret;
238 unsigned int value = 0;
239
240 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
241 ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT));
242 usleep_range(200, 300);
243 ret = regmap_read_poll_timeout(priv->regmap,
244 ACCDET_IRQ_ADDR,
245 value,
246 (value & ACCDET_IRQ_MASK_SFT) == 0,
247 0,
248 1000);
249 if (ret)
250 dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret);
251 /* clear accdet int, modify for fix interrupt trigger twice error */
252 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
253 ACCDET_IRQ_CLR_MASK_SFT, 0);
254 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
255 RG_INT_STATUS_ACCDET_MASK_SFT,
256 BIT(RG_INT_STATUS_ACCDET_SFT));
257
258 /* recover accdet debounce0,3 */
259 accdet_set_debounce(priv, accdet_state000,
260 priv->data->pwm_deb->debounce0);
261 accdet_set_debounce(priv, accdet_state001,
262 priv->data->pwm_deb->debounce1);
263 accdet_set_debounce(priv, accdet_state011,
264 priv->data->pwm_deb->debounce3);
265
266 priv->jack_type = 0;
267 priv->btn_type = 0;
268 priv->accdet_status = 0x3;
269 mt6359_accdet_jack_report(priv);
270 }
271
accdet_set_debounce(struct mt6359_accdet * priv,int state,unsigned int debounce)272 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
273 unsigned int debounce)
274 {
275 switch (state) {
276 case accdet_state000:
277 regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce);
278 break;
279 case accdet_state001:
280 regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce);
281 break;
282 case accdet_state010:
283 regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce);
284 break;
285 case accdet_state011:
286 regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce);
287 break;
288 case accdet_auxadc:
289 regmap_write(priv->regmap,
290 ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce);
291 break;
292 case eint_state000:
293 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR,
294 0xF << ACCDET_EINT_DEBOUNCE0_SFT,
295 debounce << ACCDET_EINT_DEBOUNCE0_SFT);
296 break;
297 case eint_state001:
298 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR,
299 0xF << ACCDET_EINT_DEBOUNCE1_SFT,
300 debounce << ACCDET_EINT_DEBOUNCE1_SFT);
301 break;
302 case eint_state010:
303 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR,
304 0xF << ACCDET_EINT_DEBOUNCE2_SFT,
305 debounce << ACCDET_EINT_DEBOUNCE2_SFT);
306 break;
307 case eint_state011:
308 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR,
309 0xF << ACCDET_EINT_DEBOUNCE3_SFT,
310 debounce << ACCDET_EINT_DEBOUNCE3_SFT);
311 break;
312 case eint_inverter_state000:
313 regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR,
314 debounce);
315 break;
316 default:
317 dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__,
318 state);
319 break;
320 }
321 }
322
mt6359_accdet_jack_report(struct mt6359_accdet * priv)323 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv)
324 {
325 int report = 0;
326
327 if (!priv->jack)
328 return;
329
330 report = priv->jack_type | priv->btn_type;
331 snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK);
332 }
333
check_button(struct mt6359_accdet * priv,unsigned int v)334 static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v)
335 {
336 if (priv->caps & ACCDET_FOUR_KEY) {
337 if (v < priv->data->four_key.down &&
338 v >= priv->data->four_key.up)
339 priv->btn_type = SND_JACK_BTN_1;
340 if (v < priv->data->four_key.up &&
341 v >= priv->data->four_key.voice)
342 priv->btn_type = SND_JACK_BTN_2;
343 if (v < priv->data->four_key.voice &&
344 v >= priv->data->four_key.mid)
345 priv->btn_type = SND_JACK_BTN_3;
346 if (v < priv->data->four_key.mid)
347 priv->btn_type = SND_JACK_BTN_0;
348 } else {
349 if (v < priv->data->three_key.down &&
350 v >= priv->data->three_key.up)
351 priv->btn_type = SND_JACK_BTN_1;
352 if (v < priv->data->three_key.up &&
353 v >= priv->data->three_key.mid)
354 priv->btn_type = SND_JACK_BTN_2;
355 if (v < priv->data->three_key.mid)
356 priv->btn_type = SND_JACK_BTN_0;
357 }
358 return 0;
359 }
360
is_key_pressed(struct mt6359_accdet * priv,bool pressed)361 static void is_key_pressed(struct mt6359_accdet *priv, bool pressed)
362 {
363 priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK;
364
365 if (pressed)
366 check_button(priv, priv->cali_voltage);
367 }
368
check_jack_btn_type(struct mt6359_accdet * priv)369 static inline void check_jack_btn_type(struct mt6359_accdet *priv)
370 {
371 unsigned int val = 0;
372
373 regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val);
374
375 priv->accdet_status =
376 (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK;
377
378 switch (priv->accdet_status) {
379 case 0:
380 if (priv->jack_type == SND_JACK_HEADSET)
381 is_key_pressed(priv, true);
382 else
383 priv->jack_type = SND_JACK_HEADPHONE;
384 break;
385 case 1:
386 if (priv->jack_type == SND_JACK_HEADSET) {
387 is_key_pressed(priv, false);
388 } else {
389 priv->jack_type = SND_JACK_HEADSET;
390 accdet_set_debounce(priv, eint_state011, 0x1);
391 }
392 break;
393 case 3:
394 default:
395 priv->jack_type = 0;
396 break;
397 }
398 }
399
mt6359_accdet_work(struct work_struct * work)400 static void mt6359_accdet_work(struct work_struct *work)
401 {
402 struct mt6359_accdet *priv =
403 container_of(work, struct mt6359_accdet, accdet_work);
404
405 mutex_lock(&priv->res_lock);
406 priv->pre_accdet_status = priv->accdet_status;
407 check_jack_btn_type(priv);
408
409 if (priv->jack_plugged &&
410 priv->pre_accdet_status != priv->accdet_status)
411 mt6359_accdet_jack_report(priv);
412 mutex_unlock(&priv->res_lock);
413 }
414
mt6359_accdet_jd_work(struct work_struct * work)415 static void mt6359_accdet_jd_work(struct work_struct *work)
416 {
417 int ret;
418 unsigned int value = 0;
419
420 struct mt6359_accdet *priv =
421 container_of(work, struct mt6359_accdet, jd_work);
422
423 mutex_lock(&priv->res_lock);
424 if (priv->jd_sts == M_PLUG_IN) {
425 priv->jack_plugged = true;
426
427 /* set and clear initial bit every eint interrupt */
428 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
429 ACCDET_SEQ_INIT_MASK_SFT,
430 BIT(ACCDET_SEQ_INIT_SFT));
431 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
432 ACCDET_SEQ_INIT_MASK_SFT, 0);
433 ret = regmap_read_poll_timeout(priv->regmap,
434 ACCDET_SEQ_INIT_ADDR,
435 value,
436 (value & ACCDET_SEQ_INIT_MASK_SFT) == 0,
437 0,
438 1000);
439 if (ret)
440 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
441
442 /* enable ACCDET unit */
443 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
444 ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT));
445 } else if (priv->jd_sts == M_PLUG_OUT) {
446 priv->jack_plugged = false;
447
448 accdet_set_debounce(priv, accdet_state011,
449 priv->data->pwm_deb->debounce3);
450 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
451 ACCDET_SW_EN_MASK_SFT, 0);
452 mt6359_accdet_recover_jd_setting(priv);
453 }
454
455 if (priv->caps & ACCDET_PMIC_EINT_IRQ)
456 recover_eint_setting(priv);
457 mutex_unlock(&priv->res_lock);
458 }
459
mt6359_accdet_irq(int irq,void * data)460 static irqreturn_t mt6359_accdet_irq(int irq, void *data)
461 {
462 struct mt6359_accdet *priv = data;
463 unsigned int irq_val = 0, val = 0, value = 0;
464 int ret;
465
466 mutex_lock(&priv->res_lock);
467 regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val);
468
469 if (irq_val & ACCDET_IRQ_MASK_SFT) {
470 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
471 ACCDET_IRQ_CLR_MASK_SFT,
472 BIT(ACCDET_IRQ_CLR_SFT));
473 ret = regmap_read_poll_timeout(priv->regmap,
474 ACCDET_IRQ_ADDR,
475 value,
476 (value & ACCDET_IRQ_MASK_SFT) == 0,
477 0,
478 1000);
479 if (ret) {
480 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
481 mutex_unlock(&priv->res_lock);
482 return IRQ_NONE;
483 }
484 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
485 ACCDET_IRQ_CLR_MASK_SFT, 0);
486 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
487 RG_INT_STATUS_ACCDET_MASK_SFT,
488 BIT(RG_INT_STATUS_ACCDET_SFT));
489
490 queue_work(priv->accdet_workqueue, &priv->accdet_work);
491 } else {
492 if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) {
493 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
494 ACCDET_EINT0_IRQ_CLR_MASK_SFT,
495 BIT(ACCDET_EINT0_IRQ_CLR_SFT));
496 ret = regmap_read_poll_timeout(priv->regmap,
497 ACCDET_IRQ_ADDR,
498 value,
499 (value & ACCDET_EINT0_IRQ_MASK_SFT) == 0,
500 0,
501 1000);
502 if (ret) {
503 dev_err(priv->dev, "%s(), ret %d\n", __func__,
504 ret);
505 mutex_unlock(&priv->res_lock);
506 return IRQ_NONE;
507 }
508 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
509 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0);
510 regmap_update_bits(priv->regmap,
511 RG_INT_STATUS_ACCDET_ADDR,
512 RG_INT_STATUS_ACCDET_EINT0_MASK_SFT,
513 BIT(RG_INT_STATUS_ACCDET_EINT0_SFT));
514 }
515 if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) {
516 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
517 ACCDET_EINT1_IRQ_CLR_MASK_SFT,
518 BIT(ACCDET_EINT1_IRQ_CLR_SFT));
519 ret = regmap_read_poll_timeout(priv->regmap,
520 ACCDET_IRQ_ADDR,
521 value,
522 (value & ACCDET_EINT1_IRQ_MASK_SFT) == 0,
523 0,
524 1000);
525 if (ret) {
526 dev_err(priv->dev, "%s(), ret %d\n", __func__,
527 ret);
528 mutex_unlock(&priv->res_lock);
529 return IRQ_NONE;
530 }
531 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
532 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0);
533 regmap_update_bits(priv->regmap,
534 RG_INT_STATUS_ACCDET_ADDR,
535 RG_INT_STATUS_ACCDET_EINT1_MASK_SFT,
536 BIT(RG_INT_STATUS_ACCDET_EINT1_SFT));
537 }
538 /* get jack detection status */
539 regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val);
540 priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) &
541 ACCDET_EINT0_MEM_IN_MASK);
542 /* adjust eint digital/analog setting */
543 mt6359_accdet_jd_setting(priv);
544
545 queue_work(priv->jd_workqueue, &priv->jd_work);
546 }
547 mutex_unlock(&priv->res_lock);
548
549 return IRQ_HANDLED;
550 }
551
mt6359_accdet_parse_dt(struct mt6359_accdet * priv)552 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv)
553 {
554 int ret;
555 struct device *dev = priv->dev;
556 struct device_node *node = NULL;
557 int pwm_deb[15] = {0};
558 unsigned int tmp = 0;
559
560 node = of_get_child_by_name(dev->parent->of_node, "accdet");
561 if (!node)
562 return -EINVAL;
563
564 ret = of_property_read_u32(node, "mediatek,mic-vol",
565 &priv->data->mic_vol);
566 if (ret)
567 priv->data->mic_vol = 8;
568
569 ret = of_property_read_u32(node, "mediatek,plugout-debounce",
570 &priv->data->plugout_deb);
571 if (ret)
572 priv->data->plugout_deb = 1;
573
574 ret = of_property_read_u32(node, "mediatek,mic-mode",
575 &priv->data->mic_mode);
576 if (ret)
577 priv->data->mic_mode = 2;
578
579 ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting",
580 pwm_deb, ARRAY_SIZE(pwm_deb));
581 /* debounce8(auxadc debounce) is default, needn't get from dts */
582 if (!ret)
583 memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb));
584
585 ret = of_property_read_u32(node, "mediatek,eint-level-pol",
586 &priv->data->eint_pol);
587 if (ret)
588 priv->data->eint_pol = 8;
589
590 ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp);
591 if (ret)
592 tmp = 0;
593 if (tmp == 0)
594 priv->caps |= ACCDET_PMIC_EINT_IRQ;
595 else if (tmp == 1)
596 priv->caps |= ACCDET_AP_GPIO_EINT;
597
598 ret = of_property_read_u32(node, "mediatek,eint-detect-mode",
599 &priv->data->eint_detect_mode);
600 if (ret) {
601 /* eint detection mode equals to EINT HW Mode */
602 priv->data->eint_detect_mode = 0x4;
603 }
604
605 ret = of_property_read_u32(node, "mediatek,eint-num", &tmp);
606 if (ret)
607 tmp = 0;
608 if (tmp == 0)
609 priv->caps |= ACCDET_PMIC_EINT0;
610 else if (tmp == 1)
611 priv->caps |= ACCDET_PMIC_EINT1;
612 else if (tmp == 2)
613 priv->caps |= ACCDET_PMIC_BI_EINT;
614
615 ret = of_property_read_u32(node, "mediatek,eint-trig-mode",
616 &tmp);
617 if (ret)
618 tmp = 0;
619 if (tmp == 0)
620 priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT;
621 else if (tmp == 1)
622 priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT;
623
624 ret = of_property_read_u32(node, "mediatek,eint-use-ext-res",
625 &priv->data->eint_use_ext_res);
626 if (ret) {
627 /* eint use internal resister */
628 priv->data->eint_use_ext_res = 0x0;
629 }
630
631 ret = of_property_read_u32(node, "mediatek,eint-comp-vth",
632 &priv->data->eint_comp_vth);
633 if (ret)
634 priv->data->eint_comp_vth = 0x0;
635
636 ret = of_property_read_u32(node, "mediatek,key-mode", &tmp);
637 if (ret)
638 tmp = 0;
639 if (tmp == 0) {
640 int three_key[4];
641
642 priv->caps |= ACCDET_THREE_KEY;
643 ret = of_property_read_u32_array(node,
644 "mediatek,three-key-thr",
645 three_key,
646 ARRAY_SIZE(three_key));
647 if (!ret)
648 memcpy(&priv->data->three_key, three_key + 1,
649 sizeof(struct three_key_threshold));
650 } else if (tmp == 1) {
651 int four_key[5];
652
653 priv->caps |= ACCDET_FOUR_KEY;
654 ret = of_property_read_u32_array(node,
655 "mediatek,four-key-thr",
656 four_key,
657 ARRAY_SIZE(four_key));
658 if (!ret) {
659 memcpy(&priv->data->four_key, four_key + 1,
660 sizeof(struct four_key_threshold));
661 } else {
662 dev_warn(priv->dev,
663 "accdet no 4-key-thrsh dts, use efuse\n");
664 }
665 } else if (tmp == 2) {
666 int three_key[4];
667
668 priv->caps |= ACCDET_TRI_KEY_CDD;
669 ret = of_property_read_u32_array(node,
670 "mediatek,tri-key-cdd-thr",
671 three_key,
672 ARRAY_SIZE(three_key));
673 if (!ret)
674 memcpy(&priv->data->three_key, three_key + 1,
675 sizeof(struct three_key_threshold));
676 }
677
678 of_node_put(node);
679 dev_warn(priv->dev, "accdet caps=%x\n", priv->caps);
680
681 return 0;
682 }
683
config_digital_init_by_mode(struct mt6359_accdet * priv)684 static void config_digital_init_by_mode(struct mt6359_accdet *priv)
685 {
686 /* enable eint cmpmem pwm */
687 regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,
688 (priv->data->pwm_deb->eint_pwm_width << 4 |
689 priv->data->pwm_deb->eint_pwm_thresh));
690 /* DA signal stable */
691 if (priv->caps & ACCDET_PMIC_EINT0) {
692 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
693 ACCDET_EINT0_STABLE_VAL);
694 } else if (priv->caps & ACCDET_PMIC_EINT1) {
695 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
696 ACCDET_EINT1_STABLE_VAL);
697 }
698 /* after receive n+1 number, interrupt issued. */
699 regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR,
700 ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT,
701 BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT));
702 /* setting HW mode, enable digital fast discharge
703 * if use EINT0 & EINT1 detection, please modify
704 * ACCDET_HWMODE_EN_ADDR[2:1]
705 */
706 regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100);
707
708 regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR,
709 ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0);
710
711 /* enable PWM */
712 regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67);
713 /* enable inverter detection */
714 if (priv->data->eint_detect_mode == 0x1) {
715 /* disable inverter detection */
716 if (priv->caps & ACCDET_PMIC_EINT0) {
717 regmap_update_bits(priv->regmap,
718 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
719 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
720 0);
721 } else if (priv->caps & ACCDET_PMIC_EINT1) {
722 regmap_update_bits(priv->regmap,
723 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
724 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
725 0);
726 }
727 } else {
728 if (priv->caps & ACCDET_PMIC_EINT0) {
729 regmap_update_bits(priv->regmap,
730 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
731 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
732 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
733 } else if (priv->caps & ACCDET_PMIC_EINT1) {
734 regmap_update_bits(priv->regmap,
735 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
736 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
737 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
738 }
739 }
740 }
741
config_eint_init_by_mode(struct mt6359_accdet * priv)742 static void config_eint_init_by_mode(struct mt6359_accdet *priv)
743 {
744 unsigned int val = 0;
745
746 if (priv->caps & ACCDET_PMIC_EINT0) {
747 regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR,
748 RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT));
749 } else if (priv->caps & ACCDET_PMIC_EINT1) {
750 regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR,
751 RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT));
752 }
753 /* ESD switches on */
754 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
755 1 << 8, 1 << 8);
756 /* before playback, set NCP pull low before nagative voltage */
757 regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR,
758 RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT));
759
760 if (priv->data->eint_detect_mode == 0x1 ||
761 priv->data->eint_detect_mode == 0x2 ||
762 priv->data->eint_detect_mode == 0x3) {
763 if (priv->data->eint_use_ext_res == 0x1) {
764 if (priv->caps & ACCDET_PMIC_EINT0) {
765 regmap_update_bits(priv->regmap,
766 RG_EINT0CONFIGACCDET_ADDR,
767 RG_EINT0CONFIGACCDET_MASK_SFT,
768 0);
769 } else if (priv->caps & ACCDET_PMIC_EINT1) {
770 regmap_update_bits(priv->regmap,
771 RG_EINT1CONFIGACCDET_ADDR,
772 RG_EINT1CONFIGACCDET_MASK_SFT,
773 0);
774 }
775 } else {
776 if (priv->caps & ACCDET_PMIC_EINT0) {
777 regmap_update_bits(priv->regmap,
778 RG_EINT0CONFIGACCDET_ADDR,
779 RG_EINT0CONFIGACCDET_MASK_SFT,
780 BIT(RG_EINT0CONFIGACCDET_SFT));
781 } else if (priv->caps & ACCDET_PMIC_EINT1) {
782 regmap_update_bits(priv->regmap,
783 RG_EINT1CONFIGACCDET_ADDR,
784 RG_EINT1CONFIGACCDET_MASK_SFT,
785 BIT(RG_EINT1CONFIGACCDET_SFT));
786 }
787 }
788 }
789
790 if (priv->data->eint_detect_mode != 0x1) {
791 /* current detect set 0.25uA */
792 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
793 0x3 << RG_ACCDETSPARE_SFT,
794 0x3 << RG_ACCDETSPARE_SFT);
795 }
796 regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR,
797 val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT);
798 }
799
mt6359_accdet_init(struct mt6359_accdet * priv)800 static void mt6359_accdet_init(struct mt6359_accdet *priv)
801 {
802 unsigned int reg = 0;
803
804 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
805 ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT));
806 mdelay(2);
807 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
808 ACCDET_SEQ_INIT_MASK_SFT, 0);
809 mdelay(1);
810 /* init the debounce time (debounce/32768)sec */
811 accdet_set_debounce(priv, accdet_state000,
812 priv->data->pwm_deb->debounce0);
813 accdet_set_debounce(priv, accdet_state001,
814 priv->data->pwm_deb->debounce1);
815 accdet_set_debounce(priv, accdet_state011,
816 priv->data->pwm_deb->debounce3);
817 accdet_set_debounce(priv, accdet_auxadc,
818 priv->data->pwm_deb->debounce4);
819
820 accdet_set_debounce(priv, eint_state000,
821 priv->data->pwm_deb->eint_debounce0);
822 accdet_set_debounce(priv, eint_state001,
823 priv->data->pwm_deb->eint_debounce1);
824 accdet_set_debounce(priv, eint_state011,
825 priv->data->pwm_deb->eint_debounce3);
826 accdet_set_debounce(priv, eint_inverter_state000,
827 priv->data->pwm_deb->eint_inverter_debounce);
828
829 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
830 RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT));
831 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
832 RG_ACCDET_RST_MASK_SFT, 0);
833
834 /* clear high micbias1 voltage setting */
835 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
836 0x3 << RG_AUDMICBIAS1HVEN_SFT, 0);
837 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
838 0x7 << RG_AUDMICBIAS1VREF_SFT, 0);
839
840 /* init pwm frequency, duty & rise/falling delay */
841 regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR,
842 REGISTER_VAL(priv->data->pwm_deb->pwm_width));
843 regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR,
844 REGISTER_VAL(priv->data->pwm_deb->pwm_thresh));
845 regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR,
846 (priv->data->pwm_deb->fall_delay << 15 |
847 priv->data->pwm_deb->rise_delay));
848
849 regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®);
850 if (priv->data->mic_vol <= 7) {
851 /* micbias1 <= 2.7V */
852 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
853 reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) |
854 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
855 } else if (priv->data->mic_vol == 8) {
856 /* micbias1 = 2.8v */
857 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
858 reg | (3 << RG_AUDMICBIAS1HVEN_SFT) |
859 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
860 } else if (priv->data->mic_vol == 9) {
861 /* micbias1 = 2.85v */
862 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
863 reg | (1 << RG_AUDMICBIAS1HVEN_SFT) |
864 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
865 }
866 /* mic mode setting */
867 regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®);
868 if (priv->data->mic_mode == HEADSET_MODE_1) {
869 /* ACC mode*/
870 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
871 reg | RG_ACCDET_MODE_ANA11_MODE1);
872 /* enable analog fast discharge */
873 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
874 RG_ANALOGFDEN_MASK_SFT,
875 BIT(RG_ANALOGFDEN_SFT));
876 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
877 0x3 << 11, 0x3 << 11);
878 } else if (priv->data->mic_mode == HEADSET_MODE_2) {
879 /* DCC mode Low cost mode without internal bias */
880 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
881 reg | RG_ACCDET_MODE_ANA11_MODE2);
882 /* enable analog fast discharge */
883 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
884 0x3 << RG_ANALOGFDEN_SFT,
885 0x3 << RG_ANALOGFDEN_SFT);
886 } else if (priv->data->mic_mode == HEADSET_MODE_6) {
887 /* DCC mode Low cost mode with internal bias,
888 * bit8 = 1 to use internal bias
889 */
890 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
891 reg | RG_ACCDET_MODE_ANA11_MODE6);
892 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
893 RG_AUDMICBIAS1DCSW1PEN_MASK_SFT,
894 BIT(RG_AUDMICBIAS1DCSW1PEN_SFT));
895 /* enable analog fast discharge */
896 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
897 0x3 << RG_ANALOGFDEN_SFT,
898 0x3 << RG_ANALOGFDEN_SFT);
899 }
900
901 if (priv->caps & ACCDET_PMIC_EINT_IRQ) {
902 config_eint_init_by_mode(priv);
903 config_digital_init_by_mode(priv);
904 }
905 }
906
mt6359_accdet_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)907 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
908 struct snd_soc_jack *jack)
909 {
910 struct mt6359_accdet *priv =
911 snd_soc_component_get_drvdata(component);
912
913 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
914 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN);
915 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
916 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
917
918 priv->jack = jack;
919
920 mt6359_accdet_jack_report(priv);
921
922 return 0;
923 }
924 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect);
925
mt6359_accdet_probe(struct platform_device * pdev)926 static int mt6359_accdet_probe(struct platform_device *pdev)
927 {
928 struct mt6359_accdet *priv;
929 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
930 int ret;
931
932 dev_dbg(&pdev->dev, "%s(), dev name %s\n",
933 __func__, dev_name(&pdev->dev));
934
935 priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet),
936 GFP_KERNEL);
937 if (!priv)
938 return -ENOMEM;
939
940 priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data),
941 GFP_KERNEL);
942 if (!priv->data)
943 return -ENOMEM;
944
945 priv->data->pwm_deb = devm_kzalloc(&pdev->dev,
946 sizeof(struct pwm_deb_settings),
947 GFP_KERNEL);
948 if (!priv->data->pwm_deb)
949 return -ENOMEM;
950
951 priv->regmap = mt6397->regmap;
952 if (IS_ERR(priv->regmap)) {
953 ret = PTR_ERR(priv->regmap);
954 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
955 ret);
956 return ret;
957 }
958 priv->dev = &pdev->dev;
959
960 ret = mt6359_accdet_parse_dt(priv);
961 if (ret) {
962 dev_err(&pdev->dev, "Failed to parse dts\n");
963 return ret;
964 }
965 mutex_init(&priv->res_lock);
966
967 priv->accdet_irq = platform_get_irq(pdev, 0);
968 if (priv->accdet_irq >= 0) {
969 ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq,
970 NULL, mt6359_accdet_irq,
971 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
972 "ACCDET_IRQ", priv);
973 if (ret) {
974 dev_err(&pdev->dev,
975 "Failed to request IRQ: (%d)\n", ret);
976 return ret;
977 }
978 }
979
980 if (priv->caps & ACCDET_PMIC_EINT0) {
981 priv->accdet_eint0 = platform_get_irq(pdev, 1);
982 if (priv->accdet_eint0 >= 0) {
983 ret = devm_request_threaded_irq(&pdev->dev,
984 priv->accdet_eint0,
985 NULL, mt6359_accdet_irq,
986 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
987 "ACCDET_EINT0", priv);
988 if (ret) {
989 dev_err(&pdev->dev,
990 "Failed to request eint0 IRQ (%d)\n",
991 ret);
992 return ret;
993 }
994 }
995 } else if (priv->caps & ACCDET_PMIC_EINT1) {
996 priv->accdet_eint1 = platform_get_irq(pdev, 2);
997 if (priv->accdet_eint1 >= 0) {
998 ret = devm_request_threaded_irq(&pdev->dev,
999 priv->accdet_eint1,
1000 NULL, mt6359_accdet_irq,
1001 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1002 "ACCDET_EINT1", priv);
1003 if (ret) {
1004 dev_err(&pdev->dev,
1005 "Failed to request eint1 IRQ (%d)\n",
1006 ret);
1007 return ret;
1008 }
1009 }
1010 }
1011
1012 priv->accdet_workqueue = create_singlethread_workqueue("accdet");
1013 INIT_WORK(&priv->accdet_work, mt6359_accdet_work);
1014 if (!priv->accdet_workqueue) {
1015 dev_err(&pdev->dev, "Failed to create accdet workqueue\n");
1016 ret = -1;
1017 goto err_accdet_wq;
1018 }
1019
1020 priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd");
1021 INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work);
1022 if (!priv->jd_workqueue) {
1023 dev_err(&pdev->dev, "Failed to create jack detect workqueue\n");
1024 ret = -1;
1025 goto err_eint_wq;
1026 }
1027
1028 platform_set_drvdata(pdev, priv);
1029 ret = devm_snd_soc_register_component(&pdev->dev,
1030 &mt6359_accdet_soc_driver,
1031 NULL, 0);
1032 if (ret) {
1033 dev_err(&pdev->dev, "Failed to register component\n");
1034 return ret;
1035 }
1036
1037 priv->jd_sts = M_PLUG_OUT;
1038 priv->jack_type = 0;
1039 priv->btn_type = 0;
1040 priv->accdet_status = 0x3;
1041 mt6359_accdet_init(priv);
1042
1043 mt6359_accdet_jack_report(priv);
1044
1045 return 0;
1046
1047 err_eint_wq:
1048 destroy_workqueue(priv->accdet_workqueue);
1049 err_accdet_wq:
1050 dev_err(&pdev->dev, "%s error. now exit.!\n", __func__);
1051 return ret;
1052 }
1053
1054 static struct platform_driver mt6359_accdet_driver = {
1055 .driver = {
1056 .name = "pmic-codec-accdet",
1057 },
1058 .probe = mt6359_accdet_probe,
1059 };
1060
1061 module_platform_driver(mt6359_accdet_driver)
1062
1063 /* Module information */
1064 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver");
1065 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>");
1066 MODULE_LICENSE("GPL v2");
1067